blob: 24885b3db3d504d203b5985a694175603eab82a1 [file] [log] [blame]
Thomas Gleixnerc942fdd2019-05-27 08:55:06 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Kevin Wellsc4a02082010-02-26 15:53:41 -08002/*
Roland Stiggeda03d742012-06-11 10:12:40 +02003 * GPIO driver for LPC32xx SoC
Kevin Wellsc4a02082010-02-26 15:53:41 -08004 *
5 * Author: Kevin Wells <kevin.wells@nxp.com>
6 *
7 * Copyright (C) 2010 NXP Semiconductors
Kevin Wellsc4a02082010-02-26 15:53:41 -08008 */
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/errno.h>
Linus Walleij11975f92018-04-13 14:47:59 +020014#include <linux/gpio/driver.h>
Sachin Kamat831cbd72013-10-16 15:35:01 +053015#include <linux/of.h>
Roland Stiggee92935e2012-05-18 10:19:52 +020016#include <linux/platform_device.h>
17#include <linux/module.h>
Kevin Wellsc4a02082010-02-26 15:53:41 -080018
19#include <mach/hardware.h>
20#include <mach/platform.h>
Kevin Wellsc4a02082010-02-26 15:53:41 -080021
22#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
23#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
24#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
25#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
26#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
27#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
28#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
29#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
30#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
31#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
32#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
33#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
34#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
35#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
36#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
37#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
38#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
39#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
40#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
41#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
42#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
43#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
44#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
45#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
46#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
47#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
48#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
49
50#define GPIO012_PIN_TO_BIT(x) (1 << (x))
51#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
52#define GPO3_PIN_TO_BIT(x) (1 << (x))
53#define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
54#define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x))
Roland Stigge8e5fb372012-03-05 23:01:10 +010055#define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
Kevin Wellsc4a02082010-02-26 15:53:41 -080056#define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1)
57#define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
Roland Stigge46158aa2012-03-05 23:01:11 +010058#define GPO3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
Kevin Wellsc4a02082010-02-26 15:53:41 -080059
Vladimir Zapolskiy14bf8732016-09-08 02:58:32 +030060#define LPC32XX_GPIO_P0_MAX 8
61#define LPC32XX_GPIO_P1_MAX 24
62#define LPC32XX_GPIO_P2_MAX 13
63#define LPC32XX_GPIO_P3_MAX 6
64#define LPC32XX_GPI_P3_MAX 29
65#define LPC32XX_GPO_P3_MAX 24
66
67#define LPC32XX_GPIO_P0_GRP 0
68#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
69#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
70#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
71#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
72#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
73
Kevin Wellsc4a02082010-02-26 15:53:41 -080074struct gpio_regs {
75 void __iomem *inp_state;
Roland Stigge46158aa2012-03-05 23:01:11 +010076 void __iomem *outp_state;
Kevin Wellsc4a02082010-02-26 15:53:41 -080077 void __iomem *outp_set;
78 void __iomem *outp_clr;
79 void __iomem *dir_set;
80 void __iomem *dir_clr;
81};
82
83/*
84 * GPIO names
85 */
86static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
87 "p0.0", "p0.1", "p0.2", "p0.3",
88 "p0.4", "p0.5", "p0.6", "p0.7"
89};
90
91static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
92 "p1.0", "p1.1", "p1.2", "p1.3",
93 "p1.4", "p1.5", "p1.6", "p1.7",
94 "p1.8", "p1.9", "p1.10", "p1.11",
95 "p1.12", "p1.13", "p1.14", "p1.15",
96 "p1.16", "p1.17", "p1.18", "p1.19",
97 "p1.20", "p1.21", "p1.22", "p1.23",
98};
99
100static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
101 "p2.0", "p2.1", "p2.2", "p2.3",
102 "p2.4", "p2.5", "p2.6", "p2.7",
103 "p2.8", "p2.9", "p2.10", "p2.11",
104 "p2.12"
105};
106
107static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
Roland Stigge95120d52012-01-22 18:57:57 +0100108 "gpio00", "gpio01", "gpio02", "gpio03",
Kevin Wellsc4a02082010-02-26 15:53:41 -0800109 "gpio04", "gpio05"
110};
111
112static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
113 "gpi00", "gpi01", "gpi02", "gpi03",
114 "gpi04", "gpi05", "gpi06", "gpi07",
115 "gpi08", "gpi09", NULL, NULL,
116 NULL, NULL, NULL, "gpi15",
117 "gpi16", "gpi17", "gpi18", "gpi19",
118 "gpi20", "gpi21", "gpi22", "gpi23",
Roland Stigge71fde002012-09-25 09:56:13 +0200119 "gpi24", "gpi25", "gpi26", "gpi27",
120 "gpi28"
Kevin Wellsc4a02082010-02-26 15:53:41 -0800121};
122
123static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
124 "gpo00", "gpo01", "gpo02", "gpo03",
125 "gpo04", "gpo05", "gpo06", "gpo07",
126 "gpo08", "gpo09", "gpo10", "gpo11",
127 "gpo12", "gpo13", "gpo14", "gpo15",
128 "gpo16", "gpo17", "gpo18", "gpo19",
129 "gpo20", "gpo21", "gpo22", "gpo23"
130};
131
132static struct gpio_regs gpio_grp_regs_p0 = {
133 .inp_state = LPC32XX_GPIO_P0_INP_STATE,
134 .outp_set = LPC32XX_GPIO_P0_OUTP_SET,
135 .outp_clr = LPC32XX_GPIO_P0_OUTP_CLR,
136 .dir_set = LPC32XX_GPIO_P0_DIR_SET,
137 .dir_clr = LPC32XX_GPIO_P0_DIR_CLR,
138};
139
140static struct gpio_regs gpio_grp_regs_p1 = {
141 .inp_state = LPC32XX_GPIO_P1_INP_STATE,
142 .outp_set = LPC32XX_GPIO_P1_OUTP_SET,
143 .outp_clr = LPC32XX_GPIO_P1_OUTP_CLR,
144 .dir_set = LPC32XX_GPIO_P1_DIR_SET,
145 .dir_clr = LPC32XX_GPIO_P1_DIR_CLR,
146};
147
148static struct gpio_regs gpio_grp_regs_p2 = {
149 .inp_state = LPC32XX_GPIO_P2_INP_STATE,
150 .outp_set = LPC32XX_GPIO_P2_OUTP_SET,
151 .outp_clr = LPC32XX_GPIO_P2_OUTP_CLR,
152 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
153 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
154};
155
156static struct gpio_regs gpio_grp_regs_p3 = {
157 .inp_state = LPC32XX_GPIO_P3_INP_STATE,
Roland Stigge46158aa2012-03-05 23:01:11 +0100158 .outp_state = LPC32XX_GPIO_P3_OUTP_STATE,
Kevin Wellsc4a02082010-02-26 15:53:41 -0800159 .outp_set = LPC32XX_GPIO_P3_OUTP_SET,
160 .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR,
161 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
162 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
163};
164
165struct lpc32xx_gpio_chip {
166 struct gpio_chip chip;
167 struct gpio_regs *gpio_grp;
168};
169
Kevin Wellsc4a02082010-02-26 15:53:41 -0800170static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
171 unsigned pin, int input)
172{
173 if (input)
174 __raw_writel(GPIO012_PIN_TO_BIT(pin),
175 group->gpio_grp->dir_clr);
176 else
177 __raw_writel(GPIO012_PIN_TO_BIT(pin),
178 group->gpio_grp->dir_set);
179}
180
181static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
182 unsigned pin, int input)
183{
184 u32 u = GPIO3_PIN_TO_BIT(pin);
185
186 if (input)
187 __raw_writel(u, group->gpio_grp->dir_clr);
188 else
189 __raw_writel(u, group->gpio_grp->dir_set);
190}
191
192static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
193 unsigned pin, int high)
194{
195 if (high)
196 __raw_writel(GPIO012_PIN_TO_BIT(pin),
197 group->gpio_grp->outp_set);
198 else
199 __raw_writel(GPIO012_PIN_TO_BIT(pin),
200 group->gpio_grp->outp_clr);
201}
202
203static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
204 unsigned pin, int high)
205{
206 u32 u = GPIO3_PIN_TO_BIT(pin);
207
208 if (high)
209 __raw_writel(u, group->gpio_grp->outp_set);
210 else
211 __raw_writel(u, group->gpio_grp->outp_clr);
212}
213
214static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
215 unsigned pin, int high)
216{
217 if (high)
218 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
219 else
220 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
221}
222
223static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
224 unsigned pin)
225{
226 return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
227 pin);
228}
229
230static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
231 unsigned pin)
232{
233 int state = __raw_readl(group->gpio_grp->inp_state);
234
235 /*
236 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
237 * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
238 */
239 return GPIO3_PIN_IN_SEL(state, pin);
240}
241
242static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
243 unsigned pin)
244{
245 return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
246}
247
Roland Stigge46158aa2012-03-05 23:01:11 +0100248static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
249 unsigned pin)
250{
251 return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
252}
253
Kevin Wellsc4a02082010-02-26 15:53:41 -0800254/*
Alexandre Courbot7fd2bf32013-03-28 05:07:46 -0700255 * GPIO primitives.
Kevin Wellsc4a02082010-02-26 15:53:41 -0800256 */
257static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
258 unsigned pin)
259{
Linus Walleija9bc97e2015-12-07 09:18:23 +0100260 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
Kevin Wellsc4a02082010-02-26 15:53:41 -0800261
262 __set_gpio_dir_p012(group, pin, 1);
263
264 return 0;
265}
266
267static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
268 unsigned pin)
269{
Linus Walleija9bc97e2015-12-07 09:18:23 +0100270 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
Kevin Wellsc4a02082010-02-26 15:53:41 -0800271
272 __set_gpio_dir_p3(group, pin, 1);
273
274 return 0;
275}
276
277static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
278 unsigned pin)
279{
280 return 0;
281}
282
283static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
284{
Linus Walleija9bc97e2015-12-07 09:18:23 +0100285 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
Kevin Wellsc4a02082010-02-26 15:53:41 -0800286
Linus Walleij2e6d8452015-12-21 11:10:06 +0100287 return !!__get_gpio_state_p012(group, pin);
Kevin Wellsc4a02082010-02-26 15:53:41 -0800288}
289
290static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
291{
Linus Walleija9bc97e2015-12-07 09:18:23 +0100292 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
Kevin Wellsc4a02082010-02-26 15:53:41 -0800293
Linus Walleij2e6d8452015-12-21 11:10:06 +0100294 return !!__get_gpio_state_p3(group, pin);
Kevin Wellsc4a02082010-02-26 15:53:41 -0800295}
296
297static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
298{
Linus Walleija9bc97e2015-12-07 09:18:23 +0100299 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
Kevin Wellsc4a02082010-02-26 15:53:41 -0800300
Linus Walleij2e6d8452015-12-21 11:10:06 +0100301 return !!__get_gpi_state_p3(group, pin);
Kevin Wellsc4a02082010-02-26 15:53:41 -0800302}
303
304static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
305 int value)
306{
Linus Walleija9bc97e2015-12-07 09:18:23 +0100307 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
Kevin Wellsc4a02082010-02-26 15:53:41 -0800308
Roland Stiggeb1268d32012-09-20 10:48:03 +0200309 __set_gpio_level_p012(group, pin, value);
Kevin Wellsc4a02082010-02-26 15:53:41 -0800310 __set_gpio_dir_p012(group, pin, 0);
311
312 return 0;
313}
314
315static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
316 int value)
317{
Linus Walleija9bc97e2015-12-07 09:18:23 +0100318 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
Kevin Wellsc4a02082010-02-26 15:53:41 -0800319
Roland Stiggeb1268d32012-09-20 10:48:03 +0200320 __set_gpio_level_p3(group, pin, value);
Kevin Wellsc4a02082010-02-26 15:53:41 -0800321 __set_gpio_dir_p3(group, pin, 0);
322
323 return 0;
324}
325
326static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
327 int value)
328{
Linus Walleija9bc97e2015-12-07 09:18:23 +0100329 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
Roland Stiggeb1268d32012-09-20 10:48:03 +0200330
331 __set_gpo_level_p3(group, pin, value);
Kevin Wellsc4a02082010-02-26 15:53:41 -0800332 return 0;
333}
334
335static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
336 int value)
337{
Linus Walleija9bc97e2015-12-07 09:18:23 +0100338 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
Kevin Wellsc4a02082010-02-26 15:53:41 -0800339
340 __set_gpio_level_p012(group, pin, value);
341}
342
343static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
344 int value)
345{
Linus Walleija9bc97e2015-12-07 09:18:23 +0100346 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
Kevin Wellsc4a02082010-02-26 15:53:41 -0800347
348 __set_gpio_level_p3(group, pin, value);
349}
350
351static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
352 int value)
353{
Linus Walleija9bc97e2015-12-07 09:18:23 +0100354 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
Kevin Wellsc4a02082010-02-26 15:53:41 -0800355
356 __set_gpo_level_p3(group, pin, value);
357}
358
Roland Stigge46158aa2012-03-05 23:01:11 +0100359static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
360{
Linus Walleija9bc97e2015-12-07 09:18:23 +0100361 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
Roland Stigge46158aa2012-03-05 23:01:11 +0100362
Linus Walleij2e6d8452015-12-21 11:10:06 +0100363 return !!__get_gpo_state_p3(group, pin);
Roland Stigge46158aa2012-03-05 23:01:11 +0100364}
365
Kevin Wellsc4a02082010-02-26 15:53:41 -0800366static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
367{
368 if (pin < chip->ngpio)
369 return 0;
370
371 return -EINVAL;
372}
373
Roland Stigge0bdfedd2012-06-20 16:33:52 +0200374static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset)
375{
Roland Stigge0bdfedd2012-06-20 16:33:52 +0200376 return -ENXIO;
377}
378
Sylvain Lemieux320a6482016-05-11 13:40:00 -0400379static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset)
380{
381 return -ENXIO;
382}
Roland Stigge0bdfedd2012-06-20 16:33:52 +0200383
384static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset)
385{
Roland Stigge0bdfedd2012-06-20 16:33:52 +0200386 return -ENXIO;
387}
388
Kevin Wellsc4a02082010-02-26 15:53:41 -0800389static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
390 {
391 .chip = {
392 .label = "gpio_p0",
393 .direction_input = lpc32xx_gpio_dir_input_p012,
394 .get = lpc32xx_gpio_get_value_p012,
395 .direction_output = lpc32xx_gpio_dir_output_p012,
396 .set = lpc32xx_gpio_set_value_p012,
397 .request = lpc32xx_gpio_request,
Roland Stigge0bdfedd2012-06-20 16:33:52 +0200398 .to_irq = lpc32xx_gpio_to_irq_p01,
Kevin Wellsc4a02082010-02-26 15:53:41 -0800399 .base = LPC32XX_GPIO_P0_GRP,
400 .ngpio = LPC32XX_GPIO_P0_MAX,
401 .names = gpio_p0_names,
Linus Walleij9fb1f392013-12-04 14:42:46 +0100402 .can_sleep = false,
Kevin Wellsc4a02082010-02-26 15:53:41 -0800403 },
404 .gpio_grp = &gpio_grp_regs_p0,
405 },
406 {
407 .chip = {
408 .label = "gpio_p1",
409 .direction_input = lpc32xx_gpio_dir_input_p012,
410 .get = lpc32xx_gpio_get_value_p012,
411 .direction_output = lpc32xx_gpio_dir_output_p012,
412 .set = lpc32xx_gpio_set_value_p012,
413 .request = lpc32xx_gpio_request,
Roland Stigge0bdfedd2012-06-20 16:33:52 +0200414 .to_irq = lpc32xx_gpio_to_irq_p01,
Kevin Wellsc4a02082010-02-26 15:53:41 -0800415 .base = LPC32XX_GPIO_P1_GRP,
416 .ngpio = LPC32XX_GPIO_P1_MAX,
417 .names = gpio_p1_names,
Linus Walleij9fb1f392013-12-04 14:42:46 +0100418 .can_sleep = false,
Kevin Wellsc4a02082010-02-26 15:53:41 -0800419 },
420 .gpio_grp = &gpio_grp_regs_p1,
421 },
422 {
423 .chip = {
424 .label = "gpio_p2",
425 .direction_input = lpc32xx_gpio_dir_input_p012,
426 .get = lpc32xx_gpio_get_value_p012,
427 .direction_output = lpc32xx_gpio_dir_output_p012,
428 .set = lpc32xx_gpio_set_value_p012,
429 .request = lpc32xx_gpio_request,
430 .base = LPC32XX_GPIO_P2_GRP,
431 .ngpio = LPC32XX_GPIO_P2_MAX,
432 .names = gpio_p2_names,
Linus Walleij9fb1f392013-12-04 14:42:46 +0100433 .can_sleep = false,
Kevin Wellsc4a02082010-02-26 15:53:41 -0800434 },
435 .gpio_grp = &gpio_grp_regs_p2,
436 },
437 {
438 .chip = {
439 .label = "gpio_p3",
440 .direction_input = lpc32xx_gpio_dir_input_p3,
441 .get = lpc32xx_gpio_get_value_p3,
442 .direction_output = lpc32xx_gpio_dir_output_p3,
443 .set = lpc32xx_gpio_set_value_p3,
444 .request = lpc32xx_gpio_request,
Roland Stigge0bdfedd2012-06-20 16:33:52 +0200445 .to_irq = lpc32xx_gpio_to_irq_gpio_p3,
Kevin Wellsc4a02082010-02-26 15:53:41 -0800446 .base = LPC32XX_GPIO_P3_GRP,
447 .ngpio = LPC32XX_GPIO_P3_MAX,
448 .names = gpio_p3_names,
Linus Walleij9fb1f392013-12-04 14:42:46 +0100449 .can_sleep = false,
Kevin Wellsc4a02082010-02-26 15:53:41 -0800450 },
451 .gpio_grp = &gpio_grp_regs_p3,
452 },
453 {
454 .chip = {
455 .label = "gpi_p3",
456 .direction_input = lpc32xx_gpio_dir_in_always,
457 .get = lpc32xx_gpi_get_value,
458 .request = lpc32xx_gpio_request,
Roland Stigge0bdfedd2012-06-20 16:33:52 +0200459 .to_irq = lpc32xx_gpio_to_irq_gpi_p3,
Kevin Wellsc4a02082010-02-26 15:53:41 -0800460 .base = LPC32XX_GPI_P3_GRP,
461 .ngpio = LPC32XX_GPI_P3_MAX,
462 .names = gpi_p3_names,
Linus Walleij9fb1f392013-12-04 14:42:46 +0100463 .can_sleep = false,
Kevin Wellsc4a02082010-02-26 15:53:41 -0800464 },
465 .gpio_grp = &gpio_grp_regs_p3,
466 },
467 {
468 .chip = {
469 .label = "gpo_p3",
470 .direction_output = lpc32xx_gpio_dir_out_always,
471 .set = lpc32xx_gpo_set_value,
Roland Stigge46158aa2012-03-05 23:01:11 +0100472 .get = lpc32xx_gpo_get_value,
Kevin Wellsc4a02082010-02-26 15:53:41 -0800473 .request = lpc32xx_gpio_request,
474 .base = LPC32XX_GPO_P3_GRP,
475 .ngpio = LPC32XX_GPO_P3_MAX,
476 .names = gpo_p3_names,
Linus Walleij9fb1f392013-12-04 14:42:46 +0100477 .can_sleep = false,
Kevin Wellsc4a02082010-02-26 15:53:41 -0800478 },
479 .gpio_grp = &gpio_grp_regs_p3,
480 },
481};
482
Roland Stiggee92935e2012-05-18 10:19:52 +0200483static int lpc32xx_of_xlate(struct gpio_chip *gc,
484 const struct of_phandle_args *gpiospec, u32 *flags)
485{
486 /* Is this the correct bank? */
487 u32 bank = gpiospec->args[0];
Axel Linfdc7a9f2013-04-07 20:28:20 +0800488 if ((bank >= ARRAY_SIZE(lpc32xx_gpiochip) ||
Roland Stiggee92935e2012-05-18 10:19:52 +0200489 (gc != &lpc32xx_gpiochip[bank].chip)))
490 return -EINVAL;
491
492 if (flags)
493 *flags = gpiospec->args[2];
494 return gpiospec->args[1];
495}
496
Bill Pemberton38363092012-11-19 13:22:34 -0500497static int lpc32xx_gpio_probe(struct platform_device *pdev)
Roland Stiggee92935e2012-05-18 10:19:52 +0200498{
Kevin Wellsc4a02082010-02-26 15:53:41 -0800499 int i;
500
Roland Stiggee92935e2012-05-18 10:19:52 +0200501 for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
502 if (pdev->dev.of_node) {
503 lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
504 lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
505 lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
506 }
Laxman Dewangan69c0a0a2016-02-22 17:43:28 +0530507 devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
Linus Walleija9bc97e2015-12-07 09:18:23 +0100508 &lpc32xx_gpiochip[i]);
Roland Stiggee92935e2012-05-18 10:19:52 +0200509 }
510
511 return 0;
Kevin Wellsc4a02082010-02-26 15:53:41 -0800512}
Roland Stiggee92935e2012-05-18 10:19:52 +0200513
514#ifdef CONFIG_OF
Jingoo Hane95c7c42014-06-03 21:09:02 +0900515static const struct of_device_id lpc32xx_gpio_of_match[] = {
Roland Stiggee92935e2012-05-18 10:19:52 +0200516 { .compatible = "nxp,lpc3220-gpio", },
517 { },
518};
519#endif
520
521static struct platform_driver lpc32xx_gpio_driver = {
522 .driver = {
523 .name = "lpc32xx-gpio",
Roland Stiggee92935e2012-05-18 10:19:52 +0200524 .of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
525 },
526 .probe = lpc32xx_gpio_probe,
527};
528
529module_platform_driver(lpc32xx_gpio_driver);