Thomas Gleixner | c942fdd | 2019-05-27 08:55:06 +0200 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2016 Rockchip Electronics Co. Ltd. |
| 4 | * Author: Elaine <zhangqing@rock-chips.com> |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <linux/clk-provider.h> |
Stephen Boyd | 62e59c4 | 2019-04-18 15:20:22 -0700 | [diff] [blame] | 8 | #include <linux/io.h> |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 9 | #include <linux/of.h> |
| 10 | #include <linux/of_address.h> |
| 11 | #include <linux/syscore_ops.h> |
| 12 | #include <dt-bindings/clock/rk3328-cru.h> |
| 13 | #include "clk.h" |
| 14 | |
Elaine Zhang | 9bb4db6 | 2017-02-06 10:50:35 +0800 | [diff] [blame] | 15 | #define RK3328_GRF_SOC_CON4 0x410 |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 16 | #define RK3328_GRF_SOC_STATUS0 0x480 |
| 17 | #define RK3328_GRF_MAC_CON1 0x904 |
| 18 | #define RK3328_GRF_MAC_CON2 0x908 |
| 19 | |
| 20 | enum rk3328_plls { |
| 21 | apll, dpll, cpll, gpll, npll, |
| 22 | }; |
| 23 | |
| 24 | static struct rockchip_pll_rate_table rk3328_pll_rates[] = { |
| 25 | /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ |
| 26 | RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), |
| 27 | RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), |
| 28 | RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), |
| 29 | RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), |
| 30 | RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), |
| 31 | RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), |
| 32 | RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), |
| 33 | RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), |
| 34 | RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), |
| 35 | RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), |
| 36 | RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), |
| 37 | RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), |
| 38 | RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), |
| 39 | RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), |
| 40 | RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), |
| 41 | RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), |
| 42 | RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), |
| 43 | RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), |
| 44 | RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), |
| 45 | RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), |
| 46 | RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), |
| 47 | RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), |
| 48 | RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0), |
| 49 | RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0), |
| 50 | RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0), |
| 51 | RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), |
| 52 | RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0), |
| 53 | RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0), |
| 54 | RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0), |
| 55 | RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0), |
| 56 | RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), |
| 57 | RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0), |
| 58 | RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0), |
| 59 | RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0), |
| 60 | RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0), |
| 61 | RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), |
| 62 | RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0), |
| 63 | RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0), |
| 64 | RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), |
| 65 | RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0), |
| 66 | RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), |
| 67 | RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0), |
| 68 | { /* sentinel */ }, |
| 69 | }; |
| 70 | |
| 71 | static struct rockchip_pll_rate_table rk3328_pll_frac_rates[] = { |
| 72 | /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ |
Katsuhiro Suzuki | a0e447b | 2018-12-23 01:42:49 +0900 | [diff] [blame] | 73 | RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134218), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 74 | /* vco = 1016064000 */ |
Katsuhiro Suzuki | a0e447b | 2018-12-23 01:42:49 +0900 | [diff] [blame] | 75 | RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671089), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 76 | /* vco = 983040000 */ |
Katsuhiro Suzuki | a0e447b | 2018-12-23 01:42:49 +0900 | [diff] [blame] | 77 | RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671089), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 78 | /* vco = 983040000 */ |
Katsuhiro Suzuki | a0e447b | 2018-12-23 01:42:49 +0900 | [diff] [blame] | 79 | RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671089), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 80 | /* vco = 860156000 */ |
Katsuhiro Suzuki | a0e447b | 2018-12-23 01:42:49 +0900 | [diff] [blame] | 81 | RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797895), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 82 | /* vco = 903168000 */ |
Katsuhiro Suzuki | a0e447b | 2018-12-23 01:42:49 +0900 | [diff] [blame] | 83 | RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066330), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 84 | /* vco = 819200000 */ |
| 85 | { /* sentinel */ }, |
| 86 | }; |
| 87 | |
| 88 | #define RK3328_DIV_ACLKM_MASK 0x7 |
| 89 | #define RK3328_DIV_ACLKM_SHIFT 4 |
| 90 | #define RK3328_DIV_PCLK_DBG_MASK 0xf |
| 91 | #define RK3328_DIV_PCLK_DBG_SHIFT 0 |
| 92 | |
| 93 | #define RK3328_CLKSEL1(_aclk_core, _pclk_dbg) \ |
| 94 | { \ |
| 95 | .reg = RK3328_CLKSEL_CON(1), \ |
| 96 | .val = HIWORD_UPDATE(_aclk_core, RK3328_DIV_ACLKM_MASK, \ |
| 97 | RK3328_DIV_ACLKM_SHIFT) | \ |
| 98 | HIWORD_UPDATE(_pclk_dbg, RK3328_DIV_PCLK_DBG_MASK, \ |
| 99 | RK3328_DIV_PCLK_DBG_SHIFT), \ |
| 100 | } |
| 101 | |
| 102 | #define RK3328_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \ |
| 103 | { \ |
| 104 | .prate = _prate, \ |
| 105 | .divs = { \ |
| 106 | RK3328_CLKSEL1(_aclk_core, _pclk_dbg), \ |
| 107 | }, \ |
| 108 | } |
| 109 | |
| 110 | static struct rockchip_cpuclk_rate_table rk3328_cpuclk_rates[] __initdata = { |
| 111 | RK3328_CPUCLK_RATE(1800000000, 1, 7), |
| 112 | RK3328_CPUCLK_RATE(1704000000, 1, 7), |
| 113 | RK3328_CPUCLK_RATE(1608000000, 1, 7), |
| 114 | RK3328_CPUCLK_RATE(1512000000, 1, 7), |
| 115 | RK3328_CPUCLK_RATE(1488000000, 1, 5), |
| 116 | RK3328_CPUCLK_RATE(1416000000, 1, 5), |
| 117 | RK3328_CPUCLK_RATE(1392000000, 1, 5), |
| 118 | RK3328_CPUCLK_RATE(1296000000, 1, 5), |
| 119 | RK3328_CPUCLK_RATE(1200000000, 1, 5), |
| 120 | RK3328_CPUCLK_RATE(1104000000, 1, 5), |
| 121 | RK3328_CPUCLK_RATE(1008000000, 1, 5), |
| 122 | RK3328_CPUCLK_RATE(912000000, 1, 5), |
| 123 | RK3328_CPUCLK_RATE(816000000, 1, 3), |
| 124 | RK3328_CPUCLK_RATE(696000000, 1, 3), |
| 125 | RK3328_CPUCLK_RATE(600000000, 1, 3), |
| 126 | RK3328_CPUCLK_RATE(408000000, 1, 1), |
| 127 | RK3328_CPUCLK_RATE(312000000, 1, 1), |
| 128 | RK3328_CPUCLK_RATE(216000000, 1, 1), |
| 129 | RK3328_CPUCLK_RATE(96000000, 1, 1), |
| 130 | }; |
| 131 | |
| 132 | static const struct rockchip_cpuclk_reg_data rk3328_cpuclk_data = { |
| 133 | .core_reg = RK3328_CLKSEL_CON(0), |
| 134 | .div_core_shift = 0, |
| 135 | .div_core_mask = 0x1f, |
| 136 | .mux_core_alt = 1, |
| 137 | .mux_core_main = 3, |
| 138 | .mux_core_shift = 6, |
| 139 | .mux_core_mask = 0x3, |
| 140 | }; |
| 141 | |
| 142 | PNAME(mux_pll_p) = { "xin24m" }; |
| 143 | |
| 144 | PNAME(mux_2plls_p) = { "cpll", "gpll" }; |
| 145 | PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" }; |
| 146 | PNAME(mux_cpll_gpll_apll_p) = { "cpll", "gpll", "apll" }; |
| 147 | PNAME(mux_2plls_xin24m_p) = { "cpll", "gpll", "xin24m" }; |
| 148 | PNAME(mux_2plls_hdmiphy_p) = { "cpll", "gpll", |
| 149 | "dummy_hdmiphy" }; |
| 150 | PNAME(mux_4plls_p) = { "cpll", "gpll", |
| 151 | "dummy_hdmiphy", |
| 152 | "usb480m" }; |
| 153 | PNAME(mux_2plls_u480m_p) = { "cpll", "gpll", |
| 154 | "usb480m" }; |
| 155 | PNAME(mux_2plls_24m_u480m_p) = { "cpll", "gpll", |
| 156 | "xin24m", "usb480m" }; |
| 157 | |
| 158 | PNAME(mux_ddrphy_p) = { "dpll", "apll", "cpll" }; |
| 159 | PNAME(mux_armclk_p) = { "apll_core", |
| 160 | "gpll_core", |
| 161 | "dpll_core", |
| 162 | "npll_core"}; |
| 163 | PNAME(mux_hdmiphy_p) = { "hdmi_phy", "xin24m" }; |
| 164 | PNAME(mux_usb480m_p) = { "usb480m_phy", |
| 165 | "xin24m" }; |
| 166 | |
| 167 | PNAME(mux_i2s0_p) = { "clk_i2s0_div", |
| 168 | "clk_i2s0_frac", |
| 169 | "xin12m", |
| 170 | "xin12m" }; |
| 171 | PNAME(mux_i2s1_p) = { "clk_i2s1_div", |
| 172 | "clk_i2s1_frac", |
| 173 | "clkin_i2s1", |
| 174 | "xin12m" }; |
| 175 | PNAME(mux_i2s2_p) = { "clk_i2s2_div", |
| 176 | "clk_i2s2_frac", |
| 177 | "clkin_i2s2", |
| 178 | "xin12m" }; |
| 179 | PNAME(mux_i2s1out_p) = { "clk_i2s1", "xin12m"}; |
| 180 | PNAME(mux_i2s2out_p) = { "clk_i2s2", "xin12m" }; |
| 181 | PNAME(mux_spdif_p) = { "clk_spdif_div", |
| 182 | "clk_spdif_frac", |
| 183 | "xin12m", |
| 184 | "xin12m" }; |
| 185 | PNAME(mux_uart0_p) = { "clk_uart0_div", |
| 186 | "clk_uart0_frac", |
| 187 | "xin24m" }; |
| 188 | PNAME(mux_uart1_p) = { "clk_uart1_div", |
| 189 | "clk_uart1_frac", |
| 190 | "xin24m" }; |
| 191 | PNAME(mux_uart2_p) = { "clk_uart2_div", |
| 192 | "clk_uart2_frac", |
| 193 | "xin24m" }; |
| 194 | |
| 195 | PNAME(mux_sclk_cif_p) = { "clk_cif_src", |
| 196 | "xin24m" }; |
| 197 | PNAME(mux_dclk_lcdc_p) = { "hdmiphy", |
| 198 | "dclk_lcdc_src" }; |
| 199 | PNAME(mux_aclk_peri_pre_p) = { "cpll_peri", |
| 200 | "gpll_peri", |
| 201 | "hdmiphy_peri" }; |
| 202 | PNAME(mux_ref_usb3otg_src_p) = { "xin24m", |
| 203 | "clk_usb3otg_ref" }; |
| 204 | PNAME(mux_xin24m_32k_p) = { "xin24m", |
| 205 | "clk_rtc32k" }; |
| 206 | PNAME(mux_mac2io_src_p) = { "clk_mac2io_src", |
| 207 | "gmac_clkin" }; |
| 208 | PNAME(mux_mac2phy_src_p) = { "clk_mac2phy_src", |
| 209 | "phy_50m_out" }; |
Elaine Zhang | 9bb4db6 | 2017-02-06 10:50:35 +0800 | [diff] [blame] | 210 | PNAME(mux_mac2io_ext_p) = { "clk_mac2io", |
| 211 | "gmac_clkin" }; |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 212 | |
| 213 | static struct rockchip_pll_clock rk3328_pll_clks[] __initdata = { |
| 214 | [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, |
| 215 | 0, RK3328_PLL_CON(0), |
| 216 | RK3328_MODE_CON, 0, 4, 0, rk3328_pll_frac_rates), |
| 217 | [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, |
| 218 | 0, RK3328_PLL_CON(8), |
| 219 | RK3328_MODE_CON, 4, 3, 0, NULL), |
| 220 | [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, |
| 221 | 0, RK3328_PLL_CON(16), |
| 222 | RK3328_MODE_CON, 8, 2, 0, rk3328_pll_rates), |
| 223 | [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, |
| 224 | 0, RK3328_PLL_CON(24), |
| 225 | RK3328_MODE_CON, 12, 1, 0, rk3328_pll_frac_rates), |
| 226 | [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, |
| 227 | 0, RK3328_PLL_CON(40), |
| 228 | RK3328_MODE_CON, 1, 0, 0, rk3328_pll_rates), |
| 229 | }; |
| 230 | |
| 231 | #define MFLAGS CLK_MUX_HIWORD_MASK |
| 232 | #define DFLAGS CLK_DIVIDER_HIWORD_MASK |
| 233 | #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) |
| 234 | |
| 235 | static struct rockchip_clk_branch rk3328_i2s0_fracmux __initdata = |
| 236 | MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT, |
| 237 | RK3328_CLKSEL_CON(6), 8, 2, MFLAGS); |
| 238 | |
| 239 | static struct rockchip_clk_branch rk3328_i2s1_fracmux __initdata = |
| 240 | MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT, |
| 241 | RK3328_CLKSEL_CON(8), 8, 2, MFLAGS); |
| 242 | |
| 243 | static struct rockchip_clk_branch rk3328_i2s2_fracmux __initdata = |
| 244 | MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT, |
| 245 | RK3328_CLKSEL_CON(10), 8, 2, MFLAGS); |
| 246 | |
| 247 | static struct rockchip_clk_branch rk3328_spdif_fracmux __initdata = |
| 248 | MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, CLK_SET_RATE_PARENT, |
| 249 | RK3328_CLKSEL_CON(12), 8, 2, MFLAGS); |
| 250 | |
| 251 | static struct rockchip_clk_branch rk3328_uart0_fracmux __initdata = |
| 252 | MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, |
| 253 | RK3328_CLKSEL_CON(14), 8, 2, MFLAGS); |
| 254 | |
| 255 | static struct rockchip_clk_branch rk3328_uart1_fracmux __initdata = |
| 256 | MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, |
| 257 | RK3328_CLKSEL_CON(16), 8, 2, MFLAGS); |
| 258 | |
| 259 | static struct rockchip_clk_branch rk3328_uart2_fracmux __initdata = |
| 260 | MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, |
| 261 | RK3328_CLKSEL_CON(18), 8, 2, MFLAGS); |
| 262 | |
| 263 | static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { |
| 264 | /* |
| 265 | * Clock-Architecture Diagram 1 |
| 266 | */ |
| 267 | |
| 268 | DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, |
| 269 | RK3328_CLKSEL_CON(2), 8, 5, DFLAGS), |
| 270 | COMPOSITE(SCLK_RTC32K, "clk_rtc32k", mux_2plls_xin24m_p, 0, |
| 271 | RK3328_CLKSEL_CON(38), 14, 2, MFLAGS, 0, 14, DFLAGS, |
| 272 | RK3328_CLKGATE_CON(0), 11, GFLAGS), |
| 273 | |
| 274 | /* PD_MISC */ |
| 275 | MUX(HDMIPHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT, |
| 276 | RK3328_MISC_CON, 13, 1, MFLAGS), |
| 277 | MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, |
| 278 | RK3328_MISC_CON, 15, 1, MFLAGS), |
| 279 | |
| 280 | /* |
| 281 | * Clock-Architecture Diagram 2 |
| 282 | */ |
| 283 | |
| 284 | /* PD_CORE */ |
| 285 | GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, |
| 286 | RK3328_CLKGATE_CON(0), 0, GFLAGS), |
| 287 | GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, |
| 288 | RK3328_CLKGATE_CON(0), 2, GFLAGS), |
| 289 | GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, |
| 290 | RK3328_CLKGATE_CON(0), 1, GFLAGS), |
| 291 | GATE(0, "npll_core", "npll", CLK_IGNORE_UNUSED, |
| 292 | RK3328_CLKGATE_CON(0), 12, GFLAGS), |
| 293 | COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, |
| 294 | RK3328_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, |
| 295 | RK3328_CLKGATE_CON(7), 0, GFLAGS), |
| 296 | COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED, |
| 297 | RK3328_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, |
| 298 | RK3328_CLKGATE_CON(7), 1, GFLAGS), |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 299 | GATE(0, "aclk_core_niu", "aclk_core", 0, |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 300 | RK3328_CLKGATE_CON(13), 0, GFLAGS), |
| 301 | GATE(0, "aclk_gic400", "aclk_core", CLK_IGNORE_UNUSED, |
| 302 | RK3328_CLKGATE_CON(13), 1, GFLAGS), |
| 303 | |
| 304 | GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED, |
| 305 | RK3328_CLKGATE_CON(7), 2, GFLAGS), |
| 306 | |
| 307 | /* PD_GPU */ |
| 308 | COMPOSITE(0, "aclk_gpu_pre", mux_4plls_p, 0, |
| 309 | RK3328_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 310 | RK3328_CLKGATE_CON(6), 6, GFLAGS), |
| 311 | GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_SET_RATE_PARENT, |
| 312 | RK3328_CLKGATE_CON(14), 0, GFLAGS), |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 313 | GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 0, |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 314 | RK3328_CLKGATE_CON(14), 1, GFLAGS), |
| 315 | |
| 316 | /* PD_DDR */ |
| 317 | COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED, |
| 318 | RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, |
| 319 | RK3328_CLKGATE_CON(0), 4, GFLAGS), |
| 320 | GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED, |
| 321 | RK3328_CLKGATE_CON(18), 6, GFLAGS), |
| 322 | GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED, |
| 323 | RK3328_CLKGATE_CON(18), 5, GFLAGS), |
| 324 | GATE(0, "aclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED, |
| 325 | RK3328_CLKGATE_CON(18), 4, GFLAGS), |
| 326 | GATE(0, "clk_ddrmon", "xin24m", CLK_IGNORE_UNUSED, |
| 327 | RK3328_CLKGATE_CON(0), 6, GFLAGS), |
| 328 | |
| 329 | COMPOSITE(PCLK_DDR, "pclk_ddr", mux_2plls_hdmiphy_p, 0, |
| 330 | RK3328_CLKSEL_CON(4), 13, 2, MFLAGS, 8, 3, DFLAGS, |
| 331 | RK3328_CLKGATE_CON(7), 4, GFLAGS), |
| 332 | GATE(0, "pclk_ddrupctl", "pclk_ddr", CLK_IGNORE_UNUSED, |
| 333 | RK3328_CLKGATE_CON(18), 1, GFLAGS), |
| 334 | GATE(0, "pclk_ddr_msch", "pclk_ddr", CLK_IGNORE_UNUSED, |
| 335 | RK3328_CLKGATE_CON(18), 2, GFLAGS), |
| 336 | GATE(0, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED, |
| 337 | RK3328_CLKGATE_CON(18), 3, GFLAGS), |
| 338 | GATE(0, "pclk_ddrstdby", "pclk_ddr", CLK_IGNORE_UNUSED, |
| 339 | RK3328_CLKGATE_CON(18), 7, GFLAGS), |
| 340 | GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED, |
| 341 | RK3328_CLKGATE_CON(18), 9, GFLAGS), |
| 342 | |
| 343 | /* |
| 344 | * Clock-Architecture Diagram 3 |
| 345 | */ |
| 346 | |
| 347 | /* PD_BUS */ |
| 348 | COMPOSITE(ACLK_BUS_PRE, "aclk_bus_pre", mux_2plls_hdmiphy_p, 0, |
| 349 | RK3328_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS, |
| 350 | RK3328_CLKGATE_CON(8), 0, GFLAGS), |
| 351 | COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_pre", 0, |
| 352 | RK3328_CLKSEL_CON(1), 8, 2, DFLAGS, |
| 353 | RK3328_CLKGATE_CON(8), 1, GFLAGS), |
| 354 | COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", 0, |
| 355 | RK3328_CLKSEL_CON(1), 12, 3, DFLAGS, |
| 356 | RK3328_CLKGATE_CON(8), 2, GFLAGS), |
| 357 | GATE(0, "pclk_bus", "pclk_bus_pre", 0, |
| 358 | RK3328_CLKGATE_CON(8), 3, GFLAGS), |
| 359 | GATE(0, "pclk_phy_pre", "pclk_bus_pre", 0, |
| 360 | RK3328_CLKGATE_CON(8), 4, GFLAGS), |
| 361 | |
| 362 | COMPOSITE(SCLK_TSP, "clk_tsp", mux_2plls_p, 0, |
| 363 | RK3328_CLKSEL_CON(21), 15, 1, MFLAGS, 8, 5, DFLAGS, |
| 364 | RK3328_CLKGATE_CON(2), 5, GFLAGS), |
| 365 | GATE(0, "clk_hsadc_tsp", "ext_gpio3a2", 0, |
| 366 | RK3328_CLKGATE_CON(17), 13, GFLAGS), |
| 367 | |
| 368 | /* PD_I2S */ |
| 369 | COMPOSITE(0, "clk_i2s0_div", mux_2plls_p, 0, |
| 370 | RK3328_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS, |
| 371 | RK3328_CLKGATE_CON(1), 1, GFLAGS), |
| 372 | COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT, |
| 373 | RK3328_CLKSEL_CON(7), 0, |
| 374 | RK3328_CLKGATE_CON(1), 2, GFLAGS, |
| 375 | &rk3328_i2s0_fracmux), |
| 376 | GATE(SCLK_I2S0, "clk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT, |
| 377 | RK3328_CLKGATE_CON(1), 3, GFLAGS), |
| 378 | |
| 379 | COMPOSITE(0, "clk_i2s1_div", mux_2plls_p, 0, |
| 380 | RK3328_CLKSEL_CON(8), 15, 1, MFLAGS, 0, 7, DFLAGS, |
| 381 | RK3328_CLKGATE_CON(1), 4, GFLAGS), |
| 382 | COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT, |
| 383 | RK3328_CLKSEL_CON(9), 0, |
| 384 | RK3328_CLKGATE_CON(1), 5, GFLAGS, |
| 385 | &rk3328_i2s1_fracmux), |
| 386 | GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT, |
Katsuhiro Suzuki | 5c73ac2 | 2018-11-18 13:16:12 +0900 | [diff] [blame] | 387 | RK3328_CLKGATE_CON(1), 6, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 388 | COMPOSITE_NODIV(SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_p, 0, |
| 389 | RK3328_CLKSEL_CON(8), 12, 1, MFLAGS, |
| 390 | RK3328_CLKGATE_CON(1), 7, GFLAGS), |
| 391 | |
| 392 | COMPOSITE(0, "clk_i2s2_div", mux_2plls_p, 0, |
| 393 | RK3328_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 7, DFLAGS, |
| 394 | RK3328_CLKGATE_CON(1), 8, GFLAGS), |
| 395 | COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT, |
| 396 | RK3328_CLKSEL_CON(11), 0, |
| 397 | RK3328_CLKGATE_CON(1), 9, GFLAGS, |
| 398 | &rk3328_i2s2_fracmux), |
| 399 | GATE(SCLK_I2S2, "clk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT, |
| 400 | RK3328_CLKGATE_CON(1), 10, GFLAGS), |
| 401 | COMPOSITE_NODIV(SCLK_I2S2_OUT, "i2s2_out", mux_i2s2out_p, 0, |
| 402 | RK3328_CLKSEL_CON(10), 12, 1, MFLAGS, |
| 403 | RK3328_CLKGATE_CON(1), 11, GFLAGS), |
| 404 | |
| 405 | COMPOSITE(0, "clk_spdif_div", mux_2plls_p, 0, |
| 406 | RK3328_CLKSEL_CON(12), 15, 1, MFLAGS, 0, 7, DFLAGS, |
| 407 | RK3328_CLKGATE_CON(1), 12, GFLAGS), |
| 408 | COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT, |
| 409 | RK3328_CLKSEL_CON(13), 0, |
| 410 | RK3328_CLKGATE_CON(1), 13, GFLAGS, |
| 411 | &rk3328_spdif_fracmux), |
| 412 | |
| 413 | /* PD_UART */ |
| 414 | COMPOSITE(0, "clk_uart0_div", mux_2plls_u480m_p, 0, |
| 415 | RK3328_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS, |
| 416 | RK3328_CLKGATE_CON(1), 14, GFLAGS), |
| 417 | COMPOSITE(0, "clk_uart1_div", mux_2plls_u480m_p, 0, |
| 418 | RK3328_CLKSEL_CON(16), 12, 2, MFLAGS, 0, 7, DFLAGS, |
| 419 | RK3328_CLKGATE_CON(2), 0, GFLAGS), |
| 420 | COMPOSITE(0, "clk_uart2_div", mux_2plls_u480m_p, 0, |
| 421 | RK3328_CLKSEL_CON(18), 12, 2, MFLAGS, 0, 7, DFLAGS, |
| 422 | RK3328_CLKGATE_CON(2), 2, GFLAGS), |
| 423 | COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT, |
| 424 | RK3328_CLKSEL_CON(15), 0, |
| 425 | RK3328_CLKGATE_CON(1), 15, GFLAGS, |
| 426 | &rk3328_uart0_fracmux), |
| 427 | COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT, |
| 428 | RK3328_CLKSEL_CON(17), 0, |
| 429 | RK3328_CLKGATE_CON(2), 1, GFLAGS, |
| 430 | &rk3328_uart1_fracmux), |
| 431 | COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT, |
| 432 | RK3328_CLKSEL_CON(19), 0, |
| 433 | RK3328_CLKGATE_CON(2), 3, GFLAGS, |
| 434 | &rk3328_uart2_fracmux), |
| 435 | |
| 436 | /* |
| 437 | * Clock-Architecture Diagram 4 |
| 438 | */ |
| 439 | |
| 440 | COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_2plls_p, 0, |
| 441 | RK3328_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 7, DFLAGS, |
| 442 | RK3328_CLKGATE_CON(2), 9, GFLAGS), |
| 443 | COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_2plls_p, 0, |
| 444 | RK3328_CLKSEL_CON(34), 15, 1, MFLAGS, 8, 7, DFLAGS, |
| 445 | RK3328_CLKGATE_CON(2), 10, GFLAGS), |
| 446 | COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_2plls_p, 0, |
| 447 | RK3328_CLKSEL_CON(35), 7, 1, MFLAGS, 0, 7, DFLAGS, |
| 448 | RK3328_CLKGATE_CON(2), 11, GFLAGS), |
| 449 | COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_2plls_p, 0, |
| 450 | RK3328_CLKSEL_CON(35), 15, 1, MFLAGS, 8, 7, DFLAGS, |
| 451 | RK3328_CLKGATE_CON(2), 12, GFLAGS), |
| 452 | COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_2plls_p, 0, |
Jonas Karlman | fb90339 | 2019-03-10 12:00:45 +0000 | [diff] [blame] | 453 | RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS, |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 454 | RK3328_CLKGATE_CON(2), 4, GFLAGS), |
| 455 | COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "clk_24m", 0, |
| 456 | RK3328_CLKSEL_CON(22), 0, 10, DFLAGS, |
| 457 | RK3328_CLKGATE_CON(2), 6, GFLAGS), |
| 458 | COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "clk_24m", 0, |
| 459 | RK3328_CLKSEL_CON(23), 0, 10, DFLAGS, |
| 460 | RK3328_CLKGATE_CON(2), 14, GFLAGS), |
| 461 | COMPOSITE(SCLK_SPI, "clk_spi", mux_2plls_p, 0, |
| 462 | RK3328_CLKSEL_CON(24), 7, 1, MFLAGS, 0, 7, DFLAGS, |
| 463 | RK3328_CLKGATE_CON(2), 7, GFLAGS), |
| 464 | COMPOSITE(SCLK_PWM, "clk_pwm", mux_2plls_p, 0, |
| 465 | RK3328_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 7, DFLAGS, |
| 466 | RK3328_CLKGATE_CON(2), 8, GFLAGS), |
| 467 | COMPOSITE(SCLK_OTP, "clk_otp", mux_2plls_xin24m_p, 0, |
| 468 | RK3328_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 6, DFLAGS, |
| 469 | RK3328_CLKGATE_CON(3), 8, GFLAGS), |
| 470 | COMPOSITE(SCLK_EFUSE, "clk_efuse", mux_2plls_xin24m_p, 0, |
| 471 | RK3328_CLKSEL_CON(5), 14, 2, MFLAGS, 8, 5, DFLAGS, |
| 472 | RK3328_CLKGATE_CON(2), 13, GFLAGS), |
| 473 | COMPOSITE(SCLK_PDM, "clk_pdm", mux_cpll_gpll_apll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, |
| 474 | RK3328_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS, |
| 475 | RK3328_CLKGATE_CON(2), 15, GFLAGS), |
| 476 | |
| 477 | GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, |
| 478 | RK3328_CLKGATE_CON(8), 5, GFLAGS), |
| 479 | GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, |
| 480 | RK3328_CLKGATE_CON(8), 6, GFLAGS), |
| 481 | GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, |
| 482 | RK3328_CLKGATE_CON(8), 7, GFLAGS), |
| 483 | GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, |
| 484 | RK3328_CLKGATE_CON(8), 8, GFLAGS), |
| 485 | GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, |
| 486 | RK3328_CLKGATE_CON(8), 9, GFLAGS), |
| 487 | GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, |
| 488 | RK3328_CLKGATE_CON(8), 10, GFLAGS), |
| 489 | |
| 490 | COMPOSITE(SCLK_WIFI, "clk_wifi", mux_2plls_u480m_p, 0, |
| 491 | RK3328_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 6, DFLAGS, |
| 492 | RK3328_CLKGATE_CON(0), 10, GFLAGS), |
| 493 | |
| 494 | /* |
| 495 | * Clock-Architecture Diagram 5 |
| 496 | */ |
| 497 | |
| 498 | /* PD_VIDEO */ |
| 499 | COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_4plls_p, 0, |
| 500 | RK3328_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 501 | RK3328_CLKGATE_CON(6), 0, GFLAGS), |
| 502 | FACTOR_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4, |
| 503 | RK3328_CLKGATE_CON(11), 0, GFLAGS), |
| 504 | GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", CLK_SET_RATE_PARENT, |
| 505 | RK3328_CLKGATE_CON(24), 0, GFLAGS), |
| 506 | GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", CLK_SET_RATE_PARENT, |
| 507 | RK3328_CLKGATE_CON(24), 1, GFLAGS), |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 508 | GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", 0, |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 509 | RK3328_CLKGATE_CON(24), 2, GFLAGS), |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 510 | GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", 0, |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 511 | RK3328_CLKGATE_CON(24), 3, GFLAGS), |
| 512 | |
| 513 | COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_4plls_p, 0, |
| 514 | RK3328_CLKSEL_CON(48), 14, 2, MFLAGS, 8, 5, DFLAGS, |
| 515 | RK3328_CLKGATE_CON(6), 1, GFLAGS), |
| 516 | |
| 517 | COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_4plls_p, 0, |
| 518 | RK3328_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 519 | RK3328_CLKGATE_CON(6), 2, GFLAGS), |
| 520 | |
| 521 | COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_4plls_p, 0, |
| 522 | RK3328_CLKSEL_CON(50), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 523 | RK3328_CLKGATE_CON(6), 5, GFLAGS), |
| 524 | FACTOR_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4, |
| 525 | RK3328_CLKGATE_CON(11), 8, GFLAGS), |
| 526 | GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", CLK_SET_RATE_PARENT, |
| 527 | RK3328_CLKGATE_CON(23), 0, GFLAGS), |
| 528 | GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", CLK_SET_RATE_PARENT, |
| 529 | RK3328_CLKGATE_CON(23), 1, GFLAGS), |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 530 | GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", 0, |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 531 | RK3328_CLKGATE_CON(23), 2, GFLAGS), |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 532 | GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", 0, |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 533 | RK3328_CLKGATE_CON(23), 3, GFLAGS), |
| 534 | |
| 535 | COMPOSITE(ACLK_RKVENC, "aclk_rkvenc", mux_4plls_p, 0, |
| 536 | RK3328_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 537 | RK3328_CLKGATE_CON(6), 3, GFLAGS), |
| 538 | FACTOR_GATE(HCLK_RKVENC, "hclk_rkvenc", "aclk_rkvenc", 0, 1, 4, |
| 539 | RK3328_CLKGATE_CON(11), 4, GFLAGS), |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 540 | GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", 0, |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 541 | RK3328_CLKGATE_CON(25), 0, GFLAGS), |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 542 | GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0, |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 543 | RK3328_CLKGATE_CON(25), 1, GFLAGS), |
| 544 | GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0, |
Jonas Karlman | fb90339 | 2019-03-10 12:00:45 +0000 | [diff] [blame] | 545 | RK3328_CLKGATE_CON(25), 2, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 546 | GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0, |
Jonas Karlman | fb90339 | 2019-03-10 12:00:45 +0000 | [diff] [blame] | 547 | RK3328_CLKGATE_CON(25), 3, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 548 | GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0, |
Jonas Karlman | fb90339 | 2019-03-10 12:00:45 +0000 | [diff] [blame] | 549 | RK3328_CLKGATE_CON(25), 4, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 550 | GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0, |
Jonas Karlman | fb90339 | 2019-03-10 12:00:45 +0000 | [diff] [blame] | 551 | RK3328_CLKGATE_CON(25), 5, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 552 | GATE(ACLK_AXISRAM, "aclk_axisram", "aclk_rkvenc", CLK_IGNORE_UNUSED, |
Jonas Karlman | fb90339 | 2019-03-10 12:00:45 +0000 | [diff] [blame] | 553 | RK3328_CLKGATE_CON(25), 6, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 554 | |
| 555 | COMPOSITE(SCLK_VENC_CORE, "sclk_venc_core", mux_4plls_p, 0, |
| 556 | RK3328_CLKSEL_CON(51), 14, 2, MFLAGS, 8, 5, DFLAGS, |
| 557 | RK3328_CLKGATE_CON(6), 4, GFLAGS), |
| 558 | |
| 559 | COMPOSITE(SCLK_VENC_DSP, "sclk_venc_dsp", mux_4plls_p, 0, |
| 560 | RK3328_CLKSEL_CON(52), 14, 2, MFLAGS, 8, 5, DFLAGS, |
| 561 | RK3328_CLKGATE_CON(6), 7, GFLAGS), |
| 562 | |
| 563 | /* |
| 564 | * Clock-Architecture Diagram 6 |
| 565 | */ |
| 566 | |
| 567 | /* PD_VIO */ |
| 568 | COMPOSITE(ACLK_VIO_PRE, "aclk_vio_pre", mux_4plls_p, 0, |
| 569 | RK3328_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 570 | RK3328_CLKGATE_CON(5), 2, GFLAGS), |
| 571 | DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_vio_pre", 0, |
| 572 | RK3328_CLKSEL_CON(37), 8, 5, DFLAGS), |
| 573 | |
| 574 | COMPOSITE(ACLK_RGA_PRE, "aclk_rga_pre", mux_4plls_p, 0, |
| 575 | RK3328_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS, |
| 576 | RK3328_CLKGATE_CON(5), 0, GFLAGS), |
| 577 | COMPOSITE(SCLK_RGA, "clk_rga", mux_4plls_p, 0, |
| 578 | RK3328_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 579 | RK3328_CLKGATE_CON(5), 1, GFLAGS), |
| 580 | COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_4plls_p, 0, |
| 581 | RK3328_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 582 | RK3328_CLKGATE_CON(5), 5, GFLAGS), |
Heiko Stuebner | 1d33442 | 2017-12-11 01:11:14 +0100 | [diff] [blame] | 583 | GATE(SCLK_HDMI_SFC, "sclk_hdmi_sfc", "xin24m", 0, |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 584 | RK3328_CLKGATE_CON(5), 4, GFLAGS), |
| 585 | |
| 586 | COMPOSITE_NODIV(0, "clk_cif_src", mux_2plls_p, 0, |
| 587 | RK3328_CLKSEL_CON(42), 7, 1, MFLAGS, |
| 588 | RK3328_CLKGATE_CON(5), 3, GFLAGS), |
| 589 | COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cif_out", mux_sclk_cif_p, CLK_SET_RATE_PARENT, |
| 590 | RK3328_CLKSEL_CON(42), 5, 1, MFLAGS, 0, 5, DFLAGS), |
| 591 | |
| 592 | COMPOSITE(DCLK_LCDC_SRC, "dclk_lcdc_src", mux_gpll_cpll_p, 0, |
| 593 | RK3328_CLKSEL_CON(40), 0, 1, MFLAGS, 8, 8, DFLAGS, |
| 594 | RK3328_CLKGATE_CON(5), 6, GFLAGS), |
| 595 | DIV(DCLK_HDMIPHY, "dclk_hdmiphy", "dclk_lcdc_src", 0, |
| 596 | RK3328_CLKSEL_CON(40), 3, 3, DFLAGS), |
Zheng Yang | 36ec036 | 2017-05-25 18:00:24 +0800 | [diff] [blame] | 597 | MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 598 | RK3328_CLKSEL_CON(40), 1, 1, MFLAGS), |
| 599 | |
| 600 | /* |
| 601 | * Clock-Architecture Diagram 7 |
| 602 | */ |
| 603 | |
| 604 | /* PD_PERI */ |
| 605 | GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED, |
| 606 | RK3328_CLKGATE_CON(4), 0, GFLAGS), |
| 607 | GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED, |
| 608 | RK3328_CLKGATE_CON(4), 1, GFLAGS), |
| 609 | GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED, |
| 610 | RK3328_CLKGATE_CON(4), 2, GFLAGS), |
| 611 | COMPOSITE_NOGATE(ACLK_PERI_PRE, "aclk_peri_pre", mux_aclk_peri_pre_p, 0, |
| 612 | RK3328_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS), |
| 613 | COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED, |
| 614 | RK3328_CLKSEL_CON(29), 0, 2, DFLAGS, |
| 615 | RK3328_CLKGATE_CON(10), 2, GFLAGS), |
| 616 | COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED, |
| 617 | RK3328_CLKSEL_CON(29), 4, 3, DFLAGS, |
| 618 | RK3328_CLKGATE_CON(10), 1, GFLAGS), |
| 619 | GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, |
| 620 | RK3328_CLKGATE_CON(10), 0, GFLAGS), |
| 621 | |
| 622 | COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_2plls_24m_u480m_p, 0, |
| 623 | RK3328_CLKSEL_CON(30), 8, 2, MFLAGS, 0, 8, DFLAGS, |
| 624 | RK3328_CLKGATE_CON(4), 3, GFLAGS), |
| 625 | |
| 626 | COMPOSITE(SCLK_SDIO, "clk_sdio", mux_2plls_24m_u480m_p, 0, |
| 627 | RK3328_CLKSEL_CON(31), 8, 2, MFLAGS, 0, 8, DFLAGS, |
| 628 | RK3328_CLKGATE_CON(4), 4, GFLAGS), |
| 629 | |
| 630 | COMPOSITE(SCLK_EMMC, "clk_emmc", mux_2plls_24m_u480m_p, 0, |
| 631 | RK3328_CLKSEL_CON(32), 8, 2, MFLAGS, 0, 8, DFLAGS, |
| 632 | RK3328_CLKGATE_CON(4), 5, GFLAGS), |
| 633 | |
| 634 | COMPOSITE(SCLK_SDMMC_EXT, "clk_sdmmc_ext", mux_2plls_24m_u480m_p, 0, |
| 635 | RK3328_CLKSEL_CON(43), 8, 2, MFLAGS, 0, 8, DFLAGS, |
| 636 | RK3328_CLKGATE_CON(4), 10, GFLAGS), |
| 637 | |
| 638 | COMPOSITE(SCLK_REF_USB3OTG_SRC, "clk_ref_usb3otg_src", mux_2plls_p, 0, |
| 639 | RK3328_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 7, DFLAGS, |
| 640 | RK3328_CLKGATE_CON(4), 9, GFLAGS), |
| 641 | |
| 642 | MUX(SCLK_REF_USB3OTG, "clk_ref_usb3otg", mux_ref_usb3otg_src_p, CLK_SET_RATE_PARENT, |
| 643 | RK3328_CLKSEL_CON(45), 8, 1, MFLAGS), |
| 644 | |
| 645 | GATE(SCLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0, |
| 646 | RK3328_CLKGATE_CON(4), 7, GFLAGS), |
| 647 | |
| 648 | COMPOSITE(SCLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", mux_xin24m_32k_p, 0, |
| 649 | RK3328_CLKSEL_CON(33), 15, 1, MFLAGS, 0, 10, DFLAGS, |
| 650 | RK3328_CLKGATE_CON(4), 8, GFLAGS), |
| 651 | |
| 652 | /* |
| 653 | * Clock-Architecture Diagram 8 |
| 654 | */ |
| 655 | |
| 656 | /* PD_GMAC */ |
| 657 | COMPOSITE(ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_p, 0, |
Jonas Karlman | fb90339 | 2019-03-10 12:00:45 +0000 | [diff] [blame] | 658 | RK3328_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS, |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 659 | RK3328_CLKGATE_CON(3), 2, GFLAGS), |
| 660 | COMPOSITE_NOMUX(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0, |
| 661 | RK3328_CLKSEL_CON(25), 8, 3, DFLAGS, |
| 662 | RK3328_CLKGATE_CON(9), 0, GFLAGS), |
| 663 | |
| 664 | COMPOSITE(SCLK_MAC2IO_SRC, "clk_mac2io_src", mux_2plls_p, 0, |
| 665 | RK3328_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 5, DFLAGS, |
| 666 | RK3328_CLKGATE_CON(3), 1, GFLAGS), |
| 667 | GATE(SCLK_MAC2IO_REF, "clk_mac2io_ref", "clk_mac2io", 0, |
| 668 | RK3328_CLKGATE_CON(9), 7, GFLAGS), |
| 669 | GATE(SCLK_MAC2IO_RX, "clk_mac2io_rx", "clk_mac2io", 0, |
| 670 | RK3328_CLKGATE_CON(9), 4, GFLAGS), |
| 671 | GATE(SCLK_MAC2IO_TX, "clk_mac2io_tx", "clk_mac2io", 0, |
| 672 | RK3328_CLKGATE_CON(9), 5, GFLAGS), |
| 673 | GATE(SCLK_MAC2IO_REFOUT, "clk_mac2io_refout", "clk_mac2io", 0, |
| 674 | RK3328_CLKGATE_CON(9), 6, GFLAGS), |
| 675 | COMPOSITE(SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_p, 0, |
| 676 | RK3328_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 5, DFLAGS, |
| 677 | RK3328_CLKGATE_CON(3), 5, GFLAGS), |
Elaine Zhang | 9bb4db6 | 2017-02-06 10:50:35 +0800 | [diff] [blame] | 678 | MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_p, CLK_SET_RATE_NO_REPARENT, |
| 679 | RK3328_GRF_MAC_CON1, 10, 1, MFLAGS), |
| 680 | MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, CLK_SET_RATE_NO_REPARENT, |
| 681 | RK3328_GRF_SOC_CON4, 14, 1, MFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 682 | |
| 683 | COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0, |
| 684 | RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS, |
| 685 | RK3328_CLKGATE_CON(3), 0, GFLAGS), |
| 686 | GATE(SCLK_MAC2PHY_REF, "clk_mac2phy_ref", "clk_mac2phy", 0, |
| 687 | RK3328_CLKGATE_CON(9), 3, GFLAGS), |
| 688 | GATE(SCLK_MAC2PHY_RXTX, "clk_mac2phy_rxtx", "clk_mac2phy", 0, |
| 689 | RK3328_CLKGATE_CON(9), 1, GFLAGS), |
| 690 | COMPOSITE_NOMUX(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy", 0, |
| 691 | RK3328_CLKSEL_CON(26), 8, 2, DFLAGS, |
| 692 | RK3328_CLKGATE_CON(9), 2, GFLAGS), |
Elaine Zhang | 9bb4db6 | 2017-02-06 10:50:35 +0800 | [diff] [blame] | 693 | MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_src_p, CLK_SET_RATE_NO_REPARENT, |
| 694 | RK3328_GRF_MAC_CON2, 10, 1, MFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 695 | |
| 696 | FACTOR(0, "xin12m", "xin24m", 0, 1, 2), |
| 697 | |
| 698 | /* |
| 699 | * Clock-Architecture Diagram 9 |
| 700 | */ |
| 701 | |
| 702 | /* PD_VOP */ |
| 703 | GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(21), 10, GFLAGS), |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 704 | GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(22), 3, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 705 | GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 2, GFLAGS), |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 706 | GATE(0, "aclk_vop_niu", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 4, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 707 | |
| 708 | GATE(ACLK_IEP, "aclk_iep", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 6, GFLAGS), |
| 709 | GATE(ACLK_CIF, "aclk_cif", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 8, GFLAGS), |
| 710 | GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 15, GFLAGS), |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 711 | GATE(0, "aclk_vio_niu", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 2, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 712 | |
| 713 | GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 3, GFLAGS), |
| 714 | GATE(0, "hclk_vop_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 5, GFLAGS), |
| 715 | GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 7, GFLAGS), |
| 716 | GATE(HCLK_CIF, "hclk_cif", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 9, GFLAGS), |
| 717 | GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 11, GFLAGS), |
| 718 | GATE(0, "hclk_ahb1tom", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 12, GFLAGS), |
Heiko Stuebner | 7f872cb | 2017-12-23 16:30:19 +0100 | [diff] [blame] | 719 | GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 13, GFLAGS), |
| 720 | GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 14, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 721 | GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 0, GFLAGS), |
Heiko Stuebner | a377f68 | 2017-12-10 20:03:19 +0100 | [diff] [blame] | 722 | GATE(0, "hclk_vio_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 1, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 723 | GATE(PCLK_HDMI, "pclk_hdmi", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 4, GFLAGS), |
| 724 | GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 5, GFLAGS), |
| 725 | |
| 726 | /* PD_PERI */ |
| 727 | GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 11, GFLAGS), |
Jonas Karlman | fb90339 | 2019-03-10 12:00:45 +0000 | [diff] [blame] | 728 | GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 14, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 729 | |
| 730 | GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS), |
| 731 | GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 1, GFLAGS), |
| 732 | GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 2, GFLAGS), |
| 733 | GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 15, GFLAGS), |
| 734 | GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 6, GFLAGS), |
| 735 | GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 7, GFLAGS), |
| 736 | GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 8, GFLAGS), |
| 737 | GATE(HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 9, GFLAGS), |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 738 | GATE(0, "hclk_peri_niu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 12, GFLAGS), |
| 739 | GATE(0, "pclk_peri_niu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 13, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 740 | |
| 741 | /* PD_GMAC */ |
| 742 | GATE(ACLK_MAC2PHY, "aclk_mac2phy", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 0, GFLAGS), |
| 743 | GATE(ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 2, GFLAGS), |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 744 | GATE(0, "aclk_gmac_niu", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 4, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 745 | GATE(PCLK_MAC2PHY, "pclk_mac2phy", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 1, GFLAGS), |
| 746 | GATE(PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 3, GFLAGS), |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 747 | GATE(0, "pclk_gmac_niu", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 5, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 748 | |
| 749 | /* PD_BUS */ |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 750 | GATE(0, "aclk_bus_niu", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 12, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 751 | GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 11, GFLAGS), |
| 752 | GATE(ACLK_TSP, "aclk_tsp", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 12, GFLAGS), |
| 753 | GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 0, GFLAGS), |
| 754 | GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 1, GFLAGS), |
| 755 | |
| 756 | GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 2, GFLAGS), |
| 757 | GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 3, GFLAGS), |
| 758 | GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 4, GFLAGS), |
| 759 | GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 5, GFLAGS), |
| 760 | GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 6, GFLAGS), |
| 761 | GATE(HCLK_TSP, "hclk_tsp", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 11, GFLAGS), |
| 762 | GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 7, GFLAGS), |
| 763 | GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 8, GFLAGS), |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 764 | GATE(0, "hclk_bus_niu", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 13, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 765 | GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(28), 0, GFLAGS), |
| 766 | |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 767 | GATE(0, "pclk_bus_niu", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 14, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 768 | GATE(0, "pclk_efuse", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 9, GFLAGS), |
| 769 | GATE(0, "pclk_otp", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 4, GFLAGS), |
| 770 | GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 10, GFLAGS), |
| 771 | GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 0, GFLAGS), |
| 772 | GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 1, GFLAGS), |
| 773 | GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 2, GFLAGS), |
| 774 | GATE(PCLK_TIMER, "pclk_timer0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 3, GFLAGS), |
| 775 | GATE(0, "pclk_stimer", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 4, GFLAGS), |
| 776 | GATE(PCLK_SPI, "pclk_spi", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 5, GFLAGS), |
| 777 | GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 6, GFLAGS), |
| 778 | GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 7, GFLAGS), |
| 779 | GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 8, GFLAGS), |
| 780 | GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 9, GFLAGS), |
| 781 | GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 10, GFLAGS), |
| 782 | GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 11, GFLAGS), |
| 783 | GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 12, GFLAGS), |
| 784 | GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 13, GFLAGS), |
| 785 | GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 14, GFLAGS), |
| 786 | GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 15, GFLAGS), |
| 787 | GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 0, GFLAGS), |
| 788 | GATE(0, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 4, GFLAGS), |
| 789 | GATE(0, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 6, GFLAGS), |
| 790 | GATE(0, "pclk_sim", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 10, GFLAGS), |
| 791 | GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3328_CLKGATE_CON(17), 15, GFLAGS), |
| 792 | GATE(0, "pclk_pmu", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 3, GFLAGS), |
| 793 | |
| 794 | GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 1, GFLAGS), |
| 795 | GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 2, GFLAGS), |
| 796 | GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 2, GFLAGS), |
| 797 | GATE(PCLK_USB2_GRF, "pclk_usb2_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 14, GFLAGS), |
| 798 | GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 13, GFLAGS), |
Katsuhiro Suzuki | d061824 | 2018-11-26 02:56:03 +0900 | [diff] [blame] | 799 | GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(17), 5, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 800 | GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 7, GFLAGS), |
| 801 | GATE(0, "pclk_vdacphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 8, GFLAGS), |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 802 | GATE(0, "pclk_phy_niu", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(15), 15, GFLAGS), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 803 | |
| 804 | /* PD_MMC */ |
Shawn Lin | ce84eca | 2018-03-21 10:39:18 +0800 | [diff] [blame] | 805 | MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 806 | RK3328_SDMMC_CON0, 1), |
Shawn Lin | ce84eca | 2018-03-21 10:39:18 +0800 | [diff] [blame] | 807 | MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", |
Ziyuan Xu | 82f4b67 | 2018-10-11 15:26:43 +0800 | [diff] [blame] | 808 | RK3328_SDMMC_CON1, 0), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 809 | |
Shawn Lin | ce84eca | 2018-03-21 10:39:18 +0800 | [diff] [blame] | 810 | MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 811 | RK3328_SDIO_CON0, 1), |
Shawn Lin | ce84eca | 2018-03-21 10:39:18 +0800 | [diff] [blame] | 812 | MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", |
Ziyuan Xu | 82f4b67 | 2018-10-11 15:26:43 +0800 | [diff] [blame] | 813 | RK3328_SDIO_CON1, 0), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 814 | |
Shawn Lin | ce84eca | 2018-03-21 10:39:18 +0800 | [diff] [blame] | 815 | MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 816 | RK3328_EMMC_CON0, 1), |
Shawn Lin | ce84eca | 2018-03-21 10:39:18 +0800 | [diff] [blame] | 817 | MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", |
Ziyuan Xu | 82f4b67 | 2018-10-11 15:26:43 +0800 | [diff] [blame] | 818 | RK3328_EMMC_CON1, 0), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 819 | |
Shawn Lin | ce84eca | 2018-03-21 10:39:18 +0800 | [diff] [blame] | 820 | MMC(SCLK_SDMMC_EXT_DRV, "sdmmc_ext_drv", "clk_sdmmc_ext", |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 821 | RK3328_SDMMC_EXT_CON0, 1), |
Shawn Lin | ce84eca | 2018-03-21 10:39:18 +0800 | [diff] [blame] | 822 | MMC(SCLK_SDMMC_EXT_SAMPLE, "sdmmc_ext_sample", "clk_sdmmc_ext", |
Ziyuan Xu | 82f4b67 | 2018-10-11 15:26:43 +0800 | [diff] [blame] | 823 | RK3328_SDMMC_EXT_CON1, 0), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 824 | }; |
| 825 | |
| 826 | static const char *const rk3328_critical_clocks[] __initconst = { |
| 827 | "aclk_bus", |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 828 | "aclk_bus_niu", |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 829 | "pclk_bus", |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 830 | "pclk_bus_niu", |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 831 | "hclk_bus", |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 832 | "hclk_bus_niu", |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 833 | "aclk_peri", |
| 834 | "hclk_peri", |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 835 | "hclk_peri_niu", |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 836 | "pclk_peri", |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 837 | "pclk_peri_niu", |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 838 | "pclk_dbg", |
| 839 | "aclk_core_niu", |
| 840 | "aclk_gic400", |
| 841 | "aclk_intmem", |
| 842 | "hclk_rom", |
| 843 | "pclk_grf", |
| 844 | "pclk_cru", |
| 845 | "pclk_sgrf", |
| 846 | "pclk_timer0", |
| 847 | "clk_timer0", |
| 848 | "pclk_ddr_msch", |
| 849 | "pclk_ddr_mon", |
| 850 | "pclk_ddr_grf", |
| 851 | "clk_ddrupctl", |
| 852 | "clk_ddrmsch", |
| 853 | "hclk_ahb1tom", |
| 854 | "clk_jtag", |
| 855 | "pclk_ddrphy", |
| 856 | "pclk_pmu", |
| 857 | "hclk_otg_pmu", |
| 858 | "aclk_rga_niu", |
| 859 | "pclk_vio_h2p", |
| 860 | "hclk_vio_h2p", |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 861 | "aclk_vio_niu", |
Heiko Stuebner | a377f68 | 2017-12-10 20:03:19 +0100 | [diff] [blame] | 862 | "hclk_vio_niu", |
Heiko Stuebner | 51a70db | 2017-12-12 22:49:11 +0100 | [diff] [blame] | 863 | "aclk_vop_niu", |
| 864 | "hclk_vop_niu", |
| 865 | "aclk_gpu_niu", |
| 866 | "aclk_rkvdec_niu", |
| 867 | "hclk_rkvdec_niu", |
| 868 | "aclk_vpu_niu", |
| 869 | "hclk_vpu_niu", |
| 870 | "aclk_rkvenc_niu", |
| 871 | "hclk_rkvenc_niu", |
| 872 | "aclk_gmac_niu", |
| 873 | "pclk_gmac_niu", |
| 874 | "pclk_phy_niu", |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 875 | }; |
| 876 | |
| 877 | static void __init rk3328_clk_init(struct device_node *np) |
| 878 | { |
| 879 | struct rockchip_clk_provider *ctx; |
| 880 | void __iomem *reg_base; |
| 881 | |
| 882 | reg_base = of_iomap(np, 0); |
| 883 | if (!reg_base) { |
| 884 | pr_err("%s: could not map cru region\n", __func__); |
| 885 | return; |
| 886 | } |
| 887 | |
| 888 | ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); |
| 889 | if (IS_ERR(ctx)) { |
| 890 | pr_err("%s: rockchip clk init failed\n", __func__); |
| 891 | iounmap(reg_base); |
| 892 | return; |
| 893 | } |
| 894 | |
| 895 | rockchip_clk_register_plls(ctx, rk3328_pll_clks, |
| 896 | ARRAY_SIZE(rk3328_pll_clks), |
| 897 | RK3328_GRF_SOC_STATUS0); |
| 898 | rockchip_clk_register_branches(ctx, rk3328_clk_branches, |
| 899 | ARRAY_SIZE(rk3328_clk_branches)); |
| 900 | rockchip_clk_protect_critical(rk3328_critical_clocks, |
| 901 | ARRAY_SIZE(rk3328_critical_clocks)); |
| 902 | |
| 903 | rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", |
| 904 | mux_armclk_p, ARRAY_SIZE(mux_armclk_p), |
| 905 | &rk3328_cpuclk_data, rk3328_cpuclk_rates, |
| 906 | ARRAY_SIZE(rk3328_cpuclk_rates)); |
| 907 | |
Jonas Karlman | fb90339 | 2019-03-10 12:00:45 +0000 | [diff] [blame] | 908 | rockchip_register_softrst(np, 12, reg_base + RK3328_SOFTRST_CON(0), |
Elaine Zhang | fe3511a | 2016-12-29 10:45:11 +0800 | [diff] [blame] | 909 | ROCKCHIP_SOFTRST_HIWORD_MASK); |
| 910 | |
| 911 | rockchip_register_restart_notifier(ctx, RK3328_GLB_SRST_FST, NULL); |
| 912 | |
| 913 | rockchip_clk_of_add_provider(np, ctx); |
| 914 | } |
| 915 | CLK_OF_DECLARE(rk3328_cru, "rockchip,rk3328-cru", rk3328_clk_init); |