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nv-tegra.nvidia.com / linux-5.10 / c942fddf8793b2013be8c901b47d0a8dc02bf99f / . / drivers / clk / qcom / gdsc.h
blob: bd1f2c780d0afbc56aed75578f87733f9f69805a [file] [log] [blame]
Stephen Boyd45dd0e52015-08-06 16:07:42 +0530[diff] [blame]1/*
Amit Nischal44dbeeb2018-04-09 14:11:44 +0530[diff] [blame]2 * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
Stephen Boyd45dd0e52015-08-06 16:07:42 +0530[diff] [blame]3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __QCOM_GDSC_H__
15#define __QCOM_GDSC_H__
16
17#include <linux/err.h>
18#include <linux/pm_domain.h>
19
20struct regmap;
Rajendra Nayak3c53f5e2015-08-06 16:07:45 +0530[diff] [blame]21struct reset_controller_dev;
Stephen Boyd45dd0e52015-08-06 16:07:42 +0530[diff] [blame]22
23/**
24 * struct gdsc - Globally Distributed Switch Controller
25 * @pd: generic power domain
26 * @regmap: regmap for MMIO accesses
27 * @gdscr: gsdc control register
Rajendra Nayak77b10672015-12-01 21:42:12 +0530[diff] [blame]28 * @gds_hw_ctrl: gds_hw_ctrl register
Rajendra Nayak014e1932015-08-06 16:07:44 +0530[diff] [blame]29 * @cxcs: offsets of branch registers to toggle mem/periph bits in
30 * @cxc_count: number of @cxcs
31 * @pwrsts: Possible powerdomain power states
Rajendra Nayak3c53f5e2015-08-06 16:07:45 +0530[diff] [blame]32 * @resets: ids of resets associated with this gdsc
33 * @reset_count: number of @resets
34 * @rcdev: reset controller
Stephen Boyd45dd0e52015-08-06 16:07:42 +0530[diff] [blame]35 */
36struct gdsc {
37 struct generic_pm_domain pd;
Rajendra Nayakc2c7f0a2015-12-01 21:42:11 +0530[diff] [blame]38 struct generic_pm_domain *parent;
Stephen Boyd45dd0e52015-08-06 16:07:42 +0530[diff] [blame]39 struct regmap *regmap;
40 unsigned int gdscr;
Rajendra Nayak77b10672015-12-01 21:42:12 +0530[diff] [blame]41 unsigned int gds_hw_ctrl;
Rajendra Nayake7cc4552016-10-20 15:08:06 +0530[diff] [blame]42 unsigned int clamp_io_ctrl;
Rajendra Nayak014e1932015-08-06 16:07:44 +0530[diff] [blame]43 unsigned int *cxcs;
44 unsigned int cxc_count;
45 const u8 pwrsts;
Rajendra Nayaka823bb92015-12-01 21:42:13 +0530[diff] [blame]46/* Powerdomain allowable state bitfields */
47#define PWRSTS_OFF BIT(0)
48#define PWRSTS_RET BIT(1)
49#define PWRSTS_ON BIT(2)
50#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
51#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
52 const u8 flags;
53#define VOTABLE BIT(0)
Rajendra Nayake7cc4552016-10-20 15:08:06 +0530[diff] [blame]54#define CLAMP_IO BIT(1)
Rajendra Nayak904bb4f2016-11-18 17:58:26 +0530[diff] [blame]55#define HW_CTRL BIT(2)
Amit Nischal44dbeeb2018-04-09 14:11:44 +0530[diff] [blame]56#define SW_RESET BIT(3)
57#define AON_RESET BIT(4)
Amit Nischale892e172018-05-01 10:33:33 +0530[diff] [blame]58#define POLL_CFG_GDSCR BIT(5)
Stephen Boyd77122d62018-06-04 12:34:51 -0700[diff] [blame]59#define ALWAYS_ON BIT(6)
Rajendra Nayak3c53f5e2015-08-06 16:07:45 +0530[diff] [blame]60 struct reset_controller_dev *rcdev;
61 unsigned int *resets;
62 unsigned int reset_count;
Stephen Boyd45dd0e52015-08-06 16:07:42 +0530[diff] [blame]63};
64
Rajendra Nayakc2c7f0a2015-12-01 21:42:11 +0530[diff] [blame]65struct gdsc_desc {
66 struct device *dev;
67 struct gdsc **scs;
68 size_t num;
69};
70
Stephen Boyd45dd0e52015-08-06 16:07:42 +0530[diff] [blame]71#ifdef CONFIG_QCOM_GDSC
Rajendra Nayakc2c7f0a2015-12-01 21:42:11 +0530[diff] [blame]72int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
73 struct regmap *);
74void gdsc_unregister(struct gdsc_desc *desc);
Stephen Boyd45dd0e52015-08-06 16:07:42 +0530[diff] [blame]75#else
Rajendra Nayakc2c7f0a2015-12-01 21:42:11 +0530[diff] [blame]76static inline int gdsc_register(struct gdsc_desc *desc,
Rajendra Nayak3c53f5e2015-08-06 16:07:45 +0530[diff] [blame]77 struct reset_controller_dev *rcdev,
Stephen Boyd45dd0e52015-08-06 16:07:42 +0530[diff] [blame]78 struct regmap *r)
79{
80 return -ENOSYS;
81}
82
Rajendra Nayakc2c7f0a2015-12-01 21:42:11 +0530[diff] [blame]83static inline void gdsc_unregister(struct gdsc_desc *desc) {};
Stephen Boyd45dd0e52015-08-06 16:07:42 +0530[diff] [blame]84#endif /* CONFIG_QCOM_GDSC */
85#endif /* __QCOM_GDSC_H__ */