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Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001// SPDX-License-Identifier: GPL-2.0
Yoshinori Sato7b5bb892015-05-08 23:31:57 +09002/*
3 * H8/300 divide clock driver
4 *
5 * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
6 */
7
Yoshinori Sato7b5bb892015-05-08 23:31:57 +09008#include <linux/clk-provider.h>
9#include <linux/err.h>
Stephen Boyd62e59c42019-04-18 15:20:22 -070010#include <linux/io.h>
Yoshinori Sato7b5bb892015-05-08 23:31:57 +090011#include <linux/of.h>
12#include <linux/of_address.h>
13
14static DEFINE_SPINLOCK(clklock);
15
16static void __init h8300_div_clk_setup(struct device_node *node)
17{
Stephen Boydebf3f9a2016-02-19 17:36:51 -080018 unsigned int num_parents;
Stephen Boyd8b2bdc72016-08-16 15:37:57 -070019 struct clk_hw *hw;
Yoshinori Sato7b5bb892015-05-08 23:31:57 +090020 const char *clk_name = node->name;
21 const char *parent_name;
22 void __iomem *divcr = NULL;
23 int width;
Yoshinori Satoaca25182015-05-31 23:25:35 +090024 int offset;
Yoshinori Sato7b5bb892015-05-08 23:31:57 +090025
26 num_parents = of_clk_get_parent_count(node);
Stephen Boydebf3f9a2016-02-19 17:36:51 -080027 if (!num_parents) {
Arvind Yadav1f7e6552017-11-24 12:25:33 +053028 pr_err("%s: no parent found\n", clk_name);
Yoshinori Sato7b5bb892015-05-08 23:31:57 +090029 return;
30 }
31
32 divcr = of_iomap(node, 0);
33 if (divcr == NULL) {
Arvind Yadav1f7e6552017-11-24 12:25:33 +053034 pr_err("%s: failed to map divide register\n", clk_name);
Yoshinori Sato7b5bb892015-05-08 23:31:57 +090035 goto error;
36 }
Yoshinori Satoaca25182015-05-31 23:25:35 +090037 offset = (unsigned long)divcr & 3;
38 offset = (3 - offset) * 8;
Stephen Boydd3622b52016-02-22 12:36:15 -080039 divcr = (void __iomem *)((unsigned long)divcr & ~3);
Yoshinori Sato7b5bb892015-05-08 23:31:57 +090040
41 parent_name = of_clk_get_parent_name(node, 0);
42 of_property_read_u32(node, "renesas,width", &width);
Stephen Boyd8b2bdc72016-08-16 15:37:57 -070043 hw = clk_hw_register_divider(NULL, clk_name, parent_name,
Yoshinori Satoaca25182015-05-31 23:25:35 +090044 CLK_SET_RATE_GATE, divcr, offset, width,
Yoshinori Sato7b5bb892015-05-08 23:31:57 +090045 CLK_DIVIDER_POWER_OF_TWO, &clklock);
Stephen Boyd8b2bdc72016-08-16 15:37:57 -070046 if (!IS_ERR(hw)) {
47 of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
Yoshinori Sato7b5bb892015-05-08 23:31:57 +090048 return;
49 }
50 pr_err("%s: failed to register %s div clock (%ld)\n",
Stephen Boyd8b2bdc72016-08-16 15:37:57 -070051 __func__, clk_name, PTR_ERR(hw));
Yoshinori Sato7b5bb892015-05-08 23:31:57 +090052error:
53 if (divcr)
54 iounmap(divcr);
55}
56
57CLK_OF_DECLARE(h8300_div_clk, "renesas,h8300-div-clock", h8300_div_clk_setup);