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nv-tegra.nvidia.com / linux-5.10 / c942fddf8793b2013be8c901b47d0a8dc02bf99f / . / drivers / acpi / nfit / intel.h
blob: 0aca682ab9d71256e711bf5249f010f9156e511e [file] [log] [blame]
Dan Williams0ead1112018-09-26 10:47:15 -0700[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright(c) 2018 Intel Corporation. All rights reserved.
4 * Intel specific definitions for NVDIMM Firmware Interface Table - NFIT
5 */
6#ifndef _NFIT_INTEL_H_
7#define _NFIT_INTEL_H_
8
9#define ND_INTEL_SMART 1
10
11#define ND_INTEL_SMART_SHUTDOWN_COUNT_VALID (1 << 5)
12#define ND_INTEL_SMART_SHUTDOWN_VALID (1 << 10)
13
14struct nd_intel_smart {
15 u32 status;
16 union {
17 struct {
18 u32 flags;
19 u8 reserved0[4];
20 u8 health;
21 u8 spares;
22 u8 life_used;
23 u8 alarm_flags;
24 u16 media_temperature;
25 u16 ctrl_temperature;
26 u32 shutdown_count;
27 u8 ait_status;
28 u16 pmic_temperature;
29 u8 reserved1[8];
30 u8 shutdown_state;
31 u32 vendor_size;
32 u8 vendor_data[92];
33 } __packed;
34 u8 data[128];
35 };
36} __packed;
37
Dave Jiangf2989392018-12-05 23:39:29 -0800[diff] [blame]38extern const struct nvdimm_security_ops *intel_security_ops;
39
Dave Jiangb3ed2ce2018-12-04 10:31:11 -0800[diff] [blame]40#define ND_INTEL_STATUS_SIZE 4
41#define ND_INTEL_PASSPHRASE_SIZE 32
42
43#define ND_INTEL_STATUS_NOT_SUPPORTED 1
44#define ND_INTEL_STATUS_RETRY 5
45#define ND_INTEL_STATUS_NOT_READY 9
46#define ND_INTEL_STATUS_INVALID_STATE 10
47#define ND_INTEL_STATUS_INVALID_PASS 11
48#define ND_INTEL_STATUS_OVERWRITE_UNSUPPORTED 0x10007
49#define ND_INTEL_STATUS_OQUERY_INPROGRESS 0x10007
50#define ND_INTEL_STATUS_OQUERY_SEQUENCE_ERR 0x20007
51
52#define ND_INTEL_SEC_STATE_ENABLED 0x02
53#define ND_INTEL_SEC_STATE_LOCKED 0x04
54#define ND_INTEL_SEC_STATE_FROZEN 0x08
55#define ND_INTEL_SEC_STATE_PLIMIT 0x10
56#define ND_INTEL_SEC_STATE_UNSUPPORTED 0x20
57#define ND_INTEL_SEC_STATE_OVERWRITE 0x40
58
59#define ND_INTEL_SEC_ESTATE_ENABLED 0x01
60#define ND_INTEL_SEC_ESTATE_PLIMIT 0x02
61
62struct nd_intel_get_security_state {
63 u32 status;
64 u8 extended_state;
65 u8 reserved[3];
66 u8 state;
67 u8 reserved1[3];
68} __packed;
69
70struct nd_intel_set_passphrase {
71 u8 old_pass[ND_INTEL_PASSPHRASE_SIZE];
72 u8 new_pass[ND_INTEL_PASSPHRASE_SIZE];
73 u32 status;
74} __packed;
75
76struct nd_intel_unlock_unit {
77 u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
78 u32 status;
79} __packed;
80
81struct nd_intel_disable_passphrase {
82 u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
83 u32 status;
84} __packed;
85
86struct nd_intel_freeze_lock {
87 u32 status;
88} __packed;
89
90struct nd_intel_secure_erase {
91 u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
92 u32 status;
93} __packed;
94
95struct nd_intel_overwrite {
96 u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
97 u32 status;
98} __packed;
99
100struct nd_intel_query_overwrite {
101 u32 status;
102} __packed;
103
104struct nd_intel_set_master_passphrase {
105 u8 old_pass[ND_INTEL_PASSPHRASE_SIZE];
106 u8 new_pass[ND_INTEL_PASSPHRASE_SIZE];
107 u32 status;
108} __packed;
109
110struct nd_intel_master_secure_erase {
111 u8 passphrase[ND_INTEL_PASSPHRASE_SIZE];
112 u32 status;
113} __packed;
Dan Williams0ead1112018-09-26 10:47:15 -0700[diff] [blame]114#endif