blob: 8ade997c2b6c2d98b36cbb144f4aa0863f33bf61 [file] [log] [blame]
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000018#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020019#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000020
21#define DRIVER_NAME "tegra"
22#define DRIVER_DESC "NVIDIA Tegra graphics"
23#define DRIVER_DATE "20120330"
24#define DRIVER_MAJOR 0
25#define DRIVER_MINOR 0
26#define DRIVER_PATCHLEVEL 0
27
Mikko Perttunenad926012016-12-14 13:16:11 +020028#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030029#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020030
Thierry Reding08943e62013-09-26 16:08:18 +020031struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010032 struct idr contexts;
33 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020034};
35
Thierry Redingc4755fb2017-11-13 11:08:13 +010036static struct drm_atomic_state *
37tegra_atomic_state_alloc(struct drm_device *drm)
38{
39 struct tegra_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
40
41 if (!state || drm_atomic_state_init(drm, &state->base) < 0) {
42 kfree(state);
43 return NULL;
44 }
45
46 return &state->base;
47}
48
49static void tegra_atomic_state_clear(struct drm_atomic_state *state)
50{
51 struct tegra_atomic_state *tegra = to_tegra_atomic_state(state);
52
53 drm_atomic_state_default_clear(state);
54 tegra->clk_disp = NULL;
55 tegra->dc = NULL;
56 tegra->rate = 0;
57}
58
59static void tegra_atomic_state_free(struct drm_atomic_state *state)
60{
61 drm_atomic_state_default_release(state);
62 kfree(state);
63}
64
Thierry Reding31b02ca2017-10-12 17:40:46 +020065static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
Thierry Redingf9914212014-11-26 13:03:57 +010066 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +053067#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Redingf9914212014-11-26 13:03:57 +010068 .output_poll_changed = tegra_fb_output_poll_changed,
69#endif
Thierry Reding07866962014-11-24 17:08:06 +010070 .atomic_check = drm_atomic_helper_check,
Thierry Reding31b02ca2017-10-12 17:40:46 +020071 .atomic_commit = drm_atomic_helper_commit,
Thierry Redingc4755fb2017-11-13 11:08:13 +010072 .atomic_state_alloc = tegra_atomic_state_alloc,
73 .atomic_state_clear = tegra_atomic_state_clear,
74 .atomic_state_free = tegra_atomic_state_free,
Thierry Reding31b02ca2017-10-12 17:40:46 +020075};
76
Thierry Redingc4755fb2017-11-13 11:08:13 +010077static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
78{
79 struct drm_device *drm = old_state->dev;
80 struct tegra_drm *tegra = drm->dev_private;
81
82 if (tegra->hub) {
83 drm_atomic_helper_commit_modeset_disables(drm, old_state);
84 tegra_display_hub_atomic_commit(drm, old_state);
85 drm_atomic_helper_commit_planes(drm, old_state, 0);
86 drm_atomic_helper_commit_modeset_enables(drm, old_state);
87 drm_atomic_helper_commit_hw_done(old_state);
88 drm_atomic_helper_wait_for_vblanks(drm, old_state);
89 drm_atomic_helper_cleanup_planes(drm, old_state);
90 } else {
91 drm_atomic_helper_commit_tail_rpm(old_state);
92 }
93}
94
Thierry Reding31b02ca2017-10-12 17:40:46 +020095static const struct drm_mode_config_helper_funcs
96tegra_drm_mode_config_helpers = {
Thierry Redingc4755fb2017-11-13 11:08:13 +010097 .atomic_commit_tail = tegra_atomic_commit_tail,
Thierry Redingf9914212014-11-26 13:03:57 +010098};
99
Thierry Reding776dc382013-10-14 14:43:22 +0200100static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000101{
Thierry Reding776dc382013-10-14 14:43:22 +0200102 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +0200103 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000104 int err;
105
Thierry Reding776dc382013-10-14 14:43:22 +0200106 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +0200107 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +0200108 return -ENOMEM;
109
Thierry Redingdf06b752014-06-26 21:41:53 +0200110 if (iommu_present(&platform_bus_type)) {
Mikko Perttunenad926012016-12-14 13:16:11 +0200111 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100112 struct iommu_domain_geometry *geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200113 unsigned long order;
Thierry Reding4553f732015-01-19 16:15:04 +0100114
Thierry Redingdf06b752014-06-26 21:41:53 +0200115 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +0300116 if (!tegra->domain) {
117 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +0200118 goto free;
119 }
120
Thierry Reding4553f732015-01-19 16:15:04 +0100121 geometry = &tegra->domain->geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200122 gem_start = geometry->aperture_start;
123 gem_end = geometry->aperture_end - CARVEOUT_SZ;
124 carveout_start = gem_end + 1;
125 carveout_end = geometry->aperture_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100126
Mikko Perttunenad926012016-12-14 13:16:11 +0200127 order = __ffs(tegra->domain->pgsize_bitmap);
128 init_iova_domain(&tegra->carveout.domain, 1UL << order,
Zhen Leiaa3ac942017-09-21 16:52:45 +0100129 carveout_start >> order);
Mikko Perttunenad926012016-12-14 13:16:11 +0200130
131 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
132 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
133
134 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100135 mutex_init(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200136
137 DRM_DEBUG("IOMMU apertures:\n");
138 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
139 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
140 carveout_end);
Thierry Redingdf06b752014-06-26 21:41:53 +0200141 }
142
Thierry Reding386a2a72013-09-24 13:22:17 +0200143 mutex_init(&tegra->clients_lock);
144 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100145
Thierry Reding386a2a72013-09-24 13:22:17 +0200146 drm->dev_private = tegra;
147 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000148
149 drm_mode_config_init(drm);
150
Thierry Redingf9914212014-11-26 13:03:57 +0100151 drm->mode_config.min_width = 0;
152 drm->mode_config.min_height = 0;
153
154 drm->mode_config.max_width = 4096;
155 drm->mode_config.max_height = 4096;
156
Alexandre Courbot5e911442016-11-08 16:50:42 +0900157 drm->mode_config.allow_fb_modifiers = true;
158
Thierry Reding31b02ca2017-10-12 17:40:46 +0200159 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
160 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
Thierry Redingf9914212014-11-26 13:03:57 +0100161
Thierry Redinge2215322014-06-27 17:19:25 +0200162 err = tegra_drm_fb_prepare(drm);
163 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100164 goto config;
Thierry Redinge2215322014-06-27 17:19:25 +0200165
166 drm_kms_helper_poll_init(drm);
167
Thierry Reding776dc382013-10-14 14:43:22 +0200168 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000169 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100170 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000171
Thierry Redingc4755fb2017-11-13 11:08:13 +0100172 if (tegra->hub) {
173 err = tegra_display_hub_prepare(tegra->hub);
174 if (err < 0)
175 goto device;
176 }
177
Thierry Reding603f0cc2013-04-22 21:22:14 +0200178 /*
179 * We don't use the drm_irq_install() helpers provided by the DRM
180 * core, so we need to set this manually in order to allow the
181 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
182 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300183 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200184
Thierry Reding42e9ce02015-01-28 14:43:05 +0100185 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100186 drm->max_vblank_count = 0xffffffff;
187
Thierry Reding6e5ff992012-11-28 11:45:47 +0100188 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
189 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100190 goto hub;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100191
Thierry Reding31930d42015-07-02 17:04:06 +0200192 drm_mode_config_reset(drm);
193
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000194 err = tegra_drm_fb_init(drm);
195 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100196 goto hub;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000197
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000198 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100199
Thierry Redingc4755fb2017-11-13 11:08:13 +0100200hub:
201 if (tegra->hub)
202 tegra_display_hub_cleanup(tegra->hub);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100203device:
204 host1x_device_exit(device);
205fbdev:
206 drm_kms_helper_poll_fini(drm);
207 tegra_drm_fb_free(drm);
208config:
209 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200210
211 if (tegra->domain) {
212 iommu_domain_free(tegra->domain);
213 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100214 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200215 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200216 }
217free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100218 kfree(tegra);
219 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000220}
221
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200222static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000223{
Thierry Reding776dc382013-10-14 14:43:22 +0200224 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200225 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200226 int err;
227
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000228 drm_kms_helper_poll_fini(drm);
229 tegra_drm_fb_exit(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200230 drm_mode_config_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000231
Thierry Reding776dc382013-10-14 14:43:22 +0200232 err = host1x_device_exit(device);
233 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200234 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200235
Thierry Redingdf06b752014-06-26 21:41:53 +0200236 if (tegra->domain) {
237 iommu_domain_free(tegra->domain);
238 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100239 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200240 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200241 }
242
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100243 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000244}
245
246static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
247{
Thierry Reding08943e62013-09-26 16:08:18 +0200248 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200249
250 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
251 if (!fpriv)
252 return -ENOMEM;
253
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100254 idr_init(&fpriv->contexts);
255 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200256 filp->driver_priv = fpriv;
257
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000258 return 0;
259}
260
Thierry Redingc88c3632013-09-26 16:08:22 +0200261static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200262{
263 context->client->ops->close_channel(context);
264 kfree(context);
265}
266
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000267static void tegra_drm_lastclose(struct drm_device *drm)
268{
Archit Tanejab110ef32015-10-27 13:40:59 +0530269#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding386a2a72013-09-24 13:22:17 +0200270 struct tegra_drm *tegra = drm->dev_private;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000271
Thierry Reding386a2a72013-09-24 13:22:17 +0200272 tegra_fbdev_restore_mode(tegra->fbdev);
Thierry Reding60c2f702013-10-31 13:28:50 +0100273#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000274}
275
Thierry Redingc40f0f12013-10-10 11:00:33 +0200276static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100277host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200278{
279 struct drm_gem_object *gem;
280 struct tegra_bo *bo;
281
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100282 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200283 if (!gem)
284 return NULL;
285
Thierry Redingc40f0f12013-10-10 11:00:33 +0200286 bo = to_tegra_bo(gem);
287 return &bo->base;
288}
289
Thierry Reding961e3be2014-06-10 10:25:00 +0200290static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
291 struct drm_tegra_reloc __user *src,
292 struct drm_device *drm,
293 struct drm_file *file)
294{
295 u32 cmdbuf, target;
296 int err;
297
298 err = get_user(cmdbuf, &src->cmdbuf.handle);
299 if (err < 0)
300 return err;
301
302 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
303 if (err < 0)
304 return err;
305
306 err = get_user(target, &src->target.handle);
307 if (err < 0)
308 return err;
309
David Ung31f40f82015-01-20 18:37:35 -0800310 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200311 if (err < 0)
312 return err;
313
314 err = get_user(dest->shift, &src->shift);
315 if (err < 0)
316 return err;
317
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100318 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200319 if (!dest->cmdbuf.bo)
320 return -ENOENT;
321
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100322 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200323 if (!dest->target.bo)
324 return -ENOENT;
325
326 return 0;
327}
328
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300329static int host1x_waitchk_copy_from_user(struct host1x_waitchk *dest,
330 struct drm_tegra_waitchk __user *src,
331 struct drm_file *file)
332{
333 u32 cmdbuf;
334 int err;
335
336 err = get_user(cmdbuf, &src->handle);
337 if (err < 0)
338 return err;
339
340 err = get_user(dest->offset, &src->offset);
341 if (err < 0)
342 return err;
343
344 err = get_user(dest->syncpt_id, &src->syncpt);
345 if (err < 0)
346 return err;
347
348 err = get_user(dest->thresh, &src->thresh);
349 if (err < 0)
350 return err;
351
352 dest->bo = host1x_bo_lookup(file, cmdbuf);
353 if (!dest->bo)
354 return -ENOENT;
355
356 return 0;
357}
358
Thierry Redingc40f0f12013-10-10 11:00:33 +0200359int tegra_drm_submit(struct tegra_drm_context *context,
360 struct drm_tegra_submit *args, struct drm_device *drm,
361 struct drm_file *file)
362{
363 unsigned int num_cmdbufs = args->num_cmdbufs;
364 unsigned int num_relocs = args->num_relocs;
365 unsigned int num_waitchks = args->num_waitchks;
Mikko Perttunena176c672017-09-28 15:50:44 +0300366 struct drm_tegra_cmdbuf __user *user_cmdbufs;
367 struct drm_tegra_reloc __user *user_relocs;
368 struct drm_tegra_waitchk __user *user_waitchks;
369 struct drm_tegra_syncpt __user *user_syncpt;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200370 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300371 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200372 struct drm_gem_object **refs;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300373 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200374 struct host1x_job *job;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200375 unsigned int num_refs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200376 int err;
377
Mikko Perttunena176c672017-09-28 15:50:44 +0300378 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
379 user_relocs = u64_to_user_ptr(args->relocs);
380 user_waitchks = u64_to_user_ptr(args->waitchks);
381 user_syncpt = u64_to_user_ptr(args->syncpts);
382
Thierry Redingc40f0f12013-10-10 11:00:33 +0200383 /* We don't yet support other than one syncpt_incr struct per submit */
384 if (args->num_syncpts != 1)
385 return -EINVAL;
386
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300387 /* We don't yet support waitchks */
388 if (args->num_waitchks != 0)
389 return -EINVAL;
390
Thierry Redingc40f0f12013-10-10 11:00:33 +0200391 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
392 args->num_relocs, args->num_waitchks);
393 if (!job)
394 return -ENOMEM;
395
396 job->num_relocs = args->num_relocs;
397 job->num_waitchk = args->num_waitchks;
398 job->client = (u32)args->context;
399 job->class = context->client->base.class;
400 job->serialize = true;
401
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200402 /*
403 * Track referenced BOs so that they can be unreferenced after the
404 * submission is complete.
405 */
406 num_refs = num_cmdbufs + num_relocs * 2 + num_waitchks;
407
408 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
409 if (!refs) {
410 err = -ENOMEM;
411 goto put;
412 }
413
414 /* reuse as an iterator later */
415 num_refs = 0;
416
Thierry Redingc40f0f12013-10-10 11:00:33 +0200417 while (num_cmdbufs) {
418 struct drm_tegra_cmdbuf cmdbuf;
419 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300420 struct tegra_bo *obj;
421 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200422
Mikko Perttunena176c672017-09-28 15:50:44 +0300423 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300424 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200425 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300426 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200427
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300428 /*
429 * The maximum number of CDMA gather fetches is 16383, a higher
430 * value means the words count is malformed.
431 */
432 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
433 err = -EINVAL;
434 goto fail;
435 }
436
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100437 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200438 if (!bo) {
439 err = -ENOENT;
440 goto fail;
441 }
442
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300443 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
444 obj = host1x_to_tegra_bo(bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200445 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300446
447 /*
448 * Gather buffer base address must be 4-bytes aligned,
449 * unaligned offset is malformed and cause commands stream
450 * corruption on the buffer address relocation.
451 */
452 if (offset & 3 || offset >= obj->gem.size) {
453 err = -EINVAL;
454 goto fail;
455 }
456
Thierry Redingc40f0f12013-10-10 11:00:33 +0200457 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
458 num_cmdbufs--;
Mikko Perttunena176c672017-09-28 15:50:44 +0300459 user_cmdbufs++;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200460 }
461
Thierry Reding961e3be2014-06-10 10:25:00 +0200462 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200463 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300464 struct host1x_reloc *reloc;
465 struct tegra_bo *obj;
466
Thierry Reding961e3be2014-06-10 10:25:00 +0200467 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
Mikko Perttunena176c672017-09-28 15:50:44 +0300468 &user_relocs[num_relocs], drm,
Thierry Reding961e3be2014-06-10 10:25:00 +0200469 file);
470 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200471 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300472
473 reloc = &job->relocarray[num_relocs];
474 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200475 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300476
477 /*
478 * The unaligned cmdbuf offset will cause an unaligned write
479 * during of the relocations patching, corrupting the commands
480 * stream.
481 */
482 if (reloc->cmdbuf.offset & 3 ||
483 reloc->cmdbuf.offset >= obj->gem.size) {
484 err = -EINVAL;
485 goto fail;
486 }
487
488 obj = host1x_to_tegra_bo(reloc->target.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200489 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300490
491 if (reloc->target.offset >= obj->gem.size) {
492 err = -EINVAL;
493 goto fail;
494 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200495 }
496
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300497 /* copy and resolve waitchks from submit */
498 while (num_waitchks--) {
499 struct host1x_waitchk *wait = &job->waitchk[num_waitchks];
500 struct tegra_bo *obj;
501
Mikko Perttunena176c672017-09-28 15:50:44 +0300502 err = host1x_waitchk_copy_from_user(
503 wait, &user_waitchks[num_waitchks], file);
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300504 if (err < 0)
505 goto fail;
506
507 obj = host1x_to_tegra_bo(wait->bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200508 refs[num_refs++] = &obj->gem;
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300509
510 /*
511 * The unaligned offset will cause an unaligned write during
512 * of the waitchks patching, corrupting the commands stream.
513 */
514 if (wait->offset & 3 ||
515 wait->offset >= obj->gem.size) {
516 err = -EINVAL;
517 goto fail;
518 }
Dan Carpenter9a991602013-11-08 13:07:37 +0300519 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200520
Mikko Perttunena176c672017-09-28 15:50:44 +0300521 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300522 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200523 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300524 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200525
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300526 /* check whether syncpoint ID is valid */
527 sp = host1x_syncpt_get(host1x, syncpt.id);
528 if (!sp) {
529 err = -ENOENT;
530 goto fail;
531 }
532
Thierry Redingc40f0f12013-10-10 11:00:33 +0200533 job->is_addr_reg = context->client->ops->is_addr_reg;
Dmitry Osipenko0f563a42017-06-15 02:18:37 +0300534 job->is_valid_class = context->client->ops->is_valid_class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200535 job->syncpt_incrs = syncpt.incrs;
536 job->syncpt_id = syncpt.id;
537 job->timeout = 10000;
538
539 if (args->timeout && args->timeout < 10000)
540 job->timeout = args->timeout;
541
542 err = host1x_job_pin(job, context->client->base.dev);
543 if (err)
544 goto fail;
545
546 err = host1x_job_submit(job);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200547 if (err) {
548 host1x_job_unpin(job);
549 goto fail;
550 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200551
552 args->fence = job->syncpt_end;
553
Thierry Redingc40f0f12013-10-10 11:00:33 +0200554fail:
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200555 while (num_refs--)
556 drm_gem_object_put_unlocked(refs[num_refs]);
557
558 kfree(refs);
559
560put:
Thierry Redingc40f0f12013-10-10 11:00:33 +0200561 host1x_job_put(job);
562 return err;
563}
564
565
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200566#ifdef CONFIG_DRM_TEGRA_STAGING
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200567static int tegra_gem_create(struct drm_device *drm, void *data,
568 struct drm_file *file)
569{
570 struct drm_tegra_gem_create *args = data;
571 struct tegra_bo *bo;
572
Thierry Reding773af772013-10-04 22:34:01 +0200573 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200574 &args->handle);
575 if (IS_ERR(bo))
576 return PTR_ERR(bo);
577
578 return 0;
579}
580
581static int tegra_gem_mmap(struct drm_device *drm, void *data,
582 struct drm_file *file)
583{
584 struct drm_tegra_gem_mmap *args = data;
585 struct drm_gem_object *gem;
586 struct tegra_bo *bo;
587
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100588 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200589 if (!gem)
590 return -EINVAL;
591
592 bo = to_tegra_bo(gem);
593
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200594 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200595
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300596 drm_gem_object_put_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200597
598 return 0;
599}
600
601static int tegra_syncpt_read(struct drm_device *drm, void *data,
602 struct drm_file *file)
603{
Thierry Reding776dc382013-10-14 14:43:22 +0200604 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200605 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200606 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200607
Thierry Reding776dc382013-10-14 14:43:22 +0200608 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200609 if (!sp)
610 return -EINVAL;
611
612 args->value = host1x_syncpt_read_min(sp);
613 return 0;
614}
615
616static int tegra_syncpt_incr(struct drm_device *drm, void *data,
617 struct drm_file *file)
618{
Thierry Reding776dc382013-10-14 14:43:22 +0200619 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200620 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200621 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200622
Thierry Reding776dc382013-10-14 14:43:22 +0200623 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200624 if (!sp)
625 return -EINVAL;
626
Arto Merilainenebae30b2013-05-29 13:26:08 +0300627 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200628}
629
630static int tegra_syncpt_wait(struct drm_device *drm, void *data,
631 struct drm_file *file)
632{
Thierry Reding776dc382013-10-14 14:43:22 +0200633 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200634 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200635 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200636
Thierry Reding776dc382013-10-14 14:43:22 +0200637 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200638 if (!sp)
639 return -EINVAL;
640
641 return host1x_syncpt_wait(sp, args->thresh, args->timeout,
642 &args->value);
643}
644
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100645static int tegra_client_open(struct tegra_drm_file *fpriv,
646 struct tegra_drm_client *client,
647 struct tegra_drm_context *context)
648{
649 int err;
650
651 err = client->ops->open_channel(client, context);
652 if (err < 0)
653 return err;
654
Dmitry Osipenkod6c153e2017-06-15 02:18:25 +0300655 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100656 if (err < 0) {
657 client->ops->close_channel(context);
658 return err;
659 }
660
661 context->client = client;
662 context->id = err;
663
664 return 0;
665}
666
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200667static int tegra_open_channel(struct drm_device *drm, void *data,
668 struct drm_file *file)
669{
Thierry Reding08943e62013-09-26 16:08:18 +0200670 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200671 struct tegra_drm *tegra = drm->dev_private;
672 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200673 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200674 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200675 int err = -ENODEV;
676
677 context = kzalloc(sizeof(*context), GFP_KERNEL);
678 if (!context)
679 return -ENOMEM;
680
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100681 mutex_lock(&fpriv->lock);
682
Thierry Reding776dc382013-10-14 14:43:22 +0200683 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200684 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100685 err = tegra_client_open(fpriv, client, context);
686 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200687 break;
688
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100689 args->context = context->id;
690 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200691 }
692
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100693 if (err < 0)
694 kfree(context);
695
696 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200697 return err;
698}
699
700static int tegra_close_channel(struct drm_device *drm, void *data,
701 struct drm_file *file)
702{
Thierry Reding08943e62013-09-26 16:08:18 +0200703 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200704 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200705 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100706 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200707
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100708 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200709
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300710 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100711 if (!context) {
712 err = -EINVAL;
713 goto unlock;
714 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200715
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100716 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200717 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200718
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100719unlock:
720 mutex_unlock(&fpriv->lock);
721 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200722}
723
724static int tegra_get_syncpt(struct drm_device *drm, void *data,
725 struct drm_file *file)
726{
Thierry Reding08943e62013-09-26 16:08:18 +0200727 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200728 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200729 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200730 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100731 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200732
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100733 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200734
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300735 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100736 if (!context) {
737 err = -ENODEV;
738 goto unlock;
739 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200740
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100741 if (args->index >= context->client->base.num_syncpts) {
742 err = -EINVAL;
743 goto unlock;
744 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200745
Thierry Reding53fa7f72013-09-24 15:35:40 +0200746 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200747 args->id = host1x_syncpt_id(syncpt);
748
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100749unlock:
750 mutex_unlock(&fpriv->lock);
751 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200752}
753
754static int tegra_submit(struct drm_device *drm, void *data,
755 struct drm_file *file)
756{
Thierry Reding08943e62013-09-26 16:08:18 +0200757 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200758 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200759 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100760 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200761
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100762 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200763
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300764 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100765 if (!context) {
766 err = -ENODEV;
767 goto unlock;
768 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200769
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100770 err = context->client->ops->submit(context, args, drm, file);
771
772unlock:
773 mutex_unlock(&fpriv->lock);
774 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200775}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300776
777static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
778 struct drm_file *file)
779{
780 struct tegra_drm_file *fpriv = file->driver_priv;
781 struct drm_tegra_get_syncpt_base *args = data;
782 struct tegra_drm_context *context;
783 struct host1x_syncpt_base *base;
784 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100785 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300786
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100787 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300788
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300789 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100790 if (!context) {
791 err = -ENODEV;
792 goto unlock;
793 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300794
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100795 if (args->syncpt >= context->client->base.num_syncpts) {
796 err = -EINVAL;
797 goto unlock;
798 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300799
800 syncpt = context->client->base.syncpts[args->syncpt];
801
802 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100803 if (!base) {
804 err = -ENXIO;
805 goto unlock;
806 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300807
808 args->id = host1x_syncpt_base_id(base);
809
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100810unlock:
811 mutex_unlock(&fpriv->lock);
812 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300813}
Thierry Reding7678d712014-06-03 14:56:57 +0200814
815static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
816 struct drm_file *file)
817{
818 struct drm_tegra_gem_set_tiling *args = data;
819 enum tegra_bo_tiling_mode mode;
820 struct drm_gem_object *gem;
821 unsigned long value = 0;
822 struct tegra_bo *bo;
823
824 switch (args->mode) {
825 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
826 mode = TEGRA_BO_TILING_MODE_PITCH;
827
828 if (args->value != 0)
829 return -EINVAL;
830
831 break;
832
833 case DRM_TEGRA_GEM_TILING_MODE_TILED:
834 mode = TEGRA_BO_TILING_MODE_TILED;
835
836 if (args->value != 0)
837 return -EINVAL;
838
839 break;
840
841 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
842 mode = TEGRA_BO_TILING_MODE_BLOCK;
843
844 if (args->value > 5)
845 return -EINVAL;
846
847 value = args->value;
848 break;
849
850 default:
851 return -EINVAL;
852 }
853
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100854 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200855 if (!gem)
856 return -ENOENT;
857
858 bo = to_tegra_bo(gem);
859
860 bo->tiling.mode = mode;
861 bo->tiling.value = value;
862
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300863 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200864
865 return 0;
866}
867
868static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
869 struct drm_file *file)
870{
871 struct drm_tegra_gem_get_tiling *args = data;
872 struct drm_gem_object *gem;
873 struct tegra_bo *bo;
874 int err = 0;
875
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100876 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200877 if (!gem)
878 return -ENOENT;
879
880 bo = to_tegra_bo(gem);
881
882 switch (bo->tiling.mode) {
883 case TEGRA_BO_TILING_MODE_PITCH:
884 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
885 args->value = 0;
886 break;
887
888 case TEGRA_BO_TILING_MODE_TILED:
889 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
890 args->value = 0;
891 break;
892
893 case TEGRA_BO_TILING_MODE_BLOCK:
894 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
895 args->value = bo->tiling.value;
896 break;
897
898 default:
899 err = -EINVAL;
900 break;
901 }
902
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300903 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200904
905 return err;
906}
Thierry Reding7b129082014-06-10 12:04:03 +0200907
908static int tegra_gem_set_flags(struct drm_device *drm, void *data,
909 struct drm_file *file)
910{
911 struct drm_tegra_gem_set_flags *args = data;
912 struct drm_gem_object *gem;
913 struct tegra_bo *bo;
914
915 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
916 return -EINVAL;
917
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100918 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200919 if (!gem)
920 return -ENOENT;
921
922 bo = to_tegra_bo(gem);
923 bo->flags = 0;
924
925 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
926 bo->flags |= TEGRA_BO_BOTTOM_UP;
927
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300928 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200929
930 return 0;
931}
932
933static int tegra_gem_get_flags(struct drm_device *drm, void *data,
934 struct drm_file *file)
935{
936 struct drm_tegra_gem_get_flags *args = data;
937 struct drm_gem_object *gem;
938 struct tegra_bo *bo;
939
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100940 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200941 if (!gem)
942 return -ENOENT;
943
944 bo = to_tegra_bo(gem);
945 args->flags = 0;
946
947 if (bo->flags & TEGRA_BO_BOTTOM_UP)
948 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
949
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300950 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200951
952 return 0;
953}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200954#endif
955
Rob Clarkbaa70942013-08-02 13:27:49 -0400956static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200957#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Reding6c68b712017-08-15 15:42:39 +0200958 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
959 DRM_UNLOCKED | DRM_RENDER_ALLOW),
960 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
961 DRM_UNLOCKED | DRM_RENDER_ALLOW),
962 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
963 DRM_UNLOCKED | DRM_RENDER_ALLOW),
964 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
965 DRM_UNLOCKED | DRM_RENDER_ALLOW),
966 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
967 DRM_UNLOCKED | DRM_RENDER_ALLOW),
968 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
969 DRM_UNLOCKED | DRM_RENDER_ALLOW),
970 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
971 DRM_UNLOCKED | DRM_RENDER_ALLOW),
972 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
973 DRM_UNLOCKED | DRM_RENDER_ALLOW),
974 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
975 DRM_UNLOCKED | DRM_RENDER_ALLOW),
976 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
977 DRM_UNLOCKED | DRM_RENDER_ALLOW),
978 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
979 DRM_UNLOCKED | DRM_RENDER_ALLOW),
980 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
981 DRM_UNLOCKED | DRM_RENDER_ALLOW),
982 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
983 DRM_UNLOCKED | DRM_RENDER_ALLOW),
984 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
985 DRM_UNLOCKED | DRM_RENDER_ALLOW),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200986#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000987};
988
989static const struct file_operations tegra_drm_fops = {
990 .owner = THIS_MODULE,
991 .open = drm_open,
992 .release = drm_release,
993 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +0200994 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000995 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000996 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000997 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000998 .llseek = noop_llseek,
999};
1000
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001001static int tegra_drm_context_cleanup(int id, void *p, void *data)
1002{
1003 struct tegra_drm_context *context = p;
1004
1005 tegra_drm_context_free(context);
1006
1007 return 0;
1008}
1009
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001010static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
Thierry Reding3c03c462012-11-28 12:00:18 +01001011{
Thierry Reding08943e62013-09-26 16:08:18 +02001012 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +01001013
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001014 mutex_lock(&fpriv->lock);
1015 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
1016 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001017
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001018 idr_destroy(&fpriv->contexts);
1019 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001020 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +01001021}
1022
Thierry Redinge450fcc2013-02-13 16:13:16 +01001023#ifdef CONFIG_DEBUG_FS
1024static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
1025{
1026 struct drm_info_node *node = (struct drm_info_node *)s->private;
1027 struct drm_device *drm = node->minor->dev;
1028 struct drm_framebuffer *fb;
1029
1030 mutex_lock(&drm->mode_config.fb_lock);
1031
1032 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
1033 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +02001034 fb->base.id, fb->width, fb->height,
1035 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +02001036 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +10001037 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +01001038 }
1039
1040 mutex_unlock(&drm->mode_config.fb_lock);
1041
1042 return 0;
1043}
1044
Thierry Reding28c23372015-01-23 09:16:03 +01001045static int tegra_debugfs_iova(struct seq_file *s, void *data)
1046{
1047 struct drm_info_node *node = (struct drm_info_node *)s->private;
1048 struct drm_device *drm = node->minor->dev;
1049 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +01001050 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +01001051
Michał Mirosław68d890a2017-08-14 23:53:45 +02001052 if (tegra->domain) {
1053 mutex_lock(&tegra->mm_lock);
1054 drm_mm_print(&tegra->mm, &p);
1055 mutex_unlock(&tegra->mm_lock);
1056 }
Daniel Vetterb5c37142016-12-29 12:09:24 +01001057
1058 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +01001059}
1060
Thierry Redinge450fcc2013-02-13 16:13:16 +01001061static struct drm_info_list tegra_debugfs_list[] = {
1062 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +01001063 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +01001064};
1065
1066static int tegra_debugfs_init(struct drm_minor *minor)
1067{
1068 return drm_debugfs_create_files(tegra_debugfs_list,
1069 ARRAY_SIZE(tegra_debugfs_list),
1070 minor->debugfs_root, minor);
1071}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001072#endif
1073
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001074static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +02001075 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
Thierry Reding6c68b712017-08-15 15:42:39 +02001076 DRIVER_ATOMIC | DRIVER_RENDER,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001077 .load = tegra_drm_load,
1078 .unload = tegra_drm_unload,
1079 .open = tegra_drm_open,
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001080 .postclose = tegra_drm_postclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001081 .lastclose = tegra_drm_lastclose,
1082
Thierry Redinge450fcc2013-02-13 16:13:16 +01001083#if defined(CONFIG_DEBUG_FS)
1084 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001085#endif
1086
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001087 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001088 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001089
1090 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1091 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1092 .gem_prime_export = tegra_gem_prime_export,
1093 .gem_prime_import = tegra_gem_prime_import,
1094
Arto Merilainende2ba662013-03-22 16:34:08 +02001095 .dumb_create = tegra_bo_dumb_create,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001096
1097 .ioctls = tegra_drm_ioctls,
1098 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1099 .fops = &tegra_drm_fops,
1100
1101 .name = DRIVER_NAME,
1102 .desc = DRIVER_DESC,
1103 .date = DRIVER_DATE,
1104 .major = DRIVER_MAJOR,
1105 .minor = DRIVER_MINOR,
1106 .patchlevel = DRIVER_PATCHLEVEL,
1107};
Thierry Reding776dc382013-10-14 14:43:22 +02001108
1109int tegra_drm_register_client(struct tegra_drm *tegra,
1110 struct tegra_drm_client *client)
1111{
1112 mutex_lock(&tegra->clients_lock);
1113 list_add_tail(&client->list, &tegra->clients);
1114 mutex_unlock(&tegra->clients_lock);
1115
1116 return 0;
1117}
1118
1119int tegra_drm_unregister_client(struct tegra_drm *tegra,
1120 struct tegra_drm_client *client)
1121{
1122 mutex_lock(&tegra->clients_lock);
1123 list_del_init(&client->list);
1124 mutex_unlock(&tegra->clients_lock);
1125
1126 return 0;
1127}
1128
Thierry Reding67485fb2017-11-09 13:17:11 +01001129void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
Mikko Perttunenad926012016-12-14 13:16:11 +02001130{
1131 struct iova *alloc;
1132 void *virt;
1133 gfp_t gfp;
1134 int err;
1135
1136 if (tegra->domain)
1137 size = iova_align(&tegra->carveout.domain, size);
1138 else
1139 size = PAGE_ALIGN(size);
1140
1141 gfp = GFP_KERNEL | __GFP_ZERO;
1142 if (!tegra->domain) {
1143 /*
1144 * Many units only support 32-bit addresses, even on 64-bit
1145 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1146 * virtual address space, force allocations to be in the
1147 * lower 32-bit range.
1148 */
1149 gfp |= GFP_DMA;
1150 }
1151
1152 virt = (void *)__get_free_pages(gfp, get_order(size));
1153 if (!virt)
1154 return ERR_PTR(-ENOMEM);
1155
1156 if (!tegra->domain) {
1157 /*
1158 * If IOMMU is disabled, devices address physical memory
1159 * directly.
1160 */
1161 *dma = virt_to_phys(virt);
1162 return virt;
1163 }
1164
1165 alloc = alloc_iova(&tegra->carveout.domain,
1166 size >> tegra->carveout.shift,
1167 tegra->carveout.limit, true);
1168 if (!alloc) {
1169 err = -EBUSY;
1170 goto free_pages;
1171 }
1172
1173 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1174 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1175 size, IOMMU_READ | IOMMU_WRITE);
1176 if (err < 0)
1177 goto free_iova;
1178
1179 return virt;
1180
1181free_iova:
1182 __free_iova(&tegra->carveout.domain, alloc);
1183free_pages:
1184 free_pages((unsigned long)virt, get_order(size));
1185
1186 return ERR_PTR(err);
1187}
1188
1189void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1190 dma_addr_t dma)
1191{
1192 if (tegra->domain)
1193 size = iova_align(&tegra->carveout.domain, size);
1194 else
1195 size = PAGE_ALIGN(size);
1196
1197 if (tegra->domain) {
1198 iommu_unmap(tegra->domain, dma, size);
1199 free_iova(&tegra->carveout.domain,
1200 iova_pfn(&tegra->carveout.domain, dma));
1201 }
1202
1203 free_pages((unsigned long)virt, get_order(size));
1204}
1205
Thierry Reding9910f5c2014-05-22 09:57:15 +02001206static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001207{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001208 struct drm_driver *driver = &tegra_drm_driver;
1209 struct drm_device *drm;
1210 int err;
1211
1212 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001213 if (IS_ERR(drm))
1214 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001215
Thierry Reding9910f5c2014-05-22 09:57:15 +02001216 dev_set_drvdata(&dev->dev, drm);
1217
1218 err = drm_dev_register(drm, 0);
1219 if (err < 0)
1220 goto unref;
1221
Thierry Reding9910f5c2014-05-22 09:57:15 +02001222 return 0;
1223
1224unref:
1225 drm_dev_unref(drm);
1226 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001227}
1228
Thierry Reding9910f5c2014-05-22 09:57:15 +02001229static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001230{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001231 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1232
1233 drm_dev_unregister(drm);
1234 drm_dev_unref(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001235
1236 return 0;
1237}
1238
Thierry Reding359ae682014-12-18 17:15:25 +01001239#ifdef CONFIG_PM_SLEEP
1240static int host1x_drm_suspend(struct device *dev)
1241{
1242 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001243 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001244
1245 drm_kms_helper_poll_disable(drm);
Thierry Reding986c58d2015-08-11 13:11:49 +02001246 tegra_drm_fb_suspend(drm);
1247
1248 tegra->state = drm_atomic_helper_suspend(drm);
1249 if (IS_ERR(tegra->state)) {
1250 tegra_drm_fb_resume(drm);
1251 drm_kms_helper_poll_enable(drm);
1252 return PTR_ERR(tegra->state);
1253 }
Thierry Reding359ae682014-12-18 17:15:25 +01001254
1255 return 0;
1256}
1257
1258static int host1x_drm_resume(struct device *dev)
1259{
1260 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001261 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001262
Thierry Reding986c58d2015-08-11 13:11:49 +02001263 drm_atomic_helper_resume(drm, tegra->state);
1264 tegra_drm_fb_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001265 drm_kms_helper_poll_enable(drm);
1266
1267 return 0;
1268}
1269#endif
1270
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001271static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1272 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001273
Thierry Reding776dc382013-10-14 14:43:22 +02001274static const struct of_device_id host1x_drm_subdevs[] = {
1275 { .compatible = "nvidia,tegra20-dc", },
1276 { .compatible = "nvidia,tegra20-hdmi", },
1277 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001278 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001279 { .compatible = "nvidia,tegra30-dc", },
1280 { .compatible = "nvidia,tegra30-hdmi", },
1281 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001282 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001283 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001284 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001285 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001286 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001287 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001288 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001289 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001290 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001291 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001292 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001293 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001294 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001295 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001296 { .compatible = "nvidia,tegra210-vic", },
Thierry Redingc4755fb2017-11-13 11:08:13 +01001297 { .compatible = "nvidia,tegra186-display", },
Thierry Reding47307952017-08-30 17:42:54 +02001298 { .compatible = "nvidia,tegra186-dc", },
Mikko Perttunen6e44b9a2017-09-05 11:43:06 +03001299 { .compatible = "nvidia,tegra186-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001300 { /* sentinel */ }
1301};
1302
1303static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001304 .driver = {
1305 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001306 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001307 },
Thierry Reding776dc382013-10-14 14:43:22 +02001308 .probe = host1x_drm_probe,
1309 .remove = host1x_drm_remove,
1310 .subdevs = host1x_drm_subdevs,
1311};
1312
Thierry Reding473112e2015-09-10 16:07:14 +02001313static struct platform_driver * const drivers[] = {
Thierry Redingc4755fb2017-11-13 11:08:13 +01001314 &tegra_display_hub_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001315 &tegra_dc_driver,
1316 &tegra_hdmi_driver,
1317 &tegra_dsi_driver,
1318 &tegra_dpaux_driver,
1319 &tegra_sor_driver,
1320 &tegra_gr2d_driver,
1321 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001322 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001323};
1324
Thierry Reding776dc382013-10-14 14:43:22 +02001325static int __init host1x_drm_init(void)
1326{
1327 int err;
1328
1329 err = host1x_driver_register(&host1x_drm_driver);
1330 if (err < 0)
1331 return err;
1332
Thierry Reding473112e2015-09-10 16:07:14 +02001333 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001334 if (err < 0)
1335 goto unregister_host1x;
1336
Thierry Reding776dc382013-10-14 14:43:22 +02001337 return 0;
1338
Thierry Reding776dc382013-10-14 14:43:22 +02001339unregister_host1x:
1340 host1x_driver_unregister(&host1x_drm_driver);
1341 return err;
1342}
1343module_init(host1x_drm_init);
1344
1345static void __exit host1x_drm_exit(void)
1346{
Thierry Reding473112e2015-09-10 16:07:14 +02001347 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001348 host1x_driver_unregister(&host1x_drm_driver);
1349}
1350module_exit(host1x_drm_exit);
1351
1352MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1353MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1354MODULE_LICENSE("GPL v2");