blob: 90d876fc6ea76b731b3461dd84659dd8af9d3419 [file] [log] [blame]
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000018#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020019#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000020
21#define DRIVER_NAME "tegra"
22#define DRIVER_DESC "NVIDIA Tegra graphics"
23#define DRIVER_DATE "20120330"
24#define DRIVER_MAJOR 0
25#define DRIVER_MINOR 0
26#define DRIVER_PATCHLEVEL 0
27
Mikko Perttunenad926012016-12-14 13:16:11 +020028#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030029#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020030
Thierry Reding08943e62013-09-26 16:08:18 +020031struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010032 struct idr contexts;
33 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020034};
35
Thierry Reding31b02ca2017-10-12 17:40:46 +020036static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
Thierry Redingf9914212014-11-26 13:03:57 +010037 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +053038#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Redingf9914212014-11-26 13:03:57 +010039 .output_poll_changed = tegra_fb_output_poll_changed,
40#endif
Thierry Reding07866962014-11-24 17:08:06 +010041 .atomic_check = drm_atomic_helper_check,
Thierry Reding31b02ca2017-10-12 17:40:46 +020042 .atomic_commit = drm_atomic_helper_commit,
43};
44
45static const struct drm_mode_config_helper_funcs
46tegra_drm_mode_config_helpers = {
47 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
Thierry Redingf9914212014-11-26 13:03:57 +010048};
49
Thierry Reding776dc382013-10-14 14:43:22 +020050static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000051{
Thierry Reding776dc382013-10-14 14:43:22 +020052 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +020053 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000054 int err;
55
Thierry Reding776dc382013-10-14 14:43:22 +020056 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +020057 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +020058 return -ENOMEM;
59
Thierry Redingdf06b752014-06-26 21:41:53 +020060 if (iommu_present(&platform_bus_type)) {
Mikko Perttunenad926012016-12-14 13:16:11 +020061 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding4553f732015-01-19 16:15:04 +010062 struct iommu_domain_geometry *geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +020063 unsigned long order;
Thierry Reding4553f732015-01-19 16:15:04 +010064
Thierry Redingdf06b752014-06-26 21:41:53 +020065 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +030066 if (!tegra->domain) {
67 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +020068 goto free;
69 }
70
Thierry Reding4553f732015-01-19 16:15:04 +010071 geometry = &tegra->domain->geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +020072 gem_start = geometry->aperture_start;
73 gem_end = geometry->aperture_end - CARVEOUT_SZ;
74 carveout_start = gem_end + 1;
75 carveout_end = geometry->aperture_end;
Thierry Reding4553f732015-01-19 16:15:04 +010076
Mikko Perttunenad926012016-12-14 13:16:11 +020077 order = __ffs(tegra->domain->pgsize_bitmap);
78 init_iova_domain(&tegra->carveout.domain, 1UL << order,
Zhen Leiaa3ac942017-09-21 16:52:45 +010079 carveout_start >> order);
Mikko Perttunenad926012016-12-14 13:16:11 +020080
81 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
82 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
83
84 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
Thierry Reding347ad49d2017-03-09 20:04:56 +010085 mutex_init(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +020086
87 DRM_DEBUG("IOMMU apertures:\n");
88 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
89 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
90 carveout_end);
Thierry Redingdf06b752014-06-26 21:41:53 +020091 }
92
Thierry Reding386a2a72013-09-24 13:22:17 +020093 mutex_init(&tegra->clients_lock);
94 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +010095
Thierry Reding386a2a72013-09-24 13:22:17 +020096 drm->dev_private = tegra;
97 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000098
99 drm_mode_config_init(drm);
100
Thierry Redingf9914212014-11-26 13:03:57 +0100101 drm->mode_config.min_width = 0;
102 drm->mode_config.min_height = 0;
103
104 drm->mode_config.max_width = 4096;
105 drm->mode_config.max_height = 4096;
106
Alexandre Courbot5e911442016-11-08 16:50:42 +0900107 drm->mode_config.allow_fb_modifiers = true;
108
Thierry Reding31b02ca2017-10-12 17:40:46 +0200109 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
110 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
Thierry Redingf9914212014-11-26 13:03:57 +0100111
Thierry Redinge2215322014-06-27 17:19:25 +0200112 err = tegra_drm_fb_prepare(drm);
113 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100114 goto config;
Thierry Redinge2215322014-06-27 17:19:25 +0200115
116 drm_kms_helper_poll_init(drm);
117
Thierry Reding776dc382013-10-14 14:43:22 +0200118 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000119 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100120 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000121
Thierry Reding603f0cc2013-04-22 21:22:14 +0200122 /*
123 * We don't use the drm_irq_install() helpers provided by the DRM
124 * core, so we need to set this manually in order to allow the
125 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
126 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300127 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200128
Thierry Reding42e9ce02015-01-28 14:43:05 +0100129 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100130 drm->max_vblank_count = 0xffffffff;
131
Thierry Reding6e5ff992012-11-28 11:45:47 +0100132 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
133 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100134 goto device;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100135
Thierry Reding31930d42015-07-02 17:04:06 +0200136 drm_mode_config_reset(drm);
137
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000138 err = tegra_drm_fb_init(drm);
139 if (err < 0)
Daniel Vetter00a91212017-05-24 16:52:08 +0200140 goto device;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000141
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000142 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100143
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100144device:
145 host1x_device_exit(device);
146fbdev:
147 drm_kms_helper_poll_fini(drm);
148 tegra_drm_fb_free(drm);
149config:
150 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200151
152 if (tegra->domain) {
153 iommu_domain_free(tegra->domain);
154 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100155 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200156 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200157 }
158free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100159 kfree(tegra);
160 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000161}
162
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200163static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000164{
Thierry Reding776dc382013-10-14 14:43:22 +0200165 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200166 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200167 int err;
168
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000169 drm_kms_helper_poll_fini(drm);
170 tegra_drm_fb_exit(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200171 drm_mode_config_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000172
Thierry Reding776dc382013-10-14 14:43:22 +0200173 err = host1x_device_exit(device);
174 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200175 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200176
Thierry Redingdf06b752014-06-26 21:41:53 +0200177 if (tegra->domain) {
178 iommu_domain_free(tegra->domain);
179 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100180 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200181 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200182 }
183
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100184 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000185}
186
187static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
188{
Thierry Reding08943e62013-09-26 16:08:18 +0200189 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200190
191 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
192 if (!fpriv)
193 return -ENOMEM;
194
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100195 idr_init(&fpriv->contexts);
196 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200197 filp->driver_priv = fpriv;
198
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000199 return 0;
200}
201
Thierry Redingc88c3632013-09-26 16:08:22 +0200202static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200203{
204 context->client->ops->close_channel(context);
205 kfree(context);
206}
207
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000208static void tegra_drm_lastclose(struct drm_device *drm)
209{
Archit Tanejab110ef32015-10-27 13:40:59 +0530210#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding386a2a72013-09-24 13:22:17 +0200211 struct tegra_drm *tegra = drm->dev_private;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000212
Thierry Reding386a2a72013-09-24 13:22:17 +0200213 tegra_fbdev_restore_mode(tegra->fbdev);
Thierry Reding60c2f702013-10-31 13:28:50 +0100214#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000215}
216
Thierry Redingc40f0f12013-10-10 11:00:33 +0200217static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100218host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200219{
220 struct drm_gem_object *gem;
221 struct tegra_bo *bo;
222
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100223 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200224 if (!gem)
225 return NULL;
226
Thierry Redingc40f0f12013-10-10 11:00:33 +0200227 bo = to_tegra_bo(gem);
228 return &bo->base;
229}
230
Thierry Reding961e3be2014-06-10 10:25:00 +0200231static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
232 struct drm_tegra_reloc __user *src,
233 struct drm_device *drm,
234 struct drm_file *file)
235{
236 u32 cmdbuf, target;
237 int err;
238
239 err = get_user(cmdbuf, &src->cmdbuf.handle);
240 if (err < 0)
241 return err;
242
243 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
244 if (err < 0)
245 return err;
246
247 err = get_user(target, &src->target.handle);
248 if (err < 0)
249 return err;
250
David Ung31f40f82015-01-20 18:37:35 -0800251 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200252 if (err < 0)
253 return err;
254
255 err = get_user(dest->shift, &src->shift);
256 if (err < 0)
257 return err;
258
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100259 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200260 if (!dest->cmdbuf.bo)
261 return -ENOENT;
262
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100263 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200264 if (!dest->target.bo)
265 return -ENOENT;
266
267 return 0;
268}
269
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300270static int host1x_waitchk_copy_from_user(struct host1x_waitchk *dest,
271 struct drm_tegra_waitchk __user *src,
272 struct drm_file *file)
273{
274 u32 cmdbuf;
275 int err;
276
277 err = get_user(cmdbuf, &src->handle);
278 if (err < 0)
279 return err;
280
281 err = get_user(dest->offset, &src->offset);
282 if (err < 0)
283 return err;
284
285 err = get_user(dest->syncpt_id, &src->syncpt);
286 if (err < 0)
287 return err;
288
289 err = get_user(dest->thresh, &src->thresh);
290 if (err < 0)
291 return err;
292
293 dest->bo = host1x_bo_lookup(file, cmdbuf);
294 if (!dest->bo)
295 return -ENOENT;
296
297 return 0;
298}
299
Thierry Redingc40f0f12013-10-10 11:00:33 +0200300int tegra_drm_submit(struct tegra_drm_context *context,
301 struct drm_tegra_submit *args, struct drm_device *drm,
302 struct drm_file *file)
303{
304 unsigned int num_cmdbufs = args->num_cmdbufs;
305 unsigned int num_relocs = args->num_relocs;
306 unsigned int num_waitchks = args->num_waitchks;
Mikko Perttunena176c672017-09-28 15:50:44 +0300307 struct drm_tegra_cmdbuf __user *user_cmdbufs;
308 struct drm_tegra_reloc __user *user_relocs;
309 struct drm_tegra_waitchk __user *user_waitchks;
310 struct drm_tegra_syncpt __user *user_syncpt;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200311 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300312 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200313 struct drm_gem_object **refs;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300314 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200315 struct host1x_job *job;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200316 unsigned int num_refs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200317 int err;
318
Mikko Perttunena176c672017-09-28 15:50:44 +0300319 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
320 user_relocs = u64_to_user_ptr(args->relocs);
321 user_waitchks = u64_to_user_ptr(args->waitchks);
322 user_syncpt = u64_to_user_ptr(args->syncpts);
323
Thierry Redingc40f0f12013-10-10 11:00:33 +0200324 /* We don't yet support other than one syncpt_incr struct per submit */
325 if (args->num_syncpts != 1)
326 return -EINVAL;
327
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300328 /* We don't yet support waitchks */
329 if (args->num_waitchks != 0)
330 return -EINVAL;
331
Thierry Redingc40f0f12013-10-10 11:00:33 +0200332 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
333 args->num_relocs, args->num_waitchks);
334 if (!job)
335 return -ENOMEM;
336
337 job->num_relocs = args->num_relocs;
338 job->num_waitchk = args->num_waitchks;
339 job->client = (u32)args->context;
340 job->class = context->client->base.class;
341 job->serialize = true;
342
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200343 /*
344 * Track referenced BOs so that they can be unreferenced after the
345 * submission is complete.
346 */
347 num_refs = num_cmdbufs + num_relocs * 2 + num_waitchks;
348
349 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
350 if (!refs) {
351 err = -ENOMEM;
352 goto put;
353 }
354
355 /* reuse as an iterator later */
356 num_refs = 0;
357
Thierry Redingc40f0f12013-10-10 11:00:33 +0200358 while (num_cmdbufs) {
359 struct drm_tegra_cmdbuf cmdbuf;
360 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300361 struct tegra_bo *obj;
362 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200363
Mikko Perttunena176c672017-09-28 15:50:44 +0300364 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300365 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200366 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300367 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200368
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300369 /*
370 * The maximum number of CDMA gather fetches is 16383, a higher
371 * value means the words count is malformed.
372 */
373 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
374 err = -EINVAL;
375 goto fail;
376 }
377
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100378 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200379 if (!bo) {
380 err = -ENOENT;
381 goto fail;
382 }
383
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300384 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
385 obj = host1x_to_tegra_bo(bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200386 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300387
388 /*
389 * Gather buffer base address must be 4-bytes aligned,
390 * unaligned offset is malformed and cause commands stream
391 * corruption on the buffer address relocation.
392 */
393 if (offset & 3 || offset >= obj->gem.size) {
394 err = -EINVAL;
395 goto fail;
396 }
397
Thierry Redingc40f0f12013-10-10 11:00:33 +0200398 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
399 num_cmdbufs--;
Mikko Perttunena176c672017-09-28 15:50:44 +0300400 user_cmdbufs++;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200401 }
402
Thierry Reding961e3be2014-06-10 10:25:00 +0200403 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200404 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300405 struct host1x_reloc *reloc;
406 struct tegra_bo *obj;
407
Thierry Reding961e3be2014-06-10 10:25:00 +0200408 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
Mikko Perttunena176c672017-09-28 15:50:44 +0300409 &user_relocs[num_relocs], drm,
Thierry Reding961e3be2014-06-10 10:25:00 +0200410 file);
411 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200412 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300413
414 reloc = &job->relocarray[num_relocs];
415 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200416 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300417
418 /*
419 * The unaligned cmdbuf offset will cause an unaligned write
420 * during of the relocations patching, corrupting the commands
421 * stream.
422 */
423 if (reloc->cmdbuf.offset & 3 ||
424 reloc->cmdbuf.offset >= obj->gem.size) {
425 err = -EINVAL;
426 goto fail;
427 }
428
429 obj = host1x_to_tegra_bo(reloc->target.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200430 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300431
432 if (reloc->target.offset >= obj->gem.size) {
433 err = -EINVAL;
434 goto fail;
435 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200436 }
437
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300438 /* copy and resolve waitchks from submit */
439 while (num_waitchks--) {
440 struct host1x_waitchk *wait = &job->waitchk[num_waitchks];
441 struct tegra_bo *obj;
442
Mikko Perttunena176c672017-09-28 15:50:44 +0300443 err = host1x_waitchk_copy_from_user(
444 wait, &user_waitchks[num_waitchks], file);
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300445 if (err < 0)
446 goto fail;
447
448 obj = host1x_to_tegra_bo(wait->bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200449 refs[num_refs++] = &obj->gem;
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300450
451 /*
452 * The unaligned offset will cause an unaligned write during
453 * of the waitchks patching, corrupting the commands stream.
454 */
455 if (wait->offset & 3 ||
456 wait->offset >= obj->gem.size) {
457 err = -EINVAL;
458 goto fail;
459 }
Dan Carpenter9a991602013-11-08 13:07:37 +0300460 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200461
Mikko Perttunena176c672017-09-28 15:50:44 +0300462 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300463 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200464 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300465 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200466
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300467 /* check whether syncpoint ID is valid */
468 sp = host1x_syncpt_get(host1x, syncpt.id);
469 if (!sp) {
470 err = -ENOENT;
471 goto fail;
472 }
473
Thierry Redingc40f0f12013-10-10 11:00:33 +0200474 job->is_addr_reg = context->client->ops->is_addr_reg;
Dmitry Osipenko0f563a42017-06-15 02:18:37 +0300475 job->is_valid_class = context->client->ops->is_valid_class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200476 job->syncpt_incrs = syncpt.incrs;
477 job->syncpt_id = syncpt.id;
478 job->timeout = 10000;
479
480 if (args->timeout && args->timeout < 10000)
481 job->timeout = args->timeout;
482
483 err = host1x_job_pin(job, context->client->base.dev);
484 if (err)
485 goto fail;
486
487 err = host1x_job_submit(job);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200488 if (err) {
489 host1x_job_unpin(job);
490 goto fail;
491 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200492
493 args->fence = job->syncpt_end;
494
Thierry Redingc40f0f12013-10-10 11:00:33 +0200495fail:
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200496 while (num_refs--)
497 drm_gem_object_put_unlocked(refs[num_refs]);
498
499 kfree(refs);
500
501put:
Thierry Redingc40f0f12013-10-10 11:00:33 +0200502 host1x_job_put(job);
503 return err;
504}
505
506
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200507#ifdef CONFIG_DRM_TEGRA_STAGING
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200508static int tegra_gem_create(struct drm_device *drm, void *data,
509 struct drm_file *file)
510{
511 struct drm_tegra_gem_create *args = data;
512 struct tegra_bo *bo;
513
Thierry Reding773af772013-10-04 22:34:01 +0200514 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200515 &args->handle);
516 if (IS_ERR(bo))
517 return PTR_ERR(bo);
518
519 return 0;
520}
521
522static int tegra_gem_mmap(struct drm_device *drm, void *data,
523 struct drm_file *file)
524{
525 struct drm_tegra_gem_mmap *args = data;
526 struct drm_gem_object *gem;
527 struct tegra_bo *bo;
528
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100529 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200530 if (!gem)
531 return -EINVAL;
532
533 bo = to_tegra_bo(gem);
534
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200535 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200536
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300537 drm_gem_object_put_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200538
539 return 0;
540}
541
542static int tegra_syncpt_read(struct drm_device *drm, void *data,
543 struct drm_file *file)
544{
Thierry Reding776dc382013-10-14 14:43:22 +0200545 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200546 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200547 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200548
Thierry Reding776dc382013-10-14 14:43:22 +0200549 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200550 if (!sp)
551 return -EINVAL;
552
553 args->value = host1x_syncpt_read_min(sp);
554 return 0;
555}
556
557static int tegra_syncpt_incr(struct drm_device *drm, void *data,
558 struct drm_file *file)
559{
Thierry Reding776dc382013-10-14 14:43:22 +0200560 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200561 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200562 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200563
Thierry Reding776dc382013-10-14 14:43:22 +0200564 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200565 if (!sp)
566 return -EINVAL;
567
Arto Merilainenebae30b2013-05-29 13:26:08 +0300568 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200569}
570
571static int tegra_syncpt_wait(struct drm_device *drm, void *data,
572 struct drm_file *file)
573{
Thierry Reding776dc382013-10-14 14:43:22 +0200574 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200575 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200576 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200577
Thierry Reding776dc382013-10-14 14:43:22 +0200578 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200579 if (!sp)
580 return -EINVAL;
581
582 return host1x_syncpt_wait(sp, args->thresh, args->timeout,
583 &args->value);
584}
585
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100586static int tegra_client_open(struct tegra_drm_file *fpriv,
587 struct tegra_drm_client *client,
588 struct tegra_drm_context *context)
589{
590 int err;
591
592 err = client->ops->open_channel(client, context);
593 if (err < 0)
594 return err;
595
Dmitry Osipenkod6c153e2017-06-15 02:18:25 +0300596 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100597 if (err < 0) {
598 client->ops->close_channel(context);
599 return err;
600 }
601
602 context->client = client;
603 context->id = err;
604
605 return 0;
606}
607
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200608static int tegra_open_channel(struct drm_device *drm, void *data,
609 struct drm_file *file)
610{
Thierry Reding08943e62013-09-26 16:08:18 +0200611 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200612 struct tegra_drm *tegra = drm->dev_private;
613 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200614 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200615 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200616 int err = -ENODEV;
617
618 context = kzalloc(sizeof(*context), GFP_KERNEL);
619 if (!context)
620 return -ENOMEM;
621
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100622 mutex_lock(&fpriv->lock);
623
Thierry Reding776dc382013-10-14 14:43:22 +0200624 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200625 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100626 err = tegra_client_open(fpriv, client, context);
627 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200628 break;
629
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100630 args->context = context->id;
631 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200632 }
633
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100634 if (err < 0)
635 kfree(context);
636
637 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200638 return err;
639}
640
641static int tegra_close_channel(struct drm_device *drm, void *data,
642 struct drm_file *file)
643{
Thierry Reding08943e62013-09-26 16:08:18 +0200644 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200645 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200646 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100647 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200648
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100649 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200650
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300651 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100652 if (!context) {
653 err = -EINVAL;
654 goto unlock;
655 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200656
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100657 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200658 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200659
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100660unlock:
661 mutex_unlock(&fpriv->lock);
662 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200663}
664
665static int tegra_get_syncpt(struct drm_device *drm, void *data,
666 struct drm_file *file)
667{
Thierry Reding08943e62013-09-26 16:08:18 +0200668 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200669 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200670 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200671 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100672 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200673
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100674 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200675
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300676 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100677 if (!context) {
678 err = -ENODEV;
679 goto unlock;
680 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200681
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100682 if (args->index >= context->client->base.num_syncpts) {
683 err = -EINVAL;
684 goto unlock;
685 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200686
Thierry Reding53fa7f72013-09-24 15:35:40 +0200687 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200688 args->id = host1x_syncpt_id(syncpt);
689
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100690unlock:
691 mutex_unlock(&fpriv->lock);
692 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200693}
694
695static int tegra_submit(struct drm_device *drm, void *data,
696 struct drm_file *file)
697{
Thierry Reding08943e62013-09-26 16:08:18 +0200698 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200699 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200700 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100701 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200702
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100703 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200704
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300705 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100706 if (!context) {
707 err = -ENODEV;
708 goto unlock;
709 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200710
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100711 err = context->client->ops->submit(context, args, drm, file);
712
713unlock:
714 mutex_unlock(&fpriv->lock);
715 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200716}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300717
718static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
719 struct drm_file *file)
720{
721 struct tegra_drm_file *fpriv = file->driver_priv;
722 struct drm_tegra_get_syncpt_base *args = data;
723 struct tegra_drm_context *context;
724 struct host1x_syncpt_base *base;
725 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100726 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300727
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100728 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300729
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300730 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100731 if (!context) {
732 err = -ENODEV;
733 goto unlock;
734 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300735
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100736 if (args->syncpt >= context->client->base.num_syncpts) {
737 err = -EINVAL;
738 goto unlock;
739 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300740
741 syncpt = context->client->base.syncpts[args->syncpt];
742
743 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100744 if (!base) {
745 err = -ENXIO;
746 goto unlock;
747 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300748
749 args->id = host1x_syncpt_base_id(base);
750
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100751unlock:
752 mutex_unlock(&fpriv->lock);
753 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300754}
Thierry Reding7678d712014-06-03 14:56:57 +0200755
756static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
757 struct drm_file *file)
758{
759 struct drm_tegra_gem_set_tiling *args = data;
760 enum tegra_bo_tiling_mode mode;
761 struct drm_gem_object *gem;
762 unsigned long value = 0;
763 struct tegra_bo *bo;
764
765 switch (args->mode) {
766 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
767 mode = TEGRA_BO_TILING_MODE_PITCH;
768
769 if (args->value != 0)
770 return -EINVAL;
771
772 break;
773
774 case DRM_TEGRA_GEM_TILING_MODE_TILED:
775 mode = TEGRA_BO_TILING_MODE_TILED;
776
777 if (args->value != 0)
778 return -EINVAL;
779
780 break;
781
782 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
783 mode = TEGRA_BO_TILING_MODE_BLOCK;
784
785 if (args->value > 5)
786 return -EINVAL;
787
788 value = args->value;
789 break;
790
791 default:
792 return -EINVAL;
793 }
794
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100795 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200796 if (!gem)
797 return -ENOENT;
798
799 bo = to_tegra_bo(gem);
800
801 bo->tiling.mode = mode;
802 bo->tiling.value = value;
803
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300804 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200805
806 return 0;
807}
808
809static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
810 struct drm_file *file)
811{
812 struct drm_tegra_gem_get_tiling *args = data;
813 struct drm_gem_object *gem;
814 struct tegra_bo *bo;
815 int err = 0;
816
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100817 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200818 if (!gem)
819 return -ENOENT;
820
821 bo = to_tegra_bo(gem);
822
823 switch (bo->tiling.mode) {
824 case TEGRA_BO_TILING_MODE_PITCH:
825 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
826 args->value = 0;
827 break;
828
829 case TEGRA_BO_TILING_MODE_TILED:
830 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
831 args->value = 0;
832 break;
833
834 case TEGRA_BO_TILING_MODE_BLOCK:
835 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
836 args->value = bo->tiling.value;
837 break;
838
839 default:
840 err = -EINVAL;
841 break;
842 }
843
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300844 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200845
846 return err;
847}
Thierry Reding7b129082014-06-10 12:04:03 +0200848
849static int tegra_gem_set_flags(struct drm_device *drm, void *data,
850 struct drm_file *file)
851{
852 struct drm_tegra_gem_set_flags *args = data;
853 struct drm_gem_object *gem;
854 struct tegra_bo *bo;
855
856 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
857 return -EINVAL;
858
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100859 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200860 if (!gem)
861 return -ENOENT;
862
863 bo = to_tegra_bo(gem);
864 bo->flags = 0;
865
866 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
867 bo->flags |= TEGRA_BO_BOTTOM_UP;
868
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300869 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200870
871 return 0;
872}
873
874static int tegra_gem_get_flags(struct drm_device *drm, void *data,
875 struct drm_file *file)
876{
877 struct drm_tegra_gem_get_flags *args = data;
878 struct drm_gem_object *gem;
879 struct tegra_bo *bo;
880
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100881 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200882 if (!gem)
883 return -ENOENT;
884
885 bo = to_tegra_bo(gem);
886 args->flags = 0;
887
888 if (bo->flags & TEGRA_BO_BOTTOM_UP)
889 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
890
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300891 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200892
893 return 0;
894}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200895#endif
896
Rob Clarkbaa70942013-08-02 13:27:49 -0400897static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200898#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Reding6c68b712017-08-15 15:42:39 +0200899 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
900 DRM_UNLOCKED | DRM_RENDER_ALLOW),
901 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
902 DRM_UNLOCKED | DRM_RENDER_ALLOW),
903 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
904 DRM_UNLOCKED | DRM_RENDER_ALLOW),
905 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
906 DRM_UNLOCKED | DRM_RENDER_ALLOW),
907 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
908 DRM_UNLOCKED | DRM_RENDER_ALLOW),
909 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
910 DRM_UNLOCKED | DRM_RENDER_ALLOW),
911 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
912 DRM_UNLOCKED | DRM_RENDER_ALLOW),
913 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
914 DRM_UNLOCKED | DRM_RENDER_ALLOW),
915 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
916 DRM_UNLOCKED | DRM_RENDER_ALLOW),
917 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
918 DRM_UNLOCKED | DRM_RENDER_ALLOW),
919 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
920 DRM_UNLOCKED | DRM_RENDER_ALLOW),
921 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
922 DRM_UNLOCKED | DRM_RENDER_ALLOW),
923 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
924 DRM_UNLOCKED | DRM_RENDER_ALLOW),
925 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
926 DRM_UNLOCKED | DRM_RENDER_ALLOW),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200927#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000928};
929
930static const struct file_operations tegra_drm_fops = {
931 .owner = THIS_MODULE,
932 .open = drm_open,
933 .release = drm_release,
934 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +0200935 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000936 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000937 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000938 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000939 .llseek = noop_llseek,
940};
941
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100942static int tegra_drm_context_cleanup(int id, void *p, void *data)
943{
944 struct tegra_drm_context *context = p;
945
946 tegra_drm_context_free(context);
947
948 return 0;
949}
950
Daniel Vetterbda0ecc2017-05-08 10:26:31 +0200951static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
Thierry Reding3c03c462012-11-28 12:00:18 +0100952{
Thierry Reding08943e62013-09-26 16:08:18 +0200953 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +0100954
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100955 mutex_lock(&fpriv->lock);
956 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
957 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200958
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100959 idr_destroy(&fpriv->contexts);
960 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200961 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +0100962}
963
Thierry Redinge450fcc2013-02-13 16:13:16 +0100964#ifdef CONFIG_DEBUG_FS
965static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
966{
967 struct drm_info_node *node = (struct drm_info_node *)s->private;
968 struct drm_device *drm = node->minor->dev;
969 struct drm_framebuffer *fb;
970
971 mutex_lock(&drm->mode_config.fb_lock);
972
973 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
974 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +0200975 fb->base.id, fb->width, fb->height,
976 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +0200977 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +1000978 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +0100979 }
980
981 mutex_unlock(&drm->mode_config.fb_lock);
982
983 return 0;
984}
985
Thierry Reding28c23372015-01-23 09:16:03 +0100986static int tegra_debugfs_iova(struct seq_file *s, void *data)
987{
988 struct drm_info_node *node = (struct drm_info_node *)s->private;
989 struct drm_device *drm = node->minor->dev;
990 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +0100991 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +0100992
Michał Mirosław68d890a2017-08-14 23:53:45 +0200993 if (tegra->domain) {
994 mutex_lock(&tegra->mm_lock);
995 drm_mm_print(&tegra->mm, &p);
996 mutex_unlock(&tegra->mm_lock);
997 }
Daniel Vetterb5c37142016-12-29 12:09:24 +0100998
999 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +01001000}
1001
Thierry Redinge450fcc2013-02-13 16:13:16 +01001002static struct drm_info_list tegra_debugfs_list[] = {
1003 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +01001004 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +01001005};
1006
1007static int tegra_debugfs_init(struct drm_minor *minor)
1008{
1009 return drm_debugfs_create_files(tegra_debugfs_list,
1010 ARRAY_SIZE(tegra_debugfs_list),
1011 minor->debugfs_root, minor);
1012}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001013#endif
1014
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001015static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +02001016 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
Thierry Reding6c68b712017-08-15 15:42:39 +02001017 DRIVER_ATOMIC | DRIVER_RENDER,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001018 .load = tegra_drm_load,
1019 .unload = tegra_drm_unload,
1020 .open = tegra_drm_open,
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001021 .postclose = tegra_drm_postclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001022 .lastclose = tegra_drm_lastclose,
1023
Thierry Redinge450fcc2013-02-13 16:13:16 +01001024#if defined(CONFIG_DEBUG_FS)
1025 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001026#endif
1027
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001028 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001029 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001030
1031 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1032 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1033 .gem_prime_export = tegra_gem_prime_export,
1034 .gem_prime_import = tegra_gem_prime_import,
1035
Arto Merilainende2ba662013-03-22 16:34:08 +02001036 .dumb_create = tegra_bo_dumb_create,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001037
1038 .ioctls = tegra_drm_ioctls,
1039 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1040 .fops = &tegra_drm_fops,
1041
1042 .name = DRIVER_NAME,
1043 .desc = DRIVER_DESC,
1044 .date = DRIVER_DATE,
1045 .major = DRIVER_MAJOR,
1046 .minor = DRIVER_MINOR,
1047 .patchlevel = DRIVER_PATCHLEVEL,
1048};
Thierry Reding776dc382013-10-14 14:43:22 +02001049
1050int tegra_drm_register_client(struct tegra_drm *tegra,
1051 struct tegra_drm_client *client)
1052{
1053 mutex_lock(&tegra->clients_lock);
1054 list_add_tail(&client->list, &tegra->clients);
1055 mutex_unlock(&tegra->clients_lock);
1056
1057 return 0;
1058}
1059
1060int tegra_drm_unregister_client(struct tegra_drm *tegra,
1061 struct tegra_drm_client *client)
1062{
1063 mutex_lock(&tegra->clients_lock);
1064 list_del_init(&client->list);
1065 mutex_unlock(&tegra->clients_lock);
1066
1067 return 0;
1068}
1069
Thierry Reding67485fb2017-11-09 13:17:11 +01001070void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
Mikko Perttunenad926012016-12-14 13:16:11 +02001071{
1072 struct iova *alloc;
1073 void *virt;
1074 gfp_t gfp;
1075 int err;
1076
1077 if (tegra->domain)
1078 size = iova_align(&tegra->carveout.domain, size);
1079 else
1080 size = PAGE_ALIGN(size);
1081
1082 gfp = GFP_KERNEL | __GFP_ZERO;
1083 if (!tegra->domain) {
1084 /*
1085 * Many units only support 32-bit addresses, even on 64-bit
1086 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1087 * virtual address space, force allocations to be in the
1088 * lower 32-bit range.
1089 */
1090 gfp |= GFP_DMA;
1091 }
1092
1093 virt = (void *)__get_free_pages(gfp, get_order(size));
1094 if (!virt)
1095 return ERR_PTR(-ENOMEM);
1096
1097 if (!tegra->domain) {
1098 /*
1099 * If IOMMU is disabled, devices address physical memory
1100 * directly.
1101 */
1102 *dma = virt_to_phys(virt);
1103 return virt;
1104 }
1105
1106 alloc = alloc_iova(&tegra->carveout.domain,
1107 size >> tegra->carveout.shift,
1108 tegra->carveout.limit, true);
1109 if (!alloc) {
1110 err = -EBUSY;
1111 goto free_pages;
1112 }
1113
1114 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1115 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1116 size, IOMMU_READ | IOMMU_WRITE);
1117 if (err < 0)
1118 goto free_iova;
1119
1120 return virt;
1121
1122free_iova:
1123 __free_iova(&tegra->carveout.domain, alloc);
1124free_pages:
1125 free_pages((unsigned long)virt, get_order(size));
1126
1127 return ERR_PTR(err);
1128}
1129
1130void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1131 dma_addr_t dma)
1132{
1133 if (tegra->domain)
1134 size = iova_align(&tegra->carveout.domain, size);
1135 else
1136 size = PAGE_ALIGN(size);
1137
1138 if (tegra->domain) {
1139 iommu_unmap(tegra->domain, dma, size);
1140 free_iova(&tegra->carveout.domain,
1141 iova_pfn(&tegra->carveout.domain, dma));
1142 }
1143
1144 free_pages((unsigned long)virt, get_order(size));
1145}
1146
Thierry Reding9910f5c2014-05-22 09:57:15 +02001147static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001148{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001149 struct drm_driver *driver = &tegra_drm_driver;
1150 struct drm_device *drm;
1151 int err;
1152
1153 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001154 if (IS_ERR(drm))
1155 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001156
Thierry Reding9910f5c2014-05-22 09:57:15 +02001157 dev_set_drvdata(&dev->dev, drm);
1158
1159 err = drm_dev_register(drm, 0);
1160 if (err < 0)
1161 goto unref;
1162
Thierry Reding9910f5c2014-05-22 09:57:15 +02001163 return 0;
1164
1165unref:
1166 drm_dev_unref(drm);
1167 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001168}
1169
Thierry Reding9910f5c2014-05-22 09:57:15 +02001170static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001171{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001172 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1173
1174 drm_dev_unregister(drm);
1175 drm_dev_unref(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001176
1177 return 0;
1178}
1179
Thierry Reding359ae682014-12-18 17:15:25 +01001180#ifdef CONFIG_PM_SLEEP
1181static int host1x_drm_suspend(struct device *dev)
1182{
1183 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001184 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001185
1186 drm_kms_helper_poll_disable(drm);
Thierry Reding986c58d2015-08-11 13:11:49 +02001187 tegra_drm_fb_suspend(drm);
1188
1189 tegra->state = drm_atomic_helper_suspend(drm);
1190 if (IS_ERR(tegra->state)) {
1191 tegra_drm_fb_resume(drm);
1192 drm_kms_helper_poll_enable(drm);
1193 return PTR_ERR(tegra->state);
1194 }
Thierry Reding359ae682014-12-18 17:15:25 +01001195
1196 return 0;
1197}
1198
1199static int host1x_drm_resume(struct device *dev)
1200{
1201 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001202 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001203
Thierry Reding986c58d2015-08-11 13:11:49 +02001204 drm_atomic_helper_resume(drm, tegra->state);
1205 tegra_drm_fb_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001206 drm_kms_helper_poll_enable(drm);
1207
1208 return 0;
1209}
1210#endif
1211
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001212static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1213 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001214
Thierry Reding776dc382013-10-14 14:43:22 +02001215static const struct of_device_id host1x_drm_subdevs[] = {
1216 { .compatible = "nvidia,tegra20-dc", },
1217 { .compatible = "nvidia,tegra20-hdmi", },
1218 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001219 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001220 { .compatible = "nvidia,tegra30-dc", },
1221 { .compatible = "nvidia,tegra30-hdmi", },
1222 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001223 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001224 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001225 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001226 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001227 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001228 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001229 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001230 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001231 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001232 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001233 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001234 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001235 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001236 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001237 { .compatible = "nvidia,tegra210-vic", },
Mikko Perttunen6e44b9a2017-09-05 11:43:06 +03001238 { .compatible = "nvidia,tegra186-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001239 { /* sentinel */ }
1240};
1241
1242static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001243 .driver = {
1244 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001245 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001246 },
Thierry Reding776dc382013-10-14 14:43:22 +02001247 .probe = host1x_drm_probe,
1248 .remove = host1x_drm_remove,
1249 .subdevs = host1x_drm_subdevs,
1250};
1251
Thierry Reding473112e2015-09-10 16:07:14 +02001252static struct platform_driver * const drivers[] = {
1253 &tegra_dc_driver,
1254 &tegra_hdmi_driver,
1255 &tegra_dsi_driver,
1256 &tegra_dpaux_driver,
1257 &tegra_sor_driver,
1258 &tegra_gr2d_driver,
1259 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001260 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001261};
1262
Thierry Reding776dc382013-10-14 14:43:22 +02001263static int __init host1x_drm_init(void)
1264{
1265 int err;
1266
1267 err = host1x_driver_register(&host1x_drm_driver);
1268 if (err < 0)
1269 return err;
1270
Thierry Reding473112e2015-09-10 16:07:14 +02001271 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001272 if (err < 0)
1273 goto unregister_host1x;
1274
Thierry Reding776dc382013-10-14 14:43:22 +02001275 return 0;
1276
Thierry Reding776dc382013-10-14 14:43:22 +02001277unregister_host1x:
1278 host1x_driver_unregister(&host1x_drm_driver);
1279 return err;
1280}
1281module_init(host1x_drm_init);
1282
1283static void __exit host1x_drm_exit(void)
1284{
Thierry Reding473112e2015-09-10 16:07:14 +02001285 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001286 host1x_driver_unregister(&host1x_drm_driver);
1287}
1288module_exit(host1x_drm_exit);
1289
1290MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1291MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1292MODULE_LICENSE("GPL v2");