blob: 5ba3b04cc9b134843070a1728e2a900f38f3f6e9 [file] [log] [blame]
Carlo Caionecfb61a42014-05-01 14:29:27 +02001/*
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +08002 * MFD core driver for the X-Powers' Power Management ICs
Carlo Caionecfb61a42014-05-01 14:29:27 +02003 *
Jacob Panaf7e9062014-10-06 21:17:14 -07004 * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC
5 * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
6 * as well as configurable GPIOs.
Carlo Caionecfb61a42014-05-01 14:29:27 +02007 *
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +08008 * This file contains the interface independent core functions.
9 *
Chen-Yu Tsaie7402352016-02-12 10:02:41 +080010 * Copyright (C) 2014 Carlo Caione
11 *
Carlo Caionecfb61a42014-05-01 14:29:27 +020012 * Author: Carlo Caione <carlo@caione.org>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/err.h>
Hans de Goede179dc632016-06-05 15:50:48 +020020#include <linux/delay.h>
Carlo Caionecfb61a42014-05-01 14:29:27 +020021#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/pm_runtime.h>
25#include <linux/regmap.h>
Carlo Caionecfb61a42014-05-01 14:29:27 +020026#include <linux/regulator/consumer.h>
27#include <linux/mfd/axp20x.h>
28#include <linux/mfd/core.h>
29#include <linux/of_device.h>
Jacob Panaf7e9062014-10-06 21:17:14 -070030#include <linux/acpi.h>
Carlo Caionecfb61a42014-05-01 14:29:27 +020031
32#define AXP20X_OFF 0x80
33
Rask Ingemann Lambertsenc0369692017-02-22 20:42:02 +010034#define AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE 0
Chen-Yu Tsai696f0b32017-01-05 12:01:03 +080035#define AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE BIT(4)
36
Krzysztof Kozlowskic31e8582015-03-24 11:21:17 +010037static const char * const axp20x_model_names[] = {
Michal Suchanekd8d79f82015-07-11 14:59:56 +020038 "AXP152",
Jacob Panaf7e9062014-10-06 21:17:14 -070039 "AXP202",
40 "AXP209",
Boris BREZILLONf05be582015-04-10 12:09:01 +080041 "AXP221",
Chen-Yu Tsai02071f02016-02-12 10:02:44 +080042 "AXP223",
Jacob Panaf7e9062014-10-06 21:17:14 -070043 "AXP288",
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +080044 "AXP806",
Chen-Yu Tsai20147f02016-03-29 17:22:26 +080045 "AXP809",
Jacob Panaf7e9062014-10-06 21:17:14 -070046};
47
Michal Suchanekd8d79f82015-07-11 14:59:56 +020048static const struct regmap_range axp152_writeable_ranges[] = {
49 regmap_reg_range(AXP152_LDO3456_DC1234_CTRL, AXP152_IRQ3_STATE),
50 regmap_reg_range(AXP152_DCDC_MODE, AXP152_PWM1_DUTY_CYCLE),
51};
52
53static const struct regmap_range axp152_volatile_ranges[] = {
54 regmap_reg_range(AXP152_PWR_OP_MODE, AXP152_PWR_OP_MODE),
55 regmap_reg_range(AXP152_IRQ1_EN, AXP152_IRQ3_STATE),
56 regmap_reg_range(AXP152_GPIO_INPUT, AXP152_GPIO_INPUT),
57};
58
59static const struct regmap_access_table axp152_writeable_table = {
60 .yes_ranges = axp152_writeable_ranges,
61 .n_yes_ranges = ARRAY_SIZE(axp152_writeable_ranges),
62};
63
64static const struct regmap_access_table axp152_volatile_table = {
65 .yes_ranges = axp152_volatile_ranges,
66 .n_yes_ranges = ARRAY_SIZE(axp152_volatile_ranges),
67};
68
Carlo Caionecfb61a42014-05-01 14:29:27 +020069static const struct regmap_range axp20x_writeable_ranges[] = {
70 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
Quentin Schulz97602372017-03-20 09:16:53 +010071 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
Carlo Caionecfb61a42014-05-01 14:29:27 +020072 regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES),
Bruno Prémont553ed4b2015-08-08 17:58:40 +020073 regmap_reg_range(AXP20X_RDC_H, AXP20X_OCV(AXP20X_OCV_MAX)),
Carlo Caionecfb61a42014-05-01 14:29:27 +020074};
75
76static const struct regmap_range axp20x_volatile_ranges[] = {
Bruno Prémont553ed4b2015-08-08 17:58:40 +020077 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_USB_OTG_STATUS),
78 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
Carlo Caionecfb61a42014-05-01 14:29:27 +020079 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
Bruno Prémont553ed4b2015-08-08 17:58:40 +020080 regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
81 regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL),
82 regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L),
Carlo Caionecfb61a42014-05-01 14:29:27 +020083};
84
85static const struct regmap_access_table axp20x_writeable_table = {
86 .yes_ranges = axp20x_writeable_ranges,
87 .n_yes_ranges = ARRAY_SIZE(axp20x_writeable_ranges),
88};
89
90static const struct regmap_access_table axp20x_volatile_table = {
91 .yes_ranges = axp20x_volatile_ranges,
92 .n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges),
93};
94
Chen-Yu Tsai20147f02016-03-29 17:22:26 +080095/* AXP22x ranges are shared with the AXP809, as they cover the same range */
Boris BREZILLONf05be582015-04-10 12:09:01 +080096static const struct regmap_range axp22x_writeable_ranges[] = {
97 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
Quentin Schulz97602372017-03-20 09:16:53 +010098 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP22X_CHRG_CTRL3),
Boris BREZILLONf05be582015-04-10 12:09:01 +080099 regmap_reg_range(AXP20X_DCDC_MODE, AXP22X_BATLOW_THRES1),
100};
101
102static const struct regmap_range axp22x_volatile_ranges[] = {
Hans de Goede15093252016-05-14 19:51:28 +0200103 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_PWR_OP_MODE),
Boris BREZILLONf05be582015-04-10 12:09:01 +0800104 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
Hans de Goede15093252016-05-14 19:51:28 +0200105 regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
Quentin Schulzed7311f2017-03-20 09:16:45 +0100106 regmap_reg_range(AXP22X_PMIC_TEMP_H, AXP20X_IPSOUT_V_HIGH_L),
Hans de Goede15093252016-05-14 19:51:28 +0200107 regmap_reg_range(AXP20X_FG_RES, AXP20X_FG_RES),
Boris BREZILLONf05be582015-04-10 12:09:01 +0800108};
109
110static const struct regmap_access_table axp22x_writeable_table = {
111 .yes_ranges = axp22x_writeable_ranges,
112 .n_yes_ranges = ARRAY_SIZE(axp22x_writeable_ranges),
113};
114
115static const struct regmap_access_table axp22x_volatile_table = {
116 .yes_ranges = axp22x_volatile_ranges,
117 .n_yes_ranges = ARRAY_SIZE(axp22x_volatile_ranges),
118};
119
Jacob Panaf7e9062014-10-06 21:17:14 -0700120static const struct regmap_range axp288_writeable_ranges[] = {
121 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE),
122 regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5),
123};
124
125static const struct regmap_range axp288_volatile_ranges[] = {
Hans de Goedecd532162016-12-16 21:09:06 +0100126 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP288_POWER_REASON),
127 regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL),
128 regmap_reg_range(AXP288_BC_DET_STAT, AXP288_BC_DET_STAT),
Jacob Panaf7e9062014-10-06 21:17:14 -0700129 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
Hans de Goedecd532162016-12-16 21:09:06 +0100130 regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
131 regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
132 regmap_reg_range(AXP288_RT_BATT_V_H, AXP288_RT_BATT_V_L),
133 regmap_reg_range(AXP20X_FG_RES, AXP288_FG_CC_CAP_REG),
Jacob Panaf7e9062014-10-06 21:17:14 -0700134};
135
136static const struct regmap_access_table axp288_writeable_table = {
137 .yes_ranges = axp288_writeable_ranges,
138 .n_yes_ranges = ARRAY_SIZE(axp288_writeable_ranges),
139};
140
141static const struct regmap_access_table axp288_volatile_table = {
142 .yes_ranges = axp288_volatile_ranges,
143 .n_yes_ranges = ARRAY_SIZE(axp288_volatile_ranges),
144};
145
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800146static const struct regmap_range axp806_writeable_ranges[] = {
147 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_DATACACHE(3)),
148 regmap_reg_range(AXP806_PWR_OUT_CTRL1, AXP806_CLDO3_V_CTRL),
149 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ2_EN),
150 regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
Chen-Yu Tsai34d90302016-11-11 11:29:52 +0800151 regmap_reg_range(AXP806_REG_ADDR_EXT, AXP806_REG_ADDR_EXT),
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800152};
153
154static const struct regmap_range axp806_volatile_ranges[] = {
155 regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
156};
157
158static const struct regmap_access_table axp806_writeable_table = {
159 .yes_ranges = axp806_writeable_ranges,
160 .n_yes_ranges = ARRAY_SIZE(axp806_writeable_ranges),
161};
162
163static const struct regmap_access_table axp806_volatile_table = {
164 .yes_ranges = axp806_volatile_ranges,
165 .n_yes_ranges = ARRAY_SIZE(axp806_volatile_ranges),
166};
167
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200168static struct resource axp152_pek_resources[] = {
169 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
170 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
171};
172
Michael Haascd7cf272016-05-06 07:19:49 +0200173static struct resource axp20x_ac_power_supply_resources[] = {
174 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"),
175 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"),
176 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"),
177};
178
Carlo Caionecfb61a42014-05-01 14:29:27 +0200179static struct resource axp20x_pek_resources[] = {
180 {
181 .name = "PEK_DBR",
182 .start = AXP20X_IRQ_PEK_RIS_EDGE,
183 .end = AXP20X_IRQ_PEK_RIS_EDGE,
184 .flags = IORESOURCE_IRQ,
185 }, {
186 .name = "PEK_DBF",
187 .start = AXP20X_IRQ_PEK_FAL_EDGE,
188 .end = AXP20X_IRQ_PEK_FAL_EDGE,
189 .flags = IORESOURCE_IRQ,
190 },
191};
192
Hans de Goede8de4efd2015-08-08 17:58:41 +0200193static struct resource axp20x_usb_power_supply_resources[] = {
194 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
195 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
196 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_VALID, "VBUS_VALID"),
197 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"),
198};
199
Hans de Goedeecd98cc2016-06-02 19:18:55 +0200200static struct resource axp22x_usb_power_supply_resources[] = {
201 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
202 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
203};
204
Boris BREZILLONf05be582015-04-10 12:09:01 +0800205static struct resource axp22x_pek_resources[] = {
206 {
207 .name = "PEK_DBR",
208 .start = AXP22X_IRQ_PEK_RIS_EDGE,
209 .end = AXP22X_IRQ_PEK_RIS_EDGE,
210 .flags = IORESOURCE_IRQ,
211 }, {
212 .name = "PEK_DBF",
213 .start = AXP22X_IRQ_PEK_FAL_EDGE,
214 .end = AXP22X_IRQ_PEK_FAL_EDGE,
215 .flags = IORESOURCE_IRQ,
216 },
217};
218
Borun Fue56e5ad2015-10-14 16:16:26 +0800219static struct resource axp288_power_button_resources[] = {
220 {
221 .name = "PEK_DBR",
Hans de Goede1af468e2016-12-14 14:52:07 +0100222 .start = AXP288_IRQ_POKP,
223 .end = AXP288_IRQ_POKP,
Borun Fue56e5ad2015-10-14 16:16:26 +0800224 .flags = IORESOURCE_IRQ,
225 },
226 {
227 .name = "PEK_DBF",
Hans de Goede1af468e2016-12-14 14:52:07 +0100228 .start = AXP288_IRQ_POKN,
229 .end = AXP288_IRQ_POKN,
Borun Fue56e5ad2015-10-14 16:16:26 +0800230 .flags = IORESOURCE_IRQ,
231 },
232};
233
Todd Brandtd63878742015-02-02 15:41:41 -0800234static struct resource axp288_fuel_gauge_resources[] = {
Jacob Panaf7e9062014-10-06 21:17:14 -0700235 {
236 .start = AXP288_IRQ_QWBTU,
237 .end = AXP288_IRQ_QWBTU,
238 .flags = IORESOURCE_IRQ,
239 },
240 {
241 .start = AXP288_IRQ_WBTU,
242 .end = AXP288_IRQ_WBTU,
243 .flags = IORESOURCE_IRQ,
244 },
245 {
246 .start = AXP288_IRQ_QWBTO,
247 .end = AXP288_IRQ_QWBTO,
248 .flags = IORESOURCE_IRQ,
249 },
250 {
251 .start = AXP288_IRQ_WBTO,
252 .end = AXP288_IRQ_WBTO,
253 .flags = IORESOURCE_IRQ,
254 },
255 {
256 .start = AXP288_IRQ_WL2,
257 .end = AXP288_IRQ_WL2,
258 .flags = IORESOURCE_IRQ,
259 },
260 {
261 .start = AXP288_IRQ_WL1,
262 .end = AXP288_IRQ_WL1,
263 .flags = IORESOURCE_IRQ,
264 },
265};
266
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800267static struct resource axp809_pek_resources[] = {
268 {
269 .name = "PEK_DBR",
270 .start = AXP809_IRQ_PEK_RIS_EDGE,
271 .end = AXP809_IRQ_PEK_RIS_EDGE,
272 .flags = IORESOURCE_IRQ,
273 }, {
274 .name = "PEK_DBF",
275 .start = AXP809_IRQ_PEK_FAL_EDGE,
276 .end = AXP809_IRQ_PEK_FAL_EDGE,
277 .flags = IORESOURCE_IRQ,
278 },
279};
280
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200281static const struct regmap_config axp152_regmap_config = {
282 .reg_bits = 8,
283 .val_bits = 8,
284 .wr_table = &axp152_writeable_table,
285 .volatile_table = &axp152_volatile_table,
286 .max_register = AXP152_PWM1_DUTY_CYCLE,
287 .cache_type = REGCACHE_RBTREE,
288};
289
Carlo Caionecfb61a42014-05-01 14:29:27 +0200290static const struct regmap_config axp20x_regmap_config = {
291 .reg_bits = 8,
292 .val_bits = 8,
293 .wr_table = &axp20x_writeable_table,
294 .volatile_table = &axp20x_volatile_table,
Bruno Prémont553ed4b2015-08-08 17:58:40 +0200295 .max_register = AXP20X_OCV(AXP20X_OCV_MAX),
Carlo Caionecfb61a42014-05-01 14:29:27 +0200296 .cache_type = REGCACHE_RBTREE,
297};
298
Boris BREZILLONf05be582015-04-10 12:09:01 +0800299static const struct regmap_config axp22x_regmap_config = {
300 .reg_bits = 8,
301 .val_bits = 8,
302 .wr_table = &axp22x_writeable_table,
303 .volatile_table = &axp22x_volatile_table,
304 .max_register = AXP22X_BATLOW_THRES1,
305 .cache_type = REGCACHE_RBTREE,
306};
307
Jacob Panaf7e9062014-10-06 21:17:14 -0700308static const struct regmap_config axp288_regmap_config = {
309 .reg_bits = 8,
310 .val_bits = 8,
311 .wr_table = &axp288_writeable_table,
312 .volatile_table = &axp288_volatile_table,
313 .max_register = AXP288_FG_TUNE5,
314 .cache_type = REGCACHE_RBTREE,
315};
316
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800317static const struct regmap_config axp806_regmap_config = {
318 .reg_bits = 8,
319 .val_bits = 8,
320 .wr_table = &axp806_writeable_table,
321 .volatile_table = &axp806_volatile_table,
Chen-Yu Tsai34d90302016-11-11 11:29:52 +0800322 .max_register = AXP806_REG_ADDR_EXT,
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800323 .cache_type = REGCACHE_RBTREE,
324};
325
Jacob Panaf7e9062014-10-06 21:17:14 -0700326#define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \
327 [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }
Carlo Caionecfb61a42014-05-01 14:29:27 +0200328
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200329static const struct regmap_irq axp152_regmap_irqs[] = {
330 INIT_REGMAP_IRQ(AXP152, LDO0IN_CONNECT, 0, 6),
331 INIT_REGMAP_IRQ(AXP152, LDO0IN_REMOVAL, 0, 5),
332 INIT_REGMAP_IRQ(AXP152, ALDO0IN_CONNECT, 0, 3),
333 INIT_REGMAP_IRQ(AXP152, ALDO0IN_REMOVAL, 0, 2),
334 INIT_REGMAP_IRQ(AXP152, DCDC1_V_LOW, 1, 5),
335 INIT_REGMAP_IRQ(AXP152, DCDC2_V_LOW, 1, 4),
336 INIT_REGMAP_IRQ(AXP152, DCDC3_V_LOW, 1, 3),
337 INIT_REGMAP_IRQ(AXP152, DCDC4_V_LOW, 1, 2),
338 INIT_REGMAP_IRQ(AXP152, PEK_SHORT, 1, 1),
339 INIT_REGMAP_IRQ(AXP152, PEK_LONG, 1, 0),
340 INIT_REGMAP_IRQ(AXP152, TIMER, 2, 7),
341 INIT_REGMAP_IRQ(AXP152, PEK_RIS_EDGE, 2, 6),
342 INIT_REGMAP_IRQ(AXP152, PEK_FAL_EDGE, 2, 5),
343 INIT_REGMAP_IRQ(AXP152, GPIO3_INPUT, 2, 3),
344 INIT_REGMAP_IRQ(AXP152, GPIO2_INPUT, 2, 2),
345 INIT_REGMAP_IRQ(AXP152, GPIO1_INPUT, 2, 1),
346 INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT, 2, 0),
347};
348
Carlo Caionecfb61a42014-05-01 14:29:27 +0200349static const struct regmap_irq axp20x_regmap_irqs[] = {
Jacob Panaf7e9062014-10-06 21:17:14 -0700350 INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V, 0, 7),
351 INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN, 0, 6),
352 INIT_REGMAP_IRQ(AXP20X, ACIN_REMOVAL, 0, 5),
353 INIT_REGMAP_IRQ(AXP20X, VBUS_OVER_V, 0, 4),
354 INIT_REGMAP_IRQ(AXP20X, VBUS_PLUGIN, 0, 3),
355 INIT_REGMAP_IRQ(AXP20X, VBUS_REMOVAL, 0, 2),
356 INIT_REGMAP_IRQ(AXP20X, VBUS_V_LOW, 0, 1),
357 INIT_REGMAP_IRQ(AXP20X, BATT_PLUGIN, 1, 7),
358 INIT_REGMAP_IRQ(AXP20X, BATT_REMOVAL, 1, 6),
359 INIT_REGMAP_IRQ(AXP20X, BATT_ENT_ACT_MODE, 1, 5),
360 INIT_REGMAP_IRQ(AXP20X, BATT_EXIT_ACT_MODE, 1, 4),
361 INIT_REGMAP_IRQ(AXP20X, CHARG, 1, 3),
362 INIT_REGMAP_IRQ(AXP20X, CHARG_DONE, 1, 2),
363 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_HIGH, 1, 1),
364 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_LOW, 1, 0),
365 INIT_REGMAP_IRQ(AXP20X, DIE_TEMP_HIGH, 2, 7),
366 INIT_REGMAP_IRQ(AXP20X, CHARG_I_LOW, 2, 6),
367 INIT_REGMAP_IRQ(AXP20X, DCDC1_V_LONG, 2, 5),
368 INIT_REGMAP_IRQ(AXP20X, DCDC2_V_LONG, 2, 4),
369 INIT_REGMAP_IRQ(AXP20X, DCDC3_V_LONG, 2, 3),
370 INIT_REGMAP_IRQ(AXP20X, PEK_SHORT, 2, 1),
371 INIT_REGMAP_IRQ(AXP20X, PEK_LONG, 2, 0),
372 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_ON, 3, 7),
373 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_OFF, 3, 6),
374 INIT_REGMAP_IRQ(AXP20X, VBUS_VALID, 3, 5),
375 INIT_REGMAP_IRQ(AXP20X, VBUS_NOT_VALID, 3, 4),
376 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_VALID, 3, 3),
377 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_END, 3, 2),
378 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL1, 3, 1),
379 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL2, 3, 0),
380 INIT_REGMAP_IRQ(AXP20X, TIMER, 4, 7),
381 INIT_REGMAP_IRQ(AXP20X, PEK_RIS_EDGE, 4, 6),
382 INIT_REGMAP_IRQ(AXP20X, PEK_FAL_EDGE, 4, 5),
383 INIT_REGMAP_IRQ(AXP20X, GPIO3_INPUT, 4, 3),
384 INIT_REGMAP_IRQ(AXP20X, GPIO2_INPUT, 4, 2),
385 INIT_REGMAP_IRQ(AXP20X, GPIO1_INPUT, 4, 1),
386 INIT_REGMAP_IRQ(AXP20X, GPIO0_INPUT, 4, 0),
387};
388
Boris BREZILLONf05be582015-04-10 12:09:01 +0800389static const struct regmap_irq axp22x_regmap_irqs[] = {
390 INIT_REGMAP_IRQ(AXP22X, ACIN_OVER_V, 0, 7),
391 INIT_REGMAP_IRQ(AXP22X, ACIN_PLUGIN, 0, 6),
392 INIT_REGMAP_IRQ(AXP22X, ACIN_REMOVAL, 0, 5),
393 INIT_REGMAP_IRQ(AXP22X, VBUS_OVER_V, 0, 4),
394 INIT_REGMAP_IRQ(AXP22X, VBUS_PLUGIN, 0, 3),
395 INIT_REGMAP_IRQ(AXP22X, VBUS_REMOVAL, 0, 2),
396 INIT_REGMAP_IRQ(AXP22X, VBUS_V_LOW, 0, 1),
397 INIT_REGMAP_IRQ(AXP22X, BATT_PLUGIN, 1, 7),
398 INIT_REGMAP_IRQ(AXP22X, BATT_REMOVAL, 1, 6),
399 INIT_REGMAP_IRQ(AXP22X, BATT_ENT_ACT_MODE, 1, 5),
400 INIT_REGMAP_IRQ(AXP22X, BATT_EXIT_ACT_MODE, 1, 4),
401 INIT_REGMAP_IRQ(AXP22X, CHARG, 1, 3),
402 INIT_REGMAP_IRQ(AXP22X, CHARG_DONE, 1, 2),
403 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_HIGH, 1, 1),
404 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_LOW, 1, 0),
405 INIT_REGMAP_IRQ(AXP22X, DIE_TEMP_HIGH, 2, 7),
406 INIT_REGMAP_IRQ(AXP22X, PEK_SHORT, 2, 1),
407 INIT_REGMAP_IRQ(AXP22X, PEK_LONG, 2, 0),
408 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL1, 3, 1),
409 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL2, 3, 0),
410 INIT_REGMAP_IRQ(AXP22X, TIMER, 4, 7),
411 INIT_REGMAP_IRQ(AXP22X, PEK_RIS_EDGE, 4, 6),
412 INIT_REGMAP_IRQ(AXP22X, PEK_FAL_EDGE, 4, 5),
413 INIT_REGMAP_IRQ(AXP22X, GPIO1_INPUT, 4, 1),
414 INIT_REGMAP_IRQ(AXP22X, GPIO0_INPUT, 4, 0),
415};
416
Jacob Panaf7e9062014-10-06 21:17:14 -0700417/* some IRQs are compatible with axp20x models */
418static const struct regmap_irq axp288_regmap_irqs[] = {
Jacob Panff3bbc52014-11-11 11:30:09 -0800419 INIT_REGMAP_IRQ(AXP288, VBUS_FALL, 0, 2),
420 INIT_REGMAP_IRQ(AXP288, VBUS_RISE, 0, 3),
421 INIT_REGMAP_IRQ(AXP288, OV, 0, 4),
Hans de Goede8b44e672016-12-14 14:52:06 +0100422 INIT_REGMAP_IRQ(AXP288, FALLING_ALT, 0, 5),
423 INIT_REGMAP_IRQ(AXP288, RISING_ALT, 0, 6),
424 INIT_REGMAP_IRQ(AXP288, OV_ALT, 0, 7),
Jacob Panaf7e9062014-10-06 21:17:14 -0700425
Jacob Panff3bbc52014-11-11 11:30:09 -0800426 INIT_REGMAP_IRQ(AXP288, DONE, 1, 2),
427 INIT_REGMAP_IRQ(AXP288, CHARGING, 1, 3),
Jacob Panaf7e9062014-10-06 21:17:14 -0700428 INIT_REGMAP_IRQ(AXP288, SAFE_QUIT, 1, 4),
429 INIT_REGMAP_IRQ(AXP288, SAFE_ENTER, 1, 5),
Jacob Panff3bbc52014-11-11 11:30:09 -0800430 INIT_REGMAP_IRQ(AXP288, ABSENT, 1, 6),
431 INIT_REGMAP_IRQ(AXP288, APPEND, 1, 7),
Jacob Panaf7e9062014-10-06 21:17:14 -0700432
433 INIT_REGMAP_IRQ(AXP288, QWBTU, 2, 0),
434 INIT_REGMAP_IRQ(AXP288, WBTU, 2, 1),
435 INIT_REGMAP_IRQ(AXP288, QWBTO, 2, 2),
Jacob Panff3bbc52014-11-11 11:30:09 -0800436 INIT_REGMAP_IRQ(AXP288, WBTO, 2, 3),
Jacob Panaf7e9062014-10-06 21:17:14 -0700437 INIT_REGMAP_IRQ(AXP288, QCBTU, 2, 4),
438 INIT_REGMAP_IRQ(AXP288, CBTU, 2, 5),
439 INIT_REGMAP_IRQ(AXP288, QCBTO, 2, 6),
440 INIT_REGMAP_IRQ(AXP288, CBTO, 2, 7),
441
442 INIT_REGMAP_IRQ(AXP288, WL2, 3, 0),
443 INIT_REGMAP_IRQ(AXP288, WL1, 3, 1),
444 INIT_REGMAP_IRQ(AXP288, GPADC, 3, 2),
445 INIT_REGMAP_IRQ(AXP288, OT, 3, 7),
446
447 INIT_REGMAP_IRQ(AXP288, GPIO0, 4, 0),
448 INIT_REGMAP_IRQ(AXP288, GPIO1, 4, 1),
449 INIT_REGMAP_IRQ(AXP288, POKO, 4, 2),
450 INIT_REGMAP_IRQ(AXP288, POKL, 4, 3),
451 INIT_REGMAP_IRQ(AXP288, POKS, 4, 4),
452 INIT_REGMAP_IRQ(AXP288, POKN, 4, 5),
453 INIT_REGMAP_IRQ(AXP288, POKP, 4, 6),
Jacob Panff3bbc52014-11-11 11:30:09 -0800454 INIT_REGMAP_IRQ(AXP288, TIMER, 4, 7),
Jacob Panaf7e9062014-10-06 21:17:14 -0700455
456 INIT_REGMAP_IRQ(AXP288, MV_CHNG, 5, 0),
457 INIT_REGMAP_IRQ(AXP288, BC_USB_CHNG, 5, 1),
Carlo Caionecfb61a42014-05-01 14:29:27 +0200458};
459
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800460static const struct regmap_irq axp806_regmap_irqs[] = {
461 INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV1, 0, 0),
462 INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV2, 0, 1),
463 INIT_REGMAP_IRQ(AXP806, DCDCA_V_LOW, 0, 3),
464 INIT_REGMAP_IRQ(AXP806, DCDCB_V_LOW, 0, 4),
465 INIT_REGMAP_IRQ(AXP806, DCDCC_V_LOW, 0, 5),
466 INIT_REGMAP_IRQ(AXP806, DCDCD_V_LOW, 0, 6),
467 INIT_REGMAP_IRQ(AXP806, DCDCE_V_LOW, 0, 7),
468 INIT_REGMAP_IRQ(AXP806, PWROK_LONG, 1, 0),
469 INIT_REGMAP_IRQ(AXP806, PWROK_SHORT, 1, 1),
470 INIT_REGMAP_IRQ(AXP806, WAKEUP, 1, 4),
471 INIT_REGMAP_IRQ(AXP806, PWROK_FALL, 1, 5),
472 INIT_REGMAP_IRQ(AXP806, PWROK_RISE, 1, 6),
473};
474
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800475static const struct regmap_irq axp809_regmap_irqs[] = {
476 INIT_REGMAP_IRQ(AXP809, ACIN_OVER_V, 0, 7),
477 INIT_REGMAP_IRQ(AXP809, ACIN_PLUGIN, 0, 6),
478 INIT_REGMAP_IRQ(AXP809, ACIN_REMOVAL, 0, 5),
479 INIT_REGMAP_IRQ(AXP809, VBUS_OVER_V, 0, 4),
480 INIT_REGMAP_IRQ(AXP809, VBUS_PLUGIN, 0, 3),
481 INIT_REGMAP_IRQ(AXP809, VBUS_REMOVAL, 0, 2),
482 INIT_REGMAP_IRQ(AXP809, VBUS_V_LOW, 0, 1),
483 INIT_REGMAP_IRQ(AXP809, BATT_PLUGIN, 1, 7),
484 INIT_REGMAP_IRQ(AXP809, BATT_REMOVAL, 1, 6),
485 INIT_REGMAP_IRQ(AXP809, BATT_ENT_ACT_MODE, 1, 5),
486 INIT_REGMAP_IRQ(AXP809, BATT_EXIT_ACT_MODE, 1, 4),
487 INIT_REGMAP_IRQ(AXP809, CHARG, 1, 3),
488 INIT_REGMAP_IRQ(AXP809, CHARG_DONE, 1, 2),
489 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH, 2, 7),
490 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH_END, 2, 6),
491 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW, 2, 5),
492 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW_END, 2, 4),
493 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH, 2, 3),
494 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH_END, 2, 2),
495 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW, 2, 1),
496 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW_END, 2, 0),
497 INIT_REGMAP_IRQ(AXP809, DIE_TEMP_HIGH, 3, 7),
498 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL1, 3, 1),
499 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL2, 3, 0),
500 INIT_REGMAP_IRQ(AXP809, TIMER, 4, 7),
501 INIT_REGMAP_IRQ(AXP809, PEK_RIS_EDGE, 4, 6),
502 INIT_REGMAP_IRQ(AXP809, PEK_FAL_EDGE, 4, 5),
503 INIT_REGMAP_IRQ(AXP809, PEK_SHORT, 4, 4),
504 INIT_REGMAP_IRQ(AXP809, PEK_LONG, 4, 3),
505 INIT_REGMAP_IRQ(AXP809, PEK_OVER_OFF, 4, 2),
506 INIT_REGMAP_IRQ(AXP809, GPIO1_INPUT, 4, 1),
507 INIT_REGMAP_IRQ(AXP809, GPIO0_INPUT, 4, 0),
508};
509
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200510static const struct regmap_irq_chip axp152_regmap_irq_chip = {
511 .name = "axp152_irq_chip",
512 .status_base = AXP152_IRQ1_STATE,
513 .ack_base = AXP152_IRQ1_STATE,
514 .mask_base = AXP152_IRQ1_EN,
515 .mask_invert = true,
516 .init_ack_masked = true,
517 .irqs = axp152_regmap_irqs,
518 .num_irqs = ARRAY_SIZE(axp152_regmap_irqs),
519 .num_regs = 3,
520};
521
Carlo Caionecfb61a42014-05-01 14:29:27 +0200522static const struct regmap_irq_chip axp20x_regmap_irq_chip = {
523 .name = "axp20x_irq_chip",
524 .status_base = AXP20X_IRQ1_STATE,
525 .ack_base = AXP20X_IRQ1_STATE,
526 .mask_base = AXP20X_IRQ1_EN,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200527 .mask_invert = true,
528 .init_ack_masked = true,
Jacob Panaf7e9062014-10-06 21:17:14 -0700529 .irqs = axp20x_regmap_irqs,
530 .num_irqs = ARRAY_SIZE(axp20x_regmap_irqs),
531 .num_regs = 5,
532
533};
534
Boris BREZILLONf05be582015-04-10 12:09:01 +0800535static const struct regmap_irq_chip axp22x_regmap_irq_chip = {
536 .name = "axp22x_irq_chip",
537 .status_base = AXP20X_IRQ1_STATE,
538 .ack_base = AXP20X_IRQ1_STATE,
539 .mask_base = AXP20X_IRQ1_EN,
540 .mask_invert = true,
541 .init_ack_masked = true,
542 .irqs = axp22x_regmap_irqs,
543 .num_irqs = ARRAY_SIZE(axp22x_regmap_irqs),
544 .num_regs = 5,
545};
546
Jacob Panaf7e9062014-10-06 21:17:14 -0700547static const struct regmap_irq_chip axp288_regmap_irq_chip = {
548 .name = "axp288_irq_chip",
549 .status_base = AXP20X_IRQ1_STATE,
550 .ack_base = AXP20X_IRQ1_STATE,
551 .mask_base = AXP20X_IRQ1_EN,
552 .mask_invert = true,
553 .init_ack_masked = true,
554 .irqs = axp288_regmap_irqs,
555 .num_irqs = ARRAY_SIZE(axp288_regmap_irqs),
556 .num_regs = 6,
557
Carlo Caionecfb61a42014-05-01 14:29:27 +0200558};
559
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800560static const struct regmap_irq_chip axp806_regmap_irq_chip = {
561 .name = "axp806",
562 .status_base = AXP20X_IRQ1_STATE,
563 .ack_base = AXP20X_IRQ1_STATE,
564 .mask_base = AXP20X_IRQ1_EN,
565 .mask_invert = true,
566 .init_ack_masked = true,
567 .irqs = axp806_regmap_irqs,
568 .num_irqs = ARRAY_SIZE(axp806_regmap_irqs),
569 .num_regs = 2,
570};
571
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800572static const struct regmap_irq_chip axp809_regmap_irq_chip = {
573 .name = "axp809",
574 .status_base = AXP20X_IRQ1_STATE,
575 .ack_base = AXP20X_IRQ1_STATE,
576 .mask_base = AXP20X_IRQ1_EN,
577 .mask_invert = true,
578 .init_ack_masked = true,
579 .irqs = axp809_regmap_irqs,
580 .num_irqs = ARRAY_SIZE(axp809_regmap_irqs),
581 .num_regs = 5,
582};
583
Carlo Caionecfb61a42014-05-01 14:29:27 +0200584static struct mfd_cell axp20x_cells[] = {
585 {
Maxime Ripardb419c162016-07-20 16:11:37 +0200586 .name = "axp20x-gpio",
587 .of_compatible = "x-powers,axp209-gpio",
588 }, {
Hans de Goede8de4efd2015-08-08 17:58:41 +0200589 .name = "axp20x-pek",
590 .num_resources = ARRAY_SIZE(axp20x_pek_resources),
591 .resources = axp20x_pek_resources,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200592 }, {
Hans de Goede8de4efd2015-08-08 17:58:41 +0200593 .name = "axp20x-regulator",
594 }, {
Quentin Schulz4d5e5c32017-03-20 09:16:47 +0100595 .name = "axp20x-adc",
596 }, {
Michael Haascd7cf272016-05-06 07:19:49 +0200597 .name = "axp20x-ac-power-supply",
598 .of_compatible = "x-powers,axp202-ac-power-supply",
599 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
600 .resources = axp20x_ac_power_supply_resources,
601 }, {
Hans de Goede8de4efd2015-08-08 17:58:41 +0200602 .name = "axp20x-usb-power-supply",
603 .of_compatible = "x-powers,axp202-usb-power-supply",
604 .num_resources = ARRAY_SIZE(axp20x_usb_power_supply_resources),
605 .resources = axp20x_usb_power_supply_resources,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200606 },
607};
608
Quentin Schulz4c650562016-12-09 12:04:14 +0100609static struct mfd_cell axp221_cells[] = {
610 {
611 .name = "axp20x-pek",
612 .num_resources = ARRAY_SIZE(axp22x_pek_resources),
613 .resources = axp22x_pek_resources,
614 }, {
615 .name = "axp20x-regulator",
616 }, {
Quentin Schulz4d5e5c32017-03-20 09:16:47 +0100617 .name = "axp22x-adc"
618 }, {
Quentin Schulz95c4f532017-03-20 09:16:48 +0100619 .name = "axp20x-ac-power-supply",
620 .of_compatible = "x-powers,axp221-ac-power-supply",
621 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
622 .resources = axp20x_ac_power_supply_resources,
623 }, {
Quentin Schulz4c650562016-12-09 12:04:14 +0100624 .name = "axp20x-usb-power-supply",
625 .of_compatible = "x-powers,axp221-usb-power-supply",
626 .num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources),
627 .resources = axp22x_usb_power_supply_resources,
628 },
629};
630
631static struct mfd_cell axp223_cells[] = {
Boris BREZILLONf05be582015-04-10 12:09:01 +0800632 {
633 .name = "axp20x-pek",
634 .num_resources = ARRAY_SIZE(axp22x_pek_resources),
635 .resources = axp22x_pek_resources,
Chen-Yu Tsai6d4fa892015-04-10 12:09:06 +0800636 }, {
Quentin Schulz4d5e5c32017-03-20 09:16:47 +0100637 .name = "axp22x-adc",
638 }, {
Chen-Yu Tsai6d4fa892015-04-10 12:09:06 +0800639 .name = "axp20x-regulator",
Hans de Goedeecd98cc2016-06-02 19:18:55 +0200640 }, {
Quentin Schulz95c4f532017-03-20 09:16:48 +0100641 .name = "axp20x-ac-power-supply",
642 .of_compatible = "x-powers,axp221-ac-power-supply",
643 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
644 .resources = axp20x_ac_power_supply_resources,
645 }, {
Hans de Goedeecd98cc2016-06-02 19:18:55 +0200646 .name = "axp20x-usb-power-supply",
Quentin Schulz4c650562016-12-09 12:04:14 +0100647 .of_compatible = "x-powers,axp223-usb-power-supply",
Hans de Goedeecd98cc2016-06-02 19:18:55 +0200648 .num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources),
649 .resources = axp22x_usb_power_supply_resources,
Boris BREZILLONf05be582015-04-10 12:09:01 +0800650 },
651};
652
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200653static struct mfd_cell axp152_cells[] = {
654 {
655 .name = "axp20x-pek",
656 .num_resources = ARRAY_SIZE(axp152_pek_resources),
657 .resources = axp152_pek_resources,
658 },
659};
660
Jacob Panaf7e9062014-10-06 21:17:14 -0700661static struct resource axp288_adc_resources[] = {
662 {
663 .name = "GPADC",
664 .start = AXP288_IRQ_GPADC,
665 .end = AXP288_IRQ_GPADC,
666 .flags = IORESOURCE_IRQ,
667 },
668};
669
Ramakrishna Pallalabdb01f72015-04-03 00:49:47 +0530670static struct resource axp288_extcon_resources[] = {
671 {
672 .start = AXP288_IRQ_VBUS_FALL,
673 .end = AXP288_IRQ_VBUS_FALL,
674 .flags = IORESOURCE_IRQ,
675 },
676 {
677 .start = AXP288_IRQ_VBUS_RISE,
678 .end = AXP288_IRQ_VBUS_RISE,
679 .flags = IORESOURCE_IRQ,
680 },
681 {
682 .start = AXP288_IRQ_MV_CHNG,
683 .end = AXP288_IRQ_MV_CHNG,
684 .flags = IORESOURCE_IRQ,
685 },
686 {
687 .start = AXP288_IRQ_BC_USB_CHNG,
688 .end = AXP288_IRQ_BC_USB_CHNG,
689 .flags = IORESOURCE_IRQ,
690 },
691};
692
Jacob Panaf7e9062014-10-06 21:17:14 -0700693static struct resource axp288_charger_resources[] = {
694 {
695 .start = AXP288_IRQ_OV,
696 .end = AXP288_IRQ_OV,
697 .flags = IORESOURCE_IRQ,
698 },
699 {
700 .start = AXP288_IRQ_DONE,
701 .end = AXP288_IRQ_DONE,
702 .flags = IORESOURCE_IRQ,
703 },
704 {
705 .start = AXP288_IRQ_CHARGING,
706 .end = AXP288_IRQ_CHARGING,
707 .flags = IORESOURCE_IRQ,
708 },
709 {
710 .start = AXP288_IRQ_SAFE_QUIT,
711 .end = AXP288_IRQ_SAFE_QUIT,
712 .flags = IORESOURCE_IRQ,
713 },
714 {
715 .start = AXP288_IRQ_SAFE_ENTER,
716 .end = AXP288_IRQ_SAFE_ENTER,
717 .flags = IORESOURCE_IRQ,
718 },
719 {
720 .start = AXP288_IRQ_QCBTU,
721 .end = AXP288_IRQ_QCBTU,
722 .flags = IORESOURCE_IRQ,
723 },
724 {
725 .start = AXP288_IRQ_CBTU,
726 .end = AXP288_IRQ_CBTU,
727 .flags = IORESOURCE_IRQ,
728 },
729 {
730 .start = AXP288_IRQ_QCBTO,
731 .end = AXP288_IRQ_QCBTO,
732 .flags = IORESOURCE_IRQ,
733 },
734 {
735 .start = AXP288_IRQ_CBTO,
736 .end = AXP288_IRQ_CBTO,
737 .flags = IORESOURCE_IRQ,
738 },
739};
740
741static struct mfd_cell axp288_cells[] = {
742 {
743 .name = "axp288_adc",
744 .num_resources = ARRAY_SIZE(axp288_adc_resources),
745 .resources = axp288_adc_resources,
746 },
747 {
Ramakrishna Pallalabdb01f72015-04-03 00:49:47 +0530748 .name = "axp288_extcon",
749 .num_resources = ARRAY_SIZE(axp288_extcon_resources),
750 .resources = axp288_extcon_resources,
751 },
752 {
Jacob Panaf7e9062014-10-06 21:17:14 -0700753 .name = "axp288_charger",
754 .num_resources = ARRAY_SIZE(axp288_charger_resources),
755 .resources = axp288_charger_resources,
756 },
757 {
Todd Brandtd63878742015-02-02 15:41:41 -0800758 .name = "axp288_fuel_gauge",
759 .num_resources = ARRAY_SIZE(axp288_fuel_gauge_resources),
760 .resources = axp288_fuel_gauge_resources,
Jacob Panaf7e9062014-10-06 21:17:14 -0700761 },
Aaron Lud8139f62014-11-24 17:24:47 +0800762 {
Borun Fue56e5ad2015-10-14 16:16:26 +0800763 .name = "axp20x-pek",
764 .num_resources = ARRAY_SIZE(axp288_power_button_resources),
765 .resources = axp288_power_button_resources,
766 },
767 {
Aaron Lud8139f62014-11-24 17:24:47 +0800768 .name = "axp288_pmic_acpi",
769 },
Jacob Panaf7e9062014-10-06 21:17:14 -0700770};
771
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800772static struct mfd_cell axp806_cells[] = {
773 {
774 .id = 2,
775 .name = "axp20x-regulator",
776 },
777};
778
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800779static struct mfd_cell axp809_cells[] = {
780 {
781 .name = "axp20x-pek",
782 .num_resources = ARRAY_SIZE(axp809_pek_resources),
783 .resources = axp809_pek_resources,
784 }, {
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800785 .id = 1,
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800786 .name = "axp20x-regulator",
787 },
788};
789
Carlo Caionecfb61a42014-05-01 14:29:27 +0200790static struct axp20x_dev *axp20x_pm_power_off;
791static void axp20x_power_off(void)
792{
Jacob Panaf7e9062014-10-06 21:17:14 -0700793 if (axp20x_pm_power_off->variant == AXP288_ID)
794 return;
795
Carlo Caionecfb61a42014-05-01 14:29:27 +0200796 regmap_write(axp20x_pm_power_off->regmap, AXP20X_OFF_CTRL,
797 AXP20X_OFF);
Hans de Goede179dc632016-06-05 15:50:48 +0200798
799 /* Give capacitors etc. time to drain to avoid kernel panic msg. */
800 msleep(500);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200801}
802
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800803int axp20x_match_device(struct axp20x_dev *axp20x)
Jacob Panaf7e9062014-10-06 21:17:14 -0700804{
Chen-Yu Tsaie47a3cf2016-02-12 10:02:39 +0800805 struct device *dev = axp20x->dev;
Jacob Panaf7e9062014-10-06 21:17:14 -0700806 const struct acpi_device_id *acpi_id;
807 const struct of_device_id *of_id;
808
809 if (dev->of_node) {
Chen-Yu Tsaiaf7acc32016-02-12 10:02:40 +0800810 of_id = of_match_device(dev->driver->of_match_table, dev);
Jacob Panaf7e9062014-10-06 21:17:14 -0700811 if (!of_id) {
812 dev_err(dev, "Unable to match OF ID\n");
813 return -ENODEV;
814 }
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800815 axp20x->variant = (long)of_id->data;
Jacob Panaf7e9062014-10-06 21:17:14 -0700816 } else {
817 acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev);
818 if (!acpi_id || !acpi_id->driver_data) {
819 dev_err(dev, "Unable to match ACPI ID and data\n");
820 return -ENODEV;
821 }
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800822 axp20x->variant = (long)acpi_id->driver_data;
Jacob Panaf7e9062014-10-06 21:17:14 -0700823 }
824
825 switch (axp20x->variant) {
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200826 case AXP152_ID:
827 axp20x->nr_cells = ARRAY_SIZE(axp152_cells);
828 axp20x->cells = axp152_cells;
829 axp20x->regmap_cfg = &axp152_regmap_config;
830 axp20x->regmap_irq_chip = &axp152_regmap_irq_chip;
831 break;
Jacob Panaf7e9062014-10-06 21:17:14 -0700832 case AXP202_ID:
833 case AXP209_ID:
834 axp20x->nr_cells = ARRAY_SIZE(axp20x_cells);
835 axp20x->cells = axp20x_cells;
836 axp20x->regmap_cfg = &axp20x_regmap_config;
837 axp20x->regmap_irq_chip = &axp20x_regmap_irq_chip;
838 break;
Boris BREZILLONf05be582015-04-10 12:09:01 +0800839 case AXP221_ID:
Quentin Schulz4c650562016-12-09 12:04:14 +0100840 axp20x->nr_cells = ARRAY_SIZE(axp221_cells);
841 axp20x->cells = axp221_cells;
842 axp20x->regmap_cfg = &axp22x_regmap_config;
843 axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
844 break;
Chen-Yu Tsai02071f02016-02-12 10:02:44 +0800845 case AXP223_ID:
Quentin Schulz4c650562016-12-09 12:04:14 +0100846 axp20x->nr_cells = ARRAY_SIZE(axp223_cells);
847 axp20x->cells = axp223_cells;
Boris BREZILLONf05be582015-04-10 12:09:01 +0800848 axp20x->regmap_cfg = &axp22x_regmap_config;
849 axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
850 break;
Jacob Panaf7e9062014-10-06 21:17:14 -0700851 case AXP288_ID:
852 axp20x->cells = axp288_cells;
853 axp20x->nr_cells = ARRAY_SIZE(axp288_cells);
854 axp20x->regmap_cfg = &axp288_regmap_config;
855 axp20x->regmap_irq_chip = &axp288_regmap_irq_chip;
Hans de Goede0a5454c2016-12-14 14:52:05 +0100856 axp20x->irq_flags = IRQF_TRIGGER_LOW;
Jacob Panaf7e9062014-10-06 21:17:14 -0700857 break;
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800858 case AXP806_ID:
859 axp20x->nr_cells = ARRAY_SIZE(axp806_cells);
860 axp20x->cells = axp806_cells;
861 axp20x->regmap_cfg = &axp806_regmap_config;
862 axp20x->regmap_irq_chip = &axp806_regmap_irq_chip;
863 break;
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800864 case AXP809_ID:
865 axp20x->nr_cells = ARRAY_SIZE(axp809_cells);
866 axp20x->cells = axp809_cells;
867 axp20x->regmap_cfg = &axp22x_regmap_config;
868 axp20x->regmap_irq_chip = &axp809_regmap_irq_chip;
869 break;
Jacob Panaf7e9062014-10-06 21:17:14 -0700870 default:
871 dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant);
872 return -EINVAL;
873 }
874 dev_info(dev, "AXP20x variant %s found\n",
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800875 axp20x_model_names[axp20x->variant]);
Jacob Panaf7e9062014-10-06 21:17:14 -0700876
877 return 0;
878}
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800879EXPORT_SYMBOL(axp20x_match_device);
Jacob Panaf7e9062014-10-06 21:17:14 -0700880
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800881int axp20x_device_probe(struct axp20x_dev *axp20x)
Carlo Caionecfb61a42014-05-01 14:29:27 +0200882{
Carlo Caionecfb61a42014-05-01 14:29:27 +0200883 int ret;
884
Chen-Yu Tsai696f0b32017-01-05 12:01:03 +0800885 /*
886 * The AXP806 supports either master/standalone or slave mode.
887 * Slave mode allows sharing the serial bus, even with multiple
888 * AXP806 which all have the same hardware address.
889 *
890 * This is done with extra "serial interface address extension",
891 * or AXP806_BUS_ADDR_EXT, and "register address extension", or
892 * AXP806_REG_ADDR_EXT, registers. The former is read-only, with
893 * 1 bit customizable at the factory, and 1 bit depending on the
894 * state of an external pin. The latter is writable. The device
895 * will only respond to operations to its other registers when
896 * the these device addressing bits (in the upper 4 bits of the
897 * registers) match.
898 *
Rask Ingemann Lambertsenc0369692017-02-22 20:42:02 +0100899 * By default we support an AXP806 chained to an AXP809 in slave
900 * mode. Boards which use an AXP806 in master mode can set the
901 * property "x-powers,master-mode" to override the default.
Chen-Yu Tsai696f0b32017-01-05 12:01:03 +0800902 */
Rask Ingemann Lambertsenc0369692017-02-22 20:42:02 +0100903 if (axp20x->variant == AXP806_ID) {
904 if (of_property_read_bool(axp20x->dev->of_node,
905 "x-powers,master-mode"))
906 regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
907 AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE);
908 else
909 regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
910 AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
911 }
Chen-Yu Tsai696f0b32017-01-05 12:01:03 +0800912
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800913 ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
Hans de Goede0a5454c2016-12-14 14:52:05 +0100914 IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
915 -1, axp20x->regmap_irq_chip, &axp20x->regmap_irqc);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200916 if (ret) {
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800917 dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200918 return ret;
919 }
920
Jacob Panaf7e9062014-10-06 21:17:14 -0700921 ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800922 axp20x->nr_cells, NULL, 0, NULL);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200923
924 if (ret) {
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800925 dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret);
926 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200927 return ret;
928 }
929
930 if (!pm_power_off) {
931 axp20x_pm_power_off = axp20x;
932 pm_power_off = axp20x_power_off;
933 }
934
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800935 dev_info(axp20x->dev, "AXP20X driver loaded\n");
Carlo Caionecfb61a42014-05-01 14:29:27 +0200936
937 return 0;
938}
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800939EXPORT_SYMBOL(axp20x_device_probe);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200940
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800941int axp20x_device_remove(struct axp20x_dev *axp20x)
Carlo Caionecfb61a42014-05-01 14:29:27 +0200942{
Carlo Caionecfb61a42014-05-01 14:29:27 +0200943 if (axp20x == axp20x_pm_power_off) {
944 axp20x_pm_power_off = NULL;
945 pm_power_off = NULL;
946 }
947
948 mfd_remove_devices(axp20x->dev);
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800949 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200950
951 return 0;
952}
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800953EXPORT_SYMBOL(axp20x_device_remove);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200954
955MODULE_DESCRIPTION("PMIC MFD core driver for AXP20X");
956MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
957MODULE_LICENSE("GPL");