blob: d60e2f7eff1b5b6f58de403f4fcd615ea3372316 [file] [log] [blame]
Paul Mackerras40ef8cb2005-10-10 22:50:37 +10001/*
2 *
3 * Common boot and setup code.
4 *
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
Paul Gortmaker4b16f8e2011-07-22 18:24:23 -040013#include <linux/export.h>
Paul Mackerras40ef8cb2005-10-10 22:50:37 +100014#include <linux/string.h>
15#include <linux/sched.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/reboot.h>
19#include <linux/delay.h>
20#include <linux/initrd.h>
Paul Mackerras40ef8cb2005-10-10 22:50:37 +100021#include <linux/seq_file.h>
22#include <linux/ioport.h>
23#include <linux/console.h>
24#include <linux/utsname.h>
25#include <linux/tty.h>
26#include <linux/root_dev.h>
27#include <linux/notifier.h>
28#include <linux/cpu.h>
29#include <linux/unistd.h>
30#include <linux/serial.h>
31#include <linux/serial_8250.h>
Anton Blanchard7a0268f2006-01-11 13:16:44 +110032#include <linux/bootmem.h>
Benjamin Herrenschmidt12d04ee2006-11-11 17:25:02 +110033#include <linux/pci.h>
Benjamin Herrenschmidt945feb12008-04-17 14:35:01 +100034#include <linux/lockdep.h>
Yinghai Lu95f72d12010-07-12 14:36:09 +100035#include <linux/memblock.h>
Anton Blancharda5d86252014-06-04 17:50:47 +100036#include <linux/memory.h>
Anton Blanchardc54b2bf2015-04-09 12:52:56 +100037#include <linux/nmi.h>
Becky Brucea6146882011-10-10 10:50:43 +000038
Michael Ellerman236003e2018-01-16 22:17:18 +110039#include <asm/debugfs.h>
Paul Mackerras40ef8cb2005-10-10 22:50:37 +100040#include <asm/io.h>
Michael Ellerman0cc47462005-12-04 18:39:37 +110041#include <asm/kdump.h>
Paul Mackerras40ef8cb2005-10-10 22:50:37 +100042#include <asm/prom.h>
43#include <asm/processor.h>
44#include <asm/pgtable.h>
Paul Mackerras40ef8cb2005-10-10 22:50:37 +100045#include <asm/smp.h>
46#include <asm/elf.h>
47#include <asm/machdep.h>
48#include <asm/paca.h>
Paul Mackerras40ef8cb2005-10-10 22:50:37 +100049#include <asm/time.h>
50#include <asm/cputable.h>
Nicholas Piggin5a61ef72017-05-09 13:16:52 +100051#include <asm/dt_cpu_ftrs.h>
Paul Mackerras40ef8cb2005-10-10 22:50:37 +100052#include <asm/sections.h>
53#include <asm/btext.h>
54#include <asm/nvram.h>
55#include <asm/setup.h>
Paul Mackerras40ef8cb2005-10-10 22:50:37 +100056#include <asm/rtas.h>
57#include <asm/iommu.h>
58#include <asm/serial.h>
59#include <asm/cache.h>
60#include <asm/page.h>
61#include <asm/mmu.h>
Paul Mackerras40ef8cb2005-10-10 22:50:37 +100062#include <asm/firmware.h>
Paul Mackerrasf78541dc2005-10-28 22:53:37 +100063#include <asm/xmon.h>
David Gibsondcad47f2005-11-07 09:49:43 +110064#include <asm/udbg.h>
Michael Ellerman593e5372005-11-12 00:06:06 +110065#include <asm/kexec.h>
Kumar Galad36b4c42011-04-06 00:18:48 -050066#include <asm/code-patching.h>
Michael Ellerman5d31a962016-03-24 22:04:04 +110067#include <asm/livepatch.h>
Benjamin Herrenschmidtd3cbff12016-07-05 15:03:49 +100068#include <asm/opal.h>
Benjamin Herrenschmidtb1923ca2016-07-05 15:07:51 +100069#include <asm/cputhreads.h>
Madhavan Srinivasanc2e480b2017-12-20 09:25:42 +053070#include <asm/hw_irq.h>
Paul Mackerras40ef8cb2005-10-10 22:50:37 +100071
Nicholas Piggin1696d0f2017-10-24 21:44:44 +100072#include "setup.h"
73
Paul Mackerras40ef8cb2005-10-10 22:50:37 +100074#ifdef DEBUG
75#define DBG(fmt...) udbg_printf(fmt)
76#else
77#define DBG(fmt...)
78#endif
79
Chen Gang8246aca2013-03-20 14:30:12 +080080int spinning_secondaries;
Paul Mackerras40ef8cb2005-10-10 22:50:37 +100081u64 ppc64_pft_size;
82
Olof Johanssondabcafd2005-12-08 19:40:17 -060083struct ppc64_caches ppc64_caches = {
Benjamin Herrenschmidte2827fe2017-01-08 17:31:47 -060084 .l1d = {
85 .block_size = 0x40,
86 .log_block_size = 6,
87 },
88 .l1i = {
89 .block_size = 0x40,
90 .log_block_size = 6
91 },
Olof Johanssondabcafd2005-12-08 19:40:17 -060092};
Paul Mackerras40ef8cb2005-10-10 22:50:37 +100093EXPORT_SYMBOL_GPL(ppc64_caches);
94
Scott Wood28efc352013-10-11 19:22:38 -050095#if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
Benjamin Herrenschmidtb1923ca2016-07-05 15:07:51 +100096void __init setup_tlb_core_data(void)
Scott Wood28efc352013-10-11 19:22:38 -050097{
98 int cpu;
99
Scott Wood82d86de2014-03-07 14:48:35 -0600100 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
101
Scott Wood28efc352013-10-11 19:22:38 -0500102 for_each_possible_cpu(cpu) {
103 int first = cpu_first_thread_sibling(cpu);
104
Scott Woodd9e18312015-10-06 22:48:09 -0500105 /*
106 * If we boot via kdump on a non-primary thread,
107 * make sure we point at the thread that actually
108 * set up this TLB.
109 */
110 if (cpu_first_thread_sibling(boot_cpuid) == first)
111 first = boot_cpuid;
112
Scott Wood28efc352013-10-11 19:22:38 -0500113 paca[cpu].tcd_ptr = &paca[first].tcd;
114
115 /*
116 * If we have threads, we need either tlbsrx.
117 * or e6500 tablewalk mode, or else TLB handlers
118 * will be racy and could produce duplicate entries.
Michael Ellerman0d2b5cd2017-02-15 20:24:25 +1100119 * Should we panic instead?
Scott Wood28efc352013-10-11 19:22:38 -0500120 */
Michael Ellerman0d2b5cd2017-02-15 20:24:25 +1100121 WARN_ONCE(smt_enabled_at_boot >= 2 &&
122 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
123 book3e_htw_mode != PPC_HTW_E6500,
124 "%s: unsupported MMU configuration\n", __func__);
Scott Wood28efc352013-10-11 19:22:38 -0500125 }
126}
Scott Wood28efc352013-10-11 19:22:38 -0500127#endif
128
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000129#ifdef CONFIG_SMP
130
Nathan Fontenot954e6da2010-08-05 07:42:11 +0000131static char *smt_enabled_cmdline;
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000132
133/* Look for ibm,smt-enabled OF option */
Benjamin Herrenschmidtb1923ca2016-07-05 15:07:51 +1000134void __init check_smt_enabled(void)
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000135{
136 struct device_node *dn;
Jeremy Kerra7f67bd2006-07-12 15:35:54 +1000137 const char *smt_option;
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000138
Nathan Fontenot954e6da2010-08-05 07:42:11 +0000139 /* Default to enabling all threads */
140 smt_enabled_at_boot = threads_per_core;
141
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000142 /* Allow the command line to overrule the OF option */
Nathan Fontenot954e6da2010-08-05 07:42:11 +0000143 if (smt_enabled_cmdline) {
144 if (!strcmp(smt_enabled_cmdline, "on"))
145 smt_enabled_at_boot = threads_per_core;
146 else if (!strcmp(smt_enabled_cmdline, "off"))
147 smt_enabled_at_boot = 0;
148 else {
Daniel Walter1618bd52014-08-08 14:24:01 -0700149 int smt;
Nathan Fontenot954e6da2010-08-05 07:42:11 +0000150 int rc;
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000151
Daniel Walter1618bd52014-08-08 14:24:01 -0700152 rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
Nathan Fontenot954e6da2010-08-05 07:42:11 +0000153 if (!rc)
154 smt_enabled_at_boot =
Daniel Walter1618bd52014-08-08 14:24:01 -0700155 min(threads_per_core, smt);
Nathan Fontenot954e6da2010-08-05 07:42:11 +0000156 }
157 } else {
158 dn = of_find_node_by_path("/options");
159 if (dn) {
160 smt_option = of_get_property(dn, "ibm,smt-enabled",
161 NULL);
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000162
Nathan Fontenot954e6da2010-08-05 07:42:11 +0000163 if (smt_option) {
164 if (!strcmp(smt_option, "on"))
165 smt_enabled_at_boot = threads_per_core;
166 else if (!strcmp(smt_option, "off"))
167 smt_enabled_at_boot = 0;
168 }
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000169
Nathan Fontenot954e6da2010-08-05 07:42:11 +0000170 of_node_put(dn);
171 }
172 }
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000173}
174
175/* Look for smt-enabled= cmdline option */
176static int __init early_smt_enabled(char *p)
177{
Nathan Fontenot954e6da2010-08-05 07:42:11 +0000178 smt_enabled_cmdline = p;
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000179 return 0;
180}
181early_param("smt-enabled", early_smt_enabled);
182
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000183#endif /* CONFIG_SMP */
184
Michael Ellerman25e13812013-02-12 14:44:50 +0000185/** Fix up paca fields required for the boot cpu */
Benjamin Herrenschmidt009776b2016-07-05 15:07:50 +1000186static void __init fixup_boot_paca(void)
Michael Ellerman25e13812013-02-12 14:44:50 +0000187{
188 /* The boot cpu is started */
189 get_paca()->cpu_start = 1;
190 /* Allow percpu accesses to work until we setup percpu data */
191 get_paca()->data_offset = 0;
Madhavan Srinivasanc2e480b2017-12-20 09:25:42 +0530192 /* Mark interrupts disabled in PACA */
Madhavan Srinivasan4e26bc42017-12-20 09:25:50 +0530193 irq_soft_mask_set(IRQS_DISABLED);
Michael Ellerman25e13812013-02-12 14:44:50 +0000194}
195
Benjamin Herrenschmidt009776b2016-07-05 15:07:50 +1000196static void __init configure_exceptions(void)
Benjamin Herrenschmidtd3cbff12016-07-05 15:03:49 +1000197{
198 /*
199 * Setup the trampolines from the lowmem exception vectors
200 * to the kdump kernel when not using a relocatable kernel.
201 */
202 setup_kdump_trampoline();
203
204 /* Under a PAPR hypervisor, we need hypercalls */
205 if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
206 /* Enable AIL if possible */
207 pseries_enable_reloc_on_exc();
208
209 /*
210 * Tell the hypervisor that we want our exceptions to
211 * be taken in little endian mode.
212 *
213 * We don't call this for big endian as our calling convention
214 * makes us always enter in BE, and the call may fail under
215 * some circumstances with kdump.
216 */
217#ifdef __LITTLE_ENDIAN__
218 pseries_little_endian_exceptions();
219#endif
220 } else {
221 /* Set endian mode using OPAL */
222 if (firmware_has_feature(FW_FEATURE_OPAL))
223 opal_configure_cores();
224
Benjamin Herrenschmidtc0a36012016-11-15 15:28:33 +1100225 /* AIL on native is done in cpu_ready_for_interrupts() */
Benjamin Herrenschmidtd3cbff12016-07-05 15:03:49 +1000226 }
227}
228
Benjamin Herrenschmidt8f619b542014-03-28 13:36:30 +1100229static void cpu_ready_for_interrupts(void)
230{
Benjamin Herrenschmidtc0a36012016-11-15 15:28:33 +1100231 /*
232 * Enable AIL if supported, and we are in hypervisor mode. This
233 * is called once for every processor.
234 *
235 * If we are not in hypervisor mode the job is done once for
236 * the whole partition in configure_exceptions().
237 */
Michael Ellerman5511a452017-03-21 16:24:38 +1100238 if (cpu_has_feature(CPU_FTR_HVMODE) &&
239 cpu_has_feature(CPU_FTR_ARCH_207S)) {
Benjamin Herrenschmidtc0a36012016-11-15 15:28:33 +1100240 unsigned long lpcr = mfspr(SPRN_LPCR);
241 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
242 }
243
Benjamin Herrenschmidt7ed23e12017-03-20 17:49:03 +1100244 /*
245 * Fixup HFSCR:TM based on CPU features. The bit is set by our
246 * early asm init because at that point we haven't updated our
247 * CPU features from firmware and device-tree. Here we have,
248 * so let's do it.
249 */
250 if (cpu_has_feature(CPU_FTR_HVMODE) && !cpu_has_feature(CPU_FTR_TM_COMP))
251 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
252
Benjamin Herrenschmidt8f619b542014-03-28 13:36:30 +1100253 /* Set IR and DR in PACA MSR */
254 get_paca()->kernel_msr = MSR_KERNEL;
Benjamin Herrenschmidt8f619b542014-03-28 13:36:30 +1100255}
256
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000257/*
258 * Early initialization entry point. This is called by head.S
259 * with MMU translation disabled. We rely on the "feature" of
260 * the CPU that ignores the top 2 bits of the address in real
261 * mode so we can access kernel globals normally provided we
262 * only toy with things in the RMO region. From here, we do
Yinghai Lu95f72d12010-07-12 14:36:09 +1000263 * some early parsing of the device-tree to setup out MEMBLOCK
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000264 * data structures, and allocate & initialize the hash table
265 * and segment tables so we can start running with translation
266 * enabled.
267 *
268 * It is this function which will call the probe() callback of
269 * the various platform types and copy the matching one to the
270 * global ppc_md structure. Your platform can eventually do
271 * some very early initializations from the probe() routine, but
272 * this is not recommended, be very careful as, for example, the
273 * device-tree is not accessible via normal means at this point.
274 */
275
276void __init early_setup(unsigned long dt_ptr)
277{
Geoff Levand6a7e4062013-02-13 17:03:16 +0000278 static __initdata struct paca_struct boot_paca;
279
Benjamin Herrenschmidt24d96492008-05-07 10:00:56 +1000280 /* -------- printk is _NOT_ safe to use here ! ------- */
281
Nicholas Piggin5a61ef72017-05-09 13:16:52 +1000282 /* Try new device tree based feature discovery ... */
283 if (!dt_cpu_ftrs_init(__va(dt_ptr)))
284 /* Otherwise use the old style CPU table */
285 identify_cpu(0, mfspr(SPRN_PVR));
Benjamin Herrenschmidt42c4aaa2006-10-24 16:42:40 +1000286
Michael Ellerman33dbcf72006-06-28 13:18:53 +1000287 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
Michael Ellerman1426d5a2010-01-28 13:23:22 +0000288 initialise_paca(&boot_paca, 0);
289 setup_paca(&boot_paca);
Michael Ellerman25e13812013-02-12 14:44:50 +0000290 fixup_boot_paca();
Michael Ellerman33dbcf72006-06-28 13:18:53 +1000291
Benjamin Herrenschmidt24d96492008-05-07 10:00:56 +1000292 /* -------- printk is now safe to use ------- */
293
Benjamin Herrenschmidtf2fd2512008-05-07 10:25:34 +1000294 /* Enable early debugging if any specified (see udbg.h) */
295 udbg_early_init();
296
Benjamin Herrenschmidte8222502006-03-28 23:15:54 +1100297 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000298
299 /*
Linas Vepstas3c607ce2007-09-07 03:47:29 +1000300 * Do early initialization using the flattened device
301 * tree, such as retrieving the physical memory map or
302 * calculating/retrieving the hash table size.
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000303 */
304 early_init_devtree(__va(dt_ptr));
305
Anton Blanchard4df20462006-03-25 17:25:17 +1100306 /* Now we know the logical id of our boot cpu, setup the paca. */
Michael Ellerman1426d5a2010-01-28 13:23:22 +0000307 setup_paca(&paca[boot_cpuid]);
Michael Ellerman25e13812013-02-12 14:44:50 +0000308 fixup_boot_paca();
Anton Blanchard4df20462006-03-25 17:25:17 +1100309
Benjamin Herrenschmidt63c254a2016-07-05 15:03:46 +1000310 /*
Benjamin Herrenschmidtd3cbff12016-07-05 15:03:49 +1000311 * Configure exception handlers. This include setting up trampolines
312 * if needed, setting exception endian mode, etc...
Benjamin Herrenschmidt63c254a2016-07-05 15:03:46 +1000313 */
Benjamin Herrenschmidtd3cbff12016-07-05 15:03:49 +1000314 configure_exceptions();
Michael Ellerman0cc47462005-12-04 18:39:37 +1100315
Benjamin Herrenschmidtc4bd6cb2016-07-05 15:03:42 +1000316 /* Apply all the dynamic patching */
317 apply_feature_fixups();
Benjamin Herrenschmidt97f6e0c2016-08-10 17:27:34 +1000318 setup_feature_keys();
Benjamin Herrenschmidtc4bd6cb2016-07-05 15:03:42 +1000319
Michael Ellerman9e8066f2016-07-26 21:55:48 +1000320 /* Initialize the hash table or TLB handling */
321 early_init_mmu();
322
Benjamin Herrenschmidta944a9c2014-03-28 13:36:29 +1100323 /*
Nicholas Piggin1696d0f2017-10-24 21:44:44 +1000324 * After firmware and early platform setup code has set things up,
325 * we note the SPR values for configurable control/performance
326 * registers, and use those as initial defaults.
327 */
328 record_spr_defaults();
329
330 /*
Benjamin Herrenschmidta944a9c2014-03-28 13:36:29 +1100331 * At this point, we can let interrupts switch to virtual mode
332 * (the MMU has been setup), so adjust the MSR in the PACA to
Benjamin Herrenschmidt8f619b542014-03-28 13:36:30 +1100333 * have IR and DR set and enable AIL if it exists
Benjamin Herrenschmidta944a9c2014-03-28 13:36:29 +1100334 */
Benjamin Herrenschmidt8f619b542014-03-28 13:36:30 +1100335 cpu_ready_for_interrupts();
Benjamin Herrenschmidta944a9c2014-03-28 13:36:29 +1100336
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000337 DBG(" <- early_setup()\n");
Benjamin Herrenschmidt7191b612013-07-25 12:12:32 +1000338
339#ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
340 /*
341 * This needs to be done *last* (after the above DBG() even)
342 *
343 * Right after we return from this function, we turn on the MMU
344 * which means the real-mode access trick that btext does will
345 * no longer work, it needs to switch to using a real MMU
346 * mapping. This call will ensure that it does
347 */
348 btext_map();
349#endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000350}
351
Paul Mackerras799d6042005-11-10 13:37:51 +1100352#ifdef CONFIG_SMP
353void early_setup_secondary(void)
354{
Madhavan Srinivasan103b7822016-03-04 10:31:48 +0530355 /* Mark interrupts disabled in PACA */
Madhavan Srinivasan4e26bc42017-12-20 09:25:50 +0530356 irq_soft_mask_set(IRQS_DISABLED);
Paul Mackerras799d6042005-11-10 13:37:51 +1100357
Benjamin Herrenschmidt757c74d2009-03-19 19:34:16 +0000358 /* Initialize the hash table or TLB handling */
359 early_init_mmu_secondary();
Benjamin Herrenschmidta944a9c2014-03-28 13:36:29 +1100360
361 /*
362 * At this point, we can let interrupts switch to virtual mode
363 * (the MMU has been setup), so adjust the MSR in the PACA to
364 * have IR and DR set.
365 */
Benjamin Herrenschmidt8f619b542014-03-28 13:36:30 +1100366 cpu_ready_for_interrupts();
Paul Mackerras799d6042005-11-10 13:37:51 +1100367}
368
369#endif /* CONFIG_SMP */
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000370
Thiago Jung Bauermannda665882016-11-29 23:45:50 +1100371#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
Scott Wood567cf942015-10-06 22:48:19 -0500372static bool use_spinloop(void)
373{
Nicholas Piggin339a3292017-10-23 18:05:07 +1000374 if (IS_ENABLED(CONFIG_PPC_BOOK3S)) {
375 /*
376 * See comments in head_64.S -- not all platforms insert
377 * secondaries at __secondary_hold and wait at the spin
378 * loop.
379 */
380 if (firmware_has_feature(FW_FEATURE_OPAL))
381 return false;
Scott Wood567cf942015-10-06 22:48:19 -0500382 return true;
Nicholas Piggin339a3292017-10-23 18:05:07 +1000383 }
Scott Wood567cf942015-10-06 22:48:19 -0500384
385 /*
386 * When book3e boots from kexec, the ePAPR spin table does
387 * not get used.
388 */
389 return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
390}
391
Michael Ellermanb8f51022005-11-04 12:09:42 +1100392void smp_release_cpus(void)
393{
Michael Ellerman758438a2005-12-05 15:49:00 -0600394 unsigned long *ptr;
Benjamin Herrenschmidt9d07bc82011-03-16 14:54:35 +1100395 int i;
Michael Ellermanb8f51022005-11-04 12:09:42 +1100396
Scott Wood567cf942015-10-06 22:48:19 -0500397 if (!use_spinloop())
398 return;
399
Michael Ellermanb8f51022005-11-04 12:09:42 +1100400 DBG(" -> smp_release_cpus()\n");
401
402 /* All secondary cpus are spinning on a common spinloop, release them
403 * all now so they can start to spin on their individual paca
404 * spinloops. For non SMP kernels, the secondary cpus never get out
405 * of the common spinloop.
Paul Mackerras1f6a93e2008-08-30 11:40:24 +1000406 */
Michael Ellermanb8f51022005-11-04 12:09:42 +1100407
Michael Ellerman758438a2005-12-05 15:49:00 -0600408 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
409 - PHYSICAL_START);
Anton Blanchard2751b622014-03-11 11:54:06 +1100410 *ptr = ppc_function_entry(generic_secondary_smp_init);
Benjamin Herrenschmidt9d07bc82011-03-16 14:54:35 +1100411
412 /* And wait a bit for them to catch up */
413 for (i = 0; i < 100000; i++) {
414 mb();
415 HMT_low();
Matt Evans7ac87ab2011-05-25 18:09:12 +0000416 if (spinning_secondaries == 0)
Benjamin Herrenschmidt9d07bc82011-03-16 14:54:35 +1100417 break;
418 udelay(1);
419 }
Matt Evans7ac87ab2011-05-25 18:09:12 +0000420 DBG("spinning_secondaries = %d\n", spinning_secondaries);
Michael Ellermanb8f51022005-11-04 12:09:42 +1100421
422 DBG(" <- smp_release_cpus()\n");
423}
Thiago Jung Bauermannda665882016-11-29 23:45:50 +1100424#endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
Michael Ellermanb8f51022005-11-04 12:09:42 +1100425
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000426/*
Paul Mackerras799d6042005-11-10 13:37:51 +1100427 * Initialize some remaining members of the ppc64_caches and systemcfg
428 * structures
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000429 * (at least until we get rid of them completely). This is mostly some
430 * cache informations about the CPU that will be used by cache flush
431 * routines and/or provided to userland
432 */
Benjamin Herrenschmidte2827fe2017-01-08 17:31:47 -0600433
434static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
435 u32 bsize, u32 sets)
436{
437 info->size = size;
438 info->sets = sets;
439 info->line_size = lsize;
440 info->block_size = bsize;
441 info->log_block_size = __ilog2(bsize);
Anton Blanchard6ba422c2017-03-05 10:54:34 +1100442 if (bsize)
443 info->blocks_per_page = PAGE_SIZE / bsize;
444 else
445 info->blocks_per_page = 0;
Benjamin Herrenschmidt98a5f362017-02-03 17:20:07 +1100446
447 if (sets == 0)
448 info->assoc = 0xffff;
449 else
450 info->assoc = size / (sets * lsize);
Benjamin Herrenschmidte2827fe2017-01-08 17:31:47 -0600451}
452
453static bool __init parse_cache_info(struct device_node *np,
454 bool icache,
455 struct ppc_cache_info *info)
456{
457 static const char *ipropnames[] __initdata = {
458 "i-cache-size",
459 "i-cache-sets",
460 "i-cache-block-size",
461 "i-cache-line-size",
462 };
463 static const char *dpropnames[] __initdata = {
464 "d-cache-size",
465 "d-cache-sets",
466 "d-cache-block-size",
467 "d-cache-line-size",
468 };
469 const char **propnames = icache ? ipropnames : dpropnames;
470 const __be32 *sizep, *lsizep, *bsizep, *setsp;
471 u32 size, lsize, bsize, sets;
472 bool success = true;
473
474 size = 0;
475 sets = -1u;
476 lsize = bsize = cur_cpu_spec->dcache_bsize;
477 sizep = of_get_property(np, propnames[0], NULL);
478 if (sizep != NULL)
479 size = be32_to_cpu(*sizep);
480 setsp = of_get_property(np, propnames[1], NULL);
481 if (setsp != NULL)
482 sets = be32_to_cpu(*setsp);
483 bsizep = of_get_property(np, propnames[2], NULL);
484 lsizep = of_get_property(np, propnames[3], NULL);
485 if (bsizep == NULL)
486 bsizep = lsizep;
487 if (lsizep != NULL)
488 lsize = be32_to_cpu(*lsizep);
489 if (bsizep != NULL)
490 bsize = be32_to_cpu(*bsizep);
491 if (sizep == NULL || bsizep == NULL || lsizep == NULL)
492 success = false;
493
494 /*
495 * OF is weird .. it represents fully associative caches
496 * as "1 way" which doesn't make much sense and doesn't
497 * leave room for direct mapped. We'll assume that 0
498 * in OF means direct mapped for that reason.
499 */
500 if (sets == 1)
501 sets = 0;
502 else if (sets == 0)
503 sets = 1;
504
505 init_cache_info(info, size, lsize, bsize, sets);
506
507 return success;
508}
509
Benjamin Herrenschmidtb1923ca2016-07-05 15:07:51 +1000510void __init initialize_cache_info(void)
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000511{
Benjamin Herrenschmidt608b4212017-01-08 17:31:49 -0600512 struct device_node *cpu = NULL, *l2, *l3 = NULL;
513 u32 pvr;
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000514
515 DBG(" -> initialize_cache_info()\n");
516
Benjamin Herrenschmidt608b4212017-01-08 17:31:49 -0600517 /*
518 * All shipping POWER8 machines have a firmware bug that
519 * puts incorrect information in the device-tree. This will
520 * be (hopefully) fixed for future chips but for now hard
521 * code the values if we are running on one of these
522 */
523 pvr = PVR_VER(mfspr(SPRN_PVR));
524 if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
525 pvr == PVR_POWER8NVL) {
526 /* size lsize blk sets */
527 init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32);
528 init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64);
529 init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512);
530 init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192);
531 } else
532 cpu = of_find_node_by_type(NULL, "cpu");
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000533
Benjamin Herrenschmidte2827fe2017-01-08 17:31:47 -0600534 /*
535 * We're assuming *all* of the CPUs have the same
536 * d-cache and i-cache sizes... -Peter
537 */
Benjamin Herrenschmidt65e01f32017-01-08 17:31:48 -0600538 if (cpu) {
539 if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
Benjamin Herrenschmidte2827fe2017-01-08 17:31:47 -0600540 DBG("Argh, can't find dcache properties !\n");
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000541
Benjamin Herrenschmidt65e01f32017-01-08 17:31:48 -0600542 if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
Benjamin Herrenschmidte2827fe2017-01-08 17:31:47 -0600543 DBG("Argh, can't find icache properties !\n");
Benjamin Herrenschmidt65e01f32017-01-08 17:31:48 -0600544
545 /*
546 * Try to find the L2 and L3 if any. Assume they are
547 * unified and use the D-side properties.
548 */
549 l2 = of_find_next_cache_node(cpu);
550 of_node_put(cpu);
551 if (l2) {
552 parse_cache_info(l2, false, &ppc64_caches.l2);
553 l3 = of_find_next_cache_node(l2);
554 of_node_put(l2);
555 }
556 if (l3) {
557 parse_cache_info(l3, false, &ppc64_caches.l3);
558 of_node_put(l3);
559 }
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000560 }
561
Benjamin Herrenschmidt9df549a2016-07-05 15:04:08 +1000562 /* For use by binfmt_elf */
Benjamin Herrenschmidte2827fe2017-01-08 17:31:47 -0600563 dcache_bsize = ppc64_caches.l1d.block_size;
564 icache_bsize = ppc64_caches.l1i.block_size;
Benjamin Herrenschmidt9df549a2016-07-05 15:04:08 +1000565
Nicholas Piggin5a61ef72017-05-09 13:16:52 +1000566 cur_cpu_spec->dcache_bsize = dcache_bsize;
567 cur_cpu_spec->icache_bsize = icache_bsize;
568
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000569 DBG(" <- initialize_cache_info()\n");
570}
571
Nicholas Piggin1af19332017-12-22 21:17:13 +1000572/*
573 * This returns the limit below which memory accesses to the linear
574 * mapping are guarnateed not to cause an architectural exception (e.g.,
575 * TLB or SLB miss fault).
576 *
577 * This is used to allocate PACAs and various interrupt stacks that
578 * that are accessed early in interrupt handlers that must not cause
579 * re-entrant interrupts.
Benjamin Herrenschmidt40bd5872011-05-03 14:07:01 +0000580 */
Nicholas Piggin1af19332017-12-22 21:17:13 +1000581__init u64 ppc64_bolted_size(void)
Anton Blanchard095c7962010-05-10 18:59:18 +0000582{
Benjamin Herrenschmidt40bd5872011-05-03 14:07:01 +0000583#ifdef CONFIG_PPC_BOOK3E
584 /* Freescale BookE bolts the entire linear mapping */
Nicholas Piggin1af19332017-12-22 21:17:13 +1000585 /* XXX: BookE ppc64_rma_limit setup seems to disagree? */
586 if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E))
Benjamin Herrenschmidt40bd5872011-05-03 14:07:01 +0000587 return linear_map_top;
588 /* Other BookE, we assume the first GB is bolted */
589 return 1ul << 30;
590#else
Nicholas Piggin1af19332017-12-22 21:17:13 +1000591 /* BookS radix, does not take faults on linear mapping */
Nicholas Piggind5507192017-08-13 11:33:41 +1000592 if (early_radix_enabled())
593 return ULONG_MAX;
594
Nicholas Piggin1af19332017-12-22 21:17:13 +1000595 /* BookS hash, the first segment is bolted */
596 if (early_mmu_has_feature(MMU_FTR_1T_SEGMENT))
Anton Blanchard095c7962010-05-10 18:59:18 +0000597 return 1UL << SID_SHIFT_1T;
Anton Blanchard095c7962010-05-10 18:59:18 +0000598 return 1UL << SID_SHIFT;
Benjamin Herrenschmidt40bd5872011-05-03 14:07:01 +0000599#endif
Anton Blanchard095c7962010-05-10 18:59:18 +0000600}
601
Benjamin Herrenschmidtb1923ca2016-07-05 15:07:51 +1000602void __init irqstack_early_init(void)
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000603{
Nicholas Piggin1af19332017-12-22 21:17:13 +1000604 u64 limit = ppc64_bolted_size();
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000605 unsigned int i;
606
607 /*
Anton Blanchard8f4da262010-12-08 00:55:03 +0000608 * Interrupt stacks must be in the first segment since we
Nicholas Piggind5507192017-08-13 11:33:41 +1000609 * cannot afford to take SLB misses on them. They are not
610 * accessed in realmode.
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000611 */
KAMEZAWA Hiroyuki0e551952006-03-28 14:50:51 -0800612 for_each_possible_cpu(i) {
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100613 softirq_ctx[i] = (struct thread_info *)
Yinghai Lu95f72d12010-07-12 14:36:09 +1000614 __va(memblock_alloc_base(THREAD_SIZE,
Anton Blanchard095c7962010-05-10 18:59:18 +0000615 THREAD_SIZE, limit));
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100616 hardirq_ctx[i] = (struct thread_info *)
Yinghai Lu95f72d12010-07-12 14:36:09 +1000617 __va(memblock_alloc_base(THREAD_SIZE,
Anton Blanchard095c7962010-05-10 18:59:18 +0000618 THREAD_SIZE, limit));
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000619 }
620}
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000621
Benjamin Herrenschmidt2d27cfd2009-07-23 23:15:59 +0000622#ifdef CONFIG_PPC_BOOK3E
Benjamin Herrenschmidtb1923ca2016-07-05 15:07:51 +1000623void __init exc_lvl_early_init(void)
Benjamin Herrenschmidt2d27cfd2009-07-23 23:15:59 +0000624{
625 unsigned int i;
Tiejun Chen160c7322013-10-23 17:31:21 +0800626 unsigned long sp;
Benjamin Herrenschmidt2d27cfd2009-07-23 23:15:59 +0000627
628 for_each_possible_cpu(i) {
Tiejun Chen160c7322013-10-23 17:31:21 +0800629 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
630 critirq_ctx[i] = (struct thread_info *)__va(sp);
631 paca[i].crit_kstack = __va(sp + THREAD_SIZE);
632
633 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
634 dbgirq_ctx[i] = (struct thread_info *)__va(sp);
635 paca[i].dbg_kstack = __va(sp + THREAD_SIZE);
636
637 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
638 mcheckirq_ctx[i] = (struct thread_info *)__va(sp);
639 paca[i].mc_kstack = __va(sp + THREAD_SIZE);
Benjamin Herrenschmidt2d27cfd2009-07-23 23:15:59 +0000640 }
Kumar Galad36b4c42011-04-06 00:18:48 -0500641
642 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
Kevin Hao565c2f22013-05-12 07:26:23 +0800643 patch_exception(0x040, exc_debug_debug_book3e);
Benjamin Herrenschmidt2d27cfd2009-07-23 23:15:59 +0000644}
Benjamin Herrenschmidt2d27cfd2009-07-23 23:15:59 +0000645#endif
646
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000647/*
Nicholas Piggin34f19ff2017-06-21 15:58:29 +1000648 * Emergency stacks are used for a range of things, from asynchronous
649 * NMIs (system reset, machine check) to synchronous, process context.
650 * We set preempt_count to zero, even though that isn't necessarily correct. To
651 * get the right value we'd need to copy it from the previous thread_info, but
652 * doing that might fault causing more problems.
653 * TODO: what to do with accounting?
654 */
655static void emerg_stack_init_thread_info(struct thread_info *ti, int cpu)
656{
657 ti->task = NULL;
658 ti->cpu = cpu;
659 ti->preempt_count = 0;
660 ti->local_flags = 0;
661 ti->flags = 0;
662 klp_init_thread_info(ti);
663}
664
665/*
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000666 * Stack space used when we detect a bad kernel stack pointer, and
Mahesh Salgaonkar729b0f72013-10-30 20:04:00 +0530667 * early in SMP boots before relocation is enabled. Exclusive emergency
668 * stack for machine checks.
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000669 */
Benjamin Herrenschmidtb1923ca2016-07-05 15:07:51 +1000670void __init emergency_stack_init(void)
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000671{
Anton Blanchard095c7962010-05-10 18:59:18 +0000672 u64 limit;
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000673 unsigned int i;
674
675 /*
676 * Emergency stacks must be under 256MB, we cannot afford to take
677 * SLB misses on them. The ABI also requires them to be 128-byte
678 * aligned.
679 *
680 * Since we use these as temporary stacks during secondary CPU
Nicholas Piggind5507192017-08-13 11:33:41 +1000681 * bringup, machine check, system reset, and HMI, we need to get
682 * at them in real mode. This means they must also be within the RMO
683 * region.
Nicholas Piggin34f19ff2017-06-21 15:58:29 +1000684 *
685 * The IRQ stacks allocated elsewhere in this file are zeroed and
686 * initialized in kernel/irq.c. These are initialized here in order
687 * to have emergency stacks available as early as possible.
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000688 */
Nicholas Piggin1af19332017-12-22 21:17:13 +1000689 limit = min(ppc64_bolted_size(), ppc64_rma_size);
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000690
Michael Ellerman3243d872008-04-30 13:21:45 +1000691 for_each_possible_cpu(i) {
Michael Ellerman5d31a962016-03-24 22:04:04 +1100692 struct thread_info *ti;
693 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
Nicholas Piggin34f19ff2017-06-21 15:58:29 +1000694 memset(ti, 0, THREAD_SIZE);
695 emerg_stack_init_thread_info(ti, i);
Michael Ellerman5d31a962016-03-24 22:04:04 +1100696 paca[i].emergency_sp = (void *)ti + THREAD_SIZE;
Mahesh Salgaonkar729b0f72013-10-30 20:04:00 +0530697
698#ifdef CONFIG_PPC_BOOK3S_64
Nicholas Pigginb1ee8a32016-12-20 04:30:06 +1000699 /* emergency stack for NMI exception handling. */
700 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
Nicholas Piggin34f19ff2017-06-21 15:58:29 +1000701 memset(ti, 0, THREAD_SIZE);
702 emerg_stack_init_thread_info(ti, i);
Nicholas Pigginb1ee8a32016-12-20 04:30:06 +1000703 paca[i].nmi_emergency_sp = (void *)ti + THREAD_SIZE;
704
Mahesh Salgaonkar729b0f72013-10-30 20:04:00 +0530705 /* emergency stack for machine check exception handling. */
Michael Ellerman5d31a962016-03-24 22:04:04 +1100706 ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
Nicholas Piggin34f19ff2017-06-21 15:58:29 +1000707 memset(ti, 0, THREAD_SIZE);
708 emerg_stack_init_thread_info(ti, i);
Michael Ellerman5d31a962016-03-24 22:04:04 +1100709 paca[i].mc_emergency_sp = (void *)ti + THREAD_SIZE;
Mahesh Salgaonkar729b0f72013-10-30 20:04:00 +0530710#endif
Michael Ellerman3243d872008-04-30 13:21:45 +1000711 }
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000712}
713
Anton Blanchard7a0268f2006-01-11 13:16:44 +1100714#ifdef CONFIG_SMP
Tejun Heoc2a7e812009-08-14 15:00:53 +0900715#define PCPU_DYN_SIZE ()
716
717static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
718{
Michael Ellermanba4a6482017-06-06 20:23:57 +1000719 return __alloc_bootmem_node(NODE_DATA(early_cpu_to_node(cpu)), size, align,
Tejun Heoc2a7e812009-08-14 15:00:53 +0900720 __pa(MAX_DMA_ADDRESS));
721}
722
723static void __init pcpu_fc_free(void *ptr, size_t size)
724{
725 free_bootmem(__pa(ptr), size);
726}
727
728static int pcpu_cpu_distance(unsigned int from, unsigned int to)
729{
Michael Ellermanba4a6482017-06-06 20:23:57 +1000730 if (early_cpu_to_node(from) == early_cpu_to_node(to))
Tejun Heoc2a7e812009-08-14 15:00:53 +0900731 return LOCAL_DISTANCE;
732 else
733 return REMOTE_DISTANCE;
734}
735
Anton Blanchardae01f842010-05-31 18:45:11 +0000736unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
737EXPORT_SYMBOL(__per_cpu_offset);
738
Anton Blanchard7a0268f2006-01-11 13:16:44 +1100739void __init setup_per_cpu_areas(void)
740{
Tejun Heoc2a7e812009-08-14 15:00:53 +0900741 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
742 size_t atom_size;
743 unsigned long delta;
744 unsigned int cpu;
745 int rc;
Anton Blanchard7a0268f2006-01-11 13:16:44 +1100746
Tejun Heoc2a7e812009-08-14 15:00:53 +0900747 /*
748 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
749 * to group units. For larger mappings, use 1M atom which
750 * should be large enough to contain a number of units.
751 */
752 if (mmu_linear_psize == MMU_PAGE_4K)
753 atom_size = PAGE_SIZE;
754 else
755 atom_size = 1 << 20;
Anton Blanchard7a0268f2006-01-11 13:16:44 +1100756
Tejun Heoc2a7e812009-08-14 15:00:53 +0900757 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
758 pcpu_fc_alloc, pcpu_fc_free);
759 if (rc < 0)
760 panic("cannot initialize percpu area (err=%d)", rc);
Anton Blanchard7a0268f2006-01-11 13:16:44 +1100761
Tejun Heoc2a7e812009-08-14 15:00:53 +0900762 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
Anton Blanchardae01f842010-05-31 18:45:11 +0000763 for_each_possible_cpu(cpu) {
764 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
765 paca[cpu].data_offset = __per_cpu_offset[cpu];
766 }
Anton Blanchard7a0268f2006-01-11 13:16:44 +1100767}
768#endif
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100769
Anton Blancharda5d86252014-06-04 17:50:47 +1000770#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
771unsigned long memory_block_size_bytes(void)
772{
773 if (ppc_md.memory_block_size)
774 return ppc_md.memory_block_size();
775
776 return MIN_MEMORY_BLOCK_SIZE;
777}
778#endif
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100779
Benjamin Herrenschmidtecd73cc2013-07-15 13:03:08 +1000780#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
Benjamin Herrenschmidt4cb3cee2006-11-11 17:25:10 +1100781struct ppc_pci_io ppc_pci_io;
782EXPORT_SYMBOL(ppc_pci_io);
Benjamin Herrenschmidtecd73cc2013-07-15 13:03:08 +1000783#endif
Nicholas Piggin70412c52017-08-28 14:27:19 +1000784
785#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
786u64 hw_nmi_get_sample_period(int watchdog_thresh)
787{
788 return ppc_proc_freq * watchdog_thresh;
789}
790#endif
791
792/*
793 * The perf based hardlockup detector breaks PMU event based branches, so
794 * disable it by default. Book3S has a soft-nmi hardlockup detector based
795 * on the decrementer interrupt, so it does not suffer from this problem.
796 *
797 * It is likely to get false positives in VM guests, so disable it there
798 * by default too.
799 */
800static int __init disable_hardlockup_detector(void)
801{
802#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
803 hardlockup_detector_disable();
804#else
805 if (firmware_has_feature(FW_FEATURE_LPAR))
806 hardlockup_detector_disable();
807#endif
808
809 return 0;
810}
811early_initcall(disable_hardlockup_detector);
Michael Ellermanaa8a5e02018-01-10 03:07:15 +1100812
813#ifdef CONFIG_PPC_BOOK3S_64
814static enum l1d_flush_type enabled_flush_types;
815static void *l1d_flush_fallback_area;
Michael Ellermanbc9c9302018-01-10 03:07:15 +1100816static bool no_rfi_flush;
Michael Ellermanaa8a5e02018-01-10 03:07:15 +1100817bool rfi_flush;
818
Michael Ellermanbc9c9302018-01-10 03:07:15 +1100819static int __init handle_no_rfi_flush(char *p)
820{
821 pr_info("rfi-flush: disabled on command line.");
822 no_rfi_flush = true;
823 return 0;
824}
825early_param("no_rfi_flush", handle_no_rfi_flush);
826
827/*
828 * The RFI flush is not KPTI, but because users will see doco that says to use
829 * nopti we hijack that option here to also disable the RFI flush.
830 */
831static int __init handle_no_pti(char *p)
832{
833 pr_info("rfi-flush: disabling due to 'nopti' on command line.\n");
834 handle_no_rfi_flush(NULL);
835 return 0;
836}
837early_param("nopti", handle_no_pti);
838
Michael Ellermanaa8a5e02018-01-10 03:07:15 +1100839static void do_nothing(void *unused)
840{
841 /*
842 * We don't need to do the flush explicitly, just enter+exit kernel is
843 * sufficient, the RFI exit handlers will do the right thing.
844 */
845}
846
847void rfi_flush_enable(bool enable)
848{
Michael Ellermanaa8a5e02018-01-10 03:07:15 +1100849 if (enable) {
850 do_rfi_flush_fixups(enabled_flush_types);
851 on_each_cpu(do_nothing, NULL, 1);
852 } else
853 do_rfi_flush_fixups(L1D_FLUSH_NONE);
854
855 rfi_flush = enable;
856}
857
858static void init_fallback_flush(void)
859{
860 u64 l1d_size, limit;
861 int cpu;
862
Michael Ellermanabf110f2018-03-14 19:40:39 -0300863 /* Only allocate the fallback flush area once (at boot time). */
864 if (l1d_flush_fallback_area)
865 return;
866
Michael Ellermanaa8a5e02018-01-10 03:07:15 +1100867 l1d_size = ppc64_caches.l1d.size;
Michael Ellermanebf0b6a2018-01-21 23:21:14 +1100868 limit = min(ppc64_bolted_size(), ppc64_rma_size);
Michael Ellermanaa8a5e02018-01-10 03:07:15 +1100869
870 /*
871 * Align to L1d size, and size it at 2x L1d size, to catch possible
872 * hardware prefetch runoff. We don't have a recipe for load patterns to
873 * reliably avoid the prefetcher.
874 */
875 l1d_flush_fallback_area = __va(memblock_alloc_base(l1d_size * 2, l1d_size, limit));
876 memset(l1d_flush_fallback_area, 0, l1d_size * 2);
877
878 for_each_possible_cpu(cpu) {
Michael Ellermanaa8a5e02018-01-10 03:07:15 +1100879 paca[cpu].rfi_flush_fallback_area = l1d_flush_fallback_area;
Nicholas Pigginbdcb1ae2018-01-17 23:58:18 +1000880 paca[cpu].l1d_flush_size = l1d_size;
Michael Ellermanaa8a5e02018-01-10 03:07:15 +1100881 }
882}
883
Michael Ellermanabf110f2018-03-14 19:40:39 -0300884void setup_rfi_flush(enum l1d_flush_type types, bool enable)
Michael Ellermanaa8a5e02018-01-10 03:07:15 +1100885{
886 if (types & L1D_FLUSH_FALLBACK) {
887 pr_info("rfi-flush: Using fallback displacement flush\n");
888 init_fallback_flush();
889 }
890
891 if (types & L1D_FLUSH_ORI)
892 pr_info("rfi-flush: Using ori type flush\n");
893
894 if (types & L1D_FLUSH_MTTRIG)
895 pr_info("rfi-flush: Using mttrig type flush\n");
896
897 enabled_flush_types = types;
898
Michael Ellermanbc9c9302018-01-10 03:07:15 +1100899 if (!no_rfi_flush)
900 rfi_flush_enable(enable);
Michael Ellermanaa8a5e02018-01-10 03:07:15 +1100901}
Michael Ellermanfd6e4402018-01-16 21:20:05 +1100902
Michael Ellerman236003e2018-01-16 22:17:18 +1100903#ifdef CONFIG_DEBUG_FS
904static int rfi_flush_set(void *data, u64 val)
905{
Michael Ellerman1e2a9fc2018-03-14 19:40:38 -0300906 bool enable;
907
Michael Ellerman236003e2018-01-16 22:17:18 +1100908 if (val == 1)
Michael Ellerman1e2a9fc2018-03-14 19:40:38 -0300909 enable = true;
Michael Ellerman236003e2018-01-16 22:17:18 +1100910 else if (val == 0)
Michael Ellerman1e2a9fc2018-03-14 19:40:38 -0300911 enable = false;
Michael Ellerman236003e2018-01-16 22:17:18 +1100912 else
913 return -EINVAL;
914
Michael Ellerman1e2a9fc2018-03-14 19:40:38 -0300915 /* Only do anything if we're changing state */
916 if (enable != rfi_flush)
917 rfi_flush_enable(enable);
918
Michael Ellerman236003e2018-01-16 22:17:18 +1100919 return 0;
920}
921
922static int rfi_flush_get(void *data, u64 *val)
923{
924 *val = rfi_flush ? 1 : 0;
925 return 0;
926}
927
928DEFINE_SIMPLE_ATTRIBUTE(fops_rfi_flush, rfi_flush_get, rfi_flush_set, "%llu\n");
929
930static __init int rfi_flush_debugfs_init(void)
931{
932 debugfs_create_file("rfi_flush", 0600, powerpc_debugfs_root, NULL, &fops_rfi_flush);
933 return 0;
934}
935device_initcall(rfi_flush_debugfs_init);
936#endif
937
Michael Ellermanfd6e4402018-01-16 21:20:05 +1100938ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
939{
940 if (rfi_flush)
941 return sprintf(buf, "Mitigation: RFI Flush\n");
942
943 return sprintf(buf, "Vulnerable\n");
944}
Michael Ellermanaa8a5e02018-01-10 03:07:15 +1100945#endif /* CONFIG_PPC_BOOK3S_64 */