blob: 377271decbabe4f997d66ef21475132a2622fb83 [file] [log] [blame]
Fred Richterb63b36f2014-03-24 19:56:00 -03001/*
2 * Support for LGDT3306A - 8VSB/QAM-B
3 *
4 * Copyright (C) 2013 Fred Richter <frichter@hauppauge.com>
5 * - driver structure based on lgdt3305.[ch] by Michael Krufky
6 * - code based on LG3306_V0.35 API by LG Electronics Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
Fred Richterb63b36f2014-03-24 19:56:00 -030017 */
18
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -020019#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
Fred Richterb63b36f2014-03-24 19:56:00 -030021#include <asm/div64.h>
Thomas Meyer1f679ff2017-09-03 08:19:31 -040022#include <linux/kernel.h>
Fred Richterb63b36f2014-03-24 19:56:00 -030023#include <linux/dvb/frontend.h>
Mauro Carvalho Chehabfada1932017-12-28 13:03:51 -050024#include <media/dvb_math.h>
Fred Richterb63b36f2014-03-24 19:56:00 -030025#include "lgdt3306a.h"
Kevin Cheng4f751892017-01-10 01:14:18 -020026#include <linux/i2c-mux.h>
Fred Richterb63b36f2014-03-24 19:56:00 -030027
28
29static int debug;
30module_param(debug, int, 0644);
31MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
32
33#define DBG_INFO 1
34#define DBG_REG 2
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -030035#define DBG_DUMP 4 /* FGR - comment out to remove dump code */
Fred Richterb63b36f2014-03-24 19:56:00 -030036
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -020037#define lg_debug(fmt, arg...) \
38 printk(KERN_DEBUG pr_fmt(fmt), ## arg)
Fred Richterb63b36f2014-03-24 19:56:00 -030039
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -020040#define dbg_info(fmt, arg...) \
41 do { \
42 if (debug & DBG_INFO) \
43 lg_debug(fmt, ## arg); \
44 } while (0)
45
46#define dbg_reg(fmt, arg...) \
47 do { \
48 if (debug & DBG_REG) \
49 lg_debug(fmt, ## arg); \
50 } while (0)
Fred Richterb63b36f2014-03-24 19:56:00 -030051
52#define lg_chkerr(ret) \
53({ \
54 int __ret; \
55 __ret = (ret < 0); \
56 if (__ret) \
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -020057 pr_err("error %d on line %d\n", ret, __LINE__); \
Fred Richterb63b36f2014-03-24 19:56:00 -030058 __ret; \
59})
60
61struct lgdt3306a_state {
62 struct i2c_adapter *i2c_adap;
63 const struct lgdt3306a_config *cfg;
64
65 struct dvb_frontend frontend;
66
Mauro Carvalho Chehab0df289a2015-06-07 14:53:52 -030067 enum fe_modulation current_modulation;
Fred Richterb63b36f2014-03-24 19:56:00 -030068 u32 current_frequency;
69 u32 snr;
Kevin Cheng4f751892017-01-10 01:14:18 -020070
71 struct i2c_mux_core *muxc;
Fred Richterb63b36f2014-03-24 19:56:00 -030072};
73
Mauro Carvalho Chehab95f22c52014-10-28 12:40:20 -020074/*
75 * LG3306A Register Usage
76 * (LG does not really name the registers, so this code does not either)
77 *
78 * 0000 -> 00FF Common control and status
79 * 1000 -> 10FF Synchronizer control and status
80 * 1F00 -> 1FFF Smart Antenna control and status
81 * 2100 -> 21FF VSB Equalizer control and status
82 * 2800 -> 28FF QAM Equalizer control and status
83 * 3000 -> 30FF FEC control and status
84 */
Fred Richterb63b36f2014-03-24 19:56:00 -030085
Michael Ira Krufkyf883d602014-08-03 15:29:04 -030086enum lgdt3306a_lock_status {
87 LG3306_UNLOCK = 0x00,
88 LG3306_LOCK = 0x01,
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -020089 LG3306_UNKNOWN_LOCK = 0xff
Michael Ira Krufkyf883d602014-08-03 15:29:04 -030090};
Fred Richterb63b36f2014-03-24 19:56:00 -030091
Michael Ira Krufkyf883d602014-08-03 15:29:04 -030092enum lgdt3306a_neverlock_status {
Fred Richterb63b36f2014-03-24 19:56:00 -030093 LG3306_NL_INIT = 0x00,
94 LG3306_NL_PROCESS = 0x01,
95 LG3306_NL_LOCK = 0x02,
96 LG3306_NL_FAIL = 0x03,
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -020097 LG3306_NL_UNKNOWN = 0xff
Michael Ira Krufkyf883d602014-08-03 15:29:04 -030098};
Fred Richterb63b36f2014-03-24 19:56:00 -030099
Michael Ira Krufkyf883d602014-08-03 15:29:04 -0300100enum lgdt3306a_modulation {
101 LG3306_VSB = 0x00,
102 LG3306_QAM64 = 0x01,
103 LG3306_QAM256 = 0x02,
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200104 LG3306_UNKNOWN_MODE = 0xff
Michael Ira Krufkyf883d602014-08-03 15:29:04 -0300105};
Fred Richterb63b36f2014-03-24 19:56:00 -0300106
Michael Ira Krufkyf883d602014-08-03 15:29:04 -0300107enum lgdt3306a_lock_check {
Fred Richterb63b36f2014-03-24 19:56:00 -0300108 LG3306_SYNC_LOCK,
109 LG3306_FEC_LOCK,
110 LG3306_TR_LOCK,
111 LG3306_AGC_LOCK,
Michael Ira Krufkyf883d602014-08-03 15:29:04 -0300112};
Fred Richterb63b36f2014-03-24 19:56:00 -0300113
114
115#ifdef DBG_DUMP
116static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state);
117static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state);
118#endif
119
120
121static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val)
122{
123 int ret;
124 u8 buf[] = { reg >> 8, reg & 0xff, val };
125 struct i2c_msg msg = {
126 .addr = state->cfg->i2c_addr, .flags = 0,
127 .buf = buf, .len = 3,
128 };
129
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200130 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
Fred Richterb63b36f2014-03-24 19:56:00 -0300131
132 ret = i2c_transfer(state->i2c_adap, &msg, 1);
133
134 if (ret != 1) {
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200135 pr_err("error (addr %02x %02x <- %02x, err = %i)\n",
Fred Richterb63b36f2014-03-24 19:56:00 -0300136 msg.buf[0], msg.buf[1], msg.buf[2], ret);
137 if (ret < 0)
138 return ret;
139 else
140 return -EREMOTEIO;
141 }
142 return 0;
143}
144
145static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val)
146{
147 int ret;
148 u8 reg_buf[] = { reg >> 8, reg & 0xff };
149 struct i2c_msg msg[] = {
150 { .addr = state->cfg->i2c_addr,
151 .flags = 0, .buf = reg_buf, .len = 2 },
152 { .addr = state->cfg->i2c_addr,
153 .flags = I2C_M_RD, .buf = val, .len = 1 },
154 };
155
156 ret = i2c_transfer(state->i2c_adap, msg, 2);
157
158 if (ret != 2) {
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200159 pr_err("error (addr %02x reg %04x error (ret == %i)\n",
Fred Richterb63b36f2014-03-24 19:56:00 -0300160 state->cfg->i2c_addr, reg, ret);
161 if (ret < 0)
162 return ret;
163 else
164 return -EREMOTEIO;
165 }
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200166 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val);
Fred Richterb63b36f2014-03-24 19:56:00 -0300167
168 return 0;
169}
170
171#define read_reg(state, reg) \
172({ \
173 u8 __val; \
174 int ret = lgdt3306a_read_reg(state, reg, &__val); \
175 if (lg_chkerr(ret)) \
176 __val = 0; \
177 __val; \
178})
179
180static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state,
181 u16 reg, int bit, int onoff)
182{
183 u8 val;
184 int ret;
185
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200186 dbg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
Fred Richterb63b36f2014-03-24 19:56:00 -0300187
188 ret = lgdt3306a_read_reg(state, reg, &val);
189 if (lg_chkerr(ret))
190 goto fail;
191
192 val &= ~(1 << bit);
193 val |= (onoff & 1) << bit;
194
195 ret = lgdt3306a_write_reg(state, reg, val);
196 lg_chkerr(ret);
197fail:
198 return ret;
199}
200
201/* ------------------------------------------------------------------------ */
202
203static int lgdt3306a_soft_reset(struct lgdt3306a_state *state)
204{
205 int ret;
206
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200207 dbg_info("\n");
Fred Richterb63b36f2014-03-24 19:56:00 -0300208
209 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
210 if (lg_chkerr(ret))
211 goto fail;
212
213 msleep(20);
214 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
215 lg_chkerr(ret);
216
217fail:
218 return ret;
219}
220
221static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state,
222 enum lgdt3306a_mpeg_mode mode)
223{
224 u8 val;
225 int ret;
226
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200227 dbg_info("(%d)\n", mode);
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200228 /* transport packet format - TPSENB=0x80 */
229 ret = lgdt3306a_set_reg_bit(state, 0x0071, 7,
230 mode == LGDT3306A_MPEG_PARALLEL ? 1 : 0);
Fred Richterb63b36f2014-03-24 19:56:00 -0300231 if (lg_chkerr(ret))
232 goto fail;
233
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200234 /*
235 * start of packet signal duration
236 * TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration
237 */
238 ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0);
Fred Richterb63b36f2014-03-24 19:56:00 -0300239 if (lg_chkerr(ret))
240 goto fail;
241
242 ret = lgdt3306a_read_reg(state, 0x0070, &val);
243 if (lg_chkerr(ret))
244 goto fail;
245
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300246 val |= 0x10; /* TPCLKSUPB=0x10 */
Fred Richterb63b36f2014-03-24 19:56:00 -0300247
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300248 if (mode == LGDT3306A_MPEG_PARALLEL)
Fred Richterb63b36f2014-03-24 19:56:00 -0300249 val &= ~0x10;
250
251 ret = lgdt3306a_write_reg(state, 0x0070, val);
252 lg_chkerr(ret);
253
254fail:
255 return ret;
256}
257
258static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state,
259 enum lgdt3306a_tp_clock_edge edge,
260 enum lgdt3306a_tp_valid_polarity valid)
261{
262 u8 val;
263 int ret;
264
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200265 dbg_info("edge=%d, valid=%d\n", edge, valid);
Fred Richterb63b36f2014-03-24 19:56:00 -0300266
267 ret = lgdt3306a_read_reg(state, 0x0070, &val);
268 if (lg_chkerr(ret))
269 goto fail;
270
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300271 val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */
Fred Richterb63b36f2014-03-24 19:56:00 -0300272
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300273 if (edge == LGDT3306A_TPCLK_RISING_EDGE)
Fred Richterb63b36f2014-03-24 19:56:00 -0300274 val |= 0x04;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300275 if (valid == LGDT3306A_TP_VALID_HIGH)
Fred Richterb63b36f2014-03-24 19:56:00 -0300276 val |= 0x02;
277
278 ret = lgdt3306a_write_reg(state, 0x0070, val);
279 lg_chkerr(ret);
280
281fail:
282 return ret;
283}
284
285static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state,
286 int mode)
287{
288 u8 val;
289 int ret;
290
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200291 dbg_info("(%d)\n", mode);
Fred Richterb63b36f2014-03-24 19:56:00 -0300292
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300293 if (mode) {
Fred Richterb63b36f2014-03-24 19:56:00 -0300294 ret = lgdt3306a_read_reg(state, 0x0070, &val);
295 if (lg_chkerr(ret))
296 goto fail;
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200297 /*
298 * Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20,
299 * TPDATAOUTEN=0x08
300 */
301 val &= ~0xa8;
Fred Richterb63b36f2014-03-24 19:56:00 -0300302 ret = lgdt3306a_write_reg(state, 0x0070, val);
303 if (lg_chkerr(ret))
304 goto fail;
305
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200306 /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */
307 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1);
Fred Richterb63b36f2014-03-24 19:56:00 -0300308 if (lg_chkerr(ret))
309 goto fail;
310
311 } else {
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200312 /* enable IFAGC pin */
313 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0);
Fred Richterb63b36f2014-03-24 19:56:00 -0300314 if (lg_chkerr(ret))
315 goto fail;
316
317 ret = lgdt3306a_read_reg(state, 0x0070, &val);
318 if (lg_chkerr(ret))
319 goto fail;
320
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200321 val |= 0xa8; /* enable bus */
Fred Richterb63b36f2014-03-24 19:56:00 -0300322 ret = lgdt3306a_write_reg(state, 0x0070, val);
323 if (lg_chkerr(ret))
324 goto fail;
325 }
326
327fail:
328 return ret;
329}
330
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300331static int lgdt3306a_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
Fred Richterb63b36f2014-03-24 19:56:00 -0300332{
333 struct lgdt3306a_state *state = fe->demodulator_priv;
334
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200335 dbg_info("acquire=%d\n", acquire);
Fred Richterb63b36f2014-03-24 19:56:00 -0300336
337 return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1);
338
339}
340
341static int lgdt3306a_power(struct lgdt3306a_state *state,
342 int mode)
343{
344 int ret;
345
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200346 dbg_info("(%d)\n", mode);
Fred Richterb63b36f2014-03-24 19:56:00 -0300347
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300348 if (mode == 0) {
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200349 /* into reset */
350 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
Fred Richterb63b36f2014-03-24 19:56:00 -0300351 if (lg_chkerr(ret))
352 goto fail;
353
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200354 /* power down */
355 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0);
Fred Richterb63b36f2014-03-24 19:56:00 -0300356 if (lg_chkerr(ret))
357 goto fail;
358
359 } else {
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200360 /* out of reset */
361 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
Fred Richterb63b36f2014-03-24 19:56:00 -0300362 if (lg_chkerr(ret))
363 goto fail;
364
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200365 /* power up */
366 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1);
Fred Richterb63b36f2014-03-24 19:56:00 -0300367 if (lg_chkerr(ret))
368 goto fail;
369 }
370
371#ifdef DBG_DUMP
372 lgdt3306a_DumpAllRegs(state);
373#endif
374fail:
375 return ret;
376}
377
378
379static int lgdt3306a_set_vsb(struct lgdt3306a_state *state)
380{
381 u8 val;
382 int ret;
383
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200384 dbg_info("\n");
Fred Richterb63b36f2014-03-24 19:56:00 -0300385
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300386 /* 0. Spectrum inversion detection manual; spectrum inverted */
Fred Richterb63b36f2014-03-24 19:56:00 -0300387 ret = lgdt3306a_read_reg(state, 0x0002, &val);
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200388 val &= 0xf7; /* SPECINVAUTO Off */
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300389 val |= 0x04; /* SPECINV On */
Fred Richterb63b36f2014-03-24 19:56:00 -0300390 ret = lgdt3306a_write_reg(state, 0x0002, val);
391 if (lg_chkerr(ret))
392 goto fail;
393
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300394 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
Fred Richterb63b36f2014-03-24 19:56:00 -0300395 ret = lgdt3306a_write_reg(state, 0x0008, 0x80);
396 if (lg_chkerr(ret))
397 goto fail;
398
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300399 /* 2. Bandwidth mode for VSB(6MHz) */
Fred Richterb63b36f2014-03-24 19:56:00 -0300400 ret = lgdt3306a_read_reg(state, 0x0009, &val);
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200401 val &= 0xe3;
402 val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */
Fred Richterb63b36f2014-03-24 19:56:00 -0300403 ret = lgdt3306a_write_reg(state, 0x0009, val);
404 if (lg_chkerr(ret))
405 goto fail;
406
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300407 /* 3. QAM mode detection mode(None) */
Fred Richterb63b36f2014-03-24 19:56:00 -0300408 ret = lgdt3306a_read_reg(state, 0x0009, &val);
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200409 val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */
Fred Richterb63b36f2014-03-24 19:56:00 -0300410 ret = lgdt3306a_write_reg(state, 0x0009, val);
411 if (lg_chkerr(ret))
412 goto fail;
413
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300414 /* 4. ADC sampling frequency rate(2x sampling) */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200415 ret = lgdt3306a_read_reg(state, 0x000d, &val);
416 val &= 0xbf; /* SAMPLING4XFEN=0 */
417 ret = lgdt3306a_write_reg(state, 0x000d, val);
Fred Richterb63b36f2014-03-24 19:56:00 -0300418 if (lg_chkerr(ret))
419 goto fail;
420
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300421#if 0
422 /* FGR - disable any AICC filtering, testing only */
423
Fred Richterb63b36f2014-03-24 19:56:00 -0300424 ret = lgdt3306a_write_reg(state, 0x0024, 0x00);
425 if (lg_chkerr(ret))
426 goto fail;
427
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300428 /* AICCFIXFREQ0 NT N-1(Video rejection) */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200429 ret = lgdt3306a_write_reg(state, 0x002e, 0x00);
430 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
Fred Richterb63b36f2014-03-24 19:56:00 -0300431 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
432
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300433 /* AICCFIXFREQ1 NT N-1(Audio rejection) */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200434 ret = lgdt3306a_write_reg(state, 0x002b, 0x00);
435 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
436 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
Fred Richterb63b36f2014-03-24 19:56:00 -0300437
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300438 /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
Fred Richterb63b36f2014-03-24 19:56:00 -0300439 ret = lgdt3306a_write_reg(state, 0x0028, 0x00);
440 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200441 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
Fred Richterb63b36f2014-03-24 19:56:00 -0300442
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300443 /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
Fred Richterb63b36f2014-03-24 19:56:00 -0300444 ret = lgdt3306a_write_reg(state, 0x0025, 0x00);
445 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
446 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
447
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300448#else
449 /* FGR - this works well for HVR-1955,1975 */
450
451 /* 5. AICCOPMODE NT N-1 Adj. */
Fred Richterb63b36f2014-03-24 19:56:00 -0300452 ret = lgdt3306a_write_reg(state, 0x0024, 0x5A);
453 if (lg_chkerr(ret))
454 goto fail;
455
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300456 /* AICCFIXFREQ0 NT N-1(Video rejection) */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200457 ret = lgdt3306a_write_reg(state, 0x002e, 0x5A);
458 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
Fred Richterb63b36f2014-03-24 19:56:00 -0300459 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
460
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300461 /* AICCFIXFREQ1 NT N-1(Audio rejection) */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200462 ret = lgdt3306a_write_reg(state, 0x002b, 0x36);
463 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
464 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
Fred Richterb63b36f2014-03-24 19:56:00 -0300465
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300466 /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
Fred Richterb63b36f2014-03-24 19:56:00 -0300467 ret = lgdt3306a_write_reg(state, 0x0028, 0x2A);
468 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200469 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
Fred Richterb63b36f2014-03-24 19:56:00 -0300470
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300471 /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
Fred Richterb63b36f2014-03-24 19:56:00 -0300472 ret = lgdt3306a_write_reg(state, 0x0025, 0x06);
473 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
474 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
475#endif
476
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200477 ret = lgdt3306a_read_reg(state, 0x001e, &val);
478 val &= 0x0f;
479 val |= 0xa0;
480 ret = lgdt3306a_write_reg(state, 0x001e, val);
Fred Richterb63b36f2014-03-24 19:56:00 -0300481
482 ret = lgdt3306a_write_reg(state, 0x0022, 0x08);
483
484 ret = lgdt3306a_write_reg(state, 0x0023, 0xFF);
485
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200486 ret = lgdt3306a_read_reg(state, 0x211f, &val);
487 val &= 0xef;
488 ret = lgdt3306a_write_reg(state, 0x211f, val);
Fred Richterb63b36f2014-03-24 19:56:00 -0300489
490 ret = lgdt3306a_write_reg(state, 0x2173, 0x01);
491
492 ret = lgdt3306a_read_reg(state, 0x1061, &val);
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200493 val &= 0xf8;
Fred Richterb63b36f2014-03-24 19:56:00 -0300494 val |= 0x04;
495 ret = lgdt3306a_write_reg(state, 0x1061, val);
496
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200497 ret = lgdt3306a_read_reg(state, 0x103d, &val);
498 val &= 0xcf;
499 ret = lgdt3306a_write_reg(state, 0x103d, val);
Fred Richterb63b36f2014-03-24 19:56:00 -0300500
501 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
502
503 ret = lgdt3306a_read_reg(state, 0x2141, &val);
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200504 val &= 0x3f;
Fred Richterb63b36f2014-03-24 19:56:00 -0300505 ret = lgdt3306a_write_reg(state, 0x2141, val);
506
507 ret = lgdt3306a_read_reg(state, 0x2135, &val);
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200508 val &= 0x0f;
Fred Richterb63b36f2014-03-24 19:56:00 -0300509 val |= 0x70;
510 ret = lgdt3306a_write_reg(state, 0x2135, val);
511
512 ret = lgdt3306a_read_reg(state, 0x0003, &val);
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200513 val &= 0xf7;
Fred Richterb63b36f2014-03-24 19:56:00 -0300514 ret = lgdt3306a_write_reg(state, 0x0003, val);
515
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200516 ret = lgdt3306a_read_reg(state, 0x001c, &val);
517 val &= 0x7f;
518 ret = lgdt3306a_write_reg(state, 0x001c, val);
Fred Richterb63b36f2014-03-24 19:56:00 -0300519
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300520 /* 6. EQ step size */
Fred Richterb63b36f2014-03-24 19:56:00 -0300521 ret = lgdt3306a_read_reg(state, 0x2179, &val);
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200522 val &= 0xf8;
Fred Richterb63b36f2014-03-24 19:56:00 -0300523 ret = lgdt3306a_write_reg(state, 0x2179, val);
524
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200525 ret = lgdt3306a_read_reg(state, 0x217a, &val);
526 val &= 0xf8;
527 ret = lgdt3306a_write_reg(state, 0x217a, val);
Fred Richterb63b36f2014-03-24 19:56:00 -0300528
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300529 /* 7. Reset */
Fred Richterb63b36f2014-03-24 19:56:00 -0300530 ret = lgdt3306a_soft_reset(state);
531 if (lg_chkerr(ret))
532 goto fail;
533
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200534 dbg_info("complete\n");
Fred Richterb63b36f2014-03-24 19:56:00 -0300535fail:
536 return ret;
537}
538
539static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation)
540{
541 u8 val;
542 int ret;
543
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200544 dbg_info("modulation=%d\n", modulation);
Fred Richterb63b36f2014-03-24 19:56:00 -0300545
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300546 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
Fred Richterb63b36f2014-03-24 19:56:00 -0300547 ret = lgdt3306a_write_reg(state, 0x0008, 0x08);
548 if (lg_chkerr(ret))
549 goto fail;
550
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300551 /* 1a. Spectrum inversion detection to Auto */
Fred Richterb63b36f2014-03-24 19:56:00 -0300552 ret = lgdt3306a_read_reg(state, 0x0002, &val);
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200553 val &= 0xfb; /* SPECINV Off */
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300554 val |= 0x08; /* SPECINVAUTO On */
Fred Richterb63b36f2014-03-24 19:56:00 -0300555 ret = lgdt3306a_write_reg(state, 0x0002, val);
556 if (lg_chkerr(ret))
557 goto fail;
558
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300559 /* 2. Bandwidth mode for QAM */
Fred Richterb63b36f2014-03-24 19:56:00 -0300560 ret = lgdt3306a_read_reg(state, 0x0009, &val);
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200561 val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */
Fred Richterb63b36f2014-03-24 19:56:00 -0300562 ret = lgdt3306a_write_reg(state, 0x0009, val);
563 if (lg_chkerr(ret))
564 goto fail;
565
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300566 /* 3. : 64QAM/256QAM detection(manual, auto) */
Fred Richterb63b36f2014-03-24 19:56:00 -0300567 ret = lgdt3306a_read_reg(state, 0x0009, &val);
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200568 val &= 0xfc;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300569 val |= 0x02; /* STDOPDETCMODE[1:0]=1=Manual 2=Auto */
Fred Richterb63b36f2014-03-24 19:56:00 -0300570 ret = lgdt3306a_write_reg(state, 0x0009, val);
571 if (lg_chkerr(ret))
572 goto fail;
573
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300574 /* 3a. : 64QAM/256QAM selection for manual */
Fred Richterb63b36f2014-03-24 19:56:00 -0300575 ret = lgdt3306a_read_reg(state, 0x101a, &val);
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200576 val &= 0xf8;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300577 if (modulation == QAM_64)
578 val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */
579 else
580 val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */
581
Fred Richterb63b36f2014-03-24 19:56:00 -0300582 ret = lgdt3306a_write_reg(state, 0x101a, val);
583 if (lg_chkerr(ret))
584 goto fail;
585
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300586 /* 4. ADC sampling frequency rate(4x sampling) */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200587 ret = lgdt3306a_read_reg(state, 0x000d, &val);
588 val &= 0xbf;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300589 val |= 0x40; /* SAMPLING4XFEN=1 */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200590 ret = lgdt3306a_write_reg(state, 0x000d, val);
Fred Richterb63b36f2014-03-24 19:56:00 -0300591 if (lg_chkerr(ret))
592 goto fail;
593
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300594 /* 5. No AICC operation in QAM mode */
Fred Richterb63b36f2014-03-24 19:56:00 -0300595 ret = lgdt3306a_read_reg(state, 0x0024, &val);
596 val &= 0x00;
597 ret = lgdt3306a_write_reg(state, 0x0024, val);
598 if (lg_chkerr(ret))
599 goto fail;
600
Brad Love4c7c3f92018-01-04 20:30:24 -0500601 /* 5.1 V0.36 SRDCHKALWAYS : For better QAM detection */
602 ret = lgdt3306a_read_reg(state, 0x000a, &val);
603 val &= 0xfd;
604 val |= 0x02;
605 ret = lgdt3306a_write_reg(state, 0x000a, val);
606 if (lg_chkerr(ret))
607 goto fail;
608
609 /* 5.2 V0.36 Control of "no signal" detector function */
610 ret = lgdt3306a_read_reg(state, 0x2849, &val);
611 val &= 0xdf;
612 ret = lgdt3306a_write_reg(state, 0x2849, val);
613 if (lg_chkerr(ret))
614 goto fail;
615
616 /* 5.3 Fix for Blonder Tongue HDE-2H-QAM and AQM modulators */
617 ret = lgdt3306a_read_reg(state, 0x302b, &val);
618 val &= 0x7f; /* SELFSYNCFINDEN_CQS=0; disable auto reset */
619 ret = lgdt3306a_write_reg(state, 0x302b, val);
620 if (lg_chkerr(ret))
621 goto fail;
622
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300623 /* 6. Reset */
Fred Richterb63b36f2014-03-24 19:56:00 -0300624 ret = lgdt3306a_soft_reset(state);
625 if (lg_chkerr(ret))
626 goto fail;
627
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200628 dbg_info("complete\n");
Fred Richterb63b36f2014-03-24 19:56:00 -0300629fail:
630 return ret;
631}
632
633static int lgdt3306a_set_modulation(struct lgdt3306a_state *state,
634 struct dtv_frontend_properties *p)
635{
636 int ret;
637
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200638 dbg_info("\n");
Fred Richterb63b36f2014-03-24 19:56:00 -0300639
640 switch (p->modulation) {
641 case VSB_8:
642 ret = lgdt3306a_set_vsb(state);
643 break;
644 case QAM_64:
645 ret = lgdt3306a_set_qam(state, QAM_64);
646 break;
647 case QAM_256:
648 ret = lgdt3306a_set_qam(state, QAM_256);
649 break;
650 default:
651 return -EINVAL;
652 }
653 if (lg_chkerr(ret))
654 goto fail;
655
656 state->current_modulation = p->modulation;
657
658fail:
659 return ret;
660}
661
662/* ------------------------------------------------------------------------ */
663
664static int lgdt3306a_agc_setup(struct lgdt3306a_state *state,
665 struct dtv_frontend_properties *p)
666{
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300667 /* TODO: anything we want to do here??? */
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200668 dbg_info("\n");
Fred Richterb63b36f2014-03-24 19:56:00 -0300669
670 switch (p->modulation) {
671 case VSB_8:
672 break;
673 case QAM_64:
674 case QAM_256:
675 break;
676 default:
677 return -EINVAL;
678 }
679 return 0;
680}
681
682/* ------------------------------------------------------------------------ */
683
684static int lgdt3306a_set_inversion(struct lgdt3306a_state *state,
685 int inversion)
686{
687 int ret;
688
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200689 dbg_info("(%d)\n", inversion);
Fred Richterb63b36f2014-03-24 19:56:00 -0300690
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300691 ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0);
Fred Richterb63b36f2014-03-24 19:56:00 -0300692 return ret;
693}
694
695static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state,
696 int enabled)
697{
698 int ret;
699
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200700 dbg_info("(%d)\n", enabled);
Fred Richterb63b36f2014-03-24 19:56:00 -0300701
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200702 /* 0=Manual 1=Auto(QAM only) - SPECINVAUTO=0x04 */
703 ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);
Fred Richterb63b36f2014-03-24 19:56:00 -0300704 return ret;
705}
706
707static int lgdt3306a_spectral_inversion(struct lgdt3306a_state *state,
708 struct dtv_frontend_properties *p,
709 int inversion)
710{
711 int ret = 0;
712
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200713 dbg_info("(%d)\n", inversion);
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300714#if 0
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200715 /*
716 * FGR - spectral_inversion defaults already set for VSB and QAM;
717 * can enable later if desired
718 */
Fred Richterb63b36f2014-03-24 19:56:00 -0300719
720 ret = lgdt3306a_set_inversion(state, inversion);
721
722 switch (p->modulation) {
723 case VSB_8:
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200724 /* Manual only for VSB */
725 ret = lgdt3306a_set_inversion_auto(state, 0);
Fred Richterb63b36f2014-03-24 19:56:00 -0300726 break;
727 case QAM_64:
728 case QAM_256:
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200729 /* Auto ok for QAM */
730 ret = lgdt3306a_set_inversion_auto(state, 1);
Fred Richterb63b36f2014-03-24 19:56:00 -0300731 break;
732 default:
733 ret = -EINVAL;
734 }
735#endif
736 return ret;
737}
738
739static int lgdt3306a_set_if(struct lgdt3306a_state *state,
740 struct dtv_frontend_properties *p)
741{
742 int ret;
743 u16 if_freq_khz;
744 u8 nco1, nco2;
745
746 switch (p->modulation) {
747 case VSB_8:
748 if_freq_khz = state->cfg->vsb_if_khz;
749 break;
750 case QAM_64:
751 case QAM_256:
752 if_freq_khz = state->cfg->qam_if_khz;
753 break;
754 default:
755 return -EINVAL;
756 }
757
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300758 switch (if_freq_khz) {
Fred Richterb63b36f2014-03-24 19:56:00 -0300759 default:
Colin Ian Kingf86548c2016-09-01 08:09:41 -0300760 pr_warn("IF=%d KHz is not supported, 3250 assumed\n",
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200761 if_freq_khz);
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300762 /* fallthrough */
Michael Ira Krufky34a5a2f2014-10-25 11:26:15 -0300763 case 3250: /* 3.25Mhz */
Fred Richterb63b36f2014-03-24 19:56:00 -0300764 nco1 = 0x34;
765 nco2 = 0x00;
766 break;
Michael Ira Krufky34a5a2f2014-10-25 11:26:15 -0300767 case 3500: /* 3.50Mhz */
Fred Richterb63b36f2014-03-24 19:56:00 -0300768 nco1 = 0x38;
769 nco2 = 0x00;
770 break;
Michael Ira Krufky34a5a2f2014-10-25 11:26:15 -0300771 case 4000: /* 4.00Mhz */
Fred Richterb63b36f2014-03-24 19:56:00 -0300772 nco1 = 0x40;
773 nco2 = 0x00;
774 break;
Michael Ira Krufky34a5a2f2014-10-25 11:26:15 -0300775 case 5000: /* 5.00Mhz */
Fred Richterb63b36f2014-03-24 19:56:00 -0300776 nco1 = 0x50;
777 nco2 = 0x00;
778 break;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300779 case 5380: /* 5.38Mhz */
Fred Richterb63b36f2014-03-24 19:56:00 -0300780 nco1 = 0x56;
781 nco2 = 0x14;
782 break;
783 }
784 ret = lgdt3306a_write_reg(state, 0x0010, nco1);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -0200785 if (ret)
786 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -0300787 ret = lgdt3306a_write_reg(state, 0x0011, nco2);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -0200788 if (ret)
789 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -0300790
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200791 dbg_info("if_freq=%d KHz->[%04x]\n", if_freq_khz, nco1<<8 | nco2);
Fred Richterb63b36f2014-03-24 19:56:00 -0300792
793 return 0;
794}
795
796/* ------------------------------------------------------------------------ */
797
798static int lgdt3306a_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
799{
800 struct lgdt3306a_state *state = fe->demodulator_priv;
801
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300802 if (state->cfg->deny_i2c_rptr) {
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200803 dbg_info("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr);
Fred Richterb63b36f2014-03-24 19:56:00 -0300804 return 0;
805 }
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200806 dbg_info("(%d)\n", enable);
Fred Richterb63b36f2014-03-24 19:56:00 -0300807
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200808 /* NI2CRPTEN=0x80 */
809 return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1);
Fred Richterb63b36f2014-03-24 19:56:00 -0300810}
811
812static int lgdt3306a_sleep(struct lgdt3306a_state *state)
813{
814 int ret;
815
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200816 dbg_info("\n");
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300817 state->current_frequency = -1; /* force re-tune, when we wake */
Fred Richterb63b36f2014-03-24 19:56:00 -0300818
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300819 ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */
Fred Richterb63b36f2014-03-24 19:56:00 -0300820 if (lg_chkerr(ret))
821 goto fail;
822
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300823 ret = lgdt3306a_power(state, 0); /* power down */
Fred Richterb63b36f2014-03-24 19:56:00 -0300824 lg_chkerr(ret);
825
826fail:
827 return 0;
828}
829
830static int lgdt3306a_fe_sleep(struct dvb_frontend *fe)
831{
832 struct lgdt3306a_state *state = fe->demodulator_priv;
833
834 return lgdt3306a_sleep(state);
835}
836
837static int lgdt3306a_init(struct dvb_frontend *fe)
838{
839 struct lgdt3306a_state *state = fe->demodulator_priv;
840 u8 val;
841 int ret;
842
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200843 dbg_info("\n");
Fred Richterb63b36f2014-03-24 19:56:00 -0300844
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300845 /* 1. Normal operation mode */
846 ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */
Fred Richterb63b36f2014-03-24 19:56:00 -0300847 if (lg_chkerr(ret))
848 goto fail;
849
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300850 /* 2. Spectrum inversion auto detection (Not valid for VSB) */
Fred Richterb63b36f2014-03-24 19:56:00 -0300851 ret = lgdt3306a_set_inversion_auto(state, 0);
852 if (lg_chkerr(ret))
853 goto fail;
854
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300855 /* 3. Spectrum inversion(According to the tuner configuration) */
Fred Richterb63b36f2014-03-24 19:56:00 -0300856 ret = lgdt3306a_set_inversion(state, 1);
857 if (lg_chkerr(ret))
858 goto fail;
859
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300860 /* 4. Peak-to-peak voltage of ADC input signal */
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200861
862 /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */
863 ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1);
Fred Richterb63b36f2014-03-24 19:56:00 -0300864 if (lg_chkerr(ret))
865 goto fail;
866
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300867 /* 5. ADC output data capture clock phase */
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200868
869 /* 0=same phase as ADC clock */
870 ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0);
Fred Richterb63b36f2014-03-24 19:56:00 -0300871 if (lg_chkerr(ret))
872 goto fail;
873
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300874 /* 5a. ADC sampling clock source */
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200875
876 /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */
877 ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0);
Fred Richterb63b36f2014-03-24 19:56:00 -0300878 if (lg_chkerr(ret))
879 goto fail;
880
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300881 /* 6. Automatic PLL set */
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -0200882
883 /* PLLSETAUTO=0x40; 0=off */
884 ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0);
Fred Richterb63b36f2014-03-24 19:56:00 -0300885 if (lg_chkerr(ret))
886 goto fail;
887
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300888 if (state->cfg->xtalMHz == 24) { /* 24MHz */
889 /* 7. Frequency for PLL output(0x2564 for 192MHz for 24MHz) */
Fred Richterb63b36f2014-03-24 19:56:00 -0300890 ret = lgdt3306a_read_reg(state, 0x0005, &val);
891 if (lg_chkerr(ret))
892 goto fail;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200893 val &= 0xc0;
Fred Richterb63b36f2014-03-24 19:56:00 -0300894 val |= 0x25;
895 ret = lgdt3306a_write_reg(state, 0x0005, val);
896 if (lg_chkerr(ret))
897 goto fail;
898 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
899 if (lg_chkerr(ret))
900 goto fail;
901
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300902 /* 8. ADC sampling frequency(0x180000 for 24MHz sampling) */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200903 ret = lgdt3306a_read_reg(state, 0x000d, &val);
Fred Richterb63b36f2014-03-24 19:56:00 -0300904 if (lg_chkerr(ret))
905 goto fail;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200906 val &= 0xc0;
Fred Richterb63b36f2014-03-24 19:56:00 -0300907 val |= 0x18;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200908 ret = lgdt3306a_write_reg(state, 0x000d, val);
Fred Richterb63b36f2014-03-24 19:56:00 -0300909 if (lg_chkerr(ret))
910 goto fail;
911
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300912 } else if (state->cfg->xtalMHz == 25) { /* 25MHz */
913 /* 7. Frequency for PLL output */
Fred Richterb63b36f2014-03-24 19:56:00 -0300914 ret = lgdt3306a_read_reg(state, 0x0005, &val);
915 if (lg_chkerr(ret))
916 goto fail;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200917 val &= 0xc0;
Fred Richterb63b36f2014-03-24 19:56:00 -0300918 val |= 0x25;
919 ret = lgdt3306a_write_reg(state, 0x0005, val);
920 if (lg_chkerr(ret))
921 goto fail;
922 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
923 if (lg_chkerr(ret))
924 goto fail;
925
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300926 /* 8. ADC sampling frequency(0x190000 for 25MHz sampling) */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200927 ret = lgdt3306a_read_reg(state, 0x000d, &val);
Fred Richterb63b36f2014-03-24 19:56:00 -0300928 if (lg_chkerr(ret))
929 goto fail;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200930 val &= 0xc0;
Fred Richterb63b36f2014-03-24 19:56:00 -0300931 val |= 0x19;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200932 ret = lgdt3306a_write_reg(state, 0x000d, val);
Fred Richterb63b36f2014-03-24 19:56:00 -0300933 if (lg_chkerr(ret))
934 goto fail;
935 } else {
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -0200936 pr_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz);
Fred Richterb63b36f2014-03-24 19:56:00 -0300937 }
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300938#if 0
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200939 ret = lgdt3306a_write_reg(state, 0x000e, 0x00);
940 ret = lgdt3306a_write_reg(state, 0x000f, 0x00);
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300941#endif
Fred Richterb63b36f2014-03-24 19:56:00 -0300942
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300943 /* 9. Center frequency of input signal of ADC */
944 ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */
945 ret = lgdt3306a_write_reg(state, 0x0011, 0x00);
Fred Richterb63b36f2014-03-24 19:56:00 -0300946
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300947 /* 10. Fixed gain error value */
948 ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */
Fred Richterb63b36f2014-03-24 19:56:00 -0300949
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300950 /* 10a. VSB TR BW gear shift initial step */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200951 ret = lgdt3306a_read_reg(state, 0x103c, &val);
952 val &= 0x0f;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300953 val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200954 ret = lgdt3306a_write_reg(state, 0x103c, val);
Fred Richterb63b36f2014-03-24 19:56:00 -0300955
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300956 /* 10b. Timing offset calibration in low temperature for VSB */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200957 ret = lgdt3306a_read_reg(state, 0x103d, &val);
958 val &= 0xfc;
Fred Richterb63b36f2014-03-24 19:56:00 -0300959 val |= 0x03;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200960 ret = lgdt3306a_write_reg(state, 0x103d, val);
Fred Richterb63b36f2014-03-24 19:56:00 -0300961
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300962 /* 10c. Timing offset calibration in low temperature for QAM */
Fred Richterb63b36f2014-03-24 19:56:00 -0300963 ret = lgdt3306a_read_reg(state, 0x1036, &val);
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200964 val &= 0xf0;
965 val |= 0x0c;
Fred Richterb63b36f2014-03-24 19:56:00 -0300966 ret = lgdt3306a_write_reg(state, 0x1036, val);
967
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300968 /* 11. Using the imaginary part of CIR in CIR loading */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200969 ret = lgdt3306a_read_reg(state, 0x211f, &val);
970 val &= 0xef; /* do not use imaginary of CIR */
971 ret = lgdt3306a_write_reg(state, 0x211f, val);
Fred Richterb63b36f2014-03-24 19:56:00 -0300972
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300973 /* 12. Control of no signal detector function */
Fred Richterb63b36f2014-03-24 19:56:00 -0300974 ret = lgdt3306a_read_reg(state, 0x2849, &val);
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -0200975 val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */
Fred Richterb63b36f2014-03-24 19:56:00 -0300976 ret = lgdt3306a_write_reg(state, 0x2849, val);
977
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300978 /* FGR - put demod in some known mode */
Fred Richterb63b36f2014-03-24 19:56:00 -0300979 ret = lgdt3306a_set_vsb(state);
980
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300981 /* 13. TP stream format */
Fred Richterb63b36f2014-03-24 19:56:00 -0300982 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
983
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300984 /* 14. disable output buses */
Fred Richterb63b36f2014-03-24 19:56:00 -0300985 ret = lgdt3306a_mpeg_tristate(state, 1);
986
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -0300987 /* 15. Sleep (in reset) */
Fred Richterb63b36f2014-03-24 19:56:00 -0300988 ret = lgdt3306a_sleep(state);
989 lg_chkerr(ret);
990
991fail:
992 return ret;
993}
994
995static int lgdt3306a_set_parameters(struct dvb_frontend *fe)
996{
997 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
998 struct lgdt3306a_state *state = fe->demodulator_priv;
999 int ret;
1000
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001001 dbg_info("(%d, %d)\n", p->frequency, p->modulation);
Fred Richterb63b36f2014-03-24 19:56:00 -03001002
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001003 if (state->current_frequency == p->frequency &&
1004 state->current_modulation == p->modulation) {
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001005 dbg_info(" (already set, skipping ...)\n");
Fred Richterb63b36f2014-03-24 19:56:00 -03001006 return 0;
1007 }
1008 state->current_frequency = -1;
1009 state->current_modulation = -1;
1010
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001011 ret = lgdt3306a_power(state, 1); /* power up */
Fred Richterb63b36f2014-03-24 19:56:00 -03001012 if (lg_chkerr(ret))
1013 goto fail;
1014
1015 if (fe->ops.tuner_ops.set_params) {
1016 ret = fe->ops.tuner_ops.set_params(fe);
1017 if (fe->ops.i2c_gate_ctrl)
1018 fe->ops.i2c_gate_ctrl(fe, 0);
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001019#if 0
1020 if (lg_chkerr(ret))
1021 goto fail;
1022 state->current_frequency = p->frequency;
1023#endif
Fred Richterb63b36f2014-03-24 19:56:00 -03001024 }
1025
1026 ret = lgdt3306a_set_modulation(state, p);
1027 if (lg_chkerr(ret))
1028 goto fail;
1029
1030 ret = lgdt3306a_agc_setup(state, p);
1031 if (lg_chkerr(ret))
1032 goto fail;
1033
1034 ret = lgdt3306a_set_if(state, p);
1035 if (lg_chkerr(ret))
1036 goto fail;
1037
1038 ret = lgdt3306a_spectral_inversion(state, p,
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001039 state->cfg->spectral_inversion ? 1 : 0);
Fred Richterb63b36f2014-03-24 19:56:00 -03001040 if (lg_chkerr(ret))
1041 goto fail;
1042
1043 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
1044 if (lg_chkerr(ret))
1045 goto fail;
1046
1047 ret = lgdt3306a_mpeg_mode_polarity(state,
1048 state->cfg->tpclk_edge,
1049 state->cfg->tpvalid_polarity);
1050 if (lg_chkerr(ret))
1051 goto fail;
1052
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001053 ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */
Fred Richterb63b36f2014-03-24 19:56:00 -03001054 if (lg_chkerr(ret))
1055 goto fail;
1056
1057 ret = lgdt3306a_soft_reset(state);
1058 if (lg_chkerr(ret))
1059 goto fail;
1060
1061#ifdef DBG_DUMP
1062 lgdt3306a_DumpAllRegs(state);
1063#endif
1064 state->current_frequency = p->frequency;
1065fail:
1066 return ret;
1067}
1068
Mauro Carvalho Chehab7e3e68b2016-02-04 12:58:30 -02001069static int lgdt3306a_get_frontend(struct dvb_frontend *fe,
1070 struct dtv_frontend_properties *p)
Fred Richterb63b36f2014-03-24 19:56:00 -03001071{
1072 struct lgdt3306a_state *state = fe->demodulator_priv;
Fred Richterb63b36f2014-03-24 19:56:00 -03001073
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001074 dbg_info("(%u, %d)\n",
1075 state->current_frequency, state->current_modulation);
Fred Richterb63b36f2014-03-24 19:56:00 -03001076
1077 p->modulation = state->current_modulation;
1078 p->frequency = state->current_frequency;
1079 return 0;
1080}
1081
1082static enum dvbfe_algo lgdt3306a_get_frontend_algo(struct dvb_frontend *fe)
1083{
1084#if 1
1085 return DVBFE_ALGO_CUSTOM;
1086#else
1087 return DVBFE_ALGO_HW;
1088#endif
1089}
1090
1091/* ------------------------------------------------------------------------ */
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001092static int lgdt3306a_monitor_vsb(struct lgdt3306a_state *state)
Fred Richterb63b36f2014-03-24 19:56:00 -03001093{
1094 u8 val;
1095 int ret;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001096 u8 snrRef, maxPowerMan, nCombDet;
1097 u16 fbDlyCir;
Fred Richterb63b36f2014-03-24 19:56:00 -03001098
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001099 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001100 if (ret)
1101 return ret;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001102 snrRef = val & 0x3f;
Fred Richterb63b36f2014-03-24 19:56:00 -03001103
1104 ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001105 if (ret)
1106 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001107
1108 ret = lgdt3306a_read_reg(state, 0x2191, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001109 if (ret)
1110 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001111 nCombDet = (val & 0x80) >> 7;
1112
1113 ret = lgdt3306a_read_reg(state, 0x2180, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001114 if (ret)
1115 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001116 fbDlyCir = (val & 0x03) << 8;
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001117
Fred Richterb63b36f2014-03-24 19:56:00 -03001118 ret = lgdt3306a_read_reg(state, 0x2181, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001119 if (ret)
1120 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001121 fbDlyCir |= val;
1122
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001123 dbg_info("snrRef=%d maxPowerMan=0x%x nCombDet=%d fbDlyCir=0x%x\n",
Fred Richterb63b36f2014-03-24 19:56:00 -03001124 snrRef, maxPowerMan, nCombDet, fbDlyCir);
1125
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001126 /* Carrier offset sub loop bandwidth */
Fred Richterb63b36f2014-03-24 19:56:00 -03001127 ret = lgdt3306a_read_reg(state, 0x1061, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001128 if (ret)
1129 return ret;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001130 val &= 0xf8;
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001131 if ((snrRef > 18) && (maxPowerMan > 0x68)
1132 && (nCombDet == 0x01)
1133 && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) {
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001134 /* SNR is over 18dB and no ghosting */
1135 val |= 0x00; /* final bandwidth = 0 */
Fred Richterb63b36f2014-03-24 19:56:00 -03001136 } else {
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001137 val |= 0x04; /* final bandwidth = 4 */
Fred Richterb63b36f2014-03-24 19:56:00 -03001138 }
1139 ret = lgdt3306a_write_reg(state, 0x1061, val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001140 if (ret)
1141 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001142
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001143 /* Adjust Notch Filter */
Fred Richterb63b36f2014-03-24 19:56:00 -03001144 ret = lgdt3306a_read_reg(state, 0x0024, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001145 if (ret)
1146 return ret;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001147 val &= 0x0f;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001148 if (nCombDet == 0) { /* Turn on the Notch Filter */
Fred Richterb63b36f2014-03-24 19:56:00 -03001149 val |= 0x50;
1150 }
1151 ret = lgdt3306a_write_reg(state, 0x0024, val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001152 if (ret)
1153 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001154
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001155 /* VSB Timing Recovery output normalization */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001156 ret = lgdt3306a_read_reg(state, 0x103d, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001157 if (ret)
1158 return ret;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001159 val &= 0xcf;
Fred Richterb63b36f2014-03-24 19:56:00 -03001160 val |= 0x20;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001161 ret = lgdt3306a_write_reg(state, 0x103d, val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001162
1163 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001164}
1165
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001166static enum lgdt3306a_modulation
1167lgdt3306a_check_oper_mode(struct lgdt3306a_state *state)
Fred Richterb63b36f2014-03-24 19:56:00 -03001168{
1169 u8 val = 0;
1170 int ret;
1171
1172 ret = lgdt3306a_read_reg(state, 0x0081, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001173 if (ret)
1174 goto err;
Fred Richterb63b36f2014-03-24 19:56:00 -03001175
1176 if (val & 0x80) {
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001177 dbg_info("VSB\n");
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001178 return LG3306_VSB;
Fred Richterb63b36f2014-03-24 19:56:00 -03001179 }
Michael Ira Krufkyc714efe2014-08-03 14:51:49 -03001180 if (val & 0x08) {
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001181 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001182 if (ret)
1183 goto err;
Fred Richterb63b36f2014-03-24 19:56:00 -03001184 val = val >> 2;
1185 if (val & 0x01) {
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001186 dbg_info("QAM256\n");
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001187 return LG3306_QAM256;
Fred Richterb63b36f2014-03-24 19:56:00 -03001188 }
Mauro Carvalho Chehabb4e43e92014-10-28 12:05:35 -02001189 dbg_info("QAM64\n");
1190 return LG3306_QAM64;
Fred Richterb63b36f2014-03-24 19:56:00 -03001191 }
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001192err:
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001193 pr_warn("UNKNOWN\n");
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001194 return LG3306_UNKNOWN_MODE;
Fred Richterb63b36f2014-03-24 19:56:00 -03001195}
1196
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001197static enum lgdt3306a_lock_status
1198lgdt3306a_check_lock_status(struct lgdt3306a_state *state,
1199 enum lgdt3306a_lock_check whatLock)
Fred Richterb63b36f2014-03-24 19:56:00 -03001200{
1201 u8 val = 0;
1202 int ret;
Michael Ira Krufkyf883d602014-08-03 15:29:04 -03001203 enum lgdt3306a_modulation modeOper;
1204 enum lgdt3306a_lock_status lockStatus;
Fred Richterb63b36f2014-03-24 19:56:00 -03001205
1206 modeOper = LG3306_UNKNOWN_MODE;
1207
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001208 switch (whatLock) {
1209 case LG3306_SYNC_LOCK:
Fred Richterb63b36f2014-03-24 19:56:00 -03001210 {
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001211 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001212 if (ret)
1213 return ret;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001214
1215 if ((val & 0x80) == 0x80)
1216 lockStatus = LG3306_LOCK;
1217 else
1218 lockStatus = LG3306_UNLOCK;
1219
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001220 dbg_info("SYNC_LOCK=%x\n", lockStatus);
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001221 break;
1222 }
1223 case LG3306_AGC_LOCK:
1224 {
1225 ret = lgdt3306a_read_reg(state, 0x0080, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001226 if (ret)
1227 return ret;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001228
1229 if ((val & 0x40) == 0x40)
1230 lockStatus = LG3306_LOCK;
1231 else
1232 lockStatus = LG3306_UNLOCK;
1233
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001234 dbg_info("AGC_LOCK=%x\n", lockStatus);
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001235 break;
1236 }
1237 case LG3306_TR_LOCK:
1238 {
1239 modeOper = lgdt3306a_check_oper_mode(state);
1240 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1241 ret = lgdt3306a_read_reg(state, 0x1094, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001242 if (ret)
1243 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001244
1245 if ((val & 0x80) == 0x80)
1246 lockStatus = LG3306_LOCK;
1247 else
1248 lockStatus = LG3306_UNLOCK;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001249 } else
1250 lockStatus = LG3306_UNKNOWN_LOCK;
Fred Richterb63b36f2014-03-24 19:56:00 -03001251
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001252 dbg_info("TR_LOCK=%x\n", lockStatus);
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001253 break;
1254 }
1255 case LG3306_FEC_LOCK:
1256 {
1257 modeOper = lgdt3306a_check_oper_mode(state);
1258 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
Fred Richterb63b36f2014-03-24 19:56:00 -03001259 ret = lgdt3306a_read_reg(state, 0x0080, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001260 if (ret)
1261 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001262
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001263 if ((val & 0x10) == 0x10)
Fred Richterb63b36f2014-03-24 19:56:00 -03001264 lockStatus = LG3306_LOCK;
1265 else
1266 lockStatus = LG3306_UNLOCK;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001267 } else
Fred Richterb63b36f2014-03-24 19:56:00 -03001268 lockStatus = LG3306_UNKNOWN_LOCK;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001269
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001270 dbg_info("FEC_LOCK=%x\n", lockStatus);
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001271 break;
Fred Richterb63b36f2014-03-24 19:56:00 -03001272 }
1273
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001274 default:
1275 lockStatus = LG3306_UNKNOWN_LOCK;
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001276 pr_warn("UNKNOWN whatLock=%d\n", whatLock);
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001277 break;
1278 }
1279
1280 return lockStatus;
Fred Richterb63b36f2014-03-24 19:56:00 -03001281}
1282
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001283static enum lgdt3306a_neverlock_status
1284lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state)
Fred Richterb63b36f2014-03-24 19:56:00 -03001285{
1286 u8 val = 0;
1287 int ret;
Michael Ira Krufkyf883d602014-08-03 15:29:04 -03001288 enum lgdt3306a_neverlock_status lockStatus;
Fred Richterb63b36f2014-03-24 19:56:00 -03001289
1290 ret = lgdt3306a_read_reg(state, 0x0080, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001291 if (ret)
1292 return ret;
Michael Ira Krufkyf883d602014-08-03 15:29:04 -03001293 lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03);
Fred Richterb63b36f2014-03-24 19:56:00 -03001294
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001295 dbg_info("NeverLock=%d", lockStatus);
Fred Richterb63b36f2014-03-24 19:56:00 -03001296
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001297 return lockStatus;
Fred Richterb63b36f2014-03-24 19:56:00 -03001298}
1299
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001300static int lgdt3306a_pre_monitoring(struct lgdt3306a_state *state)
Fred Richterb63b36f2014-03-24 19:56:00 -03001301{
1302 u8 val = 0;
1303 int ret;
1304 u8 currChDiffACQ, snrRef, mainStrong, aiccrejStatus;
1305
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001306 /* Channel variation */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001307 ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001308 if (ret)
1309 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001310
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001311 /* SNR of Frame sync */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001312 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001313 if (ret)
1314 return ret;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001315 snrRef = val & 0x3f;
Fred Richterb63b36f2014-03-24 19:56:00 -03001316
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001317 /* Strong Main CIR */
Fred Richterb63b36f2014-03-24 19:56:00 -03001318 ret = lgdt3306a_read_reg(state, 0x2199, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001319 if (ret)
1320 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001321 mainStrong = (val & 0x40) >> 6;
1322
1323 ret = lgdt3306a_read_reg(state, 0x0090, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001324 if (ret)
1325 return ret;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001326 aiccrejStatus = (val & 0xf0) >> 4;
Fred Richterb63b36f2014-03-24 19:56:00 -03001327
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001328 dbg_info("snrRef=%d mainStrong=%d aiccrejStatus=%d currChDiffACQ=0x%x\n",
Fred Richterb63b36f2014-03-24 19:56:00 -03001329 snrRef, mainStrong, aiccrejStatus, currChDiffACQ);
1330
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001331#if 0
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001332 /* Dynamic ghost exists */
1333 if ((mainStrong == 0) && (currChDiffACQ > 0x70))
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001334#endif
1335 if (mainStrong == 0) {
Fred Richterb63b36f2014-03-24 19:56:00 -03001336 ret = lgdt3306a_read_reg(state, 0x2135, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001337 if (ret)
1338 return ret;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001339 val &= 0x0f;
1340 val |= 0xa0;
Fred Richterb63b36f2014-03-24 19:56:00 -03001341 ret = lgdt3306a_write_reg(state, 0x2135, val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001342 if (ret)
1343 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001344
1345 ret = lgdt3306a_read_reg(state, 0x2141, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001346 if (ret)
1347 return ret;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001348 val &= 0x3f;
Fred Richterb63b36f2014-03-24 19:56:00 -03001349 val |= 0x80;
1350 ret = lgdt3306a_write_reg(state, 0x2141, val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001351 if (ret)
1352 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001353
1354 ret = lgdt3306a_write_reg(state, 0x2122, 0x70);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001355 if (ret)
1356 return ret;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001357 } else { /* Weak ghost or static channel */
Fred Richterb63b36f2014-03-24 19:56:00 -03001358 ret = lgdt3306a_read_reg(state, 0x2135, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001359 if (ret)
1360 return ret;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001361 val &= 0x0f;
Fred Richterb63b36f2014-03-24 19:56:00 -03001362 val |= 0x70;
1363 ret = lgdt3306a_write_reg(state, 0x2135, val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001364 if (ret)
1365 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001366
1367 ret = lgdt3306a_read_reg(state, 0x2141, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001368 if (ret)
1369 return ret;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001370 val &= 0x3f;
Fred Richterb63b36f2014-03-24 19:56:00 -03001371 val |= 0x40;
1372 ret = lgdt3306a_write_reg(state, 0x2141, val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001373 if (ret)
1374 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001375
1376 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001377 if (ret)
1378 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001379 }
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001380 return 0;
Fred Richterb63b36f2014-03-24 19:56:00 -03001381}
1382
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001383static enum lgdt3306a_lock_status
1384lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state)
Fred Richterb63b36f2014-03-24 19:56:00 -03001385{
Michael Ira Krufkyf883d602014-08-03 15:29:04 -03001386 enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK;
Fred Richterb63b36f2014-03-24 19:56:00 -03001387 int i;
1388
1389 for (i = 0; i < 2; i++) {
1390 msleep(30);
1391
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001392 syncLockStatus = lgdt3306a_check_lock_status(state,
1393 LG3306_SYNC_LOCK);
Fred Richterb63b36f2014-03-24 19:56:00 -03001394
1395 if (syncLockStatus == LG3306_LOCK) {
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001396 dbg_info("locked(%d)\n", i);
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001397 return LG3306_LOCK;
Fred Richterb63b36f2014-03-24 19:56:00 -03001398 }
1399 }
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001400 dbg_info("not locked\n");
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001401 return LG3306_UNLOCK;
Fred Richterb63b36f2014-03-24 19:56:00 -03001402}
1403
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001404static enum lgdt3306a_lock_status
1405lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state)
Fred Richterb63b36f2014-03-24 19:56:00 -03001406{
Michael Ira Krufkyf883d602014-08-03 15:29:04 -03001407 enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK;
Fred Richterb63b36f2014-03-24 19:56:00 -03001408 int i;
1409
1410 for (i = 0; i < 2; i++) {
1411 msleep(30);
1412
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001413 FECLockStatus = lgdt3306a_check_lock_status(state,
1414 LG3306_FEC_LOCK);
Fred Richterb63b36f2014-03-24 19:56:00 -03001415
1416 if (FECLockStatus == LG3306_LOCK) {
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001417 dbg_info("locked(%d)\n", i);
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001418 return FECLockStatus;
Fred Richterb63b36f2014-03-24 19:56:00 -03001419 }
1420 }
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001421 dbg_info("not locked\n");
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001422 return FECLockStatus;
Fred Richterb63b36f2014-03-24 19:56:00 -03001423}
1424
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001425static enum lgdt3306a_neverlock_status
1426lgdt3306a_neverlock_poll(struct lgdt3306a_state *state)
Fred Richterb63b36f2014-03-24 19:56:00 -03001427{
Michael Ira Krufkyf883d602014-08-03 15:29:04 -03001428 enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL;
Fred Richterb63b36f2014-03-24 19:56:00 -03001429 int i;
1430
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001431 for (i = 0; i < 5; i++) {
Fred Richterb63b36f2014-03-24 19:56:00 -03001432 msleep(30);
1433
1434 NLLockStatus = lgdt3306a_check_neverlock_status(state);
1435
1436 if (NLLockStatus == LG3306_NL_LOCK) {
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001437 dbg_info("NL_LOCK(%d)\n", i);
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001438 return NLLockStatus;
Fred Richterb63b36f2014-03-24 19:56:00 -03001439 }
1440 }
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001441 dbg_info("NLLockStatus=%d\n", NLLockStatus);
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001442 return NLLockStatus;
Fred Richterb63b36f2014-03-24 19:56:00 -03001443}
1444
1445static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state)
1446{
1447 u8 val;
1448 int ret;
1449
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001450 ret = lgdt3306a_read_reg(state, 0x00fa, &val);
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001451 if (ret)
1452 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001453
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001454 return val;
Fred Richterb63b36f2014-03-24 19:56:00 -03001455}
1456
Mauro Carvalho Chehab9369fe02014-10-28 12:30:44 -02001457static const u32 valx_x10[] = {
1458 10, 11, 13, 15, 17, 20, 25, 33, 41, 50, 59, 73, 87, 100
1459};
1460static const u32 log10x_x1000[] = {
Mauro Carvalho Chehab95f22c52014-10-28 12:40:20 -02001461 0, 41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000
Mauro Carvalho Chehab9369fe02014-10-28 12:30:44 -02001462};
1463
Fred Richterb63b36f2014-03-24 19:56:00 -03001464static u32 log10_x1000(u32 x)
1465{
Mauro Carvalho Chehaba132fef2014-10-28 11:07:03 -02001466 u32 diff_val, step_val, step_log10;
Fred Richterb63b36f2014-03-24 19:56:00 -03001467 u32 log_val = 0;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001468 u32 i;
Fred Richterb63b36f2014-03-24 19:56:00 -03001469
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001470 if (x <= 0)
1471 return -1000000; /* signal error */
Fred Richterb63b36f2014-03-24 19:56:00 -03001472
Mauro Carvalho Chehabb4e43e92014-10-28 12:05:35 -02001473 if (x == 10)
1474 return 0; /* log(1)=0 */
1475
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001476 if (x < 10) {
1477 while (x < 10) {
1478 x = x * 10;
Fred Richterb63b36f2014-03-24 19:56:00 -03001479 log_val--;
1480 }
Mauro Carvalho Chehabb4e43e92014-10-28 12:05:35 -02001481 } else { /* x > 10 */
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001482 while (x >= 100) {
1483 x = x / 10;
Fred Richterb63b36f2014-03-24 19:56:00 -03001484 log_val++;
1485 }
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001486 }
Fred Richterb63b36f2014-03-24 19:56:00 -03001487 log_val *= 1000;
1488
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001489 if (x == 10) /* was our input an exact multiple of 10 */
1490 return log_val; /* don't need to interpolate */
Fred Richterb63b36f2014-03-24 19:56:00 -03001491
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001492 /* find our place on the log curve */
Mauro Carvalho Chehab9369fe02014-10-28 12:30:44 -02001493 for (i = 1; i < ARRAY_SIZE(valx_x10); i++) {
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001494 if (valx_x10[i] >= x)
1495 break;
Fred Richterb63b36f2014-03-24 19:56:00 -03001496 }
Mauro Carvalho Chehab9369fe02014-10-28 12:30:44 -02001497 if (i == ARRAY_SIZE(valx_x10))
Mauro Carvalho Chehaba132fef2014-10-28 11:07:03 -02001498 return log_val + log10x_x1000[i - 1];
Fred Richterb63b36f2014-03-24 19:56:00 -03001499
Mauro Carvalho Chehaba132fef2014-10-28 11:07:03 -02001500 diff_val = x - valx_x10[i-1];
1501 step_val = valx_x10[i] - valx_x10[i - 1];
1502 step_log10 = log10x_x1000[i] - log10x_x1000[i - 1];
1503
1504 /* do a linear interpolation to get in-between values */
1505 return log_val + log10x_x1000[i - 1] +
1506 ((diff_val*step_log10) / step_val);
Fred Richterb63b36f2014-03-24 19:56:00 -03001507}
1508
1509static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state)
1510{
Michael Ira Krufky34a5a2f2014-10-25 11:26:15 -03001511 u32 mse; /* Mean-Square Error */
1512 u32 pwr; /* Constelation power */
Fred Richterb63b36f2014-03-24 19:56:00 -03001513 u32 snr_x100;
1514
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001515 mse = (read_reg(state, 0x00ec) << 8) |
1516 (read_reg(state, 0x00ed));
1517 pwr = (read_reg(state, 0x00e8) << 8) |
1518 (read_reg(state, 0x00e9));
Fred Richterb63b36f2014-03-24 19:56:00 -03001519
1520 if (mse == 0) /* no signal */
1521 return 0;
1522
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001523 snr_x100 = log10_x1000((pwr * 10000) / mse) - 3000;
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001524 dbg_info("mse=%u, pwr=%u, snr_x100=%d\n", mse, pwr, snr_x100);
Fred Richterb63b36f2014-03-24 19:56:00 -03001525
1526 return snr_x100;
1527}
1528
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001529static enum lgdt3306a_lock_status
1530lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state)
Fred Richterb63b36f2014-03-24 19:56:00 -03001531{
Mauro Carvalho Chehabe2c47fa2014-10-28 11:27:34 -02001532 int ret;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001533 u8 cnt = 0;
1534 u8 packet_error;
1535 u32 snr;
Fred Richterb63b36f2014-03-24 19:56:00 -03001536
Mauro Carvalho Chehabb1a88c72014-10-28 12:00:48 -02001537 for (cnt = 0; cnt < 10; cnt++) {
Fred Richterb63b36f2014-03-24 19:56:00 -03001538 if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) {
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001539 dbg_info("no sync lock!\n");
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001540 return LG3306_UNLOCK;
Fred Richterb63b36f2014-03-24 19:56:00 -03001541 }
Mauro Carvalho Chehabb1a88c72014-10-28 12:00:48 -02001542
1543 msleep(20);
1544 ret = lgdt3306a_pre_monitoring(state);
1545 if (ret)
1546 break;
1547
1548 packet_error = lgdt3306a_get_packet_error(state);
1549 snr = lgdt3306a_calculate_snr_x100(state);
1550 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
1551
1552 if ((snr >= 1500) && (packet_error < 0xff))
1553 return LG3306_LOCK;
Fred Richterb63b36f2014-03-24 19:56:00 -03001554 }
Mauro Carvalho Chehabb1a88c72014-10-28 12:00:48 -02001555
1556 dbg_info("not locked!\n");
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001557 return LG3306_UNLOCK;
Fred Richterb63b36f2014-03-24 19:56:00 -03001558}
1559
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001560static enum lgdt3306a_lock_status
1561lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state)
Fred Richterb63b36f2014-03-24 19:56:00 -03001562{
Mauro Carvalho Chehabb1a88c72014-10-28 12:00:48 -02001563 u8 cnt;
Fred Richterb63b36f2014-03-24 19:56:00 -03001564 u8 packet_error;
1565 u32 snr;
1566
Mauro Carvalho Chehabb1a88c72014-10-28 12:00:48 -02001567 for (cnt = 0; cnt < 10; cnt++) {
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001568 if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) {
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001569 dbg_info("no fec lock!\n");
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001570 return LG3306_UNLOCK;
Fred Richterb63b36f2014-03-24 19:56:00 -03001571 }
Mauro Carvalho Chehabb1a88c72014-10-28 12:00:48 -02001572
1573 msleep(20);
1574
1575 packet_error = lgdt3306a_get_packet_error(state);
1576 snr = lgdt3306a_calculate_snr_x100(state);
1577 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
1578
1579 if ((snr >= 1500) && (packet_error < 0xff))
1580 return LG3306_LOCK;
Fred Richterb63b36f2014-03-24 19:56:00 -03001581 }
Mauro Carvalho Chehabb1a88c72014-10-28 12:00:48 -02001582
1583 dbg_info("not locked!\n");
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001584 return LG3306_UNLOCK;
Fred Richterb63b36f2014-03-24 19:56:00 -03001585}
1586
Mauro Carvalho Chehab0df289a2015-06-07 14:53:52 -03001587static int lgdt3306a_read_status(struct dvb_frontend *fe,
1588 enum fe_status *status)
Fred Richterb63b36f2014-03-24 19:56:00 -03001589{
Fred Richterb63b36f2014-03-24 19:56:00 -03001590 struct lgdt3306a_state *state = fe->demodulator_priv;
Fred Richterb63b36f2014-03-24 19:56:00 -03001591 u16 strength = 0;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001592 int ret = 0;
1593
Fred Richterb63b36f2014-03-24 19:56:00 -03001594 if (fe->ops.tuner_ops.get_rf_strength) {
1595 ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength);
Mauro Carvalho Chehabc9897642014-10-28 12:07:52 -02001596 if (ret == 0)
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001597 dbg_info("strength=%d\n", strength);
Mauro Carvalho Chehabc9897642014-10-28 12:07:52 -02001598 else
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001599 dbg_info("fe->ops.tuner_ops.get_rf_strength() failed\n");
Fred Richterb63b36f2014-03-24 19:56:00 -03001600 }
1601
1602 *status = 0;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001603 if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) {
Fred Richterb63b36f2014-03-24 19:56:00 -03001604 *status |= FE_HAS_SIGNAL;
1605 *status |= FE_HAS_CARRIER;
1606
1607 switch (state->current_modulation) {
1608 case QAM_256:
1609 case QAM_64:
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001610 if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) {
Fred Richterb63b36f2014-03-24 19:56:00 -03001611 *status |= FE_HAS_VITERBI;
1612 *status |= FE_HAS_SYNC;
1613
1614 *status |= FE_HAS_LOCK;
1615 }
1616 break;
1617 case VSB_8:
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001618 if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) {
Fred Richterb63b36f2014-03-24 19:56:00 -03001619 *status |= FE_HAS_VITERBI;
1620 *status |= FE_HAS_SYNC;
1621
1622 *status |= FE_HAS_LOCK;
1623
Mauro Carvalho Chehabee0133e2014-10-28 11:21:48 -02001624 ret = lgdt3306a_monitor_vsb(state);
Fred Richterb63b36f2014-03-24 19:56:00 -03001625 }
1626 break;
1627 default:
1628 ret = -EINVAL;
1629 }
1630 }
1631 return ret;
1632}
1633
1634
1635static int lgdt3306a_read_snr(struct dvb_frontend *fe, u16 *snr)
1636{
1637 struct lgdt3306a_state *state = fe->demodulator_priv;
1638
1639 state->snr = lgdt3306a_calculate_snr_x100(state);
1640 /* report SNR in dB * 10 */
1641 *snr = state->snr/10;
1642
1643 return 0;
1644}
1645
1646static int lgdt3306a_read_signal_strength(struct dvb_frontend *fe,
1647 u16 *strength)
1648{
1649 /*
1650 * Calculate some sort of "strength" from SNR
1651 */
1652 struct lgdt3306a_state *state = fe->demodulator_priv;
Michael Ira Krufky34a5a2f2014-10-25 11:26:15 -03001653 u16 snr; /* snr_x10 */
Fred Richterb63b36f2014-03-24 19:56:00 -03001654 int ret;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001655 u32 ref_snr; /* snr*100 */
Fred Richterb63b36f2014-03-24 19:56:00 -03001656 u32 str;
1657
1658 *strength = 0;
1659
1660 switch (state->current_modulation) {
1661 case VSB_8:
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001662 ref_snr = 1600; /* 16dB */
Fred Richterb63b36f2014-03-24 19:56:00 -03001663 break;
1664 case QAM_64:
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001665 ref_snr = 2200; /* 22dB */
Fred Richterb63b36f2014-03-24 19:56:00 -03001666 break;
1667 case QAM_256:
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001668 ref_snr = 2800; /* 28dB */
Fred Richterb63b36f2014-03-24 19:56:00 -03001669 break;
1670 default:
1671 return -EINVAL;
1672 }
1673
1674 ret = fe->ops.read_snr(fe, &snr);
1675 if (lg_chkerr(ret))
1676 goto fail;
1677
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001678 if (state->snr <= (ref_snr - 100))
Fred Richterb63b36f2014-03-24 19:56:00 -03001679 str = 0;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001680 else if (state->snr <= ref_snr)
1681 str = (0xffff * 65) / 100; /* 65% */
Fred Richterb63b36f2014-03-24 19:56:00 -03001682 else {
1683 str = state->snr - ref_snr;
1684 str /= 50;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001685 str += 78; /* 78%-100% */
1686 if (str > 100)
Fred Richterb63b36f2014-03-24 19:56:00 -03001687 str = 100;
1688 str = (0xffff * str) / 100;
1689 }
1690 *strength = (u16)str;
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001691 dbg_info("strength=%u\n", *strength);
Fred Richterb63b36f2014-03-24 19:56:00 -03001692
1693fail:
1694 return ret;
1695}
1696
1697/* ------------------------------------------------------------------------ */
1698
1699static int lgdt3306a_read_ber(struct dvb_frontend *fe, u32 *ber)
1700{
1701 struct lgdt3306a_state *state = fe->demodulator_priv;
1702 u32 tmp;
1703
1704 *ber = 0;
1705#if 1
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001706 /* FGR - FIXME - I don't know what value is expected by dvb_core
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001707 * what is the scale of the value?? */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001708 tmp = read_reg(state, 0x00fc); /* NBERVALUE[24-31] */
1709 tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */
1710 tmp = (tmp << 8) | read_reg(state, 0x00fe); /* NBERVALUE[8-15] */
1711 tmp = (tmp << 8) | read_reg(state, 0x00ff); /* NBERVALUE[0-7] */
Fred Richterb63b36f2014-03-24 19:56:00 -03001712 *ber = tmp;
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001713 dbg_info("ber=%u\n", tmp);
Fred Richterb63b36f2014-03-24 19:56:00 -03001714#endif
1715 return 0;
1716}
1717
1718static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1719{
1720 struct lgdt3306a_state *state = fe->demodulator_priv;
1721
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001722 *ucblocks = 0;
Fred Richterb63b36f2014-03-24 19:56:00 -03001723#if 1
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001724 /* FGR - FIXME - I don't know what value is expected by dvb_core
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001725 * what happens when value wraps? */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001726 *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001727 dbg_info("ucblocks=%u\n", *ucblocks);
Fred Richterb63b36f2014-03-24 19:56:00 -03001728#endif
1729
1730 return 0;
1731}
1732
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001733static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune,
1734 unsigned int mode_flags, unsigned int *delay,
Mauro Carvalho Chehab0df289a2015-06-07 14:53:52 -03001735 enum fe_status *status)
Fred Richterb63b36f2014-03-24 19:56:00 -03001736{
1737 int ret = 0;
1738 struct lgdt3306a_state *state = fe->demodulator_priv;
1739
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001740 dbg_info("re_tune=%u\n", re_tune);
Fred Richterb63b36f2014-03-24 19:56:00 -03001741
1742 if (re_tune) {
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001743 state->current_frequency = -1; /* force re-tune */
Michael Ira Krufkyae21e442014-08-03 15:18:23 -03001744 ret = lgdt3306a_set_parameters(fe);
1745 if (ret != 0)
Fred Richterb63b36f2014-03-24 19:56:00 -03001746 return ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001747 }
1748 *delay = 125;
1749 ret = lgdt3306a_read_status(fe, status);
1750
1751 return ret;
1752}
1753
1754static int lgdt3306a_get_tune_settings(struct dvb_frontend *fe,
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001755 struct dvb_frontend_tune_settings
1756 *fe_tune_settings)
Fred Richterb63b36f2014-03-24 19:56:00 -03001757{
1758 fe_tune_settings->min_delay_ms = 100;
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001759 dbg_info("\n");
Fred Richterb63b36f2014-03-24 19:56:00 -03001760 return 0;
1761}
1762
1763static int lgdt3306a_search(struct dvb_frontend *fe)
1764{
Mauro Carvalho Chehab0df289a2015-06-07 14:53:52 -03001765 enum fe_status status = 0;
Abylay Ospandd145232016-07-25 15:38:59 -03001766 int ret;
Fred Richterb63b36f2014-03-24 19:56:00 -03001767
1768 /* set frontend */
1769 ret = lgdt3306a_set_parameters(fe);
1770 if (ret)
1771 goto error;
1772
Abylay Ospandd145232016-07-25 15:38:59 -03001773 ret = lgdt3306a_read_status(fe, &status);
1774 if (ret)
1775 goto error;
Fred Richterb63b36f2014-03-24 19:56:00 -03001776
1777 /* check if we have a valid signal */
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001778 if (status & FE_HAS_LOCK)
Fred Richterb63b36f2014-03-24 19:56:00 -03001779 return DVBFE_ALGO_SEARCH_SUCCESS;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001780 else
Fred Richterb63b36f2014-03-24 19:56:00 -03001781 return DVBFE_ALGO_SEARCH_AGAIN;
Fred Richterb63b36f2014-03-24 19:56:00 -03001782
1783error:
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001784 dbg_info("failed (%d)\n", ret);
Fred Richterb63b36f2014-03-24 19:56:00 -03001785 return DVBFE_ALGO_SEARCH_ERROR;
1786}
1787
1788static void lgdt3306a_release(struct dvb_frontend *fe)
1789{
1790 struct lgdt3306a_state *state = fe->demodulator_priv;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001791
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001792 dbg_info("\n");
Fred Richterb63b36f2014-03-24 19:56:00 -03001793 kfree(state);
1794}
1795
Max Kellermannbd336e62016-08-09 18:32:21 -03001796static const struct dvb_frontend_ops lgdt3306a_ops;
Fred Richterb63b36f2014-03-24 19:56:00 -03001797
1798struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config,
Mauro Carvalho Chehabc43e6512014-10-28 10:56:10 -02001799 struct i2c_adapter *i2c_adap)
Fred Richterb63b36f2014-03-24 19:56:00 -03001800{
1801 struct lgdt3306a_state *state = NULL;
1802 int ret;
1803 u8 val;
1804
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001805 dbg_info("(%d-%04x)\n",
Fred Richterb63b36f2014-03-24 19:56:00 -03001806 i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1807 config ? config->i2c_addr : 0);
1808
1809 state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL);
1810 if (state == NULL)
1811 goto fail;
1812
1813 state->cfg = config;
1814 state->i2c_adap = i2c_adap;
1815
1816 memcpy(&state->frontend.ops, &lgdt3306a_ops,
1817 sizeof(struct dvb_frontend_ops));
1818 state->frontend.demodulator_priv = state;
1819
1820 /* verify that we're talking to a lg3306a */
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001821 /* FGR - NOTE - there is no obvious ChipId to check; we check
1822 * some "known" bits after reset, but it's still just a guess */
Fred Richterb63b36f2014-03-24 19:56:00 -03001823 ret = lgdt3306a_read_reg(state, 0x0000, &val);
1824 if (lg_chkerr(ret))
1825 goto fail;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001826 if ((val & 0x74) != 0x74) {
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001827 pr_warn("expected 0x74, got 0x%x\n", (val & 0x74));
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001828#if 0
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001829 /* FIXME - re-enable when we know this is right */
1830 goto fail;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001831#endif
Fred Richterb63b36f2014-03-24 19:56:00 -03001832 }
1833 ret = lgdt3306a_read_reg(state, 0x0001, &val);
1834 if (lg_chkerr(ret))
1835 goto fail;
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001836 if ((val & 0xf6) != 0xc6) {
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001837 pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6));
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001838#if 0
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001839 /* FIXME - re-enable when we know this is right */
1840 goto fail;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001841#endif
Fred Richterb63b36f2014-03-24 19:56:00 -03001842 }
1843 ret = lgdt3306a_read_reg(state, 0x0002, &val);
1844 if (lg_chkerr(ret))
1845 goto fail;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001846 if ((val & 0x73) != 0x03) {
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001847 pr_warn("expected 0x03, got 0x%x\n", (val & 0x73));
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001848#if 0
Mauro Carvalho Chehab534f4362014-10-28 12:35:18 -02001849 /* FIXME - re-enable when we know this is right */
1850 goto fail;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03001851#endif
Fred Richterb63b36f2014-03-24 19:56:00 -03001852 }
1853
1854 state->current_frequency = -1;
1855 state->current_modulation = -1;
1856
1857 lgdt3306a_sleep(state);
1858
1859 return &state->frontend;
1860
1861fail:
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02001862 pr_warn("unable to detect LGDT3306A hardware\n");
Fred Richterb63b36f2014-03-24 19:56:00 -03001863 kfree(state);
1864 return NULL;
1865}
Michael Ira Krufkyebd91752014-08-03 15:05:59 -03001866EXPORT_SYMBOL(lgdt3306a_attach);
Fred Richterb63b36f2014-03-24 19:56:00 -03001867
1868#ifdef DBG_DUMP
1869
1870static const short regtab[] = {
Michael Ira Krufkycb4671c2014-10-25 11:12:25 -03001871 0x0000, /* SOFTRSTB 1'b1 1'b1 1'b1 ADCPDB 1'b1 PLLPDB GBBPDB 11111111 */
1872 0x0001, /* 1'b1 1'b1 1'b0 1'b0 AUTORPTRS */
1873 0x0002, /* NI2CRPTEN 1'b0 1'b0 1'b0 SPECINVAUT */
1874 0x0003, /* AGCRFOUT */
1875 0x0004, /* ADCSEL1V ADCCNT ADCCNF ADCCNS ADCCLKPLL */
1876 0x0005, /* PLLINDIVSE */
1877 0x0006, /* PLLCTRL[7:0] 11100001 */
1878 0x0007, /* SYSINITWAITTIME[7:0] (msec) 00001000 */
1879 0x0008, /* STDOPMODE[7:0] 10000000 */
1880 0x0009, /* 1'b0 1'b0 1'b0 STDOPDETTMODE[2:0] STDOPDETCMODE[1:0] 00011110 */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001881 0x000a, /* DAFTEN 1'b1 x x SCSYSLOCK */
1882 0x000b, /* SCSYSLOCKCHKTIME[7:0] (10msec) 01100100 */
1883 0x000d, /* x SAMPLING4 */
1884 0x000e, /* SAMFREQ[15:8] 00000000 */
1885 0x000f, /* SAMFREQ[7:0] 00000000 */
Michael Ira Krufkycb4671c2014-10-25 11:12:25 -03001886 0x0010, /* IFFREQ[15:8] 01100000 */
1887 0x0011, /* IFFREQ[7:0] 00000000 */
1888 0x0012, /* AGCEN AGCREFMO */
1889 0x0013, /* AGCRFFIXB AGCIFFIXB AGCLOCKDETRNGSEL[1:0] 1'b1 1'b0 1'b0 1'b0 11101000 */
1890 0x0014, /* AGCFIXVALUE[7:0] 01111111 */
1891 0x0015, /* AGCREF[15:8] 00001010 */
1892 0x0016, /* AGCREF[7:0] 11100100 */
1893 0x0017, /* AGCDELAY[7:0] 00100000 */
1894 0x0018, /* AGCRFBW[3:0] AGCIFBW[3:0] 10001000 */
1895 0x0019, /* AGCUDOUTMODE[1:0] AGCUDCTRLLEN[1:0] AGCUDCTRL */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001896 0x001c, /* 1'b1 PFEN MFEN AICCVSYNC */
1897 0x001d, /* 1'b0 1'b1 1'b0 1'b1 AICCVSYNC */
1898 0x001e, /* AICCALPHA[3:0] 1'b1 1'b0 1'b1 1'b0 01111010 */
1899 0x001f, /* AICCDETTH[19:16] AICCOFFTH[19:16] 00000000 */
Michael Ira Krufkycb4671c2014-10-25 11:12:25 -03001900 0x0020, /* AICCDETTH[15:8] 01111100 */
1901 0x0021, /* AICCDETTH[7:0] 00000000 */
1902 0x0022, /* AICCOFFTH[15:8] 00000101 */
1903 0x0023, /* AICCOFFTH[7:0] 11100000 */
1904 0x0024, /* AICCOPMODE3[1:0] AICCOPMODE2[1:0] AICCOPMODE1[1:0] AICCOPMODE0[1:0] 00000000 */
1905 0x0025, /* AICCFIXFREQ3[23:16] 00000000 */
1906 0x0026, /* AICCFIXFREQ3[15:8] 00000000 */
1907 0x0027, /* AICCFIXFREQ3[7:0] 00000000 */
1908 0x0028, /* AICCFIXFREQ2[23:16] 00000000 */
1909 0x0029, /* AICCFIXFREQ2[15:8] 00000000 */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001910 0x002a, /* AICCFIXFREQ2[7:0] 00000000 */
1911 0x002b, /* AICCFIXFREQ1[23:16] 00000000 */
1912 0x002c, /* AICCFIXFREQ1[15:8] 00000000 */
1913 0x002d, /* AICCFIXFREQ1[7:0] 00000000 */
1914 0x002e, /* AICCFIXFREQ0[23:16] 00000000 */
1915 0x002f, /* AICCFIXFREQ0[15:8] 00000000 */
Michael Ira Krufkycb4671c2014-10-25 11:12:25 -03001916 0x0030, /* AICCFIXFREQ0[7:0] 00000000 */
1917 0x0031, /* 1'b0 1'b1 1'b0 1'b0 x DAGC1STER */
1918 0x0032, /* DAGC1STEN DAGC1STER */
1919 0x0033, /* DAGC1STREF[15:8] 00001010 */
1920 0x0034, /* DAGC1STREF[7:0] 11100100 */
1921 0x0035, /* DAGC2NDE */
1922 0x0036, /* DAGC2NDREF[15:8] 00001010 */
1923 0x0037, /* DAGC2NDREF[7:0] 10000000 */
1924 0x0038, /* DAGC2NDLOCKDETRNGSEL[1:0] */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001925 0x003d, /* 1'b1 SAMGEARS */
Michael Ira Krufkycb4671c2014-10-25 11:12:25 -03001926 0x0040, /* SAMLFGMA */
1927 0x0041, /* SAMLFBWM */
1928 0x0044, /* 1'b1 CRGEARSHE */
1929 0x0045, /* CRLFGMAN */
1930 0x0046, /* CFLFBWMA */
1931 0x0047, /* CRLFGMAN */
1932 0x0048, /* x x x x CRLFGSTEP_VS[3:0] xxxx1001 */
1933 0x0049, /* CRLFBWMA */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001934 0x004a, /* CRLFBWMA */
Michael Ira Krufkycb4671c2014-10-25 11:12:25 -03001935 0x0050, /* 1'b0 1'b1 1'b1 1'b0 MSECALCDA */
1936 0x0070, /* TPOUTEN TPIFEN TPCLKOUTE */
1937 0x0071, /* TPSENB TPSSOPBITE */
1938 0x0073, /* TP47HINS x x CHBERINT PERMODE[1:0] PERINT[1:0] 1xx11100 */
1939 0x0075, /* x x x x x IQSWAPCTRL[2:0] xxxxx000 */
1940 0x0076, /* NBERCON NBERST NBERPOL NBERWSYN */
1941 0x0077, /* x NBERLOSTTH[2:0] NBERACQTH[3:0] x0000000 */
1942 0x0078, /* NBERPOLY[31:24] 00000000 */
1943 0x0079, /* NBERPOLY[23:16] 00000000 */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001944 0x007a, /* NBERPOLY[15:8] 00000000 */
1945 0x007b, /* NBERPOLY[7:0] 00000000 */
1946 0x007c, /* NBERPED[31:24] 00000000 */
1947 0x007d, /* NBERPED[23:16] 00000000 */
1948 0x007e, /* NBERPED[15:8] 00000000 */
1949 0x007f, /* NBERPED[7:0] 00000000 */
Michael Ira Krufkycb4671c2014-10-25 11:12:25 -03001950 0x0080, /* x AGCLOCK DAGCLOCK SYSLOCK x x NEVERLOCK[1:0] */
1951 0x0085, /* SPECINVST */
1952 0x0088, /* SYSLOCKTIME[15:8] */
1953 0x0089, /* SYSLOCKTIME[7:0] */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001954 0x008c, /* FECLOCKTIME[15:8] */
1955 0x008d, /* FECLOCKTIME[7:0] */
1956 0x008e, /* AGCACCOUT[15:8] */
1957 0x008f, /* AGCACCOUT[7:0] */
Michael Ira Krufkycb4671c2014-10-25 11:12:25 -03001958 0x0090, /* AICCREJSTATUS[3:0] AICCREJBUSY[3:0] */
1959 0x0091, /* AICCVSYNC */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001960 0x009c, /* CARRFREQOFFSET[15:8] */
1961 0x009d, /* CARRFREQOFFSET[7:0] */
1962 0x00a1, /* SAMFREQOFFSET[23:16] */
1963 0x00a2, /* SAMFREQOFFSET[15:8] */
1964 0x00a3, /* SAMFREQOFFSET[7:0] */
1965 0x00a6, /* SYNCLOCK SYNCLOCKH */
Michael Ira Krufky6da7ac92014-10-25 11:05:05 -03001966#if 0 /* covered elsewhere */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001967 0x00e8, /* CONSTPWR[15:8] */
1968 0x00e9, /* CONSTPWR[7:0] */
1969 0x00ea, /* BMSE[15:8] */
1970 0x00eb, /* BMSE[7:0] */
1971 0x00ec, /* MSE[15:8] */
1972 0x00ed, /* MSE[7:0] */
1973 0x00ee, /* CONSTI[7:0] */
1974 0x00ef, /* CONSTQ[7:0] */
Fred Richterb63b36f2014-03-24 19:56:00 -03001975#endif
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001976 0x00f4, /* TPIFTPERRCNT[7:0] */
1977 0x00f5, /* TPCORREC */
1978 0x00f6, /* VBBER[15:8] */
1979 0x00f7, /* VBBER[7:0] */
1980 0x00f8, /* VABER[15:8] */
1981 0x00f9, /* VABER[7:0] */
1982 0x00fa, /* TPERRCNT[7:0] */
1983 0x00fb, /* NBERLOCK x x x x x x x */
1984 0x00fc, /* NBERVALUE[31:24] */
1985 0x00fd, /* NBERVALUE[23:16] */
1986 0x00fe, /* NBERVALUE[15:8] */
1987 0x00ff, /* NBERVALUE[7:0] */
Michael Ira Krufkycb4671c2014-10-25 11:12:25 -03001988 0x1000, /* 1'b0 WODAGCOU */
1989 0x1005, /* x x 1'b1 1'b1 x SRD_Q_QM */
1990 0x1009, /* SRDWAITTIME[7:0] (10msec) 00100011 */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001991 0x100a, /* SRDWAITTIME_CQS[7:0] (msec) 01100100 */
1992 0x101a, /* x 1'b1 1'b0 1'b0 x QMDQAMMODE[2:0] x100x010 */
Michael Ira Krufkycb4671c2014-10-25 11:12:25 -03001993 0x1036, /* 1'b0 1'b1 1'b0 1'b0 SAMGSEND_CQS[3:0] 01001110 */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02001994 0x103c, /* SAMGSAUTOSTL_V[3:0] SAMGSAUTOEDL_V[3:0] 01000110 */
1995 0x103d, /* 1'b1 1'b1 SAMCNORMBP_V[1:0] 1'b0 1'b0 SAMMODESEL_V[1:0] 11100001 */
1996 0x103f, /* SAMZTEDSE */
1997 0x105d, /* EQSTATUSE */
1998 0x105f, /* x PMAPG2_V[2:0] x DMAPG2_V[2:0] x001x011 */
Michael Ira Krufkycb4671c2014-10-25 11:12:25 -03001999 0x1060, /* 1'b1 EQSTATUSE */
2000 0x1061, /* CRMAPBWSTL_V[3:0] CRMAPBWEDL_V[3:0] 00000100 */
2001 0x1065, /* 1'b0 x CRMODE_V[1:0] 1'b1 x 1'b1 x 0x111x1x */
2002 0x1066, /* 1'b0 1'b0 1'b1 1'b0 1'b1 PNBOOSTSE */
2003 0x1068, /* CREPHNGAIN2_V[3:0] CREPHNPBW_V[3:0] 10010001 */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02002004 0x106e, /* x x x x x CREPHNEN_ */
2005 0x106f, /* CREPHNTH_V[7:0] 00010101 */
Michael Ira Krufkycb4671c2014-10-25 11:12:25 -03002006 0x1072, /* CRSWEEPN */
2007 0x1073, /* CRPGAIN_V[3:0] x x 1'b1 1'b1 1001xx11 */
2008 0x1074, /* CRPBW_V[3:0] x x 1'b1 1'b1 0001xx11 */
2009 0x1080, /* DAFTSTATUS[1:0] x x x x x x */
2010 0x1081, /* SRDSTATUS[1:0] x x x x x SRDLOCK */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02002011 0x10a9, /* EQSTATUS_CQS[1:0] x x x x x x */
2012 0x10b7, /* EQSTATUS_V[1:0] x x x x x x */
Michael Ira Krufky6da7ac92014-10-25 11:05:05 -03002013#if 0 /* SMART_ANT */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02002014 0x1f00, /* MODEDETE */
2015 0x1f01, /* x x x x x x x SFNRST xxxxxxx0 */
2016 0x1f03, /* NUMOFANT[7:0] 10000000 */
2017 0x1f04, /* x SELMASK[6:0] x0000000 */
2018 0x1f05, /* x SETMASK[6:0] x0000000 */
2019 0x1f06, /* x TXDATA[6:0] x0000000 */
2020 0x1f07, /* x CHNUMBER[6:0] x0000000 */
2021 0x1f09, /* AGCTIME[23:16] 10011000 */
2022 0x1f0a, /* AGCTIME[15:8] 10010110 */
2023 0x1f0b, /* AGCTIME[7:0] 10000000 */
2024 0x1f0c, /* ANTTIME[31:24] 00000000 */
2025 0x1f0d, /* ANTTIME[23:16] 00000011 */
2026 0x1f0e, /* ANTTIME[15:8] 10010000 */
2027 0x1f0f, /* ANTTIME[7:0] 10010000 */
2028 0x1f11, /* SYNCTIME[23:16] 10011000 */
2029 0x1f12, /* SYNCTIME[15:8] 10010110 */
2030 0x1f13, /* SYNCTIME[7:0] 10000000 */
2031 0x1f14, /* SNRTIME[31:24] 00000001 */
2032 0x1f15, /* SNRTIME[23:16] 01111101 */
2033 0x1f16, /* SNRTIME[15:8] 01111000 */
2034 0x1f17, /* SNRTIME[7:0] 01000000 */
2035 0x1f19, /* FECTIME[23:16] 00000000 */
2036 0x1f1a, /* FECTIME[15:8] 01110010 */
2037 0x1f1b, /* FECTIME[7:0] 01110000 */
2038 0x1f1d, /* FECTHD[7:0] 00000011 */
2039 0x1f1f, /* SNRTHD[23:16] 00001000 */
2040 0x1f20, /* SNRTHD[15:8] 01111111 */
2041 0x1f21, /* SNRTHD[7:0] 10000101 */
2042 0x1f80, /* IRQFLG x x SFSDRFLG MODEBFLG SAVEFLG SCANFLG TRACKFLG */
2043 0x1f81, /* x SYNCCON SNRCON FECCON x STDBUSY SYNCRST AGCFZCO */
2044 0x1f82, /* x x x SCANOPCD[4:0] */
2045 0x1f83, /* x x x x MAINOPCD[3:0] */
2046 0x1f84, /* x x RXDATA[13:8] */
2047 0x1f85, /* RXDATA[7:0] */
2048 0x1f86, /* x x SDTDATA[13:8] */
2049 0x1f87, /* SDTDATA[7:0] */
2050 0x1f89, /* ANTSNR[23:16] */
2051 0x1f8a, /* ANTSNR[15:8] */
2052 0x1f8b, /* ANTSNR[7:0] */
2053 0x1f8c, /* x x x x ANTFEC[13:8] */
2054 0x1f8d, /* ANTFEC[7:0] */
2055 0x1f8e, /* MAXCNT[7:0] */
2056 0x1f8f, /* SCANCNT[7:0] */
2057 0x1f91, /* MAXPW[23:16] */
2058 0x1f92, /* MAXPW[15:8] */
2059 0x1f93, /* MAXPW[7:0] */
2060 0x1f95, /* CURPWMSE[23:16] */
2061 0x1f96, /* CURPWMSE[15:8] */
2062 0x1f97, /* CURPWMSE[7:0] */
Michael Ira Krufky6da7ac92014-10-25 11:05:05 -03002063#endif /* SMART_ANT */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02002064 0x211f, /* 1'b1 1'b1 1'b1 CIRQEN x x 1'b0 1'b0 1111xx00 */
2065 0x212a, /* EQAUTOST */
Michael Ira Krufkycb4671c2014-10-25 11:12:25 -03002066 0x2122, /* CHFAST[7:0] 01100000 */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02002067 0x212b, /* FFFSTEP_V[3:0] x FBFSTEP_V[2:0] 0001x001 */
2068 0x212c, /* PHDEROTBWSEL[3:0] 1'b1 1'b1 1'b1 1'b0 10001110 */
2069 0x212d, /* 1'b1 1'b1 1'b1 1'b1 x x TPIFLOCKS */
Michael Ira Krufkycb4671c2014-10-25 11:12:25 -03002070 0x2135, /* DYNTRACKFDEQ[3:0] x 1'b0 1'b0 1'b0 1010x000 */
2071 0x2141, /* TRMODE[1:0] 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 01110111 */
2072 0x2162, /* AICCCTRLE */
2073 0x2173, /* PHNCNFCNT[7:0] 00000100 */
2074 0x2179, /* 1'b0 1'b0 1'b0 1'b1 x BADSINGLEDYNTRACKFBF[2:0] 0001x001 */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02002075 0x217a, /* 1'b0 1'b0 1'b0 1'b1 x BADSLOWSINGLEDYNTRACKFBF[2:0] 0001x001 */
2076 0x217e, /* CNFCNTTPIF[7:0] 00001000 */
2077 0x217f, /* TPERRCNTTPIF[7:0] 00000001 */
Michael Ira Krufkycb4671c2014-10-25 11:12:25 -03002078 0x2180, /* x x x x x x FBDLYCIR[9:8] */
2079 0x2181, /* FBDLYCIR[7:0] */
2080 0x2185, /* MAXPWRMAIN[7:0] */
2081 0x2191, /* NCOMBDET x x x x x x x */
2082 0x2199, /* x MAINSTRON */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02002083 0x219a, /* FFFEQSTEPOUT_V[3:0] FBFSTEPOUT_V[2:0] */
2084 0x21a1, /* x x SNRREF[5:0] */
Michael Ira Krufkycb4671c2014-10-25 11:12:25 -03002085 0x2845, /* 1'b0 1'b1 x x FFFSTEP_CQS[1:0] FFFCENTERTAP[1:0] 01xx1110 */
2086 0x2846, /* 1'b0 x 1'b0 1'b1 FBFSTEP_CQS[1:0] 1'b1 1'b0 0x011110 */
2087 0x2847, /* ENNOSIGDE */
2088 0x2849, /* 1'b1 1'b1 NOUSENOSI */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02002089 0x284a, /* EQINITWAITTIME[7:0] 01100100 */
Michael Ira Krufkycb4671c2014-10-25 11:12:25 -03002090 0x3000, /* 1'b1 1'b1 1'b1 x x x 1'b0 RPTRSTM */
2091 0x3001, /* RPTRSTWAITTIME[7:0] (100msec) 00110010 */
2092 0x3031, /* FRAMELOC */
2093 0x3032, /* 1'b1 1'b0 1'b0 1'b0 x x FRAMELOCKMODE_CQS[1:0] 1000xx11 */
Mauro Carvalho Chehab4937ba92014-10-28 10:50:36 -02002094 0x30a9, /* VDLOCK_Q FRAMELOCK */
2095 0x30aa, /* MPEGLOCK */
Fred Richterb63b36f2014-03-24 19:56:00 -03002096};
2097
Thomas Meyer1f679ff2017-09-03 08:19:31 -04002098#define numDumpRegs (ARRAY_SIZE(regtab))
Fred Richterb63b36f2014-03-24 19:56:00 -03002099static u8 regval1[numDumpRegs] = {0, };
2100static u8 regval2[numDumpRegs] = {0, };
2101
2102static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state)
2103{
2104 memset(regval2, 0xff, sizeof(regval2));
2105 lgdt3306a_DumpRegs(state);
2106}
2107
2108static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state)
2109{
2110 int i;
2111 int sav_debug = debug;
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03002112
Fred Richterb63b36f2014-03-24 19:56:00 -03002113 if ((debug & DBG_DUMP) == 0)
2114 return;
Michael Ira Krufky831a9112014-10-25 11:20:57 -03002115 debug &= ~DBG_REG; /* suppress DBG_REG during reg dump */
Fred Richterb63b36f2014-03-24 19:56:00 -03002116
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02002117 lg_debug("\n");
Fred Richterb63b36f2014-03-24 19:56:00 -03002118
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03002119 for (i = 0; i < numDumpRegs; i++) {
Fred Richterb63b36f2014-03-24 19:56:00 -03002120 lgdt3306a_read_reg(state, regtab[i], &regval1[i]);
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03002121 if (regval1[i] != regval2[i]) {
Mauro Carvalho Chehab097117ca2014-10-28 11:35:16 -02002122 lg_debug(" %04X = %02X\n", regtab[i], regval1[i]);
Mauro Carvalho Chehab16afc672015-04-28 18:31:21 -03002123 regval2[i] = regval1[i];
Fred Richterb63b36f2014-03-24 19:56:00 -03002124 }
2125 }
2126 debug = sav_debug;
2127}
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03002128#endif /* DBG_DUMP */
Fred Richterb63b36f2014-03-24 19:56:00 -03002129
2130
2131
Max Kellermannbd336e62016-08-09 18:32:21 -03002132static const struct dvb_frontend_ops lgdt3306a_ops = {
Fred Richterb63b36f2014-03-24 19:56:00 -03002133 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
2134 .info = {
2135 .name = "LG Electronics LGDT3306A VSB/QAM Frontend",
Fred Richterb63b36f2014-03-24 19:56:00 -03002136 .frequency_min = 54000000,
Michael Ira Krufky8e8cd342014-07-27 19:24:24 -03002137 .frequency_max = 858000000,
Fred Richterb63b36f2014-03-24 19:56:00 -03002138 .frequency_stepsize = 62500,
2139 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
2140 },
2141 .i2c_gate_ctrl = lgdt3306a_i2c_gate_ctrl,
2142 .init = lgdt3306a_init,
2143 .sleep = lgdt3306a_fe_sleep,
2144 /* if this is set, it overrides the default swzigzag */
2145 .tune = lgdt3306a_tune,
2146 .set_frontend = lgdt3306a_set_parameters,
2147 .get_frontend = lgdt3306a_get_frontend,
2148 .get_frontend_algo = lgdt3306a_get_frontend_algo,
2149 .get_tune_settings = lgdt3306a_get_tune_settings,
2150 .read_status = lgdt3306a_read_status,
2151 .read_ber = lgdt3306a_read_ber,
2152 .read_signal_strength = lgdt3306a_read_signal_strength,
2153 .read_snr = lgdt3306a_read_snr,
2154 .read_ucblocks = lgdt3306a_read_ucblocks,
2155 .release = lgdt3306a_release,
2156 .ts_bus_ctrl = lgdt3306a_ts_bus_ctrl,
2157 .search = lgdt3306a_search,
2158};
2159
Kevin Cheng4f751892017-01-10 01:14:18 -02002160static int lgdt3306a_select(struct i2c_mux_core *muxc, u32 chan)
2161{
2162 struct i2c_client *client = i2c_mux_priv(muxc);
2163 struct lgdt3306a_state *state = i2c_get_clientdata(client);
2164
2165 return lgdt3306a_i2c_gate_ctrl(&state->frontend, 1);
2166}
2167
2168static int lgdt3306a_deselect(struct i2c_mux_core *muxc, u32 chan)
2169{
2170 struct i2c_client *client = i2c_mux_priv(muxc);
2171 struct lgdt3306a_state *state = i2c_get_clientdata(client);
2172
2173 return lgdt3306a_i2c_gate_ctrl(&state->frontend, 0);
2174}
2175
2176static int lgdt3306a_probe(struct i2c_client *client,
2177 const struct i2c_device_id *id)
2178{
2179 struct lgdt3306a_config *config;
2180 struct lgdt3306a_state *state;
2181 struct dvb_frontend *fe;
2182 int ret;
2183
2184 config = kzalloc(sizeof(struct lgdt3306a_config), GFP_KERNEL);
2185 if (config == NULL) {
2186 ret = -ENOMEM;
2187 goto fail;
2188 }
2189
2190 memcpy(config, client->dev.platform_data,
2191 sizeof(struct lgdt3306a_config));
2192
2193 config->i2c_addr = client->addr;
2194 fe = lgdt3306a_attach(config, client->adapter);
2195 if (fe == NULL) {
2196 ret = -ENODEV;
2197 goto err_fe;
2198 }
2199
2200 i2c_set_clientdata(client, fe->demodulator_priv);
2201 state = fe->demodulator_priv;
Brad Love5b3a8e92018-01-04 19:04:17 -05002202 state->frontend.ops.release = NULL;
Kevin Cheng4f751892017-01-10 01:14:18 -02002203
2204 /* create mux i2c adapter for tuner */
2205 state->muxc = i2c_mux_alloc(client->adapter, &client->dev,
2206 1, 0, I2C_MUX_LOCKED,
2207 lgdt3306a_select, lgdt3306a_deselect);
2208 if (!state->muxc) {
2209 ret = -ENOMEM;
2210 goto err_kfree;
2211 }
2212 state->muxc->priv = client;
2213 ret = i2c_mux_add_adapter(state->muxc, 0, 0, 0);
2214 if (ret)
2215 goto err_kfree;
2216
2217 /* create dvb_frontend */
2218 fe->ops.i2c_gate_ctrl = NULL;
2219 *config->i2c_adapter = state->muxc->adapter[0];
2220 *config->fe = fe;
2221
2222 return 0;
2223
2224err_kfree:
2225 kfree(state);
2226err_fe:
2227 kfree(config);
2228fail:
2229 dev_dbg(&client->dev, "failed=%d\n", ret);
2230 return ret;
2231}
2232
2233static int lgdt3306a_remove(struct i2c_client *client)
2234{
2235 struct lgdt3306a_state *state = i2c_get_clientdata(client);
2236
2237 i2c_mux_del_adapters(state->muxc);
2238
2239 state->frontend.ops.release = NULL;
2240 state->frontend.demodulator_priv = NULL;
2241
2242 kfree(state->cfg);
2243 kfree(state);
2244
2245 return 0;
2246}
2247
2248static const struct i2c_device_id lgdt3306a_id_table[] = {
2249 {"lgdt3306a", 0},
2250 {}
2251};
2252MODULE_DEVICE_TABLE(i2c, lgdt3306a_id_table);
2253
2254static struct i2c_driver lgdt3306a_driver = {
2255 .driver = {
2256 .name = "lgdt3306a",
2257 .suppress_bind_attrs = true,
2258 },
2259 .probe = lgdt3306a_probe,
2260 .remove = lgdt3306a_remove,
2261 .id_table = lgdt3306a_id_table,
2262};
2263
2264module_i2c_driver(lgdt3306a_driver);
2265
Fred Richterb63b36f2014-03-24 19:56:00 -03002266MODULE_DESCRIPTION("LG Electronics LGDT3306A ATSC/QAM-B Demodulator Driver");
2267MODULE_AUTHOR("Fred Richter <frichter@hauppauge.com>");
2268MODULE_LICENSE("GPL");
2269MODULE_VERSION("0.2");