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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/include/linux/mtd/nand.h
3 *
David Woodhousea1452a32010-08-08 20:58:20 +01004 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
Thomas Gleixner2c0a2be2006-05-23 11:50:56 +020012 * Info:
13 * Contains standard defines and IDs for NAND flash devices
Linus Torvalds1da177e2005-04-16 15:20:36 -070014 *
Thomas Gleixner2c0a2be2006-05-23 11:50:56 +020015 * Changelog:
16 * See git changelog.
Linus Torvalds1da177e2005-04-16 15:20:36 -070017 */
18#ifndef __LINUX_MTD_NAND_H
19#define __LINUX_MTD_NAND_H
20
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <linux/wait.h>
22#include <linux/spinlock.h>
23#include <linux/mtd/mtd.h>
Alessandro Rubini30631cb2009-09-20 23:28:14 +020024#include <linux/mtd/flashchip.h>
Alessandro Rubinic62d81b2009-09-20 23:28:04 +020025#include <linux/mtd/bbm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
27struct mtd_info;
David Woodhouse5e81e882010-02-26 18:32:56 +000028struct nand_flash_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -070029/* Scan and identify a NAND device */
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +020030extern int nand_scan(struct mtd_info *mtd, int max_chips);
31/*
32 * Separate phases of nand_scan(), allowing board driver to intervene
33 * and override command or ECC setup according to flash type.
34 */
David Woodhouse5e81e882010-02-26 18:32:56 +000035extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
36 struct nand_flash_dev *table);
David Woodhouse3b85c322006-09-25 17:06:53 +010037extern int nand_scan_tail(struct mtd_info *mtd);
38
Linus Torvalds1da177e2005-04-16 15:20:36 -070039/* Free resources held by the NAND device */
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +020040extern void nand_release(struct mtd_info *mtd);
Linus Torvalds1da177e2005-04-16 15:20:36 -070041
David Woodhouseb77d95c2006-09-25 21:58:50 +010042/* Internal helper for board drivers which need to override command function */
43extern void nand_wait_ready(struct mtd_info *mtd);
44
Brian Norris7854d3f2011-06-23 14:12:08 -070045/* locks all blocks present in the device */
Vimal Singh7d70f332010-02-08 15:50:49 +053046extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
47
Brian Norris7854d3f2011-06-23 14:12:08 -070048/* unlocks specified locked blocks */
Vimal Singh7d70f332010-02-08 15:50:49 +053049extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
50
Linus Torvalds1da177e2005-04-16 15:20:36 -070051/* The maximum number of NAND chips in an array */
52#define NAND_MAX_CHIPS 8
53
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +020054/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070055 * Constants for hardware specific CLE/ALE/NCE function
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020056 *
57 * These are bits which can be or'ed to set/clear multiple
58 * bits in one go.
59 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070060/* Select the chip by setting nCE to low */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020061#define NAND_NCE 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -070062/* Select the command latch by setting CLE to high */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020063#define NAND_CLE 0x02
Linus Torvalds1da177e2005-04-16 15:20:36 -070064/* Select the address latch by setting ALE to high */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020065#define NAND_ALE 0x04
66
67#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
68#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
69#define NAND_CTRL_CHANGE 0x80
Linus Torvalds1da177e2005-04-16 15:20:36 -070070
71/*
72 * Standard NAND flash commands
73 */
74#define NAND_CMD_READ0 0
75#define NAND_CMD_READ1 1
Thomas Gleixner7bc33122006-06-20 20:05:05 +020076#define NAND_CMD_RNDOUT 5
Linus Torvalds1da177e2005-04-16 15:20:36 -070077#define NAND_CMD_PAGEPROG 0x10
78#define NAND_CMD_READOOB 0x50
79#define NAND_CMD_ERASE1 0x60
80#define NAND_CMD_STATUS 0x70
Linus Torvalds1da177e2005-04-16 15:20:36 -070081#define NAND_CMD_SEQIN 0x80
Thomas Gleixner7bc33122006-06-20 20:05:05 +020082#define NAND_CMD_RNDIN 0x85
Linus Torvalds1da177e2005-04-16 15:20:36 -070083#define NAND_CMD_READID 0x90
84#define NAND_CMD_ERASE2 0xd0
Florian Fainellicaa4b6f2010-08-30 18:32:14 +020085#define NAND_CMD_PARAM 0xec
Huang Shijie7db03ec2012-09-13 14:57:52 +080086#define NAND_CMD_GET_FEATURES 0xee
87#define NAND_CMD_SET_FEATURES 0xef
Linus Torvalds1da177e2005-04-16 15:20:36 -070088#define NAND_CMD_RESET 0xff
89
Vimal Singh7d70f332010-02-08 15:50:49 +053090#define NAND_CMD_LOCK 0x2a
91#define NAND_CMD_UNLOCK1 0x23
92#define NAND_CMD_UNLOCK2 0x24
93
Linus Torvalds1da177e2005-04-16 15:20:36 -070094/* Extended commands for large page devices */
95#define NAND_CMD_READSTART 0x30
Thomas Gleixner7bc33122006-06-20 20:05:05 +020096#define NAND_CMD_RNDOUTSTART 0xE0
Linus Torvalds1da177e2005-04-16 15:20:36 -070097#define NAND_CMD_CACHEDPROG 0x15
98
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020099#define NAND_CMD_NONE -1
100
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101/* Status bits */
102#define NAND_STATUS_FAIL 0x01
103#define NAND_STATUS_FAIL_N1 0x02
104#define NAND_STATUS_TRUE_READY 0x20
105#define NAND_STATUS_READY 0x40
106#define NAND_STATUS_WP 0x80
107
Thomas Gleixner61ecfa82005-11-07 11:15:31 +0000108/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109 * Constants for ECC_MODES
110 */
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200111typedef enum {
112 NAND_ECC_NONE,
113 NAND_ECC_SOFT,
114 NAND_ECC_HW,
115 NAND_ECC_HW_SYNDROME,
Sneha Narnakaje6e0cb132009-09-18 12:51:47 -0700116 NAND_ECC_HW_OOB_FIRST,
Ivan Djelic193bd402011-03-11 11:05:33 +0100117 NAND_ECC_SOFT_BCH,
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200118} nand_ecc_modes_t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119
120/*
121 * Constants for Hardware ECC
David A. Marlin068e3c02005-01-24 03:07:46 +0000122 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123/* Reset Hardware ECC for read */
124#define NAND_ECC_READ 0
125/* Reset Hardware ECC for write */
126#define NAND_ECC_WRITE 1
Brian Norris7854d3f2011-06-23 14:12:08 -0700127/* Enable Hardware ECC before syndrome is read back from flash */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128#define NAND_ECC_READSYN 2
129
David A. Marlin068e3c02005-01-24 03:07:46 +0000130/* Bit mask for flags passed to do_nand_read_ecc */
131#define NAND_GET_DEVICE 0x80
132
133
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200134/*
135 * Option constants for bizarre disfunctionality and real
136 * features.
137 */
Brian Norris7854d3f2011-06-23 14:12:08 -0700138/* Buswidth is 16 bit */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139#define NAND_BUSWIDTH_16 0x00000002
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140/* Chip has cache program function */
141#define NAND_CACHEPRG 0x00000008
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200142/*
Brian Norris5bc7c332013-03-13 09:51:31 -0700143 * Chip requires ready check on read (for auto-incremented sequential read).
144 * True only for small page devices; large page devices do not support
145 * autoincrement.
146 */
147#define NAND_NEED_READRDY 0x00000100
148
Thomas Gleixner29072b92006-09-28 15:38:36 +0200149/* Chip does not allow subpage writes */
150#define NAND_NO_SUBPAGE_WRITE 0x00000200
151
Maxim Levitsky93edbad2010-02-22 20:39:40 +0200152/* Device is one of 'new' xD cards that expose fake nand command set */
153#define NAND_BROKEN_XD 0x00000400
154
155/* Device behaves just like nand, but is readonly */
156#define NAND_ROM 0x00000800
157
Jeff Westfahla5ff4f12012-08-13 16:35:30 -0500158/* Device supports subpage reads */
159#define NAND_SUBPAGE_READ 0x00001000
160
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161/* Options valid for Samsung large page devices */
Artem Bityutskiy3239a6c2013-03-04 14:56:18 +0200162#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163
164/* Macros to identify the above */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
Jeff Westfahla5ff4f12012-08-13 16:35:30 -0500166#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168/* Non chip related options */
Thomas Gleixner0040bf32005-02-09 12:20:00 +0000169/* This option skips the bbt scan during initialization. */
Brian Norrisb4dc53e2011-05-31 16:31:26 -0700170#define NAND_SKIP_BBTSCAN 0x00010000
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200171/*
172 * This option is defined if the board driver allocates its own buffers
173 * (e.g. because it needs them DMA-coherent).
174 */
Brian Norrisb4dc53e2011-05-31 16:31:26 -0700175#define NAND_OWN_BUFFERS 0x00020000
Ben Dooksb1c6e6d2009-11-02 18:12:33 +0000176/* Chip may not exist, so silence any errors in scan */
Brian Norrisb4dc53e2011-05-31 16:31:26 -0700177#define NAND_SCAN_SILENT_NODEV 0x00040000
Matthieu CASTET64b37b22012-11-06 11:51:44 +0100178/*
179 * Autodetect nand buswidth with readid/onfi.
180 * This suppose the driver will configure the hardware in 8 bits mode
181 * when calling nand_scan_ident, and update its configuration
182 * before calling nand_scan_tail.
183 */
184#define NAND_BUSWIDTH_AUTO 0x00080000
Ben Dooksb1c6e6d2009-11-02 18:12:33 +0000185
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186/* Options set by nand scan */
Thomas Gleixnera36ed292006-05-23 11:37:03 +0200187/* Nand scan has allocated controller struct */
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200188#define NAND_CONTROLLER_ALLOC 0x80000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189
Thomas Gleixner29072b92006-09-28 15:38:36 +0200190/* Cell info constants */
191#define NAND_CI_CHIPNR_MSK 0x03
192#define NAND_CI_CELLTYPE_MSK 0x0C
Huang Shijie7db906b2013-09-25 14:58:11 +0800193#define NAND_CI_CELLTYPE_SHIFT 2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195/* Keep gcc happy */
196struct nand_chip;
197
Huang Shijie5b40db62013-05-17 11:17:28 +0800198/* ONFI features */
199#define ONFI_FEATURE_16_BIT_BUS (1 << 0)
200#define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
201
Huang Shijie3e701922012-09-13 14:57:53 +0800202/* ONFI timing mode, used in both asynchronous and synchronous mode */
203#define ONFI_TIMING_MODE_0 (1 << 0)
204#define ONFI_TIMING_MODE_1 (1 << 1)
205#define ONFI_TIMING_MODE_2 (1 << 2)
206#define ONFI_TIMING_MODE_3 (1 << 3)
207#define ONFI_TIMING_MODE_4 (1 << 4)
208#define ONFI_TIMING_MODE_5 (1 << 5)
209#define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
210
Huang Shijie7db03ec2012-09-13 14:57:52 +0800211/* ONFI feature address */
212#define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
213
Brian Norris8429bb32013-12-03 15:51:09 -0800214/* Vendor-specific feature address (Micron) */
215#define ONFI_FEATURE_ADDR_READ_RETRY 0x89
216
Huang Shijie7db03ec2012-09-13 14:57:52 +0800217/* ONFI subfeature parameters length */
218#define ONFI_SUBFEATURE_PARAM_LEN 4
219
David Mosbergerd914c932013-05-29 15:30:13 +0300220/* ONFI optional commands SET/GET FEATURES supported? */
221#define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
222
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200223struct nand_onfi_params {
224 /* rev info and features block */
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200225 /* 'O' 'N' 'F' 'I' */
226 u8 sig[4];
227 __le16 revision;
228 __le16 features;
229 __le16 opt_cmd;
Huang Shijie5138a982013-05-17 11:17:27 +0800230 u8 reserved0[2];
231 __le16 ext_param_page_length; /* since ONFI 2.1 */
232 u8 num_of_param_pages; /* since ONFI 2.1 */
233 u8 reserved1[17];
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200234
235 /* manufacturer information block */
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200236 char manufacturer[12];
237 char model[20];
238 u8 jedec_id;
239 __le16 date_code;
240 u8 reserved2[13];
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200241
242 /* memory organization block */
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200243 __le32 byte_per_page;
244 __le16 spare_bytes_per_page;
245 __le32 data_bytes_per_ppage;
246 __le16 spare_bytes_per_ppage;
247 __le32 pages_per_block;
248 __le32 blocks_per_lun;
249 u8 lun_count;
250 u8 addr_cycles;
251 u8 bits_per_cell;
252 __le16 bb_per_lun;
253 __le16 block_endurance;
254 u8 guaranteed_good_blocks;
255 __le16 guaranteed_block_endurance;
256 u8 programs_per_page;
257 u8 ppage_attr;
258 u8 ecc_bits;
259 u8 interleaved_bits;
260 u8 interleaved_ops;
261 u8 reserved3[13];
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200262
263 /* electrical parameter block */
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200264 u8 io_pin_capacitance_max;
265 __le16 async_timing_mode;
266 __le16 program_cache_timing_mode;
267 __le16 t_prog;
268 __le16 t_bers;
269 __le16 t_r;
270 __le16 t_ccs;
271 __le16 src_sync_timing_mode;
272 __le16 src_ssync_features;
273 __le16 clk_pin_capacitance_typ;
274 __le16 io_pin_capacitance_typ;
275 __le16 input_pin_capacitance_typ;
276 u8 input_pin_capacitance_max;
Brian Norrisa55e85c2013-12-02 11:12:22 -0800277 u8 driver_strength_support;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200278 __le16 t_int_r;
279 __le16 t_ald;
280 u8 reserved4[7];
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200281
282 /* vendor */
Brian Norris6f0065b2013-12-03 12:02:20 -0800283 __le16 vendor_revision;
284 u8 vendor[88];
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200285
286 __le16 crc;
Brian Norrise2e6b7b2013-12-05 12:06:54 -0800287} __packed;
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200288
289#define ONFI_CRC_BASE 0x4F4E
290
Huang Shijie5138a982013-05-17 11:17:27 +0800291/* Extended ECC information Block Definition (since ONFI 2.1) */
292struct onfi_ext_ecc_info {
293 u8 ecc_bits;
294 u8 codeword_size;
295 __le16 bb_per_lun;
296 __le16 block_endurance;
297 u8 reserved[2];
298} __packed;
299
300#define ONFI_SECTION_TYPE_0 0 /* Unused section. */
301#define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
302#define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
303struct onfi_ext_section {
304 u8 type;
305 u8 length;
306} __packed;
307
308#define ONFI_EXT_SECTION_MAX 8
309
310/* Extended Parameter Page Definition (since ONFI 2.1) */
311struct onfi_ext_param_page {
312 __le16 crc;
313 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
314 u8 reserved0[10];
315 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
316
317 /*
318 * The actual size of the Extended Parameter Page is in
319 * @ext_param_page_length of nand_onfi_params{}.
320 * The following are the variable length sections.
321 * So we do not add any fields below. Please see the ONFI spec.
322 */
323} __packed;
324
Brian Norris6f0065b2013-12-03 12:02:20 -0800325struct nand_onfi_vendor_micron {
326 u8 two_plane_read;
327 u8 read_cache;
328 u8 read_unique_id;
329 u8 dq_imped;
330 u8 dq_imped_num_settings;
331 u8 dq_imped_feat_addr;
332 u8 rb_pulldown_strength;
333 u8 rb_pulldown_strength_feat_addr;
334 u8 rb_pulldown_strength_num_settings;
335 u8 otp_mode;
336 u8 otp_page_start;
337 u8 otp_data_prot_addr;
338 u8 otp_num_pages;
339 u8 otp_feat_addr;
340 u8 read_retry_options;
341 u8 reserved[72];
342 u8 param_revision;
343} __packed;
344
Huang Shijieafbfff02014-02-21 13:39:37 +0800345struct jedec_ecc_info {
346 u8 ecc_bits;
347 u8 codeword_size;
348 __le16 bb_per_lun;
349 __le16 block_endurance;
350 u8 reserved[2];
351} __packed;
352
Huang Shijie7852f892014-02-21 13:39:39 +0800353/* JEDEC features */
354#define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
355
Huang Shijieafbfff02014-02-21 13:39:37 +0800356struct nand_jedec_params {
357 /* rev info and features block */
358 /* 'J' 'E' 'S' 'D' */
359 u8 sig[4];
360 __le16 revision;
361 __le16 features;
362 u8 opt_cmd[3];
363 __le16 sec_cmd;
364 u8 num_of_param_pages;
365 u8 reserved0[18];
366
367 /* manufacturer information block */
368 char manufacturer[12];
369 char model[20];
370 u8 jedec_id[6];
371 u8 reserved1[10];
372
373 /* memory organization block */
374 __le32 byte_per_page;
375 __le16 spare_bytes_per_page;
376 u8 reserved2[6];
377 __le32 pages_per_block;
378 __le32 blocks_per_lun;
379 u8 lun_count;
380 u8 addr_cycles;
381 u8 bits_per_cell;
382 u8 programs_per_page;
383 u8 multi_plane_addr;
384 u8 multi_plane_op_attr;
385 u8 reserved3[38];
386
387 /* electrical parameter block */
388 __le16 async_sdr_speed_grade;
389 __le16 toggle_ddr_speed_grade;
390 __le16 sync_ddr_speed_grade;
391 u8 async_sdr_features;
392 u8 toggle_ddr_features;
393 u8 sync_ddr_features;
394 __le16 t_prog;
395 __le16 t_bers;
396 __le16 t_r;
397 __le16 t_r_multi_plane;
398 __le16 t_ccs;
399 __le16 io_pin_capacitance_typ;
400 __le16 input_pin_capacitance_typ;
401 __le16 clk_pin_capacitance_typ;
402 u8 driver_strength_support;
403 __le16 t_ald;
404 u8 reserved4[36];
405
406 /* ECC and endurance block */
407 u8 guaranteed_good_blocks;
408 __le16 guaranteed_block_endurance;
409 struct jedec_ecc_info ecc_info[4];
410 u8 reserved5[29];
411
412 /* reserved */
413 u8 reserved6[148];
414
415 /* vendor */
416 __le16 vendor_rev_num;
417 u8 reserved7[88];
418
419 /* CRC for Parameter Page */
420 __le16 crc;
421} __packed;
422
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423/**
Randy Dunlap844d3b42006-06-28 21:48:27 -0700424 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
Thomas Gleixner61ecfa82005-11-07 11:15:31 +0000425 * @lock: protection lock
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426 * @active: the mtd device which holds the controller currently
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200427 * @wq: wait queue to sleep on if a NAND operation is in
428 * progress used instead of the per chip wait queue
429 * when a hw controller is available.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430 */
431struct nand_hw_control {
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200432 spinlock_t lock;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433 struct nand_chip *active;
Thomas Gleixner0dfc6242005-05-31 20:39:20 +0100434 wait_queue_head_t wq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435};
436
437/**
Brian Norris7854d3f2011-06-23 14:12:08 -0700438 * struct nand_ecc_ctrl - Control structure for ECC
439 * @mode: ECC mode
440 * @steps: number of ECC steps per page
441 * @size: data bytes per ECC step
442 * @bytes: ECC bytes per step
Mike Dunn1d0b95b02012-03-11 14:21:10 -0700443 * @strength: max number of correctible bits per ECC step
Brian Norris7854d3f2011-06-23 14:12:08 -0700444 * @total: total number of ECC bytes per page
445 * @prepad: padding information for syndrome based ECC generators
446 * @postpad: padding information for syndrome based ECC generators
Randy Dunlap844d3b42006-06-28 21:48:27 -0700447 * @layout: ECC layout control struct pointer
Brian Norris7854d3f2011-06-23 14:12:08 -0700448 * @priv: pointer to private ECC control data
449 * @hwctl: function to control hardware ECC generator. Must only
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200450 * be provided if an hardware ECC is available
Brian Norris7854d3f2011-06-23 14:12:08 -0700451 * @calculate: function for ECC calculation or readback from ECC hardware
452 * @correct: function for ECC correction, matching to ECC generator (sw/hw)
David Woodhouse956e9442006-09-25 17:12:39 +0100453 * @read_page_raw: function to read a raw page without ECC
454 * @write_page_raw: function to write a raw page without ECC
Brian Norris7854d3f2011-06-23 14:12:08 -0700455 * @read_page: function to read a page according to the ECC generator
Mike Dunn5ca7f412012-09-11 08:59:03 -0700456 * requirements; returns maximum number of bitflips corrected in
457 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
458 * @read_subpage: function to read parts of the page covered by ECC;
459 * returns same as read_page()
Gupta, Pekon837a6ba2013-03-15 17:55:53 +0530460 * @write_subpage: function to write parts of the page covered by ECC.
Brian Norris7854d3f2011-06-23 14:12:08 -0700461 * @write_page: function to write a page according to the ECC generator
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200462 * requirements.
Brian Norris9ce244b2011-08-30 18:45:37 -0700463 * @write_oob_raw: function to write chip OOB data without ECC
Brian Norrisc46f6482011-08-30 18:45:38 -0700464 * @read_oob_raw: function to read chip OOB data without ECC
Randy Dunlap844d3b42006-06-28 21:48:27 -0700465 * @read_oob: function to read chip OOB data
466 * @write_oob: function to write chip OOB data
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200467 */
468struct nand_ecc_ctrl {
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200469 nand_ecc_modes_t mode;
470 int steps;
471 int size;
472 int bytes;
473 int total;
Mike Dunn1d0b95b02012-03-11 14:21:10 -0700474 int strength;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200475 int prepad;
476 int postpad;
Thomas Gleixner5bd34c02006-05-27 22:16:10 +0200477 struct nand_ecclayout *layout;
Ivan Djelic193bd402011-03-11 11:05:33 +0100478 void *priv;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200479 void (*hwctl)(struct mtd_info *mtd, int mode);
480 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
481 uint8_t *ecc_code);
482 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
483 uint8_t *calc_ecc);
484 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
Brian Norris1fbb9382012-05-02 10:14:55 -0700485 uint8_t *buf, int oob_required, int page);
Josh Wufdbad98d2012-06-25 18:07:45 +0800486 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
Brian Norris1fbb9382012-05-02 10:14:55 -0700487 const uint8_t *buf, int oob_required);
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200488 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
Brian Norris1fbb9382012-05-02 10:14:55 -0700489 uint8_t *buf, int oob_required, int page);
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200490 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
Huang Shijiee004deb2014-01-03 11:01:40 +0800491 uint32_t offs, uint32_t len, uint8_t *buf, int page);
Gupta, Pekon837a6ba2013-03-15 17:55:53 +0530492 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
493 uint32_t offset, uint32_t data_len,
494 const uint8_t *data_buf, int oob_required);
Josh Wufdbad98d2012-06-25 18:07:45 +0800495 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
Brian Norris1fbb9382012-05-02 10:14:55 -0700496 const uint8_t *buf, int oob_required);
Brian Norris9ce244b2011-08-30 18:45:37 -0700497 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
498 int page);
Brian Norrisc46f6482011-08-30 18:45:38 -0700499 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
Shmulik Ladkani5c2ffb12012-05-09 13:06:35 +0300500 int page);
501 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200502 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
503 int page);
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200504};
505
506/**
507 * struct nand_buffers - buffer structure for read/write
Huang Shijief02ea4e2014-01-13 14:27:12 +0800508 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
509 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
510 * @databuf: buffer pointer for data, size is (page size + oobsize).
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200511 *
512 * Do not change the order of buffers. databuf and oobrbuf must be in
513 * consecutive order.
514 */
515struct nand_buffers {
Huang Shijief02ea4e2014-01-13 14:27:12 +0800516 uint8_t *ecccalc;
517 uint8_t *ecccode;
518 uint8_t *databuf;
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200519};
520
521/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700522 * struct nand_chip - NAND Private Flash Chip Data
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200523 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
524 * flash device
525 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
526 * flash device.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700527 * @read_byte: [REPLACEABLE] read one byte from the chip
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528 * @read_word: [REPLACEABLE] read one word from the chip
Uwe Kleine-König05f78352013-12-05 22:22:04 +0100529 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
530 * low 8 I/O lines
Linus Torvalds1da177e2005-04-16 15:20:36 -0700531 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
532 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533 * @select_chip: [REPLACEABLE] select chip nr
Brian Norrisce157512013-04-11 01:34:59 -0700534 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
535 * @block_markbad: [REPLACEABLE] mark a block bad
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300536 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200537 * ALE/CLE/nCE. Also used to write command and address
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300538 * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting
Huang Shijie12a40a52010-09-27 10:43:53 +0800539 * mtd->oobsize, mtd->writesize and so on.
540 * @id_data contains the 8 bytes values of NAND_CMD_READID.
541 * Return with the bus width.
Brian Norris7854d3f2011-06-23 14:12:08 -0700542 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200543 * device ready/busy line. If set to NULL no access to
544 * ready/busy is available and the ready/busy information
545 * is read from the chip status register.
546 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
547 * commands to the chip.
548 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
549 * ready.
Brian Norrisba84fb52014-01-03 15:13:33 -0800550 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
551 * setting the read-retry mode. Mostly needed for MLC NAND.
Brian Norris7854d3f2011-06-23 14:12:08 -0700552 * @ecc: [BOARDSPECIFIC] ECC control structure
Randy Dunlap844d3b42006-06-28 21:48:27 -0700553 * @buffers: buffer structure for read/write
554 * @hwcontrol: platform-specific hardware control structure
Brian Norris49c50b92014-05-06 16:02:19 -0700555 * @erase: [REPLACEABLE] erase function
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556 * @scan_bbt: [REPLACEABLE] function to scan bad block table
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300557 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200558 * data from array to read regs (tR).
Thomas Gleixner2c0a2be2006-05-23 11:50:56 +0200559 * @state: [INTERN] the current state of the NAND device
Brian Norrise9195ed2011-08-30 18:45:43 -0700560 * @oob_poi: "poison value buffer," used for laying out OOB data
561 * before writing
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200562 * @page_shift: [INTERN] number of address bits in a page (column
563 * address bits).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
565 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
566 * @chip_shift: [INTERN] number of address bits in one chip
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200567 * @options: [BOARDSPECIFIC] various chip options. They can partly
568 * be set to inform nand_scan about special functionality.
569 * See the defines for further explanation.
Brian Norris5fb15492011-05-31 16:31:21 -0700570 * @bbt_options: [INTERN] bad block specific options. All options used
571 * here must come from bbm.h. By default, these options
572 * will be copied to the appropriate nand_bbt_descr's.
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200573 * @badblockpos: [INTERN] position of the bad block marker in the oob
574 * area.
Brian Norris661a0832012-01-13 18:11:50 -0800575 * @badblockbits: [INTERN] minimum number of set bits in a good block's
576 * bad block marker position; i.e., BBM == 11110111b is
577 * not bad when badblockbits == 7
Huang Shijie7db906b2013-09-25 14:58:11 +0800578 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
Huang Shijie4cfeca22013-05-17 11:17:25 +0800579 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
580 * Minimum amount of bit errors per @ecc_step_ds guaranteed
581 * to be correctable. If unknown, set to zero.
582 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
583 * also from the datasheet. It is the recommended ECC step
584 * size, if known; if unknown, set to zero.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700585 * @numchips: [INTERN] number of physical chips
586 * @chipsize: [INTERN] the size of one chip for multichip arrays
587 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200588 * @pagebuf: [INTERN] holds the pagenumber which is currently in
589 * data_buf.
Mike Dunnedbc45402012-04-25 12:06:11 -0700590 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
591 * currently in data_buf.
Thomas Gleixner29072b92006-09-28 15:38:36 +0200592 * @subpagesize: [INTERN] holds the subpagesize
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200593 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
594 * non 0 if ONFI supported.
Huang Shijied94abba2014-02-21 13:39:38 +0800595 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
596 * non 0 if JEDEC supported.
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200597 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
598 * supported, 0 otherwise.
Huang Shijied94abba2014-02-21 13:39:38 +0800599 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
600 * supported, 0 otherwise.
Brian Norrisba84fb52014-01-03 15:13:33 -0800601 * @read_retries: [INTERN] the number of read retry modes supported
Robert P. J. Day9ef525a2012-10-25 09:43:10 -0400602 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
603 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604 * @bbt: [INTERN] bad block table pointer
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200605 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
606 * lookup.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700607 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200608 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
609 * bad block scan.
610 * @controller: [REPLACEABLE] a pointer to a hardware controller
Brian Norris7854d3f2011-06-23 14:12:08 -0700611 * structure which is shared among multiple independent
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200612 * devices.
Brian Norris32c8db82011-08-23 17:17:35 -0700613 * @priv: [OPTIONAL] pointer to private chip data
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200614 * @errstat: [OPTIONAL] hardware specific function to perform
615 * additional error status checks (determine if errors are
616 * correctable).
Randy Dunlap351edd22006-10-29 22:46:40 -0800617 * @write_page: [REPLACEABLE] High-level page write function
Linus Torvalds1da177e2005-04-16 15:20:36 -0700618 */
Thomas Gleixner61ecfa82005-11-07 11:15:31 +0000619
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620struct nand_chip {
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200621 void __iomem *IO_ADDR_R;
622 void __iomem *IO_ADDR_W;
Thomas Gleixner61ecfa82005-11-07 11:15:31 +0000623
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200624 uint8_t (*read_byte)(struct mtd_info *mtd);
625 u16 (*read_word)(struct mtd_info *mtd);
Uwe Kleine-König05f78352013-12-05 22:22:04 +0100626 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200627 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
628 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200629 void (*select_chip)(struct mtd_info *mtd, int chip);
630 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
631 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
632 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
633 int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
634 u8 *id_data);
635 int (*dev_ready)(struct mtd_info *mtd);
636 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
637 int page_addr);
638 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
Brian Norris49c50b92014-05-06 16:02:19 -0700639 int (*erase)(struct mtd_info *mtd, int page);
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200640 int (*scan_bbt)(struct mtd_info *mtd);
641 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
642 int status, int page);
643 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
Gupta, Pekon837a6ba2013-03-15 17:55:53 +0530644 uint32_t offset, int data_len, const uint8_t *buf,
645 int oob_required, int page, int cached, int raw);
Huang Shijie7db03ec2012-09-13 14:57:52 +0800646 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
647 int feature_addr, uint8_t *subfeature_para);
648 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
649 int feature_addr, uint8_t *subfeature_para);
Brian Norrisba84fb52014-01-03 15:13:33 -0800650 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200651
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200652 int chip_delay;
653 unsigned int options;
Brian Norris5fb15492011-05-31 16:31:21 -0700654 unsigned int bbt_options;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200655
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200656 int page_shift;
657 int phys_erase_shift;
658 int bbt_erase_shift;
659 int chip_shift;
660 int numchips;
661 uint64_t chipsize;
662 int pagemask;
663 int pagebuf;
Mike Dunnedbc45402012-04-25 12:06:11 -0700664 unsigned int pagebuf_bitflips;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200665 int subpagesize;
Huang Shijie7db906b2013-09-25 14:58:11 +0800666 uint8_t bits_per_cell;
Huang Shijie4cfeca22013-05-17 11:17:25 +0800667 uint16_t ecc_strength_ds;
668 uint16_t ecc_step_ds;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200669 int badblockpos;
670 int badblockbits;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200671
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200672 int onfi_version;
Huang Shijied94abba2014-02-21 13:39:38 +0800673 int jedec_version;
674 union {
675 struct nand_onfi_params onfi_params;
676 struct nand_jedec_params jedec_params;
677 };
Florian Fainellid1e1f4e2010-08-30 18:32:24 +0200678
Brian Norrisba84fb52014-01-03 15:13:33 -0800679 int read_retries;
680
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200681 flstate_t state;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200682
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200683 uint8_t *oob_poi;
684 struct nand_hw_control *controller;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200685
686 struct nand_ecc_ctrl ecc;
David Woodhouse4bf63fc2006-09-25 17:08:04 +0100687 struct nand_buffers *buffers;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200688 struct nand_hw_control hwcontrol;
689
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200690 uint8_t *bbt;
691 struct nand_bbt_descr *bbt_td;
692 struct nand_bbt_descr *bbt_md;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200693
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200694 struct nand_bbt_descr *badblock_pattern;
Thomas Gleixnerf75e5092006-05-26 18:52:08 +0200695
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200696 void *priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697};
698
699/*
700 * NAND Flash Manufacturer ID Codes
701 */
702#define NAND_MFR_TOSHIBA 0x98
703#define NAND_MFR_SAMSUNG 0xec
704#define NAND_MFR_FUJITSU 0x04
705#define NAND_MFR_NATIONAL 0x8f
706#define NAND_MFR_RENESAS 0x07
707#define NAND_MFR_STMICRO 0x20
Thomas Gleixner2c0a2be2006-05-23 11:50:56 +0200708#define NAND_MFR_HYNIX 0xad
sshahrom@micron.com8c60e542007-03-21 18:48:02 -0700709#define NAND_MFR_MICRON 0x2c
Steven J. Hill30eb0db2007-07-18 23:29:46 -0500710#define NAND_MFR_AMD 0x01
Brian Norrisc1257b42011-11-02 13:34:42 -0700711#define NAND_MFR_MACRONIX 0xc2
Brian Norrisb1ccfab2012-05-22 07:30:47 -0700712#define NAND_MFR_EON 0x92
Huang Shijie3f97c6f2013-12-26 15:37:45 +0800713#define NAND_MFR_SANDISK 0x45
Huang Shijie4968a412014-01-03 16:50:39 +0800714#define NAND_MFR_INTEL 0x89
Linus Torvalds1da177e2005-04-16 15:20:36 -0700715
Artem Bityutskiy53552d22013-03-14 09:57:23 +0200716/* The maximum expected count of bytes in the NAND ID sequence */
717#define NAND_MAX_ID_LEN 8
718
Artem Bityutskiy8dbfae12013-03-04 15:39:18 +0200719/*
720 * A helper for defining older NAND chips where the second ID byte fully
721 * defined the chip, including the geometry (chip size, eraseblock size, page
Artem Bityutskiy5bfa9b72013-03-19 10:29:26 +0200722 * size). All these chips have 512 bytes NAND page size.
Artem Bityutskiy8dbfae12013-03-04 15:39:18 +0200723 */
Artem Bityutskiy5bfa9b72013-03-19 10:29:26 +0200724#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
725 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
726 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
Artem Bityutskiy8dbfae12013-03-04 15:39:18 +0200727
728/*
729 * A helper for defining newer chips which report their page size and
730 * eraseblock size via the extended ID bytes.
731 *
732 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
733 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
734 * device ID now only represented a particular total chip size (and voltage,
735 * buswidth), and the page size, eraseblock size, and OOB size could vary while
736 * using the same device ID.
737 */
Artem Bityutskiy8e12b472013-03-04 16:26:56 +0200738#define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
739 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
Artem Bityutskiy8dbfae12013-03-04 15:39:18 +0200740 .options = (opts) }
741
Huang Shijie2dc0bdd2013-05-17 11:17:31 +0800742#define NAND_ECC_INFO(_strength, _step) \
743 { .strength_ds = (_strength), .step_ds = (_step) }
744#define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
745#define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
746
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747/**
748 * struct nand_flash_dev - NAND Flash Device ID Structure
Artem Bityutskiy68aa352de2013-03-04 16:05:00 +0200749 * @name: a human-readable name of the NAND chip
750 * @dev_id: the device ID (the second byte of the full chip ID array)
Artem Bityutskiy8e12b472013-03-04 16:26:56 +0200751 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
752 * memory address as @id[0])
753 * @dev_id: device ID part of the full chip ID array (refers the same memory
754 * address as @id[1])
755 * @id: full device ID array
Artem Bityutskiy68aa352de2013-03-04 16:05:00 +0200756 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
757 * well as the eraseblock size) is determined from the extended NAND
758 * chip ID array)
Artem Bityutskiy68aa352de2013-03-04 16:05:00 +0200759 * @chipsize: total chip size in MiB
Artem Bityutskiyecb42fe2013-03-13 13:45:00 +0200760 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
Artem Bityutskiy68aa352de2013-03-04 16:05:00 +0200761 * @options: stores various chip bit options
Huang Shijief22d5f62013-03-15 11:00:59 +0800762 * @id_len: The valid length of the @id.
763 * @oobsize: OOB size
Huang Shijie2dc0bdd2013-05-17 11:17:31 +0800764 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
765 * @ecc_strength_ds in nand_chip{}.
766 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
767 * @ecc_step_ds in nand_chip{}, also from the datasheet.
768 * For example, the "4bit ECC for each 512Byte" can be set with
769 * NAND_ECC_INFO(4, 512).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770 */
771struct nand_flash_dev {
772 char *name;
Artem Bityutskiy8e12b472013-03-04 16:26:56 +0200773 union {
774 struct {
775 uint8_t mfr_id;
776 uint8_t dev_id;
777 };
Artem Bityutskiy53552d22013-03-14 09:57:23 +0200778 uint8_t id[NAND_MAX_ID_LEN];
Artem Bityutskiy8e12b472013-03-04 16:26:56 +0200779 };
Artem Bityutskiyecb42fe2013-03-13 13:45:00 +0200780 unsigned int pagesize;
781 unsigned int chipsize;
782 unsigned int erasesize;
783 unsigned int options;
Huang Shijief22d5f62013-03-15 11:00:59 +0800784 uint16_t id_len;
785 uint16_t oobsize;
Huang Shijie2dc0bdd2013-05-17 11:17:31 +0800786 struct {
787 uint16_t strength_ds;
788 uint16_t step_ds;
789 } ecc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790};
791
792/**
793 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
794 * @name: Manufacturer name
Thomas Gleixner2c0a2be2006-05-23 11:50:56 +0200795 * @id: manufacturer ID code of device.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796*/
797struct nand_manufacturers {
798 int id;
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200799 char *name;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700800};
801
802extern struct nand_flash_dev nand_flash_ids[];
803extern struct nand_manufacturers nand_manuf_ids[];
804
Thomas Gleixnerf5bbdac2006-05-25 10:07:16 +0200805extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
Thomas Gleixnerf5bbdac2006-05-25 10:07:16 +0200806extern int nand_default_bbt(struct mtd_info *mtd);
Brian Norrisb32843b2013-07-30 17:52:59 -0700807extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
Thomas Gleixnerf5bbdac2006-05-25 10:07:16 +0200808extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
809extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
810 int allowbbt);
811extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
Sebastian Andrzej Siewiora0491fc2010-10-05 12:41:01 +0200812 size_t *retlen, uint8_t *buf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700813
Thomas Gleixner41796c22006-05-23 11:38:59 +0200814/**
815 * struct platform_nand_chip - chip level device structure
Thomas Gleixner41796c22006-05-23 11:38:59 +0200816 * @nr_chips: max. number of chips to scan for
Randy Dunlap844d3b42006-06-28 21:48:27 -0700817 * @chip_offset: chip number offset
Thomas Gleixner8be834f2006-05-27 20:05:26 +0200818 * @nr_partitions: number of partitions pointed to by partitions (or zero)
Thomas Gleixner41796c22006-05-23 11:38:59 +0200819 * @partitions: mtd partition list
820 * @chip_delay: R/B delay value in us
821 * @options: Option flags, e.g. 16bit buswidth
Brian Norrisa40f7342011-05-31 16:31:22 -0700822 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
Brian Norris7854d3f2011-06-23 14:12:08 -0700823 * @ecclayout: ECC layout info structure
Vitaly Wool972edcb2007-05-06 18:46:57 +0400824 * @part_probe_types: NULL-terminated array of probe types
Thomas Gleixner41796c22006-05-23 11:38:59 +0200825 */
826struct platform_nand_chip {
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200827 int nr_chips;
828 int chip_offset;
829 int nr_partitions;
830 struct mtd_partition *partitions;
831 struct nand_ecclayout *ecclayout;
832 int chip_delay;
833 unsigned int options;
Brian Norrisa40f7342011-05-31 16:31:22 -0700834 unsigned int bbt_options;
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200835 const char **part_probe_types;
Thomas Gleixner41796c22006-05-23 11:38:59 +0200836};
837
H Hartley Sweetenbf95efd2009-05-12 13:46:58 -0700838/* Keep gcc happy */
839struct platform_device;
840
Thomas Gleixner41796c22006-05-23 11:38:59 +0200841/**
842 * struct platform_nand_ctrl - controller level device structure
H Hartley Sweetenbf95efd2009-05-12 13:46:58 -0700843 * @probe: platform specific function to probe/setup hardware
844 * @remove: platform specific function to remove/teardown hardware
Thomas Gleixner41796c22006-05-23 11:38:59 +0200845 * @hwcontrol: platform specific hardware control structure
846 * @dev_ready: platform specific function to read ready/busy pin
847 * @select_chip: platform specific chip select function
Vitaly Wool972edcb2007-05-06 18:46:57 +0400848 * @cmd_ctrl: platform specific function for controlling
849 * ALE/CLE/nCE. Also used to write command and address
Alexander Clouterd6fed9e2009-05-11 19:28:01 +0100850 * @write_buf: platform specific function for write buffer
851 * @read_buf: platform specific function for read buffer
Randy Dunlap25806d32012-08-18 17:41:35 -0700852 * @read_byte: platform specific function to read one byte from chip
Randy Dunlap844d3b42006-06-28 21:48:27 -0700853 * @priv: private data to transport driver specific settings
Thomas Gleixner41796c22006-05-23 11:38:59 +0200854 *
855 * All fields are optional and depend on the hardware driver requirements
856 */
857struct platform_nand_ctrl {
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200858 int (*probe)(struct platform_device *pdev);
859 void (*remove)(struct platform_device *pdev);
860 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
861 int (*dev_ready)(struct mtd_info *mtd);
862 void (*select_chip)(struct mtd_info *mtd, int chip);
863 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
864 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
865 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
John Crispinb4f7aa82012-04-30 19:30:47 +0200866 unsigned char (*read_byte)(struct mtd_info *mtd);
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200867 void *priv;
Thomas Gleixner41796c22006-05-23 11:38:59 +0200868};
869
Vitaly Wool972edcb2007-05-06 18:46:57 +0400870/**
871 * struct platform_nand_data - container structure for platform-specific data
872 * @chip: chip level chip structure
873 * @ctrl: controller level device structure
874 */
875struct platform_nand_data {
Sebastian Andrzej Siewiorb46daf72010-10-07 21:48:27 +0200876 struct platform_nand_chip chip;
877 struct platform_nand_ctrl ctrl;
Vitaly Wool972edcb2007-05-06 18:46:57 +0400878};
879
Thomas Gleixner41796c22006-05-23 11:38:59 +0200880/* Some helpers to access the data structures */
881static inline
882struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
883{
884 struct nand_chip *chip = mtd->priv;
885
886 return chip->priv;
887}
888
Huang Shijie5b40db62013-05-17 11:17:28 +0800889/* return the supported features. */
890static inline int onfi_feature(struct nand_chip *chip)
891{
892 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
893}
894
Huang Shijie3e701922012-09-13 14:57:53 +0800895/* return the supported asynchronous timing mode. */
896static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
897{
898 if (!chip->onfi_version)
899 return ONFI_TIMING_MODE_UNKNOWN;
900 return le16_to_cpu(chip->onfi_params.async_timing_mode);
901}
902
903/* return the supported synchronous timing mode. */
904static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
905{
906 if (!chip->onfi_version)
907 return ONFI_TIMING_MODE_UNKNOWN;
908 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
909}
910
Huang Shijie1d0ed692013-09-25 14:58:10 +0800911/*
912 * Check if it is a SLC nand.
913 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
914 * We do not distinguish the MLC and TLC now.
915 */
916static inline bool nand_is_slc(struct nand_chip *chip)
917{
Huang Shijie7db906b2013-09-25 14:58:11 +0800918 return chip->bits_per_cell == 1;
Huang Shijie1d0ed692013-09-25 14:58:10 +0800919}
Brian Norris3dad2342014-01-29 14:08:12 -0800920
921/**
922 * Check if the opcode's address should be sent only on the lower 8 bits
923 * @command: opcode to check
924 */
925static inline int nand_opcode_8bits(unsigned int command)
926{
David Mosbergere34fcb02014-03-21 16:05:10 -0600927 switch (command) {
928 case NAND_CMD_READID:
929 case NAND_CMD_PARAM:
930 case NAND_CMD_GET_FEATURES:
931 case NAND_CMD_SET_FEATURES:
932 return 1;
933 default:
934 break;
935 }
936 return 0;
Brian Norris3dad2342014-01-29 14:08:12 -0800937}
938
Huang Shijie7852f892014-02-21 13:39:39 +0800939/* return the supported JEDEC features. */
940static inline int jedec_feature(struct nand_chip *chip)
941{
942 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
943 : 0;
944}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700945#endif /* __LINUX_MTD_NAND_H */