blob: 441a963e7acf976bf68cc4187696f05084ea5c84 [file] [log] [blame]
Jemma Denson5afc9a22015-04-14 09:04:50 -03001/*
2 Conexant cx24120/cx24118 - DVBS/S2 Satellite demod/tuner driver
3
4 Copyright (C) 2008 Patrick Boettcher <pb@linuxtv.org>
5 Copyright (C) 2009 Sergey Tyurin <forum.free-x.de>
6 Updated 2012 by Jannis Achstetter <jannis_achstetter@web.de>
7 Copyright (C) 2015 Jemma Denson <jdenson@gmail.com>
8 April 2015
9 Refactored & simplified driver
10 Updated to work with delivery system supplied by DVBv5
11 Add frequency, fec & pilot to get_frontend
12
13 Cards supported: Technisat Skystar S2
14
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
19
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
24*/
25
26#include <linux/slab.h>
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/init.h>
31#include <linux/firmware.h>
32#include "dvb_frontend.h"
33#include "cx24120.h"
34
35#define CX24120_SEARCH_RANGE_KHZ 5000
36#define CX24120_FIRMWARE "dvb-fe-cx24120-1.20.58.2.fw"
37
38/* cx24120 i2c registers */
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -030039#define CX24120_REG_CMD_START 0x00 /* write cmd_id */
40#define CX24120_REG_CMD_ARGS 0x01 /* write command arguments */
41#define CX24120_REG_CMD_END 0x1f /* write 0x01 for end */
Jemma Denson5afc9a22015-04-14 09:04:50 -030042
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -030043#define CX24120_REG_MAILBOX 0x33
44#define CX24120_REG_FREQ3 0x34 /* frequency */
45#define CX24120_REG_FREQ2 0x35
46#define CX24120_REG_FREQ1 0x36
Jemma Denson5afc9a22015-04-14 09:04:50 -030047
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -030048#define CX24120_REG_FECMODE 0x39 /* FEC status */
49#define CX24120_REG_STATUS 0x3a /* Tuner status */
50#define CX24120_REG_SIGSTR_H 0x3a /* Signal strength high */
51#define CX24120_REG_SIGSTR_L 0x3b /* Signal strength low byte */
52#define CX24120_REG_QUALITY_H 0x40 /* SNR high byte */
53#define CX24120_REG_QUALITY_L 0x41 /* SNR low byte */
Jemma Denson5afc9a22015-04-14 09:04:50 -030054
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -030055#define CX24120_REG_BER_HH 0x47 /* BER high byte of high word */
56#define CX24120_REG_BER_HL 0x48 /* BER low byte of high word */
57#define CX24120_REG_BER_LH 0x49 /* BER high byte of low word */
58#define CX24120_REG_BER_LL 0x4a /* BER low byte of low word */
Jemma Denson5afc9a22015-04-14 09:04:50 -030059
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -030060#define CX24120_REG_UCB_H 0x50 /* UCB high byte */
61#define CX24120_REG_UCB_L 0x51 /* UCB low byte */
Jemma Denson5afc9a22015-04-14 09:04:50 -030062
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -030063#define CX24120_REG_CLKDIV 0xe6
64#define CX24120_REG_RATEDIV 0xf0
Jemma Denson5afc9a22015-04-14 09:04:50 -030065
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -030066#define CX24120_REG_REVISION 0xff /* Chip revision (ro) */
Jemma Denson5afc9a22015-04-14 09:04:50 -030067
Jemma Denson5afc9a22015-04-14 09:04:50 -030068/* Command messages */
69enum command_message_id {
70 CMD_VCO_SET = 0x10, /* cmd.len = 12; */
71 CMD_TUNEREQUEST = 0x11, /* cmd.len = 15; */
72
73 CMD_MPEG_ONOFF = 0x13, /* cmd.len = 4; */
74 CMD_MPEG_INIT = 0x14, /* cmd.len = 7; */
75 CMD_BANDWIDTH = 0x15, /* cmd.len = 12; */
76 CMD_CLOCK_READ = 0x16, /* read clock */
77 CMD_CLOCK_SET = 0x17, /* cmd.len = 10; */
78
79 CMD_DISEQC_MSG1 = 0x20, /* cmd.len = 11; */
80 CMD_DISEQC_MSG2 = 0x21, /* cmd.len = d->msg_len + 6; */
81 CMD_SETVOLTAGE = 0x22, /* cmd.len = 2; */
82 CMD_SETTONE = 0x23, /* cmd.len = 4; */
83 CMD_DISEQC_BURST = 0x24, /* cmd.len not used !!! */
84
85 CMD_READ_SNR = 0x1a, /* Read signal strength */
86 CMD_START_TUNER = 0x1b, /* ??? */
87
88 CMD_FWVERSION = 0x35,
89
90 CMD_TUNER_INIT = 0x3c, /* cmd.len = 0x03; */
91};
92
93#define CX24120_MAX_CMD_LEN 30
94
95/* pilot mask */
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -030096#define CX24120_PILOT_OFF 0x00
97#define CX24120_PILOT_ON 0x40
98#define CX24120_PILOT_AUTO 0x80
Jemma Denson5afc9a22015-04-14 09:04:50 -030099
100/* signal status */
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300101#define CX24120_HAS_SIGNAL 0x01
102#define CX24120_HAS_CARRIER 0x02
103#define CX24120_HAS_VITERBI 0x04
104#define CX24120_HAS_LOCK 0x08
105#define CX24120_HAS_UNK1 0x10
106#define CX24120_HAS_UNK2 0x20
107#define CX24120_STATUS_MASK 0x0f
108#define CX24120_SIGNAL_MASK 0xc0
Jemma Denson5afc9a22015-04-14 09:04:50 -0300109
Patrick Boettcherc5fb0f52015-04-17 06:04:53 -0300110#define info(args...) pr_info("cx24120: " args)
111#define err(args...) pr_err("cx24120: ### ERROR: " args)
Jemma Denson5afc9a22015-04-14 09:04:50 -0300112
113/* The Demod/Tuner can't easily provide these, we cache them */
114struct cx24120_tuning {
115 u32 frequency;
116 u32 symbol_rate;
117 fe_spectral_inversion_t inversion;
118 fe_code_rate_t fec;
119
120 fe_delivery_system_t delsys;
121 fe_modulation_t modulation;
122 fe_pilot_t pilot;
123
124 /* Demod values */
125 u8 fec_val;
126 u8 fec_mask;
127 u8 clkdiv;
128 u8 ratediv;
129 u8 inversion_val;
130 u8 pilot_val;
131};
132
Jemma Denson5afc9a22015-04-14 09:04:50 -0300133/* Private state */
134struct cx24120_state {
135 struct i2c_adapter *i2c;
136 const struct cx24120_config *config;
137 struct dvb_frontend frontend;
138
139 u8 cold_init;
140 u8 mpeg_enabled;
141
142 /* current and next tuning parameters */
143 struct cx24120_tuning dcur;
144 struct cx24120_tuning dnxt;
145};
146
Jemma Denson5afc9a22015-04-14 09:04:50 -0300147/* Command message to firmware */
148struct cx24120_cmd {
149 u8 id;
150 u8 len;
151 u8 arg[CX24120_MAX_CMD_LEN];
152};
153
Jemma Denson5afc9a22015-04-14 09:04:50 -0300154/* Read single register */
155static int cx24120_readreg(struct cx24120_state *state, u8 reg)
156{
157 int ret;
158 u8 buf = 0;
159 struct i2c_msg msg[] = {
160 { .addr = state->config->i2c_addr,
161 .flags = 0,
162 .len = 1,
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300163 .buf = &reg
164 }, {
165 .addr = state->config->i2c_addr,
Jemma Denson5afc9a22015-04-14 09:04:50 -0300166 .flags = I2C_M_RD,
167 .len = 1,
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300168 .buf = &buf
169 }
Jemma Denson5afc9a22015-04-14 09:04:50 -0300170 };
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300171
Jemma Denson5afc9a22015-04-14 09:04:50 -0300172 ret = i2c_transfer(state->i2c, msg, 2);
173 if (ret != 2) {
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300174 err("Read error: reg=0x%02x, ret=%i)\n", reg, ret);
Jemma Denson5afc9a22015-04-14 09:04:50 -0300175 return ret;
176 }
177
178 dev_dbg(&state->i2c->dev, "%s: reg=0x%02x; data=0x%02x\n",
179 __func__, reg, buf);
180
181 return buf;
182}
183
Jemma Denson5afc9a22015-04-14 09:04:50 -0300184/* Write single register */
185static int cx24120_writereg(struct cx24120_state *state, u8 reg, u8 data)
186{
187 u8 buf[] = { reg, data };
188 struct i2c_msg msg = {
189 .addr = state->config->i2c_addr,
190 .flags = 0,
191 .buf = buf,
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300192 .len = 2
193 };
Jemma Denson5afc9a22015-04-14 09:04:50 -0300194 int ret;
195
196 ret = i2c_transfer(state->i2c, &msg, 1);
197 if (ret != 1) {
198 err("Write error: i2c_write error(err == %i, 0x%02x: 0x%02x)\n",
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300199 ret, reg, data);
Jemma Denson5afc9a22015-04-14 09:04:50 -0300200 return ret;
201 }
202
203 dev_dbg(&state->i2c->dev, "%s: reg=0x%02x; data=0x%02x\n",
204 __func__, reg, data);
205
206 return 0;
207}
208
Patrick Boettcherf7a77eb2015-04-28 02:47:42 -0300209/* Write multiple registers in chunks of i2c_wr_max-sized buffers */
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300210static int cx24120_writeregs(struct cx24120_state *state,
211 u8 reg, const u8 *values, u16 len, u8 incr)
Jemma Denson5afc9a22015-04-14 09:04:50 -0300212{
213 int ret;
Patrick Boettcherf7a77eb2015-04-28 02:47:42 -0300214 u16 max = state->config->i2c_wr_max > 0 ?
215 state->config->i2c_wr_max :
216 len;
Jemma Denson5afc9a22015-04-14 09:04:50 -0300217
218 struct i2c_msg msg = {
219 .addr = state->config->i2c_addr,
220 .flags = 0,
Patrick Boettcherf7a77eb2015-04-28 02:47:42 -0300221 };
222
223 msg.buf = kmalloc(max + 1, GFP_KERNEL);
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300224 if (!msg.buf)
Patrick Boettcherf7a77eb2015-04-28 02:47:42 -0300225 return -ENOMEM;
Jemma Denson5afc9a22015-04-14 09:04:50 -0300226
227 while (len) {
Patrick Boettcherf7a77eb2015-04-28 02:47:42 -0300228 msg.buf[0] = reg;
229 msg.len = len > max ? max : len;
230 memcpy(&msg.buf[1], values, msg.len);
Jemma Denson5afc9a22015-04-14 09:04:50 -0300231
Patrick Boettcherf7a77eb2015-04-28 02:47:42 -0300232 len -= msg.len; /* data length revers counter */
233 values += msg.len; /* incr data pointer */
Jemma Denson5afc9a22015-04-14 09:04:50 -0300234
235 if (incr)
236 reg += msg.len;
Patrick Boettcherf7a77eb2015-04-28 02:47:42 -0300237 msg.len++; /* don't forget the addr byte */
Jemma Denson5afc9a22015-04-14 09:04:50 -0300238
239 ret = i2c_transfer(state->i2c, &msg, 1);
240 if (ret != 1) {
241 err("i2c_write error(err == %i, 0x%02x)\n", ret, reg);
Patrick Boettcherf7a77eb2015-04-28 02:47:42 -0300242 goto out;
Jemma Denson5afc9a22015-04-14 09:04:50 -0300243 }
244
245 dev_dbg(&state->i2c->dev,
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300246 "%s: reg=0x%02x; data=%*ph\n",
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300247 __func__, reg, msg.len, msg.buf + 1);
Jemma Denson5afc9a22015-04-14 09:04:50 -0300248 }
249
Patrick Boettcherf7a77eb2015-04-28 02:47:42 -0300250 ret = 0;
251
252out:
253 kfree(msg.buf);
254 return ret;
Jemma Denson5afc9a22015-04-14 09:04:50 -0300255}
256
Jemma Denson5afc9a22015-04-14 09:04:50 -0300257static struct dvb_frontend_ops cx24120_ops;
258
259struct dvb_frontend *cx24120_attach(const struct cx24120_config *config,
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300260 struct i2c_adapter *i2c)
Jemma Denson5afc9a22015-04-14 09:04:50 -0300261{
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300262 struct cx24120_state *state;
Jemma Denson5afc9a22015-04-14 09:04:50 -0300263 int demod_rev;
264
265 info("Conexant cx24120/cx24118 - DVBS/S2 Satellite demod/tuner\n");
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300266 state = kzalloc(sizeof(*state), GFP_KERNEL);
267 if (!state) {
Jemma Denson5afc9a22015-04-14 09:04:50 -0300268 err("Unable to allocate memory for cx24120_state\n");
269 goto error;
270 }
271
272 /* setup the state */
273 state->config = config;
274 state->i2c = i2c;
275
276 /* check if the demod is present and has proper type */
277 demod_rev = cx24120_readreg(state, CX24120_REG_REVISION);
278 switch (demod_rev) {
279 case 0x07:
280 info("Demod cx24120 rev. 0x07 detected.\n");
281 break;
282 case 0x05:
283 info("Demod cx24120 rev. 0x05 detected.\n");
284 break;
285 default:
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300286 err("Unsupported demod revision: 0x%x detected.\n", demod_rev);
Jemma Denson5afc9a22015-04-14 09:04:50 -0300287 goto error;
288 }
289
290 /* create dvb_frontend */
291 state->cold_init = 0;
292 memcpy(&state->frontend.ops, &cx24120_ops,
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300293 sizeof(struct dvb_frontend_ops));
Jemma Denson5afc9a22015-04-14 09:04:50 -0300294 state->frontend.demodulator_priv = state;
295
296 info("Conexant cx24120/cx24118 attached.\n");
297 return &state->frontend;
298
299error:
300 kfree(state);
301 return NULL;
302}
303EXPORT_SYMBOL(cx24120_attach);
304
305static int cx24120_test_rom(struct cx24120_state *state)
306{
307 int err, ret;
308
309 err = cx24120_readreg(state, 0xfd);
310 if (err & 4) {
311 ret = cx24120_readreg(state, 0xdf) & 0xfe;
312 err = cx24120_writereg(state, 0xdf, ret);
313 }
314 return err;
315}
316
Jemma Denson5afc9a22015-04-14 09:04:50 -0300317static int cx24120_read_snr(struct dvb_frontend *fe, u16 *snr)
318{
319 struct cx24120_state *state = fe->demodulator_priv;
320
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300321 *snr = (cx24120_readreg(state, CX24120_REG_QUALITY_H) << 8) |
Jemma Denson5afc9a22015-04-14 09:04:50 -0300322 (cx24120_readreg(state, CX24120_REG_QUALITY_L));
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300323 dev_dbg(&state->i2c->dev, "%s: read SNR index = %d\n", __func__, *snr);
Jemma Denson5afc9a22015-04-14 09:04:50 -0300324
325 return 0;
326}
327
Jemma Denson5afc9a22015-04-14 09:04:50 -0300328static int cx24120_read_ber(struct dvb_frontend *fe, u32 *ber)
329{
330 struct cx24120_state *state = fe->demodulator_priv;
331
332 *ber = (cx24120_readreg(state, CX24120_REG_BER_HH) << 24) |
333 (cx24120_readreg(state, CX24120_REG_BER_HL) << 16) |
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300334 (cx24120_readreg(state, CX24120_REG_BER_LH) << 8) |
Jemma Denson5afc9a22015-04-14 09:04:50 -0300335 cx24120_readreg(state, CX24120_REG_BER_LL);
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300336 dev_dbg(&state->i2c->dev, "%s: read BER index = %d\n", __func__, *ber);
Jemma Denson5afc9a22015-04-14 09:04:50 -0300337
338 return 0;
339}
340
341static int cx24120_msg_mpeg_output_global_config(struct cx24120_state *state,
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300342 u8 flag);
Jemma Denson5afc9a22015-04-14 09:04:50 -0300343
344/* Check if we're running a command that needs to disable mpeg out */
345static void cx24120_check_cmd(struct cx24120_state *state, u8 id)
346{
347 switch (id) {
348 case CMD_TUNEREQUEST:
349 case CMD_CLOCK_READ:
350 case CMD_DISEQC_MSG1:
351 case CMD_DISEQC_MSG2:
352 case CMD_SETVOLTAGE:
353 case CMD_SETTONE:
354 cx24120_msg_mpeg_output_global_config(state, 0);
355 /* Old driver would do a msleep(100) here */
356 default:
357 return;
358 }
359}
360
Jemma Denson5afc9a22015-04-14 09:04:50 -0300361/* Send a message to the firmware */
362static int cx24120_message_send(struct cx24120_state *state,
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300363 struct cx24120_cmd *cmd)
Jemma Denson5afc9a22015-04-14 09:04:50 -0300364{
365 int ret, ficus;
366
367 if (state->mpeg_enabled) {
368 /* Disable mpeg out on certain commands */
369 cx24120_check_cmd(state, cmd->id);
370 }
371
372 ret = cx24120_writereg(state, CX24120_REG_CMD_START, cmd->id);
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300373 ret = cx24120_writeregs(state, CX24120_REG_CMD_ARGS, &cmd->arg[0],
Jemma Denson5afc9a22015-04-14 09:04:50 -0300374 cmd->len, 1);
375 ret = cx24120_writereg(state, CX24120_REG_CMD_END, 0x01);
376
377 ficus = 1000;
378 while (cx24120_readreg(state, CX24120_REG_CMD_END)) {
379 msleep(20);
380 ficus -= 20;
381 if (ficus == 0) {
382 err("Error sending message to firmware\n");
383 return -EREMOTEIO;
384 }
385 }
386 dev_dbg(&state->i2c->dev, "%s: Successfully send message 0x%02x\n",
387 __func__, cmd->id);
388
389 return 0;
390}
391
392/* Send a message and fill arg[] with the results */
393static int cx24120_message_sendrcv(struct cx24120_state *state,
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300394 struct cx24120_cmd *cmd, u8 numreg)
Jemma Denson5afc9a22015-04-14 09:04:50 -0300395{
396 int ret, i;
397
398 if (numreg > CX24120_MAX_CMD_LEN) {
399 err("Too many registers to read. cmd->reg = %d", numreg);
400 return -EREMOTEIO;
401 }
402
403 ret = cx24120_message_send(state, cmd);
404 if (ret != 0)
405 return ret;
406
407 if (!numreg)
408 return 0;
409
410 /* Read numreg registers starting from register cmd->len */
411 for (i = 0; i < numreg; i++)
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300412 cmd->arg[i] = cx24120_readreg(state, (cmd->len + i + 1));
Jemma Denson5afc9a22015-04-14 09:04:50 -0300413
414 return 0;
415}
416
Jemma Denson5afc9a22015-04-14 09:04:50 -0300417static int cx24120_read_signal_strength(struct dvb_frontend *fe,
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300418 u16 *signal_strength)
Jemma Denson5afc9a22015-04-14 09:04:50 -0300419{
420 struct cx24120_state *state = fe->demodulator_priv;
421 struct cx24120_cmd cmd;
422 int ret, sigstr_h, sigstr_l;
423
424 cmd.id = CMD_READ_SNR;
425 cmd.len = 1;
426 cmd.arg[0] = 0x00;
427
428 ret = cx24120_message_send(state, &cmd);
429 if (ret != 0) {
430 err("error reading signal strength\n");
431 return -EREMOTEIO;
432 }
433
434 /* raw */
435 sigstr_h = (cx24120_readreg(state, CX24120_REG_SIGSTR_H) >> 6) << 8;
436 sigstr_l = cx24120_readreg(state, CX24120_REG_SIGSTR_L);
437 dev_dbg(&state->i2c->dev, "%s: Signal strength from firmware= 0x%x\n",
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300438 __func__, (sigstr_h | sigstr_l));
Jemma Denson5afc9a22015-04-14 09:04:50 -0300439
440 /* cooked */
441 *signal_strength = ((sigstr_h | sigstr_l) << 5) & 0x0000ffff;
442 dev_dbg(&state->i2c->dev, "%s: Signal strength= 0x%x\n",
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300443 __func__, *signal_strength);
Jemma Denson5afc9a22015-04-14 09:04:50 -0300444
445 return 0;
446}
447
Jemma Denson5afc9a22015-04-14 09:04:50 -0300448static int cx24120_msg_mpeg_output_global_config(struct cx24120_state *state,
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300449 u8 enable)
Jemma Denson5afc9a22015-04-14 09:04:50 -0300450{
451 struct cx24120_cmd cmd;
452 int ret;
453
454 cmd.id = CMD_MPEG_ONOFF;
455 cmd.len = 4;
456 cmd.arg[0] = 0x01;
457 cmd.arg[1] = 0x00;
458 cmd.arg[2] = enable ? 0 : (u8)(-1);
459 cmd.arg[3] = 0x01;
460
461 ret = cx24120_message_send(state, &cmd);
462 if (ret != 0) {
463 dev_dbg(&state->i2c->dev,
464 "%s: Failed to set MPEG output to %s\n",
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300465 __func__, enable ? "enabled" : "disabled");
Jemma Denson5afc9a22015-04-14 09:04:50 -0300466 return ret;
467 }
468
469 state->mpeg_enabled = enable;
470 dev_dbg(&state->i2c->dev, "%s: MPEG output %s\n",
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300471 __func__, enable ? "enabled" : "disabled");
Jemma Denson5afc9a22015-04-14 09:04:50 -0300472
473 return 0;
474}
475
Jemma Denson5afc9a22015-04-14 09:04:50 -0300476static int cx24120_msg_mpeg_output_config(struct cx24120_state *state, u8 seq)
477{
478 struct cx24120_cmd cmd;
479 struct cx24120_initial_mpeg_config i =
480 state->config->initial_mpeg_config;
481
482 cmd.id = CMD_MPEG_INIT;
483 cmd.len = 7;
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300484 cmd.arg[0] = seq; /* sequental number - can be 0,1,2 */
Jemma Denson5afc9a22015-04-14 09:04:50 -0300485 cmd.arg[1] = ((i.x1 & 0x01) << 1) | ((i.x1 >> 1) & 0x01);
486 cmd.arg[2] = 0x05;
487 cmd.arg[3] = 0x02;
488 cmd.arg[4] = ((i.x2 >> 1) & 0x01);
489 cmd.arg[5] = (i.x2 & 0xf0) | (i.x3 & 0x0f);
490 cmd.arg[6] = 0x10;
491
492 return cx24120_message_send(state, &cmd);
493}
494
Jemma Denson5afc9a22015-04-14 09:04:50 -0300495static int cx24120_diseqc_send_burst(struct dvb_frontend *fe,
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300496 fe_sec_mini_cmd_t burst)
Jemma Denson5afc9a22015-04-14 09:04:50 -0300497{
498 struct cx24120_state *state = fe->demodulator_priv;
499 struct cx24120_cmd cmd;
500
501 /* Yes, cmd.len is set to zero. The old driver
502 * didn't specify any len, but also had a
503 * memset 0 before every use of the cmd struct
504 * which would have set it to zero.
505 * This quite probably needs looking into.
506 */
507 cmd.id = CMD_DISEQC_BURST;
508 cmd.len = 0;
509 cmd.arg[0] = 0x00;
510 if (burst)
511 cmd.arg[1] = 0x01;
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300512
Jemma Denson5afc9a22015-04-14 09:04:50 -0300513 dev_dbg(&state->i2c->dev, "%s: burst sent.\n", __func__);
514
515 return cx24120_message_send(state, &cmd);
516}
517
Jemma Denson5afc9a22015-04-14 09:04:50 -0300518static int cx24120_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
519{
520 struct cx24120_state *state = fe->demodulator_priv;
521 struct cx24120_cmd cmd;
522
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300523 dev_dbg(&state->i2c->dev, "%s(%d)\n", __func__, tone);
Jemma Denson5afc9a22015-04-14 09:04:50 -0300524
525 if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
526 err("Invalid tone=%d\n", tone);
527 return -EINVAL;
528 }
529
530 cmd.id = CMD_SETTONE;
531 cmd.len = 4;
532 cmd.arg[0] = 0x00;
533 cmd.arg[1] = 0x00;
534 cmd.arg[2] = 0x00;
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300535 cmd.arg[3] = (tone == SEC_TONE_ON) ? 0x01 : 0x00;
Jemma Denson5afc9a22015-04-14 09:04:50 -0300536
537 return cx24120_message_send(state, &cmd);
538}
539
Jemma Denson5afc9a22015-04-14 09:04:50 -0300540static int cx24120_set_voltage(struct dvb_frontend *fe,
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300541 fe_sec_voltage_t voltage)
Jemma Denson5afc9a22015-04-14 09:04:50 -0300542{
543 struct cx24120_state *state = fe->demodulator_priv;
544 struct cx24120_cmd cmd;
545
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300546 dev_dbg(&state->i2c->dev, "%s(%d)\n", __func__, voltage);
Jemma Denson5afc9a22015-04-14 09:04:50 -0300547
548 cmd.id = CMD_SETVOLTAGE;
549 cmd.len = 2;
550 cmd.arg[0] = 0x00;
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300551 cmd.arg[1] = (voltage == SEC_VOLTAGE_18) ? 0x01 : 0x00;
Jemma Denson5afc9a22015-04-14 09:04:50 -0300552
553 return cx24120_message_send(state, &cmd);
554}
555
Jemma Denson5afc9a22015-04-14 09:04:50 -0300556static int cx24120_send_diseqc_msg(struct dvb_frontend *fe,
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300557 struct dvb_diseqc_master_cmd *d)
Jemma Denson5afc9a22015-04-14 09:04:50 -0300558{
559 struct cx24120_state *state = fe->demodulator_priv;
560 struct cx24120_cmd cmd;
561 int back_count;
562
563 dev_dbg(&state->i2c->dev, "%s()\n", __func__);
564
565 cmd.id = CMD_DISEQC_MSG1;
566 cmd.len = 11;
567 cmd.arg[0] = 0x00;
568 cmd.arg[1] = 0x00;
569 cmd.arg[2] = 0x03;
570 cmd.arg[3] = 0x16;
571 cmd.arg[4] = 0x28;
572 cmd.arg[5] = 0x01;
573 cmd.arg[6] = 0x01;
574 cmd.arg[7] = 0x14;
575 cmd.arg[8] = 0x19;
576 cmd.arg[9] = 0x14;
577 cmd.arg[10] = 0x1e;
578
579 if (cx24120_message_send(state, &cmd)) {
580 err("send 1st message(0x%x) failed\n", cmd.id);
581 return -EREMOTEIO;
582 }
583
584 cmd.id = CMD_DISEQC_MSG2;
585 cmd.len = d->msg_len + 6;
586 cmd.arg[0] = 0x00;
587 cmd.arg[1] = 0x01;
588 cmd.arg[2] = 0x02;
589 cmd.arg[3] = 0x00;
590 cmd.arg[4] = 0x00;
591 cmd.arg[5] = d->msg_len;
592
593 memcpy(&cmd.arg[6], &d->msg, d->msg_len);
594
595 if (cx24120_message_send(state, &cmd)) {
596 err("send 2nd message(0x%x) failed\n", cmd.id);
597 return -EREMOTEIO;
598 }
599
600 back_count = 500;
601 do {
602 if (!(cx24120_readreg(state, 0x93) & 0x01)) {
603 dev_dbg(&state->i2c->dev,
604 "%s: diseqc sequence sent success\n",
605 __func__);
606 return 0;
607 }
608 msleep(20);
609 back_count -= 20;
610 } while (back_count);
611
612 err("Too long waiting for diseqc.\n");
613 return -ETIMEDOUT;
614}
615
Jemma Denson5afc9a22015-04-14 09:04:50 -0300616/* Read current tuning status */
617static int cx24120_read_status(struct dvb_frontend *fe, fe_status_t *status)
618{
619 struct cx24120_state *state = fe->demodulator_priv;
620 int lock;
621
622 lock = cx24120_readreg(state, CX24120_REG_STATUS);
623
624 dev_dbg(&state->i2c->dev, "%s() status = 0x%02x\n",
625 __func__, lock);
626
627 *status = 0;
628
629 if (lock & CX24120_HAS_SIGNAL)
630 *status = FE_HAS_SIGNAL;
631 if (lock & CX24120_HAS_CARRIER)
632 *status |= FE_HAS_CARRIER;
633 if (lock & CX24120_HAS_VITERBI)
634 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
635 if (lock & CX24120_HAS_LOCK)
636 *status |= FE_HAS_LOCK;
637
638 /* TODO: is FE_HAS_SYNC in the right place?
639 * Other cx241xx drivers have this slightly
640 * different */
641
642 return 0;
643}
644
Jemma Denson5afc9a22015-04-14 09:04:50 -0300645/* FEC & modulation lookup table
646 * Used for decoding the REG_FECMODE register
647 * once tuned in.
648 */
649static struct cx24120_modfec {
650 fe_delivery_system_t delsys;
651 fe_modulation_t mod;
652 fe_code_rate_t fec;
653 u8 val;
654} modfec_lookup_table[] = {
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300655 /*delsys mod fec val */
656 { SYS_DVBS, QPSK, FEC_1_2, 0x01 },
657 { SYS_DVBS, QPSK, FEC_2_3, 0x02 },
658 { SYS_DVBS, QPSK, FEC_3_4, 0x03 },
659 { SYS_DVBS, QPSK, FEC_4_5, 0x04 },
660 { SYS_DVBS, QPSK, FEC_5_6, 0x05 },
661 { SYS_DVBS, QPSK, FEC_6_7, 0x06 },
662 { SYS_DVBS, QPSK, FEC_7_8, 0x07 },
Jemma Denson5afc9a22015-04-14 09:04:50 -0300663
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300664 { SYS_DVBS2, QPSK, FEC_1_2, 0x04 },
665 { SYS_DVBS2, QPSK, FEC_3_5, 0x05 },
666 { SYS_DVBS2, QPSK, FEC_2_3, 0x06 },
667 { SYS_DVBS2, QPSK, FEC_3_4, 0x07 },
668 { SYS_DVBS2, QPSK, FEC_4_5, 0x08 },
669 { SYS_DVBS2, QPSK, FEC_5_6, 0x09 },
670 { SYS_DVBS2, QPSK, FEC_8_9, 0x0a },
671 { SYS_DVBS2, QPSK, FEC_9_10, 0x0b },
Jemma Denson5afc9a22015-04-14 09:04:50 -0300672
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300673 { SYS_DVBS2, PSK_8, FEC_3_5, 0x0c },
674 { SYS_DVBS2, PSK_8, FEC_2_3, 0x0d },
675 { SYS_DVBS2, PSK_8, FEC_3_4, 0x0e },
676 { SYS_DVBS2, PSK_8, FEC_5_6, 0x0f },
677 { SYS_DVBS2, PSK_8, FEC_8_9, 0x10 },
678 { SYS_DVBS2, PSK_8, FEC_9_10, 0x11 },
Jemma Denson5afc9a22015-04-14 09:04:50 -0300679};
680
Jemma Denson5afc9a22015-04-14 09:04:50 -0300681/* Retrieve current fec, modulation & pilot values */
682static int cx24120_get_fec(struct dvb_frontend *fe)
683{
684 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
685 struct cx24120_state *state = fe->demodulator_priv;
686 int idx;
687 int ret;
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300688 int fec;
Jemma Denson5afc9a22015-04-14 09:04:50 -0300689
690 dev_dbg(&state->i2c->dev, "%s()\n", __func__);
691
692 ret = cx24120_readreg(state, CX24120_REG_FECMODE);
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300693 fec = ret & 0x3f; /* Lower 6 bits */
Jemma Denson5afc9a22015-04-14 09:04:50 -0300694
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300695 dev_dbg(&state->i2c->dev, "%s: Get FEC: %d\n", __func__, fec);
Jemma Denson5afc9a22015-04-14 09:04:50 -0300696
697 for (idx = 0; idx < ARRAY_SIZE(modfec_lookup_table); idx++) {
698 if (modfec_lookup_table[idx].delsys != state->dcur.delsys)
699 continue;
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300700 if (modfec_lookup_table[idx].val != fec)
Jemma Denson5afc9a22015-04-14 09:04:50 -0300701 continue;
702
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300703 break; /* found */
Jemma Denson5afc9a22015-04-14 09:04:50 -0300704 }
705
706 if (idx >= ARRAY_SIZE(modfec_lookup_table)) {
707 dev_dbg(&state->i2c->dev, "%s: Couldn't find fec!\n",
708 __func__);
709 return -EINVAL;
710 }
711
712 /* save values back to cache */
713 c->modulation = modfec_lookup_table[idx].mod;
714 c->fec_inner = modfec_lookup_table[idx].fec;
715 c->pilot = (ret & 0x80) ? PILOT_ON : PILOT_OFF;
716
717 dev_dbg(&state->i2c->dev,
718 "%s: mod(%d), fec(%d), pilot(%d)\n",
719 __func__,
720 c->modulation, c->fec_inner, c->pilot);
721
722 return 0;
723}
724
Jemma Denson5afc9a22015-04-14 09:04:50 -0300725/* Clock ratios lookup table
726 *
727 * Values obtained from much larger table in old driver
728 * which had numerous entries which would never match.
729 *
730 * There's probably some way of calculating these but I
731 * can't determine the pattern
732*/
733static struct cx24120_clock_ratios_table {
734 fe_delivery_system_t delsys;
735 fe_pilot_t pilot;
736 fe_modulation_t mod;
737 fe_code_rate_t fec;
738 u32 m_rat;
739 u32 n_rat;
740 u32 rate;
741} clock_ratios_table[] = {
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300742 /*delsys pilot mod fec m_rat n_rat rate */
743 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_1_2, 273088, 254505, 274 },
744 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_3_5, 17272, 13395, 330 },
745 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_2_3, 24344, 16967, 367 },
746 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_3_4, 410788, 254505, 413 },
747 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_4_5, 438328, 254505, 440 },
748 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_5_6, 30464, 16967, 459 },
749 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_8_9, 487832, 254505, 490 },
750 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_9_10, 493952, 254505, 496 },
751 { SYS_DVBS2, PILOT_OFF, PSK_8, FEC_3_5, 328168, 169905, 494 },
752 { SYS_DVBS2, PILOT_OFF, PSK_8, FEC_2_3, 24344, 11327, 550 },
753 { SYS_DVBS2, PILOT_OFF, PSK_8, FEC_3_4, 410788, 169905, 618 },
754 { SYS_DVBS2, PILOT_OFF, PSK_8, FEC_5_6, 30464, 11327, 688 },
755 { SYS_DVBS2, PILOT_OFF, PSK_8, FEC_8_9, 487832, 169905, 735 },
756 { SYS_DVBS2, PILOT_OFF, PSK_8, FEC_9_10, 493952, 169905, 744 },
757 { SYS_DVBS2, PILOT_ON, QPSK, FEC_1_2, 273088, 260709, 268 },
758 { SYS_DVBS2, PILOT_ON, QPSK, FEC_3_5, 328168, 260709, 322 },
759 { SYS_DVBS2, PILOT_ON, QPSK, FEC_2_3, 121720, 86903, 358 },
760 { SYS_DVBS2, PILOT_ON, QPSK, FEC_3_4, 410788, 260709, 403 },
761 { SYS_DVBS2, PILOT_ON, QPSK, FEC_4_5, 438328, 260709, 430 },
762 { SYS_DVBS2, PILOT_ON, QPSK, FEC_5_6, 152320, 86903, 448 },
763 { SYS_DVBS2, PILOT_ON, QPSK, FEC_8_9, 487832, 260709, 479 },
764 { SYS_DVBS2, PILOT_ON, QPSK, FEC_9_10, 493952, 260709, 485 },
765 { SYS_DVBS2, PILOT_ON, PSK_8, FEC_3_5, 328168, 173853, 483 },
766 { SYS_DVBS2, PILOT_ON, PSK_8, FEC_2_3, 121720, 57951, 537 },
767 { SYS_DVBS2, PILOT_ON, PSK_8, FEC_3_4, 410788, 173853, 604 },
768 { SYS_DVBS2, PILOT_ON, PSK_8, FEC_5_6, 152320, 57951, 672 },
769 { SYS_DVBS2, PILOT_ON, PSK_8, FEC_8_9, 487832, 173853, 718 },
770 { SYS_DVBS2, PILOT_ON, PSK_8, FEC_9_10, 493952, 173853, 727 },
771 { SYS_DVBS, PILOT_OFF, QPSK, FEC_1_2, 152592, 152592, 256 },
772 { SYS_DVBS, PILOT_OFF, QPSK, FEC_2_3, 305184, 228888, 341 },
773 { SYS_DVBS, PILOT_OFF, QPSK, FEC_3_4, 457776, 305184, 384 },
774 { SYS_DVBS, PILOT_OFF, QPSK, FEC_5_6, 762960, 457776, 427 },
775 { SYS_DVBS, PILOT_OFF, QPSK, FEC_7_8, 1068144, 610368, 448 },
Jemma Denson5afc9a22015-04-14 09:04:50 -0300776};
777
Jemma Denson5afc9a22015-04-14 09:04:50 -0300778/* Set clock ratio from lookup table */
779static void cx24120_set_clock_ratios(struct dvb_frontend *fe)
780{
781 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
782 struct cx24120_state *state = fe->demodulator_priv;
783 struct cx24120_cmd cmd;
784 int ret, idx;
785
786 /* Find fec, modulation, pilot */
787 ret = cx24120_get_fec(fe);
788 if (ret != 0)
789 return;
790
791 /* Find the clock ratios in the lookup table */
792 for (idx = 0; idx < ARRAY_SIZE(clock_ratios_table); idx++) {
793 if (clock_ratios_table[idx].delsys != state->dcur.delsys)
794 continue;
795 if (clock_ratios_table[idx].mod != c->modulation)
796 continue;
797 if (clock_ratios_table[idx].fec != c->fec_inner)
798 continue;
799 if (clock_ratios_table[idx].pilot != c->pilot)
800 continue;
801
802 break; /* found */
803 }
804
805 if (idx >= ARRAY_SIZE(clock_ratios_table)) {
806 info("Clock ratio not found - data reception in danger\n");
807 return;
808 }
809
Jemma Denson5afc9a22015-04-14 09:04:50 -0300810 /* Read current values? */
811 cmd.id = CMD_CLOCK_READ;
812 cmd.len = 1;
813 cmd.arg[0] = 0x00;
814 ret = cx24120_message_sendrcv(state, &cmd, 6);
815 if (ret != 0)
816 return;
817 /* in cmd[0]-[5] - result */
818
819 dev_dbg(&state->i2c->dev,
820 "%s: m=%d, n=%d; idx: %d m=%d, n=%d, rate=%d\n",
821 __func__,
822 cmd.arg[2] | (cmd.arg[1] << 8) | (cmd.arg[0] << 16),
823 cmd.arg[5] | (cmd.arg[4] << 8) | (cmd.arg[3] << 16),
824 idx,
825 clock_ratios_table[idx].m_rat,
826 clock_ratios_table[idx].n_rat,
827 clock_ratios_table[idx].rate);
828
Jemma Denson5afc9a22015-04-14 09:04:50 -0300829 /* Set the clock */
830 cmd.id = CMD_CLOCK_SET;
831 cmd.len = 10;
832 cmd.arg[0] = 0;
833 cmd.arg[1] = 0x10;
834 cmd.arg[2] = (clock_ratios_table[idx].m_rat >> 16) & 0xff;
835 cmd.arg[3] = (clock_ratios_table[idx].m_rat >> 8) & 0xff;
836 cmd.arg[4] = (clock_ratios_table[idx].m_rat >> 0) & 0xff;
837 cmd.arg[5] = (clock_ratios_table[idx].n_rat >> 16) & 0xff;
838 cmd.arg[6] = (clock_ratios_table[idx].n_rat >> 8) & 0xff;
839 cmd.arg[7] = (clock_ratios_table[idx].n_rat >> 0) & 0xff;
840 cmd.arg[8] = (clock_ratios_table[idx].rate >> 8) & 0xff;
841 cmd.arg[9] = (clock_ratios_table[idx].rate >> 0) & 0xff;
842
843 cx24120_message_send(state, &cmd);
Jemma Denson5afc9a22015-04-14 09:04:50 -0300844}
845
Jemma Denson5afc9a22015-04-14 09:04:50 -0300846/* Set inversion value */
847static int cx24120_set_inversion(struct cx24120_state *state,
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300848 fe_spectral_inversion_t inversion)
Jemma Denson5afc9a22015-04-14 09:04:50 -0300849{
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300850 dev_dbg(&state->i2c->dev, "%s(%d)\n", __func__, inversion);
Jemma Denson5afc9a22015-04-14 09:04:50 -0300851
852 switch (inversion) {
853 case INVERSION_OFF:
854 state->dnxt.inversion_val = 0x00;
855 break;
856 case INVERSION_ON:
857 state->dnxt.inversion_val = 0x04;
858 break;
859 case INVERSION_AUTO:
860 state->dnxt.inversion_val = 0x0c;
861 break;
862 default:
863 return -EINVAL;
864 }
865
866 state->dnxt.inversion = inversion;
867
868 return 0;
869}
870
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300871/*
872 * FEC lookup table for tuning Some DVB-S2 val's have been found by
873 * trial and error. Sofar it seems to match up with the contents of
874 * the REG_FECMODE after tuning The rest will probably be the same but
875 * would need testing. Anything not in the table will run with
876 * FEC_AUTO and take a while longer to tune in ( c.500ms instead of
877 * 30ms )
Jemma Denson5afc9a22015-04-14 09:04:50 -0300878 */
879static struct cx24120_modfec_table {
880 fe_delivery_system_t delsys;
881 fe_modulation_t mod;
882 fe_code_rate_t fec;
883 u8 val;
884} modfec_table[] = {
885/*delsys mod fec val */
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300886 { SYS_DVBS, QPSK, FEC_1_2, 0x2e },
887 { SYS_DVBS, QPSK, FEC_2_3, 0x2f },
888 { SYS_DVBS, QPSK, FEC_3_4, 0x30 },
889 { SYS_DVBS, QPSK, FEC_5_6, 0x31 },
890 { SYS_DVBS, QPSK, FEC_6_7, 0x32 },
891 { SYS_DVBS, QPSK, FEC_7_8, 0x33 },
Jemma Denson5afc9a22015-04-14 09:04:50 -0300892
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300893 { SYS_DVBS2, QPSK, FEC_3_4, 0x07 },
Jemma Denson5afc9a22015-04-14 09:04:50 -0300894
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300895 { SYS_DVBS2, PSK_8, FEC_2_3, 0x0d },
896 { SYS_DVBS2, PSK_8, FEC_3_4, 0x0e },
Jemma Denson5afc9a22015-04-14 09:04:50 -0300897};
898
899/* Set fec_val & fec_mask values from delsys, modulation & fec */
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300900static int cx24120_set_fec(struct cx24120_state *state, fe_modulation_t mod,
901 fe_code_rate_t fec)
Jemma Denson5afc9a22015-04-14 09:04:50 -0300902{
903 int idx;
904
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300905 dev_dbg(&state->i2c->dev, "%s(0x%02x,0x%02x)\n", __func__, mod, fec);
Jemma Denson5afc9a22015-04-14 09:04:50 -0300906
907 state->dnxt.fec = fec;
908
909 /* Lookup fec_val from modfec table */
910 for (idx = 0; idx < ARRAY_SIZE(modfec_table); idx++) {
911 if (modfec_table[idx].delsys != state->dnxt.delsys)
912 continue;
913 if (modfec_table[idx].mod != mod)
914 continue;
915 if (modfec_table[idx].fec != fec)
916 continue;
917
918 /* found */
919 state->dnxt.fec_mask = 0x00;
920 state->dnxt.fec_val = modfec_table[idx].val;
921 return 0;
922 }
923
Jemma Denson5afc9a22015-04-14 09:04:50 -0300924 if (state->dnxt.delsys == SYS_DVBS2) {
925 /* DVBS2 auto is 0x00/0x00 */
926 state->dnxt.fec_mask = 0x00;
927 state->dnxt.fec_val = 0x00;
928 } else {
929 /* Set DVB-S to auto */
930 state->dnxt.fec_val = 0x2e;
931 state->dnxt.fec_mask = 0xac;
932 }
933
934 return 0;
935}
936
Jemma Denson5afc9a22015-04-14 09:04:50 -0300937/* Set pilot */
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -0300938static int cx24120_set_pilot(struct cx24120_state *state, fe_pilot_t pilot)
939{
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300940 dev_dbg(&state->i2c->dev, "%s(%d)\n", __func__, pilot);
Jemma Denson5afc9a22015-04-14 09:04:50 -0300941
942 /* Pilot only valid in DVBS2 */
943 if (state->dnxt.delsys != SYS_DVBS2) {
944 state->dnxt.pilot_val = CX24120_PILOT_OFF;
945 return 0;
946 }
947
Jemma Denson5afc9a22015-04-14 09:04:50 -0300948 switch (pilot) {
949 case PILOT_OFF:
950 state->dnxt.pilot_val = CX24120_PILOT_OFF;
951 break;
952 case PILOT_ON:
953 state->dnxt.pilot_val = CX24120_PILOT_ON;
954 break;
955 case PILOT_AUTO:
956 default:
957 state->dnxt.pilot_val = CX24120_PILOT_AUTO;
958 }
959
960 return 0;
961}
962
963/* Set symbol rate */
964static int cx24120_set_symbolrate(struct cx24120_state *state, u32 rate)
965{
966 dev_dbg(&state->i2c->dev, "%s(%d)\n",
967 __func__, rate);
968
969 state->dnxt.symbol_rate = rate;
970
971 /* Check symbol rate */
972 if (rate > 31000000) {
973 state->dnxt.clkdiv = (-(rate < 31000001) & 3) + 2;
974 state->dnxt.ratediv = (-(rate < 31000001) & 6) + 4;
975 } else {
976 state->dnxt.clkdiv = 3;
977 state->dnxt.ratediv = 6;
978 }
979
980 return 0;
981}
982
Jemma Denson5afc9a22015-04-14 09:04:50 -0300983/* Overwrite the current tuning params, we are about to tune */
984static void cx24120_clone_params(struct dvb_frontend *fe)
985{
986 struct cx24120_state *state = fe->demodulator_priv;
987
988 state->dcur = state->dnxt;
989}
990
Jemma Denson5afc9a22015-04-14 09:04:50 -0300991/* Table of time to tune for different symrates */
992static struct cx24120_symrate_delay {
993 fe_delivery_system_t delsys;
994 u32 symrate; /* Check for >= this symrate */
995 u32 delay; /* Timeout in ms */
996} symrates_delay_table[] = {
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -0300997 { SYS_DVBS, 10000000, 400 },
998 { SYS_DVBS, 8000000, 2000 },
999 { SYS_DVBS, 6000000, 5000 },
1000 { SYS_DVBS, 3000000, 10000 },
1001 { SYS_DVBS, 0, 15000 },
1002 { SYS_DVBS2, 10000000, 600 }, /* DVBS2 needs a little longer */
1003 { SYS_DVBS2, 8000000, 2000 }, /* (so these might need bumping too) */
1004 { SYS_DVBS2, 6000000, 5000 },
1005 { SYS_DVBS2, 3000000, 10000 },
1006 { SYS_DVBS2, 0, 15000 },
Jemma Denson5afc9a22015-04-14 09:04:50 -03001007};
1008
Jemma Denson5afc9a22015-04-14 09:04:50 -03001009static int cx24120_set_frontend(struct dvb_frontend *fe)
1010{
1011 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1012 struct cx24120_state *state = fe->demodulator_priv;
1013 struct cx24120_cmd cmd;
1014 int ret;
1015 int delay_cnt, sd_idx = 0;
1016 fe_status_t status;
1017
1018 switch (c->delivery_system) {
1019 case SYS_DVBS2:
1020 dev_dbg(&state->i2c->dev, "%s() DVB-S2\n",
1021 __func__);
1022 break;
1023 case SYS_DVBS:
1024 dev_dbg(&state->i2c->dev, "%s() DVB-S\n",
1025 __func__);
1026 break;
1027 default:
1028 dev_dbg(&state->i2c->dev,
1029 "%s() Delivery system(%d) not supported\n",
1030 __func__, c->delivery_system);
1031 ret = -EINVAL;
1032 break;
1033 }
1034
Jemma Denson5afc9a22015-04-14 09:04:50 -03001035 state->dnxt.delsys = c->delivery_system;
1036 state->dnxt.modulation = c->modulation;
1037 state->dnxt.frequency = c->frequency;
1038 state->dnxt.pilot = c->pilot;
1039
1040 ret = cx24120_set_inversion(state, c->inversion);
1041 if (ret != 0)
1042 return ret;
1043
1044 ret = cx24120_set_fec(state, c->modulation, c->fec_inner);
1045 if (ret != 0)
1046 return ret;
1047
1048 ret = cx24120_set_pilot(state, c->pilot);
1049 if (ret != 0)
1050 return ret;
1051
1052 ret = cx24120_set_symbolrate(state, c->symbol_rate);
1053 if (ret != 0)
1054 return ret;
1055
Jemma Denson5afc9a22015-04-14 09:04:50 -03001056 /* discard the 'current' tuning parameters and prepare to tune */
1057 cx24120_clone_params(fe);
1058
1059 dev_dbg(&state->i2c->dev,
1060 "%s: delsys = %d\n", __func__, state->dcur.delsys);
1061 dev_dbg(&state->i2c->dev,
1062 "%s: modulation = %d\n", __func__, state->dcur.modulation);
1063 dev_dbg(&state->i2c->dev,
1064 "%s: frequency = %d\n", __func__, state->dcur.frequency);
1065 dev_dbg(&state->i2c->dev,
1066 "%s: pilot = %d (val = 0x%02x)\n", __func__,
1067 state->dcur.pilot, state->dcur.pilot_val);
1068 dev_dbg(&state->i2c->dev,
1069 "%s: symbol_rate = %d (clkdiv/ratediv = 0x%02x/0x%02x)\n",
1070 __func__, state->dcur.symbol_rate,
1071 state->dcur.clkdiv, state->dcur.ratediv);
1072 dev_dbg(&state->i2c->dev,
1073 "%s: FEC = %d (mask/val = 0x%02x/0x%02x)\n", __func__,
1074 state->dcur.fec, state->dcur.fec_mask, state->dcur.fec_val);
1075 dev_dbg(&state->i2c->dev,
1076 "%s: Inversion = %d (val = 0x%02x)\n", __func__,
1077 state->dcur.inversion, state->dcur.inversion_val);
1078
Jemma Denson5afc9a22015-04-14 09:04:50 -03001079 /* Tune in */
1080 cmd.id = CMD_TUNEREQUEST;
1081 cmd.len = 15;
1082 cmd.arg[0] = 0;
1083 cmd.arg[1] = (state->dcur.frequency & 0xff0000) >> 16;
1084 cmd.arg[2] = (state->dcur.frequency & 0x00ff00) >> 8;
1085 cmd.arg[3] = (state->dcur.frequency & 0x0000ff);
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -03001086 cmd.arg[4] = ((state->dcur.symbol_rate / 1000) & 0xff00) >> 8;
1087 cmd.arg[5] = ((state->dcur.symbol_rate / 1000) & 0x00ff);
Jemma Denson5afc9a22015-04-14 09:04:50 -03001088 cmd.arg[6] = state->dcur.inversion;
1089 cmd.arg[7] = state->dcur.fec_val | state->dcur.pilot_val;
1090 cmd.arg[8] = CX24120_SEARCH_RANGE_KHZ >> 8;
1091 cmd.arg[9] = CX24120_SEARCH_RANGE_KHZ & 0xff;
1092 cmd.arg[10] = 0; /* maybe rolloff? */
1093 cmd.arg[11] = state->dcur.fec_mask;
1094 cmd.arg[12] = state->dcur.ratediv;
1095 cmd.arg[13] = state->dcur.clkdiv;
1096 cmd.arg[14] = 0;
1097
Jemma Denson5afc9a22015-04-14 09:04:50 -03001098 /* Send tune command */
1099 ret = cx24120_message_send(state, &cmd);
1100 if (ret != 0)
1101 return ret;
1102
1103 /* Write symbol rate values */
1104 ret = cx24120_writereg(state, CX24120_REG_CLKDIV, state->dcur.clkdiv);
1105 ret = cx24120_readreg(state, CX24120_REG_RATEDIV);
1106 ret &= 0xfffffff0;
1107 ret |= state->dcur.ratediv;
1108 ret = cx24120_writereg(state, CX24120_REG_RATEDIV, ret);
1109
1110 /* Default time to tune */
1111 delay_cnt = 500;
1112
1113 /* Establish time to tune from symrates_delay_table */
1114 for (sd_idx = 0; sd_idx < ARRAY_SIZE(symrates_delay_table); sd_idx++) {
1115 if (state->dcur.delsys != symrates_delay_table[sd_idx].delsys)
1116 continue;
1117 if (c->symbol_rate < symrates_delay_table[sd_idx].symrate)
1118 continue;
1119
1120 /* found */
1121 delay_cnt = symrates_delay_table[sd_idx].delay;
1122 dev_dbg(&state->i2c->dev, "%s: Found symrate delay = %d\n",
1123 __func__, delay_cnt);
1124 break;
1125 }
1126
1127 /* Wait for tuning */
1128 while (delay_cnt >= 0) {
1129 cx24120_read_status(fe, &status);
1130 if (status & FE_HAS_LOCK)
1131 goto tuned;
1132 msleep(20);
1133 delay_cnt -= 20;
1134 }
1135
Jemma Denson5afc9a22015-04-14 09:04:50 -03001136 /* Fail to tune */
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -03001137 dev_dbg(&state->i2c->dev, "%s: Tuning failed\n", __func__);
Jemma Denson5afc9a22015-04-14 09:04:50 -03001138
1139 return -EINVAL;
1140
Jemma Denson5afc9a22015-04-14 09:04:50 -03001141tuned:
Patrick Boettcher2e89a5e2015-04-28 13:18:05 -03001142 dev_dbg(&state->i2c->dev, "%s: Tuning successful\n", __func__);
Jemma Denson5afc9a22015-04-14 09:04:50 -03001143
1144 /* Set clock ratios */
1145 cx24120_set_clock_ratios(fe);
1146
1147 /* Old driver would do a msleep(200) here */
1148
1149 /* Renable mpeg output */
1150 if (!state->mpeg_enabled)
1151 cx24120_msg_mpeg_output_global_config(state, 1);
1152
1153 return 0;
1154}
1155
Jemma Denson5afc9a22015-04-14 09:04:50 -03001156/* Calculate vco from config */
1157static u64 cx24120_calculate_vco(struct cx24120_state *state)
1158{
1159 u32 vco;
1160 u64 inv_vco, res, xxyyzz;
1161 u32 xtal_khz = state->config->xtal_khz;
1162
1163 xxyyzz = 0x400000000ULL;
1164 vco = xtal_khz * 10 * 4;
1165 inv_vco = xxyyzz / vco;
1166 res = xxyyzz % vco;
1167
1168 if (inv_vco > xtal_khz * 10 * 2)
1169 ++inv_vco;
1170
1171 dev_dbg(&state->i2c->dev,
1172 "%s: xtal=%d, vco=%d, inv_vco=%lld, res=%lld\n",
1173 __func__, xtal_khz, vco, inv_vco, res);
1174
1175 return inv_vco;
1176}
1177
Jemma Denson5afc9a22015-04-14 09:04:50 -03001178int cx24120_init(struct dvb_frontend *fe)
1179{
1180 const struct firmware *fw;
1181 struct cx24120_state *state = fe->demodulator_priv;
1182 struct cx24120_cmd cmd;
1183 u8 ret, ret_EA, reg1;
1184 u64 inv_vco;
1185 int reset_result;
1186
1187 int i;
1188 unsigned char vers[4];
1189
1190 if (state->cold_init)
1191 return 0;
1192
1193 /* ???? */
1194 ret = cx24120_writereg(state, 0xea, 0x00);
1195 ret = cx24120_test_rom(state);
1196 ret = cx24120_readreg(state, 0xfb) & 0xfe;
1197 ret = cx24120_writereg(state, 0xfb, ret);
1198 ret = cx24120_readreg(state, 0xfc) & 0xfe;
1199 ret = cx24120_writereg(state, 0xfc, ret);
1200 ret = cx24120_writereg(state, 0xc3, 0x04);
1201 ret = cx24120_writereg(state, 0xc4, 0x04);
1202 ret = cx24120_writereg(state, 0xce, 0x00);
1203 ret = cx24120_writereg(state, 0xcf, 0x00);
1204 ret_EA = cx24120_readreg(state, 0xea) & 0xfe;
1205 ret = cx24120_writereg(state, 0xea, ret_EA);
1206 ret = cx24120_writereg(state, 0xeb, 0x0c);
1207 ret = cx24120_writereg(state, 0xec, 0x06);
1208 ret = cx24120_writereg(state, 0xed, 0x05);
1209 ret = cx24120_writereg(state, 0xee, 0x03);
1210 ret = cx24120_writereg(state, 0xef, 0x05);
1211 ret = cx24120_writereg(state, 0xf3, 0x03);
1212 ret = cx24120_writereg(state, 0xf4, 0x44);
1213
1214 for (reg1 = 0xf0; reg1 < 0xf3; reg1++) {
1215 cx24120_writereg(state, reg1, 0x04);
1216 cx24120_writereg(state, reg1 - 10, 0x02);
1217 }
1218
1219 ret = cx24120_writereg(state, 0xea, (ret_EA | 0x01));
1220 for (reg1 = 0xc5; reg1 < 0xcb; reg1 += 2) {
1221 ret = cx24120_writereg(state, reg1, 0x00);
1222 ret = cx24120_writereg(state, reg1 + 1, 0x00);
1223 }
1224
1225 ret = cx24120_writereg(state, 0xe4, 0x03);
1226 ret = cx24120_writereg(state, 0xeb, 0x0a);
1227
1228 dev_dbg(&state->i2c->dev,
1229 "%s: Requesting firmware (%s) to download...\n",
1230 __func__, CX24120_FIRMWARE);
1231
1232 ret = state->config->request_firmware(fe, &fw, CX24120_FIRMWARE);
1233 if (ret) {
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -03001234 err("Could not load firmware (%s): %d\n", CX24120_FIRMWARE,
1235 ret);
Jemma Denson5afc9a22015-04-14 09:04:50 -03001236 return ret;
1237 }
1238
1239 dev_dbg(&state->i2c->dev,
1240 "%s: Firmware found, size %d bytes (%02x %02x .. %02x %02x)\n",
1241 __func__,
1242 (int)fw->size, /* firmware_size in bytes */
1243 fw->data[0], /* fw 1st byte */
1244 fw->data[1], /* fw 2d byte */
1245 fw->data[fw->size - 2], /* fw before last byte */
1246 fw->data[fw->size - 1]); /* fw last byte */
1247
1248 ret = cx24120_test_rom(state);
1249 ret = cx24120_readreg(state, 0xfb) & 0xfe;
1250 ret = cx24120_writereg(state, 0xfb, ret);
1251 ret = cx24120_writereg(state, 0xe0, 0x76);
1252 ret = cx24120_writereg(state, 0xf7, 0x81);
1253 ret = cx24120_writereg(state, 0xf8, 0x00);
1254 ret = cx24120_writereg(state, 0xf9, 0x00);
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -03001255 ret = cx24120_writeregs(state, 0xfa, fw->data, (fw->size - 1), 0x00);
Jemma Denson5afc9a22015-04-14 09:04:50 -03001256 ret = cx24120_writereg(state, 0xf7, 0xc0);
1257 ret = cx24120_writereg(state, 0xe0, 0x00);
1258 ret = (fw->size - 2) & 0x00ff;
1259 ret = cx24120_writereg(state, 0xf8, ret);
1260 ret = ((fw->size - 2) >> 8) & 0x00ff;
1261 ret = cx24120_writereg(state, 0xf9, ret);
1262 ret = cx24120_writereg(state, 0xf7, 0x00);
1263 ret = cx24120_writereg(state, 0xdc, 0x00);
1264 ret = cx24120_writereg(state, 0xdc, 0x07);
1265 msleep(500);
1266
1267 /* Check final byte matches final byte of firmware */
1268 ret = cx24120_readreg(state, 0xe1);
1269 if (ret == fw->data[fw->size - 1]) {
1270 dev_dbg(&state->i2c->dev,
1271 "%s: Firmware uploaded successfully\n",
1272 __func__);
1273 reset_result = 0;
1274 } else {
1275 err("Firmware upload failed. Last byte returned=0x%x\n", ret);
1276 reset_result = -EREMOTEIO;
1277 }
1278 ret = cx24120_writereg(state, 0xdc, 0x00);
1279 release_firmware(fw);
1280 if (reset_result != 0)
1281 return reset_result;
1282
Jemma Denson5afc9a22015-04-14 09:04:50 -03001283 /* Start tuner */
1284 cmd.id = CMD_START_TUNER;
1285 cmd.len = 3;
1286 cmd.arg[0] = 0x00;
1287 cmd.arg[1] = 0x00;
1288 cmd.arg[2] = 0x00;
1289
1290 if (cx24120_message_send(state, &cmd) != 0) {
1291 err("Error tuner start! :(\n");
1292 return -EREMOTEIO;
1293 }
1294
1295 /* Set VCO */
1296 inv_vco = cx24120_calculate_vco(state);
1297
1298 cmd.id = CMD_VCO_SET;
1299 cmd.len = 12;
1300 cmd.arg[0] = 0x06;
1301 cmd.arg[1] = 0x2b;
1302 cmd.arg[2] = 0xd8;
1303 cmd.arg[3] = (inv_vco >> 8) & 0xff;
1304 cmd.arg[4] = (inv_vco) & 0xff;
1305 cmd.arg[5] = 0x03;
1306 cmd.arg[6] = 0x9d;
1307 cmd.arg[7] = 0xfc;
1308 cmd.arg[8] = 0x06;
1309 cmd.arg[9] = 0x03;
1310 cmd.arg[10] = 0x27;
1311 cmd.arg[11] = 0x7f;
1312
1313 if (cx24120_message_send(state, &cmd)) {
1314 err("Error set VCO! :(\n");
1315 return -EREMOTEIO;
1316 }
1317
Jemma Denson5afc9a22015-04-14 09:04:50 -03001318 /* set bandwidth */
1319 cmd.id = CMD_BANDWIDTH;
1320 cmd.len = 12;
1321 cmd.arg[0] = 0x00;
1322 cmd.arg[1] = 0x00;
1323 cmd.arg[2] = 0x00;
1324 cmd.arg[3] = 0x00;
1325 cmd.arg[4] = 0x05;
1326 cmd.arg[5] = 0x02;
1327 cmd.arg[6] = 0x02;
1328 cmd.arg[7] = 0x00;
1329 cmd.arg[8] = 0x05;
1330 cmd.arg[9] = 0x02;
1331 cmd.arg[10] = 0x02;
1332 cmd.arg[11] = 0x00;
1333
1334 if (cx24120_message_send(state, &cmd)) {
1335 err("Error set bandwidth!\n");
1336 return -EREMOTEIO;
1337 }
1338
1339 ret = cx24120_readreg(state, 0xba);
1340 if (ret > 3) {
1341 dev_dbg(&state->i2c->dev, "%s: Reset-readreg 0xba: %x\n",
1342 __func__, ret);
1343 err("Error initialising tuner!\n");
1344 return -EREMOTEIO;
1345 }
1346
1347 dev_dbg(&state->i2c->dev, "%s: Tuner initialised correctly.\n",
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -03001348 __func__);
Jemma Denson5afc9a22015-04-14 09:04:50 -03001349
1350 /* Initialise mpeg outputs */
1351 ret = cx24120_writereg(state, 0xeb, 0x0a);
1352 if (cx24120_msg_mpeg_output_global_config(state, 0) ||
1353 cx24120_msg_mpeg_output_config(state, 0) ||
1354 cx24120_msg_mpeg_output_config(state, 1) ||
1355 cx24120_msg_mpeg_output_config(state, 2)) {
1356 err("Error initialising mpeg output. :(\n");
1357 return -EREMOTEIO;
1358 }
1359
Jemma Denson5afc9a22015-04-14 09:04:50 -03001360 /* ???? */
1361 cmd.id = CMD_TUNER_INIT;
1362 cmd.len = 3;
1363 cmd.arg[0] = 0x00;
1364 cmd.arg[1] = 0x10;
1365 cmd.arg[2] = 0x10;
1366 if (cx24120_message_send(state, &cmd)) {
1367 err("Error sending final init message. :(\n");
1368 return -EREMOTEIO;
1369 }
1370
Jemma Denson5afc9a22015-04-14 09:04:50 -03001371 /* Firmware CMD 35: Get firmware version */
1372 cmd.id = CMD_FWVERSION;
1373 cmd.len = 1;
1374 for (i = 0; i < 4; i++) {
1375 cmd.arg[0] = i;
1376 ret = cx24120_message_send(state, &cmd);
1377 if (ret != 0)
1378 return ret;
1379 vers[i] = cx24120_readreg(state, CX24120_REG_MAILBOX);
1380 }
1381 info("FW version %i.%i.%i.%i\n", vers[0], vers[1], vers[2], vers[3]);
1382
Jemma Denson5afc9a22015-04-14 09:04:50 -03001383 state->cold_init = 1;
1384 return 0;
1385}
1386
Jemma Denson5afc9a22015-04-14 09:04:50 -03001387static int cx24120_tune(struct dvb_frontend *fe, bool re_tune,
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -03001388 unsigned int mode_flags, unsigned int *delay,
1389 fe_status_t *status)
Jemma Denson5afc9a22015-04-14 09:04:50 -03001390{
1391 struct cx24120_state *state = fe->demodulator_priv;
1392 int ret;
1393
1394 dev_dbg(&state->i2c->dev, "%s(%d)\n", __func__, re_tune);
1395
1396 /* TODO: Do we need to set delay? */
1397
1398 if (re_tune) {
1399 ret = cx24120_set_frontend(fe);
1400 if (ret)
1401 return ret;
1402 }
1403
1404 return cx24120_read_status(fe, status);
1405}
1406
Jemma Denson5afc9a22015-04-14 09:04:50 -03001407static int cx24120_get_algo(struct dvb_frontend *fe)
1408{
1409 return DVBFE_ALGO_HW;
1410}
1411
Jemma Denson5afc9a22015-04-14 09:04:50 -03001412static int cx24120_sleep(struct dvb_frontend *fe)
1413{
1414 return 0;
1415}
1416
Jemma Denson5afc9a22015-04-14 09:04:50 -03001417static int cx24120_get_frontend(struct dvb_frontend *fe)
1418{
1419 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1420 struct cx24120_state *state = fe->demodulator_priv;
1421 u8 freq1, freq2, freq3;
1422
1423 dev_dbg(&state->i2c->dev, "%s()", __func__);
1424
1425 /* don't return empty data if we're not tuned in */
1426 if (state->mpeg_enabled)
1427 return 0;
1428
1429 /* Get frequency */
1430 freq1 = cx24120_readreg(state, CX24120_REG_FREQ1);
1431 freq2 = cx24120_readreg(state, CX24120_REG_FREQ2);
1432 freq3 = cx24120_readreg(state, CX24120_REG_FREQ3);
1433 c->frequency = (freq3 << 16) | (freq2 << 8) | freq1;
1434 dev_dbg(&state->i2c->dev, "%s frequency = %d\n", __func__,
1435 c->frequency);
1436
1437 /* Get modulation, fec, pilot */
1438 cx24120_get_fec(fe);
1439
1440 return 0;
1441}
1442
Jemma Denson5afc9a22015-04-14 09:04:50 -03001443static void cx24120_release(struct dvb_frontend *fe)
1444{
1445 struct cx24120_state *state = fe->demodulator_priv;
1446
1447 dev_dbg(&state->i2c->dev, "%s: Clear state structure\n", __func__);
1448 kfree(state);
1449}
1450
Jemma Denson5afc9a22015-04-14 09:04:50 -03001451static int cx24120_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1452{
1453 struct cx24120_state *state = fe->demodulator_priv;
1454
1455 *ucblocks = (cx24120_readreg(state, CX24120_REG_UCB_H) << 8) |
1456 cx24120_readreg(state, CX24120_REG_UCB_L);
1457
Patrick Boettcher1ff2e8e2015-04-28 13:39:20 -03001458 dev_dbg(&state->i2c->dev, "%s: Blocks = %d\n", __func__, *ucblocks);
Jemma Denson5afc9a22015-04-14 09:04:50 -03001459 return 0;
1460}
1461
Jemma Denson5afc9a22015-04-14 09:04:50 -03001462static struct dvb_frontend_ops cx24120_ops = {
1463 .delsys = { SYS_DVBS, SYS_DVBS2 },
1464 .info = {
1465 .name = "Conexant CX24120/CX24118",
1466 .frequency_min = 950000,
1467 .frequency_max = 2150000,
1468 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
1469 .frequency_tolerance = 5000,
1470 .symbol_rate_min = 1000000,
1471 .symbol_rate_max = 45000000,
1472 .caps = FE_CAN_INVERSION_AUTO |
1473 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1474 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1475 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1476 FE_CAN_2G_MODULATION |
1477 FE_CAN_QPSK | FE_CAN_RECOVER
1478 },
1479 .release = cx24120_release,
1480
1481 .init = cx24120_init,
1482 .sleep = cx24120_sleep,
1483
1484 .tune = cx24120_tune,
1485 .get_frontend_algo = cx24120_get_algo,
1486 .set_frontend = cx24120_set_frontend,
1487
1488 .get_frontend = cx24120_get_frontend,
1489 .read_status = cx24120_read_status,
1490 .read_ber = cx24120_read_ber,
1491 .read_signal_strength = cx24120_read_signal_strength,
1492 .read_snr = cx24120_read_snr,
1493 .read_ucblocks = cx24120_read_ucblocks,
1494
1495 .diseqc_send_master_cmd = cx24120_send_diseqc_msg,
1496
1497 .diseqc_send_burst = cx24120_diseqc_send_burst,
1498 .set_tone = cx24120_set_tone,
1499 .set_voltage = cx24120_set_voltage,
1500};
1501
1502MODULE_DESCRIPTION("DVB Frontend module for Conexant CX24120/CX24118 hardware");
1503MODULE_AUTHOR("Jemma Denson");
1504MODULE_LICENSE("GPL");