| Dan Murphy | 5df7f71 | 2014-07-14 15:10:45 -0500 | [diff] [blame] | 1 | /* |
| 2 | * tas2552.h - ALSA SoC Texas Instruments TAS2552 Mono Audio Amplifier |
| 3 | * |
| 4 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com |
| 5 | * |
| 6 | * Author: Dan Murphy <dmurphy@ti.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License |
| 10 | * version 2 as published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, but |
| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #ifndef __TAS2552_H__ |
| 19 | #define __TAS2552_H__ |
| 20 | |
| 21 | /* Register Address Map */ |
| 22 | #define TAS2552_DEVICE_STATUS 0x00 |
| 23 | #define TAS2552_CFG_1 0x01 |
| 24 | #define TAS2552_CFG_2 0x02 |
| 25 | #define TAS2552_CFG_3 0x03 |
| 26 | #define TAS2552_DOUT 0x04 |
| 27 | #define TAS2552_SER_CTRL_1 0x05 |
| 28 | #define TAS2552_SER_CTRL_2 0x06 |
| 29 | #define TAS2552_OUTPUT_DATA 0x07 |
| 30 | #define TAS2552_PLL_CTRL_1 0x08 |
| 31 | #define TAS2552_PLL_CTRL_2 0x09 |
| 32 | #define TAS2552_PLL_CTRL_3 0x0a |
| 33 | #define TAS2552_BTIP 0x0b |
| 34 | #define TAS2552_BTS_CTRL 0x0c |
| 35 | #define TAS2552_RESERVED_0D 0x0d |
| 36 | #define TAS2552_LIMIT_RATE_HYS 0x0e |
| 37 | #define TAS2552_LIMIT_RELEASE 0x0f |
| 38 | #define TAS2552_LIMIT_INT_COUNT 0x10 |
| 39 | #define TAS2552_PDM_CFG 0x11 |
| 40 | #define TAS2552_PGA_GAIN 0x12 |
| 41 | #define TAS2552_EDGE_RATE_CTRL 0x13 |
| 42 | #define TAS2552_BOOST_PT_CTRL 0x14 |
| 43 | #define TAS2552_VER_NUM 0x16 |
| 44 | #define TAS2552_VBAT_DATA 0x19 |
| 45 | #define TAS2552_MAX_REG 0x20 |
| 46 | |
| 47 | /* CFG1 Register Masks */ |
| Peter Ujfalusi | 7de544f | 2015-06-04 16:04:17 +0300 | [diff] [blame] | 48 | #define TAS2552_DEV_RESET (1 << 0) |
| 49 | #define TAS2552_SWS (1 << 1) |
| 50 | #define TAS2552_MUTE (1 << 2) |
| 51 | #define TAS2552_PLL_SRC_MCLK (0x0 << 4) |
| 52 | #define TAS2552_PLL_SRC_BCLK (0x1 << 4) |
| 53 | #define TAS2552_PLL_SRC_IVCLKIN (0x2 << 4) |
| 54 | #define TAS2552_PLL_SRC_1_8_FIXED (0x3 << 4) |
| 55 | #define TAS2552_PLL_SRC_MASK TAS2552_PLL_SRC_1_8_FIXED |
| Dan Murphy | 5df7f71 | 2014-07-14 15:10:45 -0500 | [diff] [blame] | 56 | |
| 57 | /* CFG2 Register Masks */ |
| 58 | #define TAS2552_CLASSD_EN (1 << 7) |
| 59 | #define TAS2552_BOOST_EN (1 << 6) |
| 60 | #define TAS2552_APT_EN (1 << 5) |
| 61 | #define TAS2552_PLL_ENABLE (1 << 3) |
| 62 | #define TAS2552_LIM_EN (1 << 2) |
| 63 | #define TAS2552_IVSENSE_EN (1 << 1) |
| 64 | |
| Peter Ujfalusi | 1b68c7d | 2015-06-04 16:04:24 +0300 | [diff] [blame^] | 65 | /* Serial Interface Control Register Masks */ |
| 66 | #define TAS2552_DATAFORMAT_I2S (0x0 << 2) |
| 67 | #define TAS2552_DATAFORMAT_DSP (0x1 << 2) |
| 68 | #define TAS2552_DATAFORMAT_RIGHT_J (0x2 << 2) |
| 69 | #define TAS2552_DATAFORMAT_LEFT_J (0x3 << 2) |
| 70 | #define TAS2552_DATAFORMAT_MASK TAS2552_DATAFORMAT_LEFT_J |
| 71 | #define TAS2552_BCLKDIR (1 << 6) |
| 72 | #define TAS2552_WCLKDIR (1 << 7) |
| Dan Murphy | 5df7f71 | 2014-07-14 15:10:45 -0500 | [diff] [blame] | 73 | |
| Dan Murphy | 5df7f71 | 2014-07-14 15:10:45 -0500 | [diff] [blame] | 74 | #define TAS2552_DIN_SRC_SEL_MUTED 0x00 |
| 75 | #define TAS2552_DIN_SRC_SEL_LEFT (1 << 4) |
| 76 | #define TAS2552_DIN_SRC_SEL_RIGHT (1 << 5) |
| 77 | #define TAS2552_DIN_SRC_SEL_AVG_L_R (0x11 << 4) |
| 78 | |
| 79 | #define TAS2552_PDM_IN_SEL (1 << 5) |
| 80 | #define TAS2552_I2S_OUT_SEL (1 << 6) |
| 81 | #define TAS2552_ANALOG_IN_SEL (1 << 7) |
| 82 | |
| 83 | /* CFG3 WCLK Dividers */ |
| 84 | #define TAS2552_8KHZ 0x00 |
| 85 | #define TAS2552_11_12KHZ (1 << 1) |
| 86 | #define TAS2552_16KHZ (1 << 2) |
| 87 | #define TAS2552_22_24KHZ (1 << 3) |
| 88 | #define TAS2552_32KHZ (1 << 4) |
| 89 | #define TAS2552_44_48KHZ (1 << 5) |
| 90 | #define TAS2552_88_96KHZ (1 << 6) |
| 91 | #define TAS2552_176_192KHZ (1 << 7) |
| 92 | |
| 93 | /* OUTPUT_DATA register */ |
| 94 | #define TAS2552_PDM_DATA_I 0x00 |
| 95 | #define TAS2552_PDM_DATA_V (1 << 6) |
| 96 | #define TAS2552_PDM_DATA_I_V (1 << 7) |
| 97 | #define TAS2552_PDM_DATA_V_I (0x11 << 6) |
| 98 | |
| 99 | /* PDM CFG Register */ |
| Peter Ujfalusi | 89683fd | 2015-06-04 16:04:16 +0300 | [diff] [blame] | 100 | #define TAS2552_PDM_CLK_SEL_PLL (0x0 << 0) |
| 101 | #define TAS2552_PDM_CLK_SEL_IVCLKIN (0x1 << 0) |
| 102 | #define TAS2552_PDM_CLK_SEL_BCLK (0x2 << 0) |
| 103 | #define TAS2552_PDM_CLK_SEL_MCLK (0x3 << 0) |
| 104 | #define TAS2552_PDM_CLK_SEL_MASK TAS2552_PDM_CLK_SEL_MCLK |
| 105 | #define TAS2552_PDM_DATA_ES (1 << 2) |
| Dan Murphy | 5df7f71 | 2014-07-14 15:10:45 -0500 | [diff] [blame] | 106 | |
| 107 | /* Boost pass-through register */ |
| 108 | #define TAS2552_APT_DELAY_50 0x00 |
| 109 | #define TAS2552_APT_DELAY_75 (1 << 1) |
| 110 | #define TAS2552_APT_DELAY_125 (1 << 2) |
| 111 | #define TAS2552_APT_DELAY_200 (1 << 3) |
| 112 | |
| 113 | #define TAS2552_APT_THRESH_2_5 0x00 |
| 114 | #define TAS2552_APT_THRESH_1_7 (1 << 3) |
| 115 | #define TAS2552_APT_THRESH_1_4_1_1 (1 << 4) |
| 116 | #define TAS2552_APT_THRESH_2_1_7 (0x11 << 2) |
| 117 | |
| 118 | /* PLL Control Register */ |
| 119 | #define TAS2552_245MHZ_CLK 24576000 |
| 120 | #define TAS2552_225MHZ_CLK 22579200 |
| 121 | #define TAS2552_PLL_J_MASK 0x7f |
| 122 | #define TAS2552_PLL_D_UPPER_MASK 0x3f |
| 123 | #define TAS2552_PLL_D_LOWER_MASK 0xff |
| 124 | #define TAS2552_PLL_BYPASS_MASK 0x80 |
| 125 | #define TAS2552_PLL_BYPASS 0x80 |
| 126 | |
| 127 | #endif |