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nv-tegra.nvidia.com / linux-5.10 / 1a59d1b8e05ea6ab45f7e18897de1ef0e6bc3da6 / . / arch / arm / mach-socfpga / core.h
blob: fc2608b18a0d048c62aed905f4f76da438f94426 [file] [log] [blame]
Thomas Gleixner1a59d1b82019-05-27 08:55:05 +0200[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-or-later */
Dinh Nguyen9c4566a2012-10-25 10:41:39 -0600[diff] [blame]2/*
3 * Copyright 2012 Pavel Machek <pavel@denx.de>
Alan Tull44fd8c72015-06-05 08:24:52 -0500[diff] [blame]4 * Copyright (C) 2012-2015 Altera Corporation
Dinh Nguyen9c4566a2012-10-25 10:41:39 -0600[diff] [blame]5 */
6
7#ifndef __MACH_CORE_H
8#define __MACH_CORE_H
9
Dinh Nguyen5c04b572013-04-11 10:55:24 -0500[diff] [blame]10#define SOCFPGA_RSTMGR_CTRL 0x04
Alan Tulld686ce42014-10-14 19:33:38 +0000[diff] [blame]11#define SOCFPGA_RSTMGR_MODMPURST 0x10
Dinh Nguyen5c04b572013-04-11 10:55:24 -0500[diff] [blame]12#define SOCFPGA_RSTMGR_MODPERRST 0x14
13#define SOCFPGA_RSTMGR_BRGMODRST 0x1c
14
Dinh Nguyencd871d52015-07-20 11:23:13 -0500[diff] [blame]15#define SOCFPGA_A10_RSTMGR_CTRL 0xC
Dinh Nguyen45be0cd2015-06-02 21:14:02 -0500[diff] [blame]16#define SOCFPGA_A10_RSTMGR_MODMPURST 0x20
17
Dinh Nguyen5c04b572013-04-11 10:55:24 -0500[diff] [blame]18/* System Manager bits */
19#define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */
20#define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */
21
Alan Tulld686ce42014-10-14 19:33:38 +0000[diff] [blame]22#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
23
Thor Thayer4d113832016-02-10 13:26:23 -0600[diff] [blame]24void socfpga_init_l2_ecc(void);
Thor Thayer7cc5a5d2016-02-10 13:26:24 -0600[diff] [blame]25void socfpga_init_ocram_ecc(void);
Thor Thayerff6fd142016-03-21 11:01:45 -0500[diff] [blame]26void socfpga_init_arria10_l2_ecc(void);
Thor Thayerc5fb04c2016-04-11 12:01:34 -0500[diff] [blame]27void socfpga_init_arria10_ocram_ecc(void);
Dinh Nguyen9c4566a2012-10-25 10:41:39 -0600[diff] [blame]28
Dinh Nguyen5c04b572013-04-11 10:55:24 -0500[diff] [blame]29extern void __iomem *sys_manager_base_addr;
30extern void __iomem *rst_manager_base_addr;
Alan Tull44fd8c72015-06-05 08:24:52 -0500[diff] [blame]31extern void __iomem *sdr_ctl_base_addr;
Dinh Nguyen5c04b572013-04-11 10:55:24 -0500[diff] [blame]32
Alan Tull44fd8c72015-06-05 08:24:52 -0500[diff] [blame]33u32 socfpga_sdram_self_refresh(u32 sdr_base);
34extern unsigned int socfpga_sdram_self_refresh_sz;
Dinh Nguyen9c4566a2012-10-25 10:41:39 -0600[diff] [blame]35
Dinh Nguyen9c4566a2012-10-25 10:41:39 -0600[diff] [blame]36extern char secondary_trampoline, secondary_trampoline_end;
37
Dinh Nguyen3a4356c2014-10-01 05:44:48 -0500[diff] [blame]38extern unsigned long socfpga_cpu1start_addr;
Dinh Nguyen9c4566a2012-10-25 10:41:39 -0600[diff] [blame]39
Vince Bridgersde042612015-02-11 18:34:25 +0000[diff] [blame]40#define SOCFPGA_SCU_VIRT_BASE 0xfee00000
Dinh Nguyen9c4566a2012-10-25 10:41:39 -0600[diff] [blame]41
42#endif