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Vineet Gupta820970a2015-03-06 14:08:20 +05301/*
2 * Copyright (C) 2014 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#include <linux/interrupt.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/irqdomain.h>
14#include <linux/irqchip.h>
Vineet Gupta820970a2015-03-06 14:08:20 +053015#include <asm/irq.h>
16
Vineet Gupta179cf192017-02-01 09:44:33 -080017#define NR_EXCEPTIONS 16
18
19struct bcr_irq_arcv2 {
20#ifdef CONFIG_CPU_BIG_ENDIAN
21 unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
22#else
23 unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
24#endif
25};
Vineet Guptafe7b1092017-02-01 10:14:11 -080026
Vineet Gupta820970a2015-03-06 14:08:20 +053027/*
28 * Early Hardware specific Interrupt setup
29 * -Called very early (start_kernel -> setup_arch -> setup_processor)
30 * -Platform Independent (must for any ARC Core)
31 * -Needed for each CPU (hence not foldable into init_IRQ)
32 */
33void arc_init_IRQ(void)
34{
Vineet Gupta107177b2016-09-30 16:13:28 -070035 unsigned int tmp, irq_prio;
Vineet Gupta179cf192017-02-01 09:44:33 -080036 struct bcr_irq_arcv2 irq_bcr;
Vineet Guptadec2b282016-02-07 12:54:35 +053037
Vineet Gupta820970a2015-03-06 14:08:20 +053038 struct aux_irq_ctrl {
39#ifdef CONFIG_CPU_BIG_ENDIAN
40 unsigned int res3:18, save_idx_regs:1, res2:1,
41 save_u_to_u:1, save_lp_regs:1, save_blink:1,
42 res:4, save_nr_gpr_pairs:5;
43#else
44 unsigned int save_nr_gpr_pairs:5, res:4,
45 save_blink:1, save_lp_regs:1, save_u_to_u:1,
46 res2:1, save_idx_regs:1, res3:18;
47#endif
48 } ictrl;
49
50 *(unsigned int *)&ictrl = 0;
51
52 ictrl.save_nr_gpr_pairs = 6; /* r0 to r11 (r12 saved manually) */
53 ictrl.save_blink = 1;
54 ictrl.save_lp_regs = 1; /* LP_COUNT, LP_START, LP_END */
55 ictrl.save_u_to_u = 0; /* user ctxt saved on kernel stack */
56 ictrl.save_idx_regs = 1; /* JLI, LDI, EI */
57
58 WRITE_AUX(AUX_IRQ_CTRL, ictrl);
59
Vineet Gupta820970a2015-03-06 14:08:20 +053060 /*
61 * ARCv2 core intc provides multiple interrupt priorities (upto 16).
62 * Typical builds though have only two levels (0-high, 1-low)
63 * Linux by default uses lower prio 1 for most irqs, reserving 0 for
64 * NMI style interrupts in future (say perf)
Vineet Gupta820970a2015-03-06 14:08:20 +053065 */
Vineet Guptadec2b282016-02-07 12:54:35 +053066
67 READ_BCR(ARC_REG_IRQ_BCR, irq_bcr);
68
69 irq_prio = irq_bcr.prio; /* Encoded as N-1 for N levels */
70 pr_info("archs-intc\t: %d priority levels (default %d)%s\n",
Vineet Gupta107177b2016-09-30 16:13:28 -070071 irq_prio + 1, ARCV2_IRQ_DEF_PRIO,
Vineet Guptadec2b282016-02-07 12:54:35 +053072 irq_bcr.firq ? " FIRQ (not used)":"");
73
74 /* setup status32, don't enable intr yet as kernel doesn't want */
Yuriy Kolerove98a7bf2017-01-31 14:45:21 +030075 tmp = read_aux_reg(ARC_REG_STATUS32);
Vineet Gupta107177b2016-09-30 16:13:28 -070076 tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1);
Vineet Guptadec2b282016-02-07 12:54:35 +053077 tmp &= ~STATUS_IE_MASK;
Yuriy Kolerovbc0c7ec2016-09-12 18:55:03 +030078 asm volatile("kflag %0 \n"::"r"(tmp));
Vineet Gupta820970a2015-03-06 14:08:20 +053079}
80
81static void arcv2_irq_mask(struct irq_data *data)
82{
Yuriy Kolerov21632662016-12-28 11:46:24 +030083 write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
Vineet Gupta820970a2015-03-06 14:08:20 +053084 write_aux_reg(AUX_IRQ_ENABLE, 0);
85}
86
87static void arcv2_irq_unmask(struct irq_data *data)
88{
Yuriy Kolerov21632662016-12-28 11:46:24 +030089 write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
Vineet Gupta820970a2015-03-06 14:08:20 +053090 write_aux_reg(AUX_IRQ_ENABLE, 1);
91}
92
93void arcv2_irq_enable(struct irq_data *data)
94{
95 /* set default priority */
Yuriy Kolerov21632662016-12-28 11:46:24 +030096 write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
Vineet Gupta107177b2016-09-30 16:13:28 -070097 write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
Vineet Gupta820970a2015-03-06 14:08:20 +053098
99 /*
100 * hw auto enables (linux unmask) all by default
101 * So no need to do IRQ_ENABLE here
102 * XXX: However OSCI LAN need it
103 */
104 write_aux_reg(AUX_IRQ_ENABLE, 1);
105}
106
107static struct irq_chip arcv2_irq_chip = {
108 .name = "ARCv2 core Intc",
109 .irq_mask = arcv2_irq_mask,
110 .irq_unmask = arcv2_irq_unmask,
111 .irq_enable = arcv2_irq_enable
112};
113
114static int arcv2_irq_map(struct irq_domain *d, unsigned int irq,
115 irq_hw_number_t hw)
116{
Vineet Gupta8eb09842015-12-11 15:54:03 +0530117 /*
118 * core intc IRQs [16, 23]:
119 * Statically assigned always private-per-core (Timers, WDT, IPI, PCT)
120 */
Vineet Gupta179cf192017-02-01 09:44:33 -0800121 if (hw < FIRST_EXT_IRQ) {
Vineet Gupta8eb09842015-12-11 15:54:03 +0530122 /*
123 * A subsequent request_percpu_irq() fails if percpu_devid is
124 * not set. That in turns sets NOAUTOEN, meaning each core needs
125 * to call enable_percpu_irq()
126 */
127 irq_set_percpu_devid(irq);
Vineet Gupta820970a2015-03-06 14:08:20 +0530128 irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_percpu_irq);
Vineet Gupta8eb09842015-12-11 15:54:03 +0530129 } else {
Vineet Gupta820970a2015-03-06 14:08:20 +0530130 irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_level_irq);
Vineet Gupta8eb09842015-12-11 15:54:03 +0530131 }
Vineet Gupta820970a2015-03-06 14:08:20 +0530132
133 return 0;
134}
135
136static const struct irq_domain_ops arcv2_irq_ops = {
137 .xlate = irq_domain_xlate_onecell,
138 .map = arcv2_irq_map,
139};
140
Vineet Gupta820970a2015-03-06 14:08:20 +0530141
142static int __init
143init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
144{
Vineet Gupta1b0ccb82016-01-01 15:12:54 +0530145 struct irq_domain *root_domain;
Vineet Gupta179cf192017-02-01 09:44:33 -0800146 struct bcr_irq_arcv2 irq_bcr;
147 unsigned int nr_cpu_irqs;
148
149 READ_BCR(ARC_REG_IRQ_BCR, irq_bcr);
150 nr_cpu_irqs = irq_bcr.irqs + NR_EXCEPTIONS;
Vineet Gupta1b0ccb82016-01-01 15:12:54 +0530151
Vineet Gupta820970a2015-03-06 14:08:20 +0530152 if (parent)
153 panic("DeviceTree incore intc not a root irq controller\n");
154
Vineet Gupta179cf192017-02-01 09:44:33 -0800155 root_domain = irq_domain_add_linear(intc, nr_cpu_irqs, &arcv2_irq_ops, NULL);
Vineet Gupta820970a2015-03-06 14:08:20 +0530156 if (!root_domain)
157 panic("root irq domain not avail\n");
158
Vineet Gupta1b0ccb82016-01-01 15:12:54 +0530159 /*
160 * Needed for primary domain lookup to succeed
161 * This is a primary irqchip, and can never have a parent
162 */
Vineet Gupta820970a2015-03-06 14:08:20 +0530163 irq_set_default_host(root_domain);
164
Vineet Guptad21beff2016-01-28 09:40:10 +0530165#ifdef CONFIG_SMP
166 irq_create_mapping(root_domain, IPI_IRQ);
167#endif
168 irq_create_mapping(root_domain, SOFTIRQ_IRQ);
169
Vineet Gupta820970a2015-03-06 14:08:20 +0530170 return 0;
171}
172
173IRQCHIP_DECLARE(arc_intc, "snps,archs-intc", init_onchip_IRQ);