Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Pierre Ossman | 70f1048 | 2007-07-11 20:04:50 +0200 | [diff] [blame] | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 5 | * Copyright (C) 2010 ST-Ericsson SA |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | #include <linux/module.h> |
| 12 | #include <linux/moduleparam.h> |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/ioport.h> |
| 15 | #include <linux/device.h> |
Ulf Hansson | ef28998 | 2014-03-17 13:56:32 +0100 | [diff] [blame] | 16 | #include <linux/io.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | #include <linux/interrupt.h> |
Russell King | 613b152 | 2011-01-30 21:06:53 +0000 | [diff] [blame] | 18 | #include <linux/kernel.h> |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 19 | #include <linux/slab.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | #include <linux/delay.h> |
| 21 | #include <linux/err.h> |
| 22 | #include <linux/highmem.h> |
Nicolas Pitre | 019a5f5 | 2007-10-11 01:06:03 -0400 | [diff] [blame] | 23 | #include <linux/log2.h> |
Ulf Hansson | 70be208 | 2013-01-07 15:35:06 +0100 | [diff] [blame] | 24 | #include <linux/mmc/pm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | #include <linux/mmc/host.h> |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 26 | #include <linux/mmc/card.h> |
Ulf Hansson | d276209 | 2014-03-17 13:56:19 +0100 | [diff] [blame] | 27 | #include <linux/mmc/slot-gpio.h> |
Russell King | a62c80e | 2006-01-07 13:52:45 +0000 | [diff] [blame] | 28 | #include <linux/amba/bus.h> |
Russell King | f8ce254 | 2006-01-07 16:15:52 +0000 | [diff] [blame] | 29 | #include <linux/clk.h> |
Jens Axboe | bd6dee6 | 2007-10-24 09:01:09 +0200 | [diff] [blame] | 30 | #include <linux/scatterlist.h> |
Linus Walleij | 9ef986a | 2018-09-20 16:01:10 -0700 | [diff] [blame] | 31 | #include <linux/of.h> |
Linus Walleij | 34e84f3 | 2009-09-22 14:41:40 +0100 | [diff] [blame] | 32 | #include <linux/regulator/consumer.h> |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 33 | #include <linux/dmaengine.h> |
| 34 | #include <linux/dma-mapping.h> |
| 35 | #include <linux/amba/mmci.h> |
Russell King | 1c3be36 | 2011-08-14 09:17:05 +0100 | [diff] [blame] | 36 | #include <linux/pm_runtime.h> |
Viresh Kumar | 258aea7 | 2012-02-01 16:12:19 +0530 | [diff] [blame] | 37 | #include <linux/types.h> |
Linus Walleij | a9a8378 | 2012-10-29 14:39:30 +0100 | [diff] [blame] | 38 | #include <linux/pinctrl/consumer.h> |
Ludovic Barre | 15878e5 | 2018-10-08 14:08:51 +0200 | [diff] [blame^] | 39 | #include <linux/reset.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | |
Russell King | 7b09cda | 2005-07-01 12:02:59 +0100 | [diff] [blame] | 41 | #include <asm/div64.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | #include <asm/io.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | |
| 44 | #include "mmci.h" |
Srinivas Kandagatla | 9cb1514 | 2014-07-29 03:50:30 +0100 | [diff] [blame] | 45 | #include "mmci_qcom_dml.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | |
| 47 | #define DRIVER_NAME "mmci-pl18x" |
| 48 | |
Ludovic Barre | c3647fd | 2018-10-08 14:08:33 +0200 | [diff] [blame] | 49 | #ifdef CONFIG_DMA_ENGINE |
| 50 | void mmci_variant_init(struct mmci_host *host); |
| 51 | #else |
| 52 | static inline void mmci_variant_init(struct mmci_host *host) {} |
| 53 | #endif |
| 54 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | static unsigned int fmax = 515633; |
| 56 | |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 57 | static struct variant_data variant_arm = { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 58 | .fifosize = 16 * 4, |
| 59 | .fifohalfsize = 8 * 4, |
Ludovic Barre | 0f24480 | 2018-10-08 14:08:45 +0200 | [diff] [blame] | 60 | .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, |
| 61 | .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, |
| 62 | .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, |
| 63 | .cmdreg_srsp = MCI_CPSM_RESPONSE, |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 64 | .datalength_bits = 16, |
Ludovic Barre | c931d49 | 2018-10-08 14:08:43 +0200 | [diff] [blame] | 65 | .datactrl_blocksz = 11, |
Ludovic Barre | 9b27994 | 2018-10-08 14:08:46 +0200 | [diff] [blame] | 66 | .datactrl_dpsm_enable = MCI_DPSM_ENABLE, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 67 | .pwrreg_powerup = MCI_PWR_UP, |
Srinivas Kandagatla | dc6500b | 2014-06-02 10:09:47 +0100 | [diff] [blame] | 68 | .f_max = 100000000, |
Ulf Hansson | 7878289 | 2014-06-13 13:21:38 +0200 | [diff] [blame] | 69 | .reversed_irq_handling = true, |
Patrice Chotard | 6ea9cdf | 2018-01-18 15:34:17 +0100 | [diff] [blame] | 70 | .mmcimask1 = true, |
Ludovic Barre | 59db5e2 | 2018-10-08 14:08:47 +0200 | [diff] [blame] | 71 | .irq_pio_mask = MCI_IRQ_PIO_MASK, |
Patrice Chotard | 7f7b550 | 2018-01-18 15:34:18 +0100 | [diff] [blame] | 72 | .start_err = MCI_STARTBITERR, |
Patrice Chotard | 11dfb97 | 2018-01-18 15:34:19 +0100 | [diff] [blame] | 73 | .opendrain = MCI_ROD, |
Ludovic Barre | c3647fd | 2018-10-08 14:08:33 +0200 | [diff] [blame] | 74 | .init = mmci_variant_init, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 75 | }; |
| 76 | |
Pawel Moll | 768fbc1 | 2011-03-11 17:18:07 +0000 | [diff] [blame] | 77 | static struct variant_data variant_arm_extended_fifo = { |
| 78 | .fifosize = 128 * 4, |
| 79 | .fifohalfsize = 64 * 4, |
Ludovic Barre | 0f24480 | 2018-10-08 14:08:45 +0200 | [diff] [blame] | 80 | .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, |
| 81 | .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, |
| 82 | .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, |
| 83 | .cmdreg_srsp = MCI_CPSM_RESPONSE, |
Pawel Moll | 768fbc1 | 2011-03-11 17:18:07 +0000 | [diff] [blame] | 84 | .datalength_bits = 16, |
Ludovic Barre | c931d49 | 2018-10-08 14:08:43 +0200 | [diff] [blame] | 85 | .datactrl_blocksz = 11, |
Ludovic Barre | 9b27994 | 2018-10-08 14:08:46 +0200 | [diff] [blame] | 86 | .datactrl_dpsm_enable = MCI_DPSM_ENABLE, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 87 | .pwrreg_powerup = MCI_PWR_UP, |
Srinivas Kandagatla | dc6500b | 2014-06-02 10:09:47 +0100 | [diff] [blame] | 88 | .f_max = 100000000, |
Patrice Chotard | 6ea9cdf | 2018-01-18 15:34:17 +0100 | [diff] [blame] | 89 | .mmcimask1 = true, |
Ludovic Barre | 59db5e2 | 2018-10-08 14:08:47 +0200 | [diff] [blame] | 90 | .irq_pio_mask = MCI_IRQ_PIO_MASK, |
Patrice Chotard | 7f7b550 | 2018-01-18 15:34:18 +0100 | [diff] [blame] | 91 | .start_err = MCI_STARTBITERR, |
Patrice Chotard | 11dfb97 | 2018-01-18 15:34:19 +0100 | [diff] [blame] | 92 | .opendrain = MCI_ROD, |
Ludovic Barre | c3647fd | 2018-10-08 14:08:33 +0200 | [diff] [blame] | 93 | .init = mmci_variant_init, |
Pawel Moll | 768fbc1 | 2011-03-11 17:18:07 +0000 | [diff] [blame] | 94 | }; |
| 95 | |
Pawel Moll | 3a37298 | 2013-01-24 14:12:45 +0100 | [diff] [blame] | 96 | static struct variant_data variant_arm_extended_fifo_hwfc = { |
| 97 | .fifosize = 128 * 4, |
| 98 | .fifohalfsize = 64 * 4, |
| 99 | .clkreg_enable = MCI_ARM_HWFCEN, |
Ludovic Barre | 0f24480 | 2018-10-08 14:08:45 +0200 | [diff] [blame] | 100 | .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, |
| 101 | .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, |
| 102 | .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, |
| 103 | .cmdreg_srsp = MCI_CPSM_RESPONSE, |
Pawel Moll | 3a37298 | 2013-01-24 14:12:45 +0100 | [diff] [blame] | 104 | .datalength_bits = 16, |
Ludovic Barre | c931d49 | 2018-10-08 14:08:43 +0200 | [diff] [blame] | 105 | .datactrl_blocksz = 11, |
Ludovic Barre | 9b27994 | 2018-10-08 14:08:46 +0200 | [diff] [blame] | 106 | .datactrl_dpsm_enable = MCI_DPSM_ENABLE, |
Pawel Moll | 3a37298 | 2013-01-24 14:12:45 +0100 | [diff] [blame] | 107 | .pwrreg_powerup = MCI_PWR_UP, |
Srinivas Kandagatla | dc6500b | 2014-06-02 10:09:47 +0100 | [diff] [blame] | 108 | .f_max = 100000000, |
Patrice Chotard | 6ea9cdf | 2018-01-18 15:34:17 +0100 | [diff] [blame] | 109 | .mmcimask1 = true, |
Ludovic Barre | 59db5e2 | 2018-10-08 14:08:47 +0200 | [diff] [blame] | 110 | .irq_pio_mask = MCI_IRQ_PIO_MASK, |
Patrice Chotard | 7f7b550 | 2018-01-18 15:34:18 +0100 | [diff] [blame] | 111 | .start_err = MCI_STARTBITERR, |
Patrice Chotard | 11dfb97 | 2018-01-18 15:34:19 +0100 | [diff] [blame] | 112 | .opendrain = MCI_ROD, |
Ludovic Barre | c3647fd | 2018-10-08 14:08:33 +0200 | [diff] [blame] | 113 | .init = mmci_variant_init, |
Pawel Moll | 3a37298 | 2013-01-24 14:12:45 +0100 | [diff] [blame] | 114 | }; |
| 115 | |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 116 | static struct variant_data variant_u300 = { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 117 | .fifosize = 16 * 4, |
| 118 | .fifohalfsize = 8 * 4, |
Linus Walleij | 49ac215 | 2011-03-04 14:54:16 +0100 | [diff] [blame] | 119 | .clkreg_enable = MCI_ST_U300_HWFCEN, |
Srinivas Kandagatla | e1412d8 | 2014-06-02 10:09:23 +0100 | [diff] [blame] | 120 | .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, |
Ludovic Barre | 0f24480 | 2018-10-08 14:08:45 +0200 | [diff] [blame] | 121 | .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, |
| 122 | .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, |
| 123 | .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, |
| 124 | .cmdreg_srsp = MCI_CPSM_RESPONSE, |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 125 | .datalength_bits = 16, |
Ludovic Barre | c931d49 | 2018-10-08 14:08:43 +0200 | [diff] [blame] | 126 | .datactrl_blocksz = 11, |
Ludovic Barre | 9b27994 | 2018-10-08 14:08:46 +0200 | [diff] [blame] | 127 | .datactrl_dpsm_enable = MCI_DPSM_ENABLE, |
Linus Walleij | 5db3eee | 2016-10-25 11:06:05 +0200 | [diff] [blame] | 128 | .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, |
Srinivas Kandagatla | c735413 | 2014-08-22 05:55:16 +0100 | [diff] [blame] | 129 | .st_sdio = true, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 130 | .pwrreg_powerup = MCI_PWR_ON, |
Srinivas Kandagatla | dc6500b | 2014-06-02 10:09:47 +0100 | [diff] [blame] | 131 | .f_max = 100000000, |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 132 | .signal_direction = true, |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 133 | .pwrreg_clkgate = true, |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 134 | .pwrreg_nopower = true, |
Patrice Chotard | 6ea9cdf | 2018-01-18 15:34:17 +0100 | [diff] [blame] | 135 | .mmcimask1 = true, |
Ludovic Barre | 59db5e2 | 2018-10-08 14:08:47 +0200 | [diff] [blame] | 136 | .irq_pio_mask = MCI_IRQ_PIO_MASK, |
Patrice Chotard | 7f7b550 | 2018-01-18 15:34:18 +0100 | [diff] [blame] | 137 | .start_err = MCI_STARTBITERR, |
Patrice Chotard | 11dfb97 | 2018-01-18 15:34:19 +0100 | [diff] [blame] | 138 | .opendrain = MCI_OD, |
Ludovic Barre | c3647fd | 2018-10-08 14:08:33 +0200 | [diff] [blame] | 139 | .init = mmci_variant_init, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 140 | }; |
| 141 | |
Linus Walleij | 34fd421 | 2012-04-10 17:43:59 +0100 | [diff] [blame] | 142 | static struct variant_data variant_nomadik = { |
| 143 | .fifosize = 16 * 4, |
| 144 | .fifohalfsize = 8 * 4, |
| 145 | .clkreg = MCI_CLK_ENABLE, |
Linus Walleij | f5abc76 | 2016-01-04 02:22:08 +0100 | [diff] [blame] | 146 | .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, |
Ludovic Barre | 0f24480 | 2018-10-08 14:08:45 +0200 | [diff] [blame] | 147 | .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, |
| 148 | .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, |
| 149 | .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, |
| 150 | .cmdreg_srsp = MCI_CPSM_RESPONSE, |
Linus Walleij | 34fd421 | 2012-04-10 17:43:59 +0100 | [diff] [blame] | 151 | .datalength_bits = 24, |
Ludovic Barre | c931d49 | 2018-10-08 14:08:43 +0200 | [diff] [blame] | 152 | .datactrl_blocksz = 11, |
Ludovic Barre | 9b27994 | 2018-10-08 14:08:46 +0200 | [diff] [blame] | 153 | .datactrl_dpsm_enable = MCI_DPSM_ENABLE, |
Linus Walleij | 5db3eee | 2016-10-25 11:06:05 +0200 | [diff] [blame] | 154 | .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, |
Srinivas Kandagatla | c735413 | 2014-08-22 05:55:16 +0100 | [diff] [blame] | 155 | .st_sdio = true, |
Linus Walleij | 34fd421 | 2012-04-10 17:43:59 +0100 | [diff] [blame] | 156 | .st_clkdiv = true, |
| 157 | .pwrreg_powerup = MCI_PWR_ON, |
Srinivas Kandagatla | dc6500b | 2014-06-02 10:09:47 +0100 | [diff] [blame] | 158 | .f_max = 100000000, |
Linus Walleij | 34fd421 | 2012-04-10 17:43:59 +0100 | [diff] [blame] | 159 | .signal_direction = true, |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 160 | .pwrreg_clkgate = true, |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 161 | .pwrreg_nopower = true, |
Patrice Chotard | 6ea9cdf | 2018-01-18 15:34:17 +0100 | [diff] [blame] | 162 | .mmcimask1 = true, |
Ludovic Barre | 59db5e2 | 2018-10-08 14:08:47 +0200 | [diff] [blame] | 163 | .irq_pio_mask = MCI_IRQ_PIO_MASK, |
Patrice Chotard | 7f7b550 | 2018-01-18 15:34:18 +0100 | [diff] [blame] | 164 | .start_err = MCI_STARTBITERR, |
Patrice Chotard | 11dfb97 | 2018-01-18 15:34:19 +0100 | [diff] [blame] | 165 | .opendrain = MCI_OD, |
Ludovic Barre | c3647fd | 2018-10-08 14:08:33 +0200 | [diff] [blame] | 166 | .init = mmci_variant_init, |
Linus Walleij | 34fd421 | 2012-04-10 17:43:59 +0100 | [diff] [blame] | 167 | }; |
| 168 | |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 169 | static struct variant_data variant_ux500 = { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 170 | .fifosize = 30 * 4, |
| 171 | .fifohalfsize = 8 * 4, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 172 | .clkreg = MCI_CLK_ENABLE, |
Linus Walleij | 49ac215 | 2011-03-04 14:54:16 +0100 | [diff] [blame] | 173 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
Srinivas Kandagatla | e1412d8 | 2014-06-02 10:09:23 +0100 | [diff] [blame] | 174 | .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, |
Srinivas Kandagatla | e874064 | 2014-06-02 10:09:30 +0100 | [diff] [blame] | 175 | .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, |
Ludovic Barre | 0f24480 | 2018-10-08 14:08:45 +0200 | [diff] [blame] | 176 | .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, |
| 177 | .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, |
| 178 | .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, |
| 179 | .cmdreg_srsp = MCI_CPSM_RESPONSE, |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 180 | .datalength_bits = 24, |
Ludovic Barre | c931d49 | 2018-10-08 14:08:43 +0200 | [diff] [blame] | 181 | .datactrl_blocksz = 11, |
Ludovic Barre | 9b27994 | 2018-10-08 14:08:46 +0200 | [diff] [blame] | 182 | .datactrl_dpsm_enable = MCI_DPSM_ENABLE, |
Linus Walleij | 5db3eee | 2016-10-25 11:06:05 +0200 | [diff] [blame] | 183 | .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, |
Srinivas Kandagatla | c735413 | 2014-08-22 05:55:16 +0100 | [diff] [blame] | 184 | .st_sdio = true, |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 185 | .st_clkdiv = true, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 186 | .pwrreg_powerup = MCI_PWR_ON, |
Srinivas Kandagatla | dc6500b | 2014-06-02 10:09:47 +0100 | [diff] [blame] | 187 | .f_max = 100000000, |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 188 | .signal_direction = true, |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 189 | .pwrreg_clkgate = true, |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 190 | .busy_detect = true, |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 191 | .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, |
| 192 | .busy_detect_flag = MCI_ST_CARDBUSY, |
| 193 | .busy_detect_mask = MCI_ST_BUSYENDMASK, |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 194 | .pwrreg_nopower = true, |
Patrice Chotard | 6ea9cdf | 2018-01-18 15:34:17 +0100 | [diff] [blame] | 195 | .mmcimask1 = true, |
Ludovic Barre | 59db5e2 | 2018-10-08 14:08:47 +0200 | [diff] [blame] | 196 | .irq_pio_mask = MCI_IRQ_PIO_MASK, |
Patrice Chotard | 7f7b550 | 2018-01-18 15:34:18 +0100 | [diff] [blame] | 197 | .start_err = MCI_STARTBITERR, |
Patrice Chotard | 11dfb97 | 2018-01-18 15:34:19 +0100 | [diff] [blame] | 198 | .opendrain = MCI_OD, |
Ludovic Barre | c3647fd | 2018-10-08 14:08:33 +0200 | [diff] [blame] | 199 | .init = mmci_variant_init, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 200 | }; |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 201 | |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 202 | static struct variant_data variant_ux500v2 = { |
| 203 | .fifosize = 30 * 4, |
| 204 | .fifohalfsize = 8 * 4, |
| 205 | .clkreg = MCI_CLK_ENABLE, |
| 206 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
Srinivas Kandagatla | e1412d8 | 2014-06-02 10:09:23 +0100 | [diff] [blame] | 207 | .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, |
Srinivas Kandagatla | e874064 | 2014-06-02 10:09:30 +0100 | [diff] [blame] | 208 | .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, |
Ludovic Barre | 0f24480 | 2018-10-08 14:08:45 +0200 | [diff] [blame] | 209 | .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, |
| 210 | .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, |
| 211 | .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, |
| 212 | .cmdreg_srsp = MCI_CPSM_RESPONSE, |
Linus Walleij | 5db3eee | 2016-10-25 11:06:05 +0200 | [diff] [blame] | 213 | .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 214 | .datalength_bits = 24, |
Ludovic Barre | c931d49 | 2018-10-08 14:08:43 +0200 | [diff] [blame] | 215 | .datactrl_blocksz = 11, |
Ludovic Barre | 9b27994 | 2018-10-08 14:08:46 +0200 | [diff] [blame] | 216 | .datactrl_dpsm_enable = MCI_DPSM_ENABLE, |
Linus Walleij | 5db3eee | 2016-10-25 11:06:05 +0200 | [diff] [blame] | 217 | .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, |
Srinivas Kandagatla | c735413 | 2014-08-22 05:55:16 +0100 | [diff] [blame] | 218 | .st_sdio = true, |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 219 | .st_clkdiv = true, |
| 220 | .blksz_datactrl16 = true, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 221 | .pwrreg_powerup = MCI_PWR_ON, |
Srinivas Kandagatla | dc6500b | 2014-06-02 10:09:47 +0100 | [diff] [blame] | 222 | .f_max = 100000000, |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 223 | .signal_direction = true, |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 224 | .pwrreg_clkgate = true, |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 225 | .busy_detect = true, |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 226 | .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, |
| 227 | .busy_detect_flag = MCI_ST_CARDBUSY, |
| 228 | .busy_detect_mask = MCI_ST_BUSYENDMASK, |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 229 | .pwrreg_nopower = true, |
Patrice Chotard | 6ea9cdf | 2018-01-18 15:34:17 +0100 | [diff] [blame] | 230 | .mmcimask1 = true, |
Ludovic Barre | 59db5e2 | 2018-10-08 14:08:47 +0200 | [diff] [blame] | 231 | .irq_pio_mask = MCI_IRQ_PIO_MASK, |
Patrice Chotard | 7f7b550 | 2018-01-18 15:34:18 +0100 | [diff] [blame] | 232 | .start_err = MCI_STARTBITERR, |
Patrice Chotard | 11dfb97 | 2018-01-18 15:34:19 +0100 | [diff] [blame] | 233 | .opendrain = MCI_OD, |
Ludovic Barre | c3647fd | 2018-10-08 14:08:33 +0200 | [diff] [blame] | 234 | .init = mmci_variant_init, |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 235 | }; |
| 236 | |
Patrice Chotard | 2a9d6c8 | 2018-01-18 15:34:21 +0100 | [diff] [blame] | 237 | static struct variant_data variant_stm32 = { |
| 238 | .fifosize = 32 * 4, |
| 239 | .fifohalfsize = 8 * 4, |
| 240 | .clkreg = MCI_CLK_ENABLE, |
| 241 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
| 242 | .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, |
| 243 | .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, |
Ludovic Barre | 0f24480 | 2018-10-08 14:08:45 +0200 | [diff] [blame] | 244 | .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, |
| 245 | .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, |
| 246 | .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, |
| 247 | .cmdreg_srsp = MCI_CPSM_RESPONSE, |
Ludovic Barre | 59db5e2 | 2018-10-08 14:08:47 +0200 | [diff] [blame] | 248 | .irq_pio_mask = MCI_IRQ_PIO_MASK, |
Patrice Chotard | 2a9d6c8 | 2018-01-18 15:34:21 +0100 | [diff] [blame] | 249 | .datalength_bits = 24, |
Ludovic Barre | c931d49 | 2018-10-08 14:08:43 +0200 | [diff] [blame] | 250 | .datactrl_blocksz = 11, |
Ludovic Barre | 9b27994 | 2018-10-08 14:08:46 +0200 | [diff] [blame] | 251 | .datactrl_dpsm_enable = MCI_DPSM_ENABLE, |
Patrice Chotard | 2a9d6c8 | 2018-01-18 15:34:21 +0100 | [diff] [blame] | 252 | .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, |
| 253 | .st_sdio = true, |
| 254 | .st_clkdiv = true, |
| 255 | .pwrreg_powerup = MCI_PWR_ON, |
| 256 | .f_max = 48000000, |
| 257 | .pwrreg_clkgate = true, |
| 258 | .pwrreg_nopower = true, |
Ludovic Barre | c3647fd | 2018-10-08 14:08:33 +0200 | [diff] [blame] | 259 | .init = mmci_variant_init, |
Patrice Chotard | 2a9d6c8 | 2018-01-18 15:34:21 +0100 | [diff] [blame] | 260 | }; |
| 261 | |
Srinivas Kandagatla | 55b604a | 2014-06-02 10:10:13 +0100 | [diff] [blame] | 262 | static struct variant_data variant_qcom = { |
| 263 | .fifosize = 16 * 4, |
| 264 | .fifohalfsize = 8 * 4, |
| 265 | .clkreg = MCI_CLK_ENABLE, |
| 266 | .clkreg_enable = MCI_QCOM_CLK_FLOWENA | |
| 267 | MCI_QCOM_CLK_SELECT_IN_FBCLK, |
| 268 | .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, |
| 269 | .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, |
Ludovic Barre | 0f24480 | 2018-10-08 14:08:45 +0200 | [diff] [blame] | 270 | .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, |
| 271 | .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, |
| 272 | .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, |
| 273 | .cmdreg_srsp = MCI_CPSM_RESPONSE, |
Linus Walleij | 5db3eee | 2016-10-25 11:06:05 +0200 | [diff] [blame] | 274 | .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, |
Srinivas Kandagatla | 55b604a | 2014-06-02 10:10:13 +0100 | [diff] [blame] | 275 | .blksz_datactrl4 = true, |
| 276 | .datalength_bits = 24, |
Ludovic Barre | c931d49 | 2018-10-08 14:08:43 +0200 | [diff] [blame] | 277 | .datactrl_blocksz = 11, |
Ludovic Barre | 9b27994 | 2018-10-08 14:08:46 +0200 | [diff] [blame] | 278 | .datactrl_dpsm_enable = MCI_DPSM_ENABLE, |
Srinivas Kandagatla | 55b604a | 2014-06-02 10:10:13 +0100 | [diff] [blame] | 279 | .pwrreg_powerup = MCI_PWR_UP, |
| 280 | .f_max = 208000000, |
| 281 | .explicit_mclk_control = true, |
| 282 | .qcom_fifo = true, |
Srinivas Kandagatla | 9cb1514 | 2014-07-29 03:50:30 +0100 | [diff] [blame] | 283 | .qcom_dml = true, |
Patrice Chotard | 6ea9cdf | 2018-01-18 15:34:17 +0100 | [diff] [blame] | 284 | .mmcimask1 = true, |
Ludovic Barre | 59db5e2 | 2018-10-08 14:08:47 +0200 | [diff] [blame] | 285 | .irq_pio_mask = MCI_IRQ_PIO_MASK, |
Patrice Chotard | 7f7b550 | 2018-01-18 15:34:18 +0100 | [diff] [blame] | 286 | .start_err = MCI_STARTBITERR, |
Patrice Chotard | 11dfb97 | 2018-01-18 15:34:19 +0100 | [diff] [blame] | 287 | .opendrain = MCI_ROD, |
Ulf Hansson | 29aba07 | 2018-07-16 13:08:18 +0200 | [diff] [blame] | 288 | .init = qcom_variant_init, |
Srinivas Kandagatla | 55b604a | 2014-06-02 10:10:13 +0100 | [diff] [blame] | 289 | }; |
| 290 | |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 291 | /* Busy detection for the ST Micro variant */ |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 292 | static int mmci_card_busy(struct mmc_host *mmc) |
| 293 | { |
| 294 | struct mmci_host *host = mmc_priv(mmc); |
| 295 | unsigned long flags; |
| 296 | int busy = 0; |
| 297 | |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 298 | spin_lock_irqsave(&host->lock, flags); |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 299 | if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 300 | busy = 1; |
| 301 | spin_unlock_irqrestore(&host->lock, flags); |
| 302 | |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 303 | return busy; |
| 304 | } |
| 305 | |
Ulf Hansson | f829c04 | 2013-09-04 09:01:15 +0100 | [diff] [blame] | 306 | static void mmci_reg_delay(struct mmci_host *host) |
| 307 | { |
| 308 | /* |
| 309 | * According to the spec, at least three feedback clock cycles |
| 310 | * of max 52 MHz must pass between two writes to the MMCICLOCK reg. |
| 311 | * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. |
| 312 | * Worst delay time during card init is at 100 kHz => 30 us. |
| 313 | * Worst delay time when up and running is at 25 MHz => 120 ns. |
| 314 | */ |
| 315 | if (host->cclk < 25000000) |
| 316 | udelay(30); |
| 317 | else |
| 318 | ndelay(120); |
| 319 | } |
| 320 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 321 | /* |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 322 | * This must be called with host->lock held |
| 323 | */ |
Ludovic Barre | cd3ee8c | 2018-10-08 14:08:42 +0200 | [diff] [blame] | 324 | void mmci_write_clkreg(struct mmci_host *host, u32 clk) |
Ulf Hansson | 7437cfa | 2012-01-18 09:17:27 +0100 | [diff] [blame] | 325 | { |
| 326 | if (host->clk_reg != clk) { |
| 327 | host->clk_reg = clk; |
| 328 | writel(clk, host->base + MMCICLOCK); |
| 329 | } |
| 330 | } |
| 331 | |
| 332 | /* |
| 333 | * This must be called with host->lock held |
| 334 | */ |
Ludovic Barre | cd3ee8c | 2018-10-08 14:08:42 +0200 | [diff] [blame] | 335 | void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) |
Ulf Hansson | 7437cfa | 2012-01-18 09:17:27 +0100 | [diff] [blame] | 336 | { |
| 337 | if (host->pwr_reg != pwr) { |
| 338 | host->pwr_reg = pwr; |
| 339 | writel(pwr, host->base + MMCIPOWER); |
| 340 | } |
| 341 | } |
| 342 | |
| 343 | /* |
| 344 | * This must be called with host->lock held |
| 345 | */ |
Ulf Hansson | 9cc639a | 2013-05-15 20:48:23 +0100 | [diff] [blame] | 346 | static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) |
| 347 | { |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 348 | /* Keep busy mode in DPSM if enabled */ |
| 349 | datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 350 | |
Ulf Hansson | 9cc639a | 2013-05-15 20:48:23 +0100 | [diff] [blame] | 351 | if (host->datactrl_reg != datactrl) { |
| 352 | host->datactrl_reg = datactrl; |
| 353 | writel(datactrl, host->base + MMCIDATACTRL); |
| 354 | } |
| 355 | } |
| 356 | |
| 357 | /* |
| 358 | * This must be called with host->lock held |
| 359 | */ |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 360 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) |
| 361 | { |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 362 | struct variant_data *variant = host->variant; |
| 363 | u32 clk = variant->clkreg; |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 364 | |
Ulf Hansson | c58a850 | 2013-05-13 15:40:03 +0100 | [diff] [blame] | 365 | /* Make sure cclk reflects the current calculated clock */ |
| 366 | host->cclk = 0; |
| 367 | |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 368 | if (desired) { |
Srinivas Kandagatla | 3f4e6f7 | 2014-06-02 10:09:55 +0100 | [diff] [blame] | 369 | if (variant->explicit_mclk_control) { |
| 370 | host->cclk = host->mclk; |
| 371 | } else if (desired >= host->mclk) { |
Linus Walleij | 991a86e | 2010-12-10 09:35:53 +0100 | [diff] [blame] | 372 | clk = MCI_CLK_BYPASS; |
Linus Walleij | 399bc48 | 2011-04-01 07:59:17 +0100 | [diff] [blame] | 373 | if (variant->st_clkdiv) |
| 374 | clk |= MCI_ST_UX500_NEG_EDGE; |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 375 | host->cclk = host->mclk; |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 376 | } else if (variant->st_clkdiv) { |
| 377 | /* |
| 378 | * DB8500 TRM says f = mclk / (clkdiv + 2) |
| 379 | * => clkdiv = (mclk / f) - 2 |
| 380 | * Round the divider up so we don't exceed the max |
| 381 | * frequency |
| 382 | */ |
| 383 | clk = DIV_ROUND_UP(host->mclk, desired) - 2; |
| 384 | if (clk >= 256) |
| 385 | clk = 255; |
| 386 | host->cclk = host->mclk / (clk + 2); |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 387 | } else { |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 388 | /* |
| 389 | * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) |
| 390 | * => clkdiv = mclk / (2 * f) - 1 |
| 391 | */ |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 392 | clk = host->mclk / (2 * desired) - 1; |
| 393 | if (clk >= 256) |
| 394 | clk = 255; |
| 395 | host->cclk = host->mclk / (2 * (clk + 1)); |
| 396 | } |
Rabin Vincent | 4380c14 | 2010-07-21 12:55:18 +0100 | [diff] [blame] | 397 | |
| 398 | clk |= variant->clkreg_enable; |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 399 | clk |= MCI_CLK_ENABLE; |
| 400 | /* This hasn't proven to be worthwhile */ |
| 401 | /* clk |= MCI_CLK_PWRSAVE; */ |
| 402 | } |
| 403 | |
Ulf Hansson | c58a850 | 2013-05-13 15:40:03 +0100 | [diff] [blame] | 404 | /* Set actual clock for debug */ |
| 405 | host->mmc->actual_clock = host->cclk; |
| 406 | |
Linus Walleij | 9e6c82c | 2009-09-14 12:57:11 +0100 | [diff] [blame] | 407 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
Linus Walleij | 771dc15 | 2010-04-08 07:38:52 +0100 | [diff] [blame] | 408 | clk |= MCI_4BIT_BUS; |
| 409 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) |
Srinivas Kandagatla | e1412d8 | 2014-06-02 10:09:23 +0100 | [diff] [blame] | 410 | clk |= variant->clkreg_8bit_bus_enable; |
Linus Walleij | 9e6c82c | 2009-09-14 12:57:11 +0100 | [diff] [blame] | 411 | |
Seungwon Jeon | 6dad6c9 | 2014-03-14 21:12:13 +0900 | [diff] [blame] | 412 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || |
| 413 | host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) |
Srinivas Kandagatla | e874064 | 2014-06-02 10:09:30 +0100 | [diff] [blame] | 414 | clk |= variant->clkreg_neg_edge_enable; |
Ulf Hansson | 6dbb6ee | 2013-01-07 15:30:44 +0100 | [diff] [blame] | 415 | |
Ulf Hansson | 7437cfa | 2012-01-18 09:17:27 +0100 | [diff] [blame] | 416 | mmci_write_clkreg(host, clk); |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 417 | } |
| 418 | |
Ludovic Barre | c3647fd | 2018-10-08 14:08:33 +0200 | [diff] [blame] | 419 | void mmci_dma_release(struct mmci_host *host) |
| 420 | { |
| 421 | if (host->ops && host->ops->dma_release) |
| 422 | host->ops->dma_release(host); |
| 423 | |
| 424 | host->use_dma = false; |
| 425 | } |
| 426 | |
| 427 | void mmci_dma_setup(struct mmci_host *host) |
| 428 | { |
| 429 | if (!host->ops || !host->ops->dma_setup) |
| 430 | return; |
| 431 | |
| 432 | if (host->ops->dma_setup(host)) |
| 433 | return; |
| 434 | |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 435 | /* initialize pre request cookie */ |
| 436 | host->next_cookie = 1; |
| 437 | |
Ludovic Barre | c3647fd | 2018-10-08 14:08:33 +0200 | [diff] [blame] | 438 | host->use_dma = true; |
| 439 | } |
| 440 | |
Ludovic Barre | e0da172 | 2018-10-08 14:08:41 +0200 | [diff] [blame] | 441 | /* |
| 442 | * Validate mmc prerequisites |
| 443 | */ |
| 444 | static int mmci_validate_data(struct mmci_host *host, |
| 445 | struct mmc_data *data) |
| 446 | { |
| 447 | if (!data) |
| 448 | return 0; |
| 449 | |
| 450 | if (!is_power_of_2(data->blksz)) { |
| 451 | dev_err(mmc_dev(host->mmc), |
| 452 | "unsupported block size (%d bytes)\n", data->blksz); |
| 453 | return -EINVAL; |
| 454 | } |
| 455 | |
| 456 | if (host->ops && host->ops->validate_data) |
| 457 | return host->ops->validate_data(host, data); |
| 458 | |
| 459 | return 0; |
| 460 | } |
| 461 | |
Ludovic Barre | 4798351 | 2018-10-08 14:08:36 +0200 | [diff] [blame] | 462 | int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next) |
| 463 | { |
| 464 | int err; |
| 465 | |
| 466 | if (!host->ops || !host->ops->prep_data) |
| 467 | return 0; |
| 468 | |
| 469 | err = host->ops->prep_data(host, data, next); |
| 470 | |
| 471 | if (next && !err) |
| 472 | data->host_cookie = ++host->next_cookie < 0 ? |
| 473 | 1 : host->next_cookie; |
| 474 | |
| 475 | return err; |
| 476 | } |
| 477 | |
| 478 | void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data, |
| 479 | int err) |
| 480 | { |
| 481 | if (host->ops && host->ops->unprep_data) |
| 482 | host->ops->unprep_data(host, data, err); |
| 483 | |
| 484 | data->host_cookie = 0; |
| 485 | } |
| 486 | |
Ludovic Barre | 0276996 | 2018-10-08 14:08:37 +0200 | [diff] [blame] | 487 | void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
| 488 | { |
| 489 | WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); |
| 490 | |
| 491 | if (host->ops && host->ops->get_next_data) |
| 492 | host->ops->get_next_data(host, data); |
| 493 | } |
| 494 | |
Ludovic Barre | 135ea30 | 2018-10-08 14:08:38 +0200 | [diff] [blame] | 495 | int mmci_dma_start(struct mmci_host *host, unsigned int datactrl) |
| 496 | { |
| 497 | struct mmc_data *data = host->data; |
| 498 | int ret; |
| 499 | |
| 500 | if (!host->use_dma) |
| 501 | return -EINVAL; |
| 502 | |
| 503 | ret = mmci_prep_data(host, data, false); |
| 504 | if (ret) |
| 505 | return ret; |
| 506 | |
| 507 | if (!host->ops || !host->ops->dma_start) |
| 508 | return -EINVAL; |
| 509 | |
| 510 | /* Okay, go for it. */ |
| 511 | dev_vdbg(mmc_dev(host->mmc), |
| 512 | "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", |
| 513 | data->sg_len, data->blksz, data->blocks, data->flags); |
| 514 | |
| 515 | host->ops->dma_start(host, &datactrl); |
| 516 | |
| 517 | /* Trigger the DMA transfer */ |
| 518 | mmci_write_datactrlreg(host, datactrl); |
| 519 | |
| 520 | /* |
| 521 | * Let the MMCI say when the data is ended and it's time |
| 522 | * to fire next DMA request. When that happens, MMCI will |
| 523 | * call mmci_data_end() |
| 524 | */ |
| 525 | writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, |
| 526 | host->base + MMCIMASK0); |
| 527 | return 0; |
| 528 | } |
| 529 | |
Ludovic Barre | 5a9f10c | 2018-10-08 14:08:39 +0200 | [diff] [blame] | 530 | void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) |
| 531 | { |
| 532 | if (!host->use_dma) |
| 533 | return; |
| 534 | |
| 535 | if (host->ops && host->ops->dma_finalize) |
| 536 | host->ops->dma_finalize(host, data); |
| 537 | } |
| 538 | |
Ludovic Barre | cfccc6a | 2018-10-08 14:08:40 +0200 | [diff] [blame] | 539 | void mmci_dma_error(struct mmci_host *host) |
| 540 | { |
| 541 | if (!host->use_dma) |
| 542 | return; |
| 543 | |
| 544 | if (host->ops && host->ops->dma_error) |
| 545 | host->ops->dma_error(host); |
| 546 | } |
| 547 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 548 | static void |
| 549 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) |
| 550 | { |
| 551 | writel(0, host->base + MMCICOMMAND); |
| 552 | |
Russell King | e47c222 | 2007-01-08 16:42:51 +0000 | [diff] [blame] | 553 | BUG_ON(host->data); |
| 554 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 555 | host->mrq = NULL; |
| 556 | host->cmd = NULL; |
| 557 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 558 | mmc_request_done(host->mmc, mrq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 559 | } |
| 560 | |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 561 | static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) |
| 562 | { |
| 563 | void __iomem *base = host->base; |
Patrice Chotard | 6ea9cdf | 2018-01-18 15:34:17 +0100 | [diff] [blame] | 564 | struct variant_data *variant = host->variant; |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 565 | |
| 566 | if (host->singleirq) { |
| 567 | unsigned int mask0 = readl(base + MMCIMASK0); |
| 568 | |
Ludovic Barre | 59db5e2 | 2018-10-08 14:08:47 +0200 | [diff] [blame] | 569 | mask0 &= ~variant->irq_pio_mask; |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 570 | mask0 |= mask; |
| 571 | |
| 572 | writel(mask0, base + MMCIMASK0); |
| 573 | } |
| 574 | |
Patrice Chotard | 6ea9cdf | 2018-01-18 15:34:17 +0100 | [diff] [blame] | 575 | if (variant->mmcimask1) |
| 576 | writel(mask, base + MMCIMASK1); |
| 577 | |
| 578 | host->mask1_reg = mask; |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 579 | } |
| 580 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 581 | static void mmci_stop_data(struct mmci_host *host) |
| 582 | { |
Ulf Hansson | 9cc639a | 2013-05-15 20:48:23 +0100 | [diff] [blame] | 583 | mmci_write_datactrlreg(host, 0); |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 584 | mmci_set_mask1(host, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 585 | host->data = NULL; |
| 586 | } |
| 587 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 588 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
| 589 | { |
| 590 | unsigned int flags = SG_MITER_ATOMIC; |
| 591 | |
| 592 | if (data->flags & MMC_DATA_READ) |
| 593 | flags |= SG_MITER_TO_SG; |
| 594 | else |
| 595 | flags |= SG_MITER_FROM_SG; |
| 596 | |
| 597 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); |
| 598 | } |
| 599 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 600 | /* |
| 601 | * All the DMA operation mode stuff goes inside this ifdef. |
| 602 | * This assumes that you have a generic DMA device interface, |
| 603 | * no custom DMA interfaces are supported. |
| 604 | */ |
| 605 | #ifdef CONFIG_DMA_ENGINE |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 606 | struct mmci_dmae_next { |
| 607 | struct dma_async_tx_descriptor *desc; |
| 608 | struct dma_chan *chan; |
| 609 | }; |
| 610 | |
| 611 | struct mmci_dmae_priv { |
| 612 | struct dma_chan *cur; |
| 613 | struct dma_chan *rx_channel; |
| 614 | struct dma_chan *tx_channel; |
| 615 | struct dma_async_tx_descriptor *desc_current; |
| 616 | struct mmci_dmae_next next_data; |
| 617 | }; |
| 618 | |
Ludovic Barre | c3647fd | 2018-10-08 14:08:33 +0200 | [diff] [blame] | 619 | int mmci_dmae_setup(struct mmci_host *host) |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 620 | { |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 621 | const char *rxname, *txname; |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 622 | struct mmci_dmae_priv *dmae; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 623 | |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 624 | dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); |
| 625 | if (!dmae) |
| 626 | return -ENOMEM; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 627 | |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 628 | host->dma_priv = dmae; |
| 629 | |
| 630 | dmae->rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), |
| 631 | "rx"); |
| 632 | dmae->tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), |
| 633 | "tx"); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 634 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 635 | /* |
| 636 | * If only an RX channel is specified, the driver will |
| 637 | * attempt to use it bidirectionally, however if it is |
| 638 | * is specified but cannot be located, DMA will be disabled. |
| 639 | */ |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 640 | if (dmae->rx_channel && !dmae->tx_channel) |
| 641 | dmae->tx_channel = dmae->rx_channel; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 642 | |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 643 | if (dmae->rx_channel) |
| 644 | rxname = dma_chan_name(dmae->rx_channel); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 645 | else |
| 646 | rxname = "none"; |
| 647 | |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 648 | if (dmae->tx_channel) |
| 649 | txname = dma_chan_name(dmae->tx_channel); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 650 | else |
| 651 | txname = "none"; |
| 652 | |
| 653 | dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", |
| 654 | rxname, txname); |
| 655 | |
| 656 | /* |
| 657 | * Limit the maximum segment size in any SG entry according to |
| 658 | * the parameters of the DMA engine device. |
| 659 | */ |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 660 | if (dmae->tx_channel) { |
| 661 | struct device *dev = dmae->tx_channel->device->dev; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 662 | unsigned int max_seg_size = dma_get_max_seg_size(dev); |
| 663 | |
| 664 | if (max_seg_size < host->mmc->max_seg_size) |
| 665 | host->mmc->max_seg_size = max_seg_size; |
| 666 | } |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 667 | if (dmae->rx_channel) { |
| 668 | struct device *dev = dmae->rx_channel->device->dev; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 669 | unsigned int max_seg_size = dma_get_max_seg_size(dev); |
| 670 | |
| 671 | if (max_seg_size < host->mmc->max_seg_size) |
| 672 | host->mmc->max_seg_size = max_seg_size; |
| 673 | } |
Srinivas Kandagatla | 9cb1514 | 2014-07-29 03:50:30 +0100 | [diff] [blame] | 674 | |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 675 | if (!dmae->tx_channel || !dmae->rx_channel) { |
Ludovic Barre | c3647fd | 2018-10-08 14:08:33 +0200 | [diff] [blame] | 676 | mmci_dmae_release(host); |
| 677 | return -EINVAL; |
| 678 | } |
| 679 | |
| 680 | return 0; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 681 | } |
| 682 | |
| 683 | /* |
Bill Pemberton | 6e0ee71 | 2012-11-19 13:26:03 -0500 | [diff] [blame] | 684 | * This is used in or so inline it |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 685 | * so it can be discarded. |
| 686 | */ |
Ludovic Barre | c3647fd | 2018-10-08 14:08:33 +0200 | [diff] [blame] | 687 | void mmci_dmae_release(struct mmci_host *host) |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 688 | { |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 689 | struct mmci_dmae_priv *dmae = host->dma_priv; |
| 690 | |
| 691 | if (dmae->rx_channel) |
| 692 | dma_release_channel(dmae->rx_channel); |
| 693 | if (dmae->tx_channel) |
| 694 | dma_release_channel(dmae->tx_channel); |
| 695 | dmae->rx_channel = dmae->tx_channel = NULL; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 696 | } |
| 697 | |
| 698 | static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) |
| 699 | { |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 700 | struct mmci_dmae_priv *dmae = host->dma_priv; |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 701 | struct dma_chan *chan; |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 702 | |
Heiner Kallweit | feeef09 | 2017-03-26 20:45:56 +0200 | [diff] [blame] | 703 | if (data->flags & MMC_DATA_READ) |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 704 | chan = dmae->rx_channel; |
Heiner Kallweit | feeef09 | 2017-03-26 20:45:56 +0200 | [diff] [blame] | 705 | else |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 706 | chan = dmae->tx_channel; |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 707 | |
Heiner Kallweit | feeef09 | 2017-03-26 20:45:56 +0200 | [diff] [blame] | 708 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, |
| 709 | mmc_get_dma_dir(data)); |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 710 | } |
| 711 | |
Ludovic Barre | cfccc6a | 2018-10-08 14:08:40 +0200 | [diff] [blame] | 712 | void mmci_dmae_error(struct mmci_host *host) |
Ludovic Barre | 7b2a6d5 | 2018-09-21 11:45:55 +0200 | [diff] [blame] | 713 | { |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 714 | struct mmci_dmae_priv *dmae = host->dma_priv; |
| 715 | |
Ludovic Barre | cfccc6a | 2018-10-08 14:08:40 +0200 | [diff] [blame] | 716 | if (!dma_inprogress(host)) |
Ludovic Barre | cdea194 | 2018-09-21 11:45:56 +0200 | [diff] [blame] | 717 | return; |
| 718 | |
Ludovic Barre | 7b2a6d5 | 2018-09-21 11:45:55 +0200 | [diff] [blame] | 719 | dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 720 | dmaengine_terminate_all(dmae->cur); |
Ludovic Barre | 7b2a6d5 | 2018-09-21 11:45:55 +0200 | [diff] [blame] | 721 | host->dma_in_progress = false; |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 722 | dmae->cur = NULL; |
| 723 | dmae->desc_current = NULL; |
Ludovic Barre | 7b2a6d5 | 2018-09-21 11:45:55 +0200 | [diff] [blame] | 724 | host->data->host_cookie = 0; |
| 725 | |
| 726 | mmci_dma_unmap(host, host->data); |
| 727 | } |
| 728 | |
Ludovic Barre | 5a9f10c | 2018-10-08 14:08:39 +0200 | [diff] [blame] | 729 | void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data) |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 730 | { |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 731 | struct mmci_dmae_priv *dmae = host->dma_priv; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 732 | u32 status; |
| 733 | int i; |
| 734 | |
Ludovic Barre | 5a9f10c | 2018-10-08 14:08:39 +0200 | [diff] [blame] | 735 | if (!dma_inprogress(host)) |
Ludovic Barre | cdea194 | 2018-09-21 11:45:56 +0200 | [diff] [blame] | 736 | return; |
| 737 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 738 | /* Wait up to 1ms for the DMA to complete */ |
| 739 | for (i = 0; ; i++) { |
| 740 | status = readl(host->base + MMCISTATUS); |
| 741 | if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) |
| 742 | break; |
| 743 | udelay(10); |
| 744 | } |
| 745 | |
| 746 | /* |
| 747 | * Check to see whether we still have some data left in the FIFO - |
| 748 | * this catches DMA controllers which are unable to monitor the |
| 749 | * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- |
| 750 | * contiguous buffers. On TX, we'll get a FIFO underrun error. |
| 751 | */ |
| 752 | if (status & MCI_RXDATAAVLBLMASK) { |
Ludovic Barre | cfccc6a | 2018-10-08 14:08:40 +0200 | [diff] [blame] | 753 | mmci_dma_error(host); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 754 | if (!data->error) |
| 755 | data->error = -EIO; |
Ludovic Barre | 7b2a6d5 | 2018-09-21 11:45:55 +0200 | [diff] [blame] | 756 | } else if (!data->host_cookie) { |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 757 | mmci_dma_unmap(host, data); |
Ludovic Barre | 7b2a6d5 | 2018-09-21 11:45:55 +0200 | [diff] [blame] | 758 | } |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 759 | |
| 760 | /* |
| 761 | * Use of DMA with scatter-gather is impossible. |
| 762 | * Give up with DMA and switch back to PIO mode. |
| 763 | */ |
| 764 | if (status & MCI_RXDATAAVLBLMASK) { |
| 765 | dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); |
| 766 | mmci_dma_release(host); |
| 767 | } |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 768 | |
Linus Walleij | e13934b | 2017-01-27 15:04:54 +0100 | [diff] [blame] | 769 | host->dma_in_progress = false; |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 770 | dmae->cur = NULL; |
| 771 | dmae->desc_current = NULL; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 772 | } |
| 773 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 774 | /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ |
Ludovic Barre | 4798351 | 2018-10-08 14:08:36 +0200 | [diff] [blame] | 775 | static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 776 | struct dma_chan **dma_chan, |
| 777 | struct dma_async_tx_descriptor **dma_desc) |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 778 | { |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 779 | struct mmci_dmae_priv *dmae = host->dma_priv; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 780 | struct variant_data *variant = host->variant; |
| 781 | struct dma_slave_config conf = { |
| 782 | .src_addr = host->phybase + MMCIFIFO, |
| 783 | .dst_addr = host->phybase + MMCIFIFO, |
| 784 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, |
| 785 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, |
| 786 | .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ |
| 787 | .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ |
Viresh Kumar | 258aea7 | 2012-02-01 16:12:19 +0530 | [diff] [blame] | 788 | .device_fc = false, |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 789 | }; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 790 | struct dma_chan *chan; |
| 791 | struct dma_device *device; |
| 792 | struct dma_async_tx_descriptor *desc; |
| 793 | int nr_sg; |
Srinivas Kandagatla | 9cb1514 | 2014-07-29 03:50:30 +0100 | [diff] [blame] | 794 | unsigned long flags = DMA_CTRL_ACK; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 795 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 796 | if (data->flags & MMC_DATA_READ) { |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 797 | conf.direction = DMA_DEV_TO_MEM; |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 798 | chan = dmae->rx_channel; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 799 | } else { |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 800 | conf.direction = DMA_MEM_TO_DEV; |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 801 | chan = dmae->tx_channel; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 802 | } |
| 803 | |
| 804 | /* If there's no DMA channel, fall back to PIO */ |
| 805 | if (!chan) |
| 806 | return -EINVAL; |
| 807 | |
| 808 | /* If less than or equal to the fifo size, don't bother with DMA */ |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 809 | if (data->blksz * data->blocks <= variant->fifosize) |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 810 | return -EINVAL; |
| 811 | |
| 812 | device = chan->device; |
Heiner Kallweit | feeef09 | 2017-03-26 20:45:56 +0200 | [diff] [blame] | 813 | nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, |
| 814 | mmc_get_dma_dir(data)); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 815 | if (nr_sg == 0) |
| 816 | return -EINVAL; |
| 817 | |
Srinivas Kandagatla | 9cb1514 | 2014-07-29 03:50:30 +0100 | [diff] [blame] | 818 | if (host->variant->qcom_dml) |
| 819 | flags |= DMA_PREP_INTERRUPT; |
| 820 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 821 | dmaengine_slave_config(chan, &conf); |
Alexandre Bounine | 1605282 | 2012-03-08 16:11:18 -0500 | [diff] [blame] | 822 | desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, |
Srinivas Kandagatla | 9cb1514 | 2014-07-29 03:50:30 +0100 | [diff] [blame] | 823 | conf.direction, flags); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 824 | if (!desc) |
| 825 | goto unmap_exit; |
| 826 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 827 | *dma_chan = chan; |
| 828 | *dma_desc = desc; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 829 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 830 | return 0; |
| 831 | |
| 832 | unmap_exit: |
Heiner Kallweit | feeef09 | 2017-03-26 20:45:56 +0200 | [diff] [blame] | 833 | dma_unmap_sg(device->dev, data->sg, data->sg_len, |
| 834 | mmc_get_dma_dir(data)); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 835 | return -ENOMEM; |
| 836 | } |
| 837 | |
Ludovic Barre | 4798351 | 2018-10-08 14:08:36 +0200 | [diff] [blame] | 838 | int mmci_dmae_prep_data(struct mmci_host *host, |
| 839 | struct mmc_data *data, |
| 840 | bool next) |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 841 | { |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 842 | struct mmci_dmae_priv *dmae = host->dma_priv; |
Ludovic Barre | ad7b891 | 2018-10-08 14:08:35 +0200 | [diff] [blame] | 843 | struct mmci_dmae_next *nd = &dmae->next_data; |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 844 | |
Ludovic Barre | 4798351 | 2018-10-08 14:08:36 +0200 | [diff] [blame] | 845 | if (!host->use_dma) |
| 846 | return -EINVAL; |
| 847 | |
Ludovic Barre | ad7b891 | 2018-10-08 14:08:35 +0200 | [diff] [blame] | 848 | if (next) |
Ludovic Barre | 4798351 | 2018-10-08 14:08:36 +0200 | [diff] [blame] | 849 | return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 850 | /* Check if next job is already prepared. */ |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 851 | if (dmae->cur && dmae->desc_current) |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 852 | return 0; |
| 853 | |
| 854 | /* No job were prepared thus do it now. */ |
Ludovic Barre | 4798351 | 2018-10-08 14:08:36 +0200 | [diff] [blame] | 855 | return _mmci_dmae_prep_data(host, data, &dmae->cur, |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 856 | &dmae->desc_current); |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 857 | } |
| 858 | |
Ludovic Barre | 135ea30 | 2018-10-08 14:08:38 +0200 | [diff] [blame] | 859 | int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl) |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 860 | { |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 861 | struct mmci_dmae_priv *dmae = host->dma_priv; |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 862 | struct mmc_data *data = host->data; |
| 863 | |
Linus Walleij | e13934b | 2017-01-27 15:04:54 +0100 | [diff] [blame] | 864 | host->dma_in_progress = true; |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 865 | dmaengine_submit(dmae->desc_current); |
| 866 | dma_async_issue_pending(dmae->cur); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 867 | |
Srinivas Kandagatla | 9cb1514 | 2014-07-29 03:50:30 +0100 | [diff] [blame] | 868 | if (host->variant->qcom_dml) |
| 869 | dml_start_xfer(host, data); |
| 870 | |
Ludovic Barre | 135ea30 | 2018-10-08 14:08:38 +0200 | [diff] [blame] | 871 | *datactrl |= MCI_DPSM_DMAENABLE; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 872 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 873 | return 0; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 874 | } |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 875 | |
Ludovic Barre | 0276996 | 2018-10-08 14:08:37 +0200 | [diff] [blame] | 876 | void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data) |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 877 | { |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 878 | struct mmci_dmae_priv *dmae = host->dma_priv; |
| 879 | struct mmci_dmae_next *next = &dmae->next_data; |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 880 | |
Ludovic Barre | c3647fd | 2018-10-08 14:08:33 +0200 | [diff] [blame] | 881 | if (!host->use_dma) |
| 882 | return; |
| 883 | |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 884 | WARN_ON(!data->host_cookie && (next->desc || next->chan)); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 885 | |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 886 | dmae->desc_current = next->desc; |
| 887 | dmae->cur = next->chan; |
| 888 | next->desc = NULL; |
| 889 | next->chan = NULL; |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 890 | } |
| 891 | |
Ludovic Barre | 4798351 | 2018-10-08 14:08:36 +0200 | [diff] [blame] | 892 | void mmci_dmae_unprep_data(struct mmci_host *host, |
| 893 | struct mmc_data *data, int err) |
| 894 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 895 | { |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 896 | struct mmci_dmae_priv *dmae = host->dma_priv; |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 897 | |
Ludovic Barre | 4798351 | 2018-10-08 14:08:36 +0200 | [diff] [blame] | 898 | if (!host->use_dma) |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 899 | return; |
| 900 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 901 | mmci_dma_unmap(host, data); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 902 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 903 | if (err) { |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 904 | struct mmci_dmae_next *next = &dmae->next_data; |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 905 | struct dma_chan *chan; |
| 906 | if (data->flags & MMC_DATA_READ) |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 907 | chan = dmae->rx_channel; |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 908 | else |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 909 | chan = dmae->tx_channel; |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 910 | dmaengine_terminate_all(chan); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 911 | |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 912 | if (dmae->desc_current == next->desc) |
| 913 | dmae->desc_current = NULL; |
Srinivas Kandagatla | b5c16a6 | 2014-10-08 12:25:17 +0100 | [diff] [blame] | 914 | |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 915 | if (dmae->cur == next->chan) { |
Linus Walleij | e13934b | 2017-01-27 15:04:54 +0100 | [diff] [blame] | 916 | host->dma_in_progress = false; |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 917 | dmae->cur = NULL; |
Linus Walleij | e13934b | 2017-01-27 15:04:54 +0100 | [diff] [blame] | 918 | } |
Srinivas Kandagatla | b5c16a6 | 2014-10-08 12:25:17 +0100 | [diff] [blame] | 919 | |
Ludovic Barre | a813f2a | 2018-10-08 14:08:34 +0200 | [diff] [blame] | 920 | next->desc = NULL; |
| 921 | next->chan = NULL; |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 922 | } |
| 923 | } |
| 924 | |
Ludovic Barre | c3647fd | 2018-10-08 14:08:33 +0200 | [diff] [blame] | 925 | static struct mmci_host_ops mmci_variant_ops = { |
Ludovic Barre | 4798351 | 2018-10-08 14:08:36 +0200 | [diff] [blame] | 926 | .prep_data = mmci_dmae_prep_data, |
| 927 | .unprep_data = mmci_dmae_unprep_data, |
Ludovic Barre | 0276996 | 2018-10-08 14:08:37 +0200 | [diff] [blame] | 928 | .get_next_data = mmci_dmae_get_next_data, |
Ludovic Barre | c3647fd | 2018-10-08 14:08:33 +0200 | [diff] [blame] | 929 | .dma_setup = mmci_dmae_setup, |
| 930 | .dma_release = mmci_dmae_release, |
Ludovic Barre | 135ea30 | 2018-10-08 14:08:38 +0200 | [diff] [blame] | 931 | .dma_start = mmci_dmae_start, |
Ludovic Barre | 5a9f10c | 2018-10-08 14:08:39 +0200 | [diff] [blame] | 932 | .dma_finalize = mmci_dmae_finalize, |
Ludovic Barre | cfccc6a | 2018-10-08 14:08:40 +0200 | [diff] [blame] | 933 | .dma_error = mmci_dmae_error, |
Ludovic Barre | c3647fd | 2018-10-08 14:08:33 +0200 | [diff] [blame] | 934 | }; |
| 935 | |
| 936 | void mmci_variant_init(struct mmci_host *host) |
| 937 | { |
| 938 | host->ops = &mmci_variant_ops; |
| 939 | } |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 940 | #endif |
| 941 | |
Ludovic Barre | 4798351 | 2018-10-08 14:08:36 +0200 | [diff] [blame] | 942 | static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) |
| 943 | { |
| 944 | struct mmci_host *host = mmc_priv(mmc); |
| 945 | struct mmc_data *data = mrq->data; |
| 946 | |
| 947 | if (!data) |
| 948 | return; |
| 949 | |
| 950 | WARN_ON(data->host_cookie); |
| 951 | |
| 952 | if (mmci_validate_data(host, data)) |
| 953 | return; |
| 954 | |
| 955 | mmci_prep_data(host, data, true); |
| 956 | } |
| 957 | |
| 958 | static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, |
| 959 | int err) |
| 960 | { |
| 961 | struct mmci_host *host = mmc_priv(mmc); |
| 962 | struct mmc_data *data = mrq->data; |
| 963 | |
| 964 | if (!data || !data->host_cookie) |
| 965 | return; |
| 966 | |
| 967 | mmci_unprep_data(host, data, err); |
| 968 | } |
| 969 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 970 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
| 971 | { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 972 | struct variant_data *variant = host->variant; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 973 | unsigned int datactrl, timeout, irqmask; |
Russell King | 7b09cda | 2005-07-01 12:02:59 +0100 | [diff] [blame] | 974 | unsigned long long clks; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 975 | void __iomem *base; |
Russell King | 3bc87f2 | 2006-08-27 13:51:28 +0100 | [diff] [blame] | 976 | int blksz_bits; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 977 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 978 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
| 979 | data->blksz, data->blocks, data->flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 980 | |
| 981 | host->data = data; |
Rabin Vincent | 528320d | 2010-07-21 12:49:49 +0100 | [diff] [blame] | 982 | host->size = data->blksz * data->blocks; |
Russell King | 51d4375 | 2011-01-27 10:56:52 +0000 | [diff] [blame] | 983 | data->bytes_xfered = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 984 | |
Russell King | 7b09cda | 2005-07-01 12:02:59 +0100 | [diff] [blame] | 985 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
Srinivas Kandagatla | c4a3576 | 2014-06-02 10:08:39 +0100 | [diff] [blame] | 986 | do_div(clks, NSEC_PER_SEC); |
Russell King | 7b09cda | 2005-07-01 12:02:59 +0100 | [diff] [blame] | 987 | |
| 988 | timeout = data->timeout_clks + (unsigned int)clks; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 989 | |
| 990 | base = host->base; |
| 991 | writel(timeout, base + MMCIDATATIMER); |
| 992 | writel(host->size, base + MMCIDATALENGTH); |
| 993 | |
Russell King | 3bc87f2 | 2006-08-27 13:51:28 +0100 | [diff] [blame] | 994 | blksz_bits = ffs(data->blksz) - 1; |
| 995 | BUG_ON(1 << blksz_bits != data->blksz); |
| 996 | |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 997 | if (variant->blksz_datactrl16) |
Ludovic Barre | 9b27994 | 2018-10-08 14:08:46 +0200 | [diff] [blame] | 998 | datactrl = variant->datactrl_dpsm_enable | (data->blksz << 16); |
Srinivas Kandagatla | ff78323 | 2014-06-02 10:09:06 +0100 | [diff] [blame] | 999 | else if (variant->blksz_datactrl4) |
Ludovic Barre | 9b27994 | 2018-10-08 14:08:46 +0200 | [diff] [blame] | 1000 | datactrl = variant->datactrl_dpsm_enable | (data->blksz << 4); |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 1001 | else |
Ludovic Barre | 9b27994 | 2018-10-08 14:08:46 +0200 | [diff] [blame] | 1002 | datactrl = variant->datactrl_dpsm_enable | blksz_bits << 4; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 1003 | |
| 1004 | if (data->flags & MMC_DATA_READ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1005 | datactrl |= MCI_DPSM_DIRECTION; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 1006 | |
Srinivas Kandagatla | c735413 | 2014-08-22 05:55:16 +0100 | [diff] [blame] | 1007 | if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { |
| 1008 | u32 clk; |
Ulf Hansson | 7258db7 | 2011-12-13 17:05:28 +0100 | [diff] [blame] | 1009 | |
Srinivas Kandagatla | c735413 | 2014-08-22 05:55:16 +0100 | [diff] [blame] | 1010 | datactrl |= variant->datactrl_mask_sdio; |
Ulf Hansson | 06c1a12 | 2012-10-12 14:01:50 +0100 | [diff] [blame] | 1011 | |
Srinivas Kandagatla | c735413 | 2014-08-22 05:55:16 +0100 | [diff] [blame] | 1012 | /* |
| 1013 | * The ST Micro variant for SDIO small write transfers |
| 1014 | * needs to have clock H/W flow control disabled, |
| 1015 | * otherwise the transfer will not start. The threshold |
| 1016 | * depends on the rate of MCLK. |
| 1017 | */ |
| 1018 | if (variant->st_sdio && data->flags & MMC_DATA_WRITE && |
| 1019 | (host->size < 8 || |
| 1020 | (host->size <= 8 && host->mclk > 50000000))) |
| 1021 | clk = host->clk_reg & ~variant->clkreg_enable; |
| 1022 | else |
| 1023 | clk = host->clk_reg | variant->clkreg_enable; |
| 1024 | |
| 1025 | mmci_write_clkreg(host, clk); |
| 1026 | } |
Ulf Hansson | 06c1a12 | 2012-10-12 14:01:50 +0100 | [diff] [blame] | 1027 | |
Seungwon Jeon | 6dad6c9 | 2014-03-14 21:12:13 +0900 | [diff] [blame] | 1028 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || |
| 1029 | host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) |
Srinivas Kandagatla | e17dca2 | 2014-06-02 10:09:15 +0100 | [diff] [blame] | 1030 | datactrl |= variant->datactrl_mask_ddrmode; |
Ulf Hansson | 6dbb6ee | 2013-01-07 15:30:44 +0100 | [diff] [blame] | 1031 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 1032 | /* |
| 1033 | * Attempt to use DMA operation mode, if this |
| 1034 | * should fail, fall back to PIO mode |
| 1035 | */ |
Ludovic Barre | 135ea30 | 2018-10-08 14:08:38 +0200 | [diff] [blame] | 1036 | if (!mmci_dma_start(host, datactrl)) |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 1037 | return; |
| 1038 | |
| 1039 | /* IRQ mode, map the SG list for CPU reading/writing */ |
| 1040 | mmci_init_sg(host, data); |
| 1041 | |
| 1042 | if (data->flags & MMC_DATA_READ) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1043 | irqmask = MCI_RXFIFOHALFFULLMASK; |
Russell King | 0425a14 | 2006-02-16 16:48:31 +0000 | [diff] [blame] | 1044 | |
| 1045 | /* |
Russell King | c4d877c | 2011-01-27 09:50:13 +0000 | [diff] [blame] | 1046 | * If we have less than the fifo 'half-full' threshold to |
| 1047 | * transfer, trigger a PIO interrupt as soon as any data |
| 1048 | * is available. |
Russell King | 0425a14 | 2006-02-16 16:48:31 +0000 | [diff] [blame] | 1049 | */ |
Russell King | c4d877c | 2011-01-27 09:50:13 +0000 | [diff] [blame] | 1050 | if (host->size < variant->fifohalfsize) |
Russell King | 0425a14 | 2006-02-16 16:48:31 +0000 | [diff] [blame] | 1051 | irqmask |= MCI_RXDATAAVLBLMASK; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1052 | } else { |
| 1053 | /* |
| 1054 | * We don't actually need to include "FIFO empty" here |
| 1055 | * since its implicit in "FIFO half empty". |
| 1056 | */ |
| 1057 | irqmask = MCI_TXFIFOHALFEMPTYMASK; |
| 1058 | } |
| 1059 | |
Ulf Hansson | 9cc639a | 2013-05-15 20:48:23 +0100 | [diff] [blame] | 1060 | mmci_write_datactrlreg(host, datactrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1061 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1062 | mmci_set_mask1(host, irqmask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1063 | } |
| 1064 | |
| 1065 | static void |
| 1066 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) |
| 1067 | { |
| 1068 | void __iomem *base = host->base; |
| 1069 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1070 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1071 | cmd->opcode, cmd->arg, cmd->flags); |
| 1072 | |
Ludovic Barre | 0f24480 | 2018-10-08 14:08:45 +0200 | [diff] [blame] | 1073 | if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1074 | writel(0, base + MMCICOMMAND); |
Srinivas Kandagatla | 6adb2a8 | 2014-06-02 10:08:57 +0100 | [diff] [blame] | 1075 | mmci_reg_delay(host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1076 | } |
| 1077 | |
Ludovic Barre | 0f24480 | 2018-10-08 14:08:45 +0200 | [diff] [blame] | 1078 | c |= cmd->opcode | host->variant->cmdreg_cpsm_enable; |
Russell King | e922517 | 2006-02-02 12:23:12 +0000 | [diff] [blame] | 1079 | if (cmd->flags & MMC_RSP_PRESENT) { |
| 1080 | if (cmd->flags & MMC_RSP_136) |
Ludovic Barre | 0f24480 | 2018-10-08 14:08:45 +0200 | [diff] [blame] | 1081 | c |= host->variant->cmdreg_lrsp_crc; |
| 1082 | else if (cmd->flags & MMC_RSP_CRC) |
| 1083 | c |= host->variant->cmdreg_srsp_crc; |
| 1084 | else |
| 1085 | c |= host->variant->cmdreg_srsp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1086 | } |
| 1087 | if (/*interrupt*/0) |
| 1088 | c |= MCI_CPSM_INTERRUPT; |
| 1089 | |
Srinivas Kandagatla | ae7b006 | 2014-06-02 10:09:39 +0100 | [diff] [blame] | 1090 | if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) |
| 1091 | c |= host->variant->data_cmd_enable; |
| 1092 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1093 | host->cmd = cmd; |
| 1094 | |
| 1095 | writel(cmd->arg, base + MMCIARGUMENT); |
| 1096 | writel(c, base + MMCICOMMAND); |
| 1097 | } |
| 1098 | |
| 1099 | static void |
| 1100 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, |
| 1101 | unsigned int status) |
| 1102 | { |
Ludovic Barre | daf9713 | 2018-10-08 14:08:44 +0200 | [diff] [blame] | 1103 | unsigned int status_err; |
| 1104 | |
Ulf Hansson | 1cb9da5 | 2014-06-12 14:42:23 +0200 | [diff] [blame] | 1105 | /* Make sure we have data to handle */ |
| 1106 | if (!data) |
| 1107 | return; |
| 1108 | |
Linus Walleij | f20f8f21 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 1109 | /* First check for errors */ |
Ludovic Barre | daf9713 | 2018-10-08 14:08:44 +0200 | [diff] [blame] | 1110 | status_err = status & (host->variant->start_err | |
| 1111 | MCI_DATACRCFAIL | MCI_DATATIMEOUT | |
| 1112 | MCI_TXUNDERRUN | MCI_RXOVERRUN); |
| 1113 | |
| 1114 | if (status_err) { |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 1115 | u32 remain, success; |
Linus Walleij | f20f8f21 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 1116 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 1117 | /* Terminate the DMA transfer */ |
Ludovic Barre | cfccc6a | 2018-10-08 14:08:40 +0200 | [diff] [blame] | 1118 | mmci_dma_error(host); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 1119 | |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 1120 | /* |
| 1121 | * Calculate how far we are into the transfer. Note that |
| 1122 | * the data counter gives the number of bytes transferred |
| 1123 | * on the MMC bus, not on the host side. On reads, this |
| 1124 | * can be as much as a FIFO-worth of data ahead. This |
| 1125 | * matters for FIFO overruns only. |
| 1126 | */ |
Ludovic Barre | b79220b | 2018-10-08 14:08:49 +0200 | [diff] [blame] | 1127 | if (!host->variant->datacnt_useless) { |
| 1128 | remain = readl(host->base + MMCIDATACNT); |
| 1129 | success = data->blksz * data->blocks - remain; |
| 1130 | } else { |
| 1131 | success = 0; |
| 1132 | } |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 1133 | |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 1134 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", |
Ludovic Barre | daf9713 | 2018-10-08 14:08:44 +0200 | [diff] [blame] | 1135 | status_err, success); |
| 1136 | if (status_err & MCI_DATACRCFAIL) { |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 1137 | /* Last block was not successful */ |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 1138 | success -= 1; |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 1139 | data->error = -EILSEQ; |
Ludovic Barre | daf9713 | 2018-10-08 14:08:44 +0200 | [diff] [blame] | 1140 | } else if (status_err & MCI_DATATIMEOUT) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 1141 | data->error = -ETIMEDOUT; |
Ludovic Barre | daf9713 | 2018-10-08 14:08:44 +0200 | [diff] [blame] | 1142 | } else if (status_err & MCI_STARTBITERR) { |
Linus Walleij | 757df74 | 2011-06-30 15:10:21 +0100 | [diff] [blame] | 1143 | data->error = -ECOMM; |
Ludovic Barre | daf9713 | 2018-10-08 14:08:44 +0200 | [diff] [blame] | 1144 | } else if (status_err & MCI_TXUNDERRUN) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 1145 | data->error = -EIO; |
Ludovic Barre | daf9713 | 2018-10-08 14:08:44 +0200 | [diff] [blame] | 1146 | } else if (status_err & MCI_RXOVERRUN) { |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 1147 | if (success > host->variant->fifosize) |
| 1148 | success -= host->variant->fifosize; |
| 1149 | else |
| 1150 | success = 0; |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 1151 | data->error = -EIO; |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 1152 | } |
Russell King | 51d4375 | 2011-01-27 10:56:52 +0000 | [diff] [blame] | 1153 | data->bytes_xfered = round_down(success, data->blksz); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1154 | } |
Linus Walleij | f20f8f21 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 1155 | |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 1156 | if (status & MCI_DATABLOCKEND) |
| 1157 | dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); |
Linus Walleij | f20f8f21 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 1158 | |
Russell King | ccff9b5 | 2011-01-30 21:03:50 +0000 | [diff] [blame] | 1159 | if (status & MCI_DATAEND || data->error) { |
Ludovic Barre | cdea194 | 2018-09-21 11:45:56 +0200 | [diff] [blame] | 1160 | mmci_dma_finalize(host, data); |
| 1161 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1162 | mmci_stop_data(host); |
| 1163 | |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 1164 | if (!data->error) |
| 1165 | /* The error clause is handled above, success! */ |
Russell King | 51d4375 | 2011-01-27 10:56:52 +0000 | [diff] [blame] | 1166 | data->bytes_xfered = data->blksz * data->blocks; |
Linus Walleij | f20f8f21 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 1167 | |
Ulf Hansson | 024629c | 2013-05-13 15:40:56 +0100 | [diff] [blame] | 1168 | if (!data->stop || host->mrq->sbc) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1169 | mmci_request_end(host, data->mrq); |
| 1170 | } else { |
| 1171 | mmci_start_command(host, data->stop, 0); |
| 1172 | } |
| 1173 | } |
| 1174 | } |
| 1175 | |
| 1176 | static void |
| 1177 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, |
| 1178 | unsigned int status) |
| 1179 | { |
| 1180 | void __iomem *base = host->base; |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1181 | bool sbc; |
Ulf Hansson | ad82bfe | 2014-06-12 15:01:57 +0200 | [diff] [blame] | 1182 | |
| 1183 | if (!cmd) |
| 1184 | return; |
| 1185 | |
| 1186 | sbc = (cmd == host->mrq->sbc); |
Ulf Hansson | ad82bfe | 2014-06-12 15:01:57 +0200 | [diff] [blame] | 1187 | |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1188 | /* |
| 1189 | * We need to be one of these interrupts to be considered worth |
| 1190 | * handling. Note that we tag on any latent IRQs postponed |
| 1191 | * due to waiting for busy status. |
| 1192 | */ |
| 1193 | if (!((status|host->busy_status) & |
| 1194 | (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND))) |
Ulf Hansson | ad82bfe | 2014-06-12 15:01:57 +0200 | [diff] [blame] | 1195 | return; |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame] | 1196 | |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1197 | /* |
| 1198 | * ST Micro variant: handle busy detection. |
| 1199 | */ |
| 1200 | if (host->variant->busy_detect) { |
| 1201 | bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY); |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame] | 1202 | |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1203 | /* We are busy with a command, return */ |
| 1204 | if (host->busy_status && |
| 1205 | (status & host->variant->busy_detect_flag)) |
| 1206 | return; |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame] | 1207 | |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1208 | /* |
| 1209 | * We were not busy, but we now got a busy response on |
| 1210 | * something that was not an error, and we double-check |
| 1211 | * that the special busy status bit is still set before |
| 1212 | * proceeding. |
| 1213 | */ |
| 1214 | if (!host->busy_status && busy_resp && |
| 1215 | !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && |
| 1216 | (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { |
Jean-Nicolas Graux | 5cad24d | 2017-02-07 12:12:41 +0100 | [diff] [blame] | 1217 | |
| 1218 | /* Clear the busy start IRQ */ |
| 1219 | writel(host->variant->busy_detect_mask, |
| 1220 | host->base + MMCICLEAR); |
| 1221 | |
| 1222 | /* Unmask the busy end IRQ */ |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1223 | writel(readl(base + MMCIMASK0) | |
| 1224 | host->variant->busy_detect_mask, |
| 1225 | base + MMCIMASK0); |
| 1226 | /* |
| 1227 | * Now cache the last response status code (until |
| 1228 | * the busy bit goes low), and return. |
| 1229 | */ |
| 1230 | host->busy_status = |
| 1231 | status & (MCI_CMDSENT|MCI_CMDRESPEND); |
| 1232 | return; |
| 1233 | } |
| 1234 | |
| 1235 | /* |
| 1236 | * At this point we are not busy with a command, we have |
Jean-Nicolas Graux | 5cad24d | 2017-02-07 12:12:41 +0100 | [diff] [blame] | 1237 | * not received a new busy request, clear and mask the busy |
| 1238 | * end IRQ and fall through to process the IRQ. |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1239 | */ |
| 1240 | if (host->busy_status) { |
Jean-Nicolas Graux | 5cad24d | 2017-02-07 12:12:41 +0100 | [diff] [blame] | 1241 | |
| 1242 | writel(host->variant->busy_detect_mask, |
| 1243 | host->base + MMCICLEAR); |
| 1244 | |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1245 | writel(readl(base + MMCIMASK0) & |
| 1246 | ~host->variant->busy_detect_mask, |
| 1247 | base + MMCIMASK0); |
| 1248 | host->busy_status = 0; |
| 1249 | } |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame] | 1250 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1251 | |
| 1252 | host->cmd = NULL; |
| 1253 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1254 | if (status & MCI_CMDTIMEOUT) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 1255 | cmd->error = -ETIMEDOUT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1256 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 1257 | cmd->error = -EILSEQ; |
Russell King - ARM Linux | 9047b43 | 2011-01-11 16:35:56 +0000 | [diff] [blame] | 1258 | } else { |
| 1259 | cmd->resp[0] = readl(base + MMCIRESPONSE0); |
| 1260 | cmd->resp[1] = readl(base + MMCIRESPONSE1); |
| 1261 | cmd->resp[2] = readl(base + MMCIRESPONSE2); |
| 1262 | cmd->resp[3] = readl(base + MMCIRESPONSE3); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1263 | } |
| 1264 | |
Ulf Hansson | 024629c | 2013-05-13 15:40:56 +0100 | [diff] [blame] | 1265 | if ((!sbc && !cmd->data) || cmd->error) { |
Ulf Hansson | 3b6e3c7 | 2011-12-13 16:58:43 +0100 | [diff] [blame] | 1266 | if (host->data) { |
| 1267 | /* Terminate the DMA transfer */ |
Ludovic Barre | cfccc6a | 2018-10-08 14:08:40 +0200 | [diff] [blame] | 1268 | mmci_dma_error(host); |
Ludovic Barre | 7b2a6d5 | 2018-09-21 11:45:55 +0200 | [diff] [blame] | 1269 | |
Russell King | e47c222 | 2007-01-08 16:42:51 +0000 | [diff] [blame] | 1270 | mmci_stop_data(host); |
Ulf Hansson | 3b6e3c7 | 2011-12-13 16:58:43 +0100 | [diff] [blame] | 1271 | } |
Ulf Hansson | 024629c | 2013-05-13 15:40:56 +0100 | [diff] [blame] | 1272 | mmci_request_end(host, host->mrq); |
| 1273 | } else if (sbc) { |
| 1274 | mmci_start_command(host, host->mrq->cmd, 0); |
Ludovic Barre | d214154 | 2018-10-08 14:08:48 +0200 | [diff] [blame] | 1275 | } else if (!host->variant->datactrl_first && |
| 1276 | !(cmd->data->flags & MMC_DATA_READ)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1277 | mmci_start_data(host, cmd->data); |
| 1278 | } |
| 1279 | } |
| 1280 | |
Srinivas Kandagatla | 9c34b73 | 2014-06-02 10:10:04 +0100 | [diff] [blame] | 1281 | static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) |
| 1282 | { |
| 1283 | return remain - (readl(host->base + MMCIFIFOCNT) << 2); |
| 1284 | } |
| 1285 | |
| 1286 | static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) |
| 1287 | { |
| 1288 | /* |
| 1289 | * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses |
| 1290 | * from the fifo range should be used |
| 1291 | */ |
| 1292 | if (status & MCI_RXFIFOHALFFULL) |
| 1293 | return host->variant->fifohalfsize; |
| 1294 | else if (status & MCI_RXDATAAVLBL) |
| 1295 | return 4; |
| 1296 | |
| 1297 | return 0; |
| 1298 | } |
| 1299 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1300 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) |
| 1301 | { |
| 1302 | void __iomem *base = host->base; |
| 1303 | char *ptr = buffer; |
Srinivas Kandagatla | 9c34b73 | 2014-06-02 10:10:04 +0100 | [diff] [blame] | 1304 | u32 status = readl(host->base + MMCISTATUS); |
Linus Walleij | 26eed9a | 2008-04-26 23:39:44 +0100 | [diff] [blame] | 1305 | int host_remain = host->size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1306 | |
| 1307 | do { |
Srinivas Kandagatla | 9c34b73 | 2014-06-02 10:10:04 +0100 | [diff] [blame] | 1308 | int count = host->get_rx_fifocnt(host, status, host_remain); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1309 | |
| 1310 | if (count > remain) |
| 1311 | count = remain; |
| 1312 | |
| 1313 | if (count <= 0) |
| 1314 | break; |
| 1315 | |
Ulf Hansson | 393e5e2 | 2011-12-13 17:08:04 +0100 | [diff] [blame] | 1316 | /* |
| 1317 | * SDIO especially may want to send something that is |
| 1318 | * not divisible by 4 (as opposed to card sectors |
| 1319 | * etc). Therefore make sure to always read the last bytes |
| 1320 | * while only doing full 32-bit reads towards the FIFO. |
| 1321 | */ |
| 1322 | if (unlikely(count & 0x3)) { |
| 1323 | if (count < 4) { |
| 1324 | unsigned char buf[4]; |
Davide Ciminaghi | 4b85da0 | 2012-12-10 14:47:21 +0100 | [diff] [blame] | 1325 | ioread32_rep(base + MMCIFIFO, buf, 1); |
Ulf Hansson | 393e5e2 | 2011-12-13 17:08:04 +0100 | [diff] [blame] | 1326 | memcpy(ptr, buf, count); |
| 1327 | } else { |
Davide Ciminaghi | 4b85da0 | 2012-12-10 14:47:21 +0100 | [diff] [blame] | 1328 | ioread32_rep(base + MMCIFIFO, ptr, count >> 2); |
Ulf Hansson | 393e5e2 | 2011-12-13 17:08:04 +0100 | [diff] [blame] | 1329 | count &= ~0x3; |
| 1330 | } |
| 1331 | } else { |
Davide Ciminaghi | 4b85da0 | 2012-12-10 14:47:21 +0100 | [diff] [blame] | 1332 | ioread32_rep(base + MMCIFIFO, ptr, count >> 2); |
Ulf Hansson | 393e5e2 | 2011-12-13 17:08:04 +0100 | [diff] [blame] | 1333 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1334 | |
| 1335 | ptr += count; |
| 1336 | remain -= count; |
Linus Walleij | 26eed9a | 2008-04-26 23:39:44 +0100 | [diff] [blame] | 1337 | host_remain -= count; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1338 | |
| 1339 | if (remain == 0) |
| 1340 | break; |
| 1341 | |
| 1342 | status = readl(base + MMCISTATUS); |
| 1343 | } while (status & MCI_RXDATAAVLBL); |
| 1344 | |
| 1345 | return ptr - buffer; |
| 1346 | } |
| 1347 | |
| 1348 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) |
| 1349 | { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 1350 | struct variant_data *variant = host->variant; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1351 | void __iomem *base = host->base; |
| 1352 | char *ptr = buffer; |
| 1353 | |
| 1354 | do { |
| 1355 | unsigned int count, maxcnt; |
| 1356 | |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 1357 | maxcnt = status & MCI_TXFIFOEMPTY ? |
| 1358 | variant->fifosize : variant->fifohalfsize; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1359 | count = min(remain, maxcnt); |
| 1360 | |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 1361 | /* |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 1362 | * SDIO especially may want to send something that is |
| 1363 | * not divisible by 4 (as opposed to card sectors |
| 1364 | * etc), and the FIFO only accept full 32-bit writes. |
| 1365 | * So compensate by adding +3 on the count, a single |
| 1366 | * byte become a 32bit write, 7 bytes will be two |
| 1367 | * 32bit writes etc. |
| 1368 | */ |
Davide Ciminaghi | 4b85da0 | 2012-12-10 14:47:21 +0100 | [diff] [blame] | 1369 | iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1370 | |
| 1371 | ptr += count; |
| 1372 | remain -= count; |
| 1373 | |
| 1374 | if (remain == 0) |
| 1375 | break; |
| 1376 | |
| 1377 | status = readl(base + MMCISTATUS); |
| 1378 | } while (status & MCI_TXFIFOHALFEMPTY); |
| 1379 | |
| 1380 | return ptr - buffer; |
| 1381 | } |
| 1382 | |
| 1383 | /* |
| 1384 | * PIO data transfer IRQ handler. |
| 1385 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1386 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1387 | { |
| 1388 | struct mmci_host *host = dev_id; |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 1389 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 1390 | struct variant_data *variant = host->variant; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1391 | void __iomem *base = host->base; |
| 1392 | u32 status; |
| 1393 | |
| 1394 | status = readl(base + MMCISTATUS); |
| 1395 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1396 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1397 | |
| 1398 | do { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1399 | unsigned int remain, len; |
| 1400 | char *buffer; |
| 1401 | |
| 1402 | /* |
| 1403 | * For write, we only need to test the half-empty flag |
| 1404 | * here - if the FIFO is completely empty, then by |
| 1405 | * definition it is more than half empty. |
| 1406 | * |
| 1407 | * For read, check for data available. |
| 1408 | */ |
| 1409 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) |
| 1410 | break; |
| 1411 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 1412 | if (!sg_miter_next(sg_miter)) |
| 1413 | break; |
| 1414 | |
| 1415 | buffer = sg_miter->addr; |
| 1416 | remain = sg_miter->length; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1417 | |
| 1418 | len = 0; |
| 1419 | if (status & MCI_RXACTIVE) |
| 1420 | len = mmci_pio_read(host, buffer, remain); |
| 1421 | if (status & MCI_TXACTIVE) |
| 1422 | len = mmci_pio_write(host, buffer, remain, status); |
| 1423 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 1424 | sg_miter->consumed = len; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1425 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1426 | host->size -= len; |
| 1427 | remain -= len; |
| 1428 | |
| 1429 | if (remain) |
| 1430 | break; |
| 1431 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1432 | status = readl(base + MMCISTATUS); |
| 1433 | } while (1); |
| 1434 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 1435 | sg_miter_stop(sg_miter); |
| 1436 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1437 | /* |
Russell King | c4d877c | 2011-01-27 09:50:13 +0000 | [diff] [blame] | 1438 | * If we have less than the fifo 'half-full' threshold to transfer, |
| 1439 | * trigger a PIO interrupt as soon as any data is available. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1440 | */ |
Russell King | c4d877c | 2011-01-27 09:50:13 +0000 | [diff] [blame] | 1441 | if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1442 | mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1443 | |
| 1444 | /* |
| 1445 | * If we run out of data, disable the data IRQs; this |
| 1446 | * prevents a race where the FIFO becomes empty before |
| 1447 | * the chip itself has disabled the data path, and |
| 1448 | * stops us racing with our data end IRQ. |
| 1449 | */ |
| 1450 | if (host->size == 0) { |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1451 | mmci_set_mask1(host, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1452 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); |
| 1453 | } |
| 1454 | |
| 1455 | return IRQ_HANDLED; |
| 1456 | } |
| 1457 | |
| 1458 | /* |
| 1459 | * Handle completion of command and data transfers. |
| 1460 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1461 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1462 | { |
| 1463 | struct mmci_host *host = dev_id; |
| 1464 | u32 status; |
| 1465 | int ret = 0; |
| 1466 | |
| 1467 | spin_lock(&host->lock); |
| 1468 | |
| 1469 | do { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1470 | status = readl(host->base + MMCISTATUS); |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1471 | |
| 1472 | if (host->singleirq) { |
Patrice Chotard | 6ea9cdf | 2018-01-18 15:34:17 +0100 | [diff] [blame] | 1473 | if (status & host->mask1_reg) |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1474 | mmci_pio_irq(irq, dev_id); |
| 1475 | |
Ludovic Barre | 59db5e2 | 2018-10-08 14:08:47 +0200 | [diff] [blame] | 1476 | status &= ~host->variant->irq_pio_mask; |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1477 | } |
| 1478 | |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame] | 1479 | /* |
Jean-Nicolas Graux | 5cad24d | 2017-02-07 12:12:41 +0100 | [diff] [blame] | 1480 | * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's |
| 1481 | * enabled) in mmci_cmd_irq() function where ST Micro busy |
| 1482 | * detection variant is handled. Considering the HW seems to be |
| 1483 | * triggering the IRQ on both edges while monitoring DAT0 for |
| 1484 | * busy completion and that same status bit is used to monitor |
| 1485 | * start and end of busy detection, special care must be taken |
| 1486 | * to make sure that both start and end interrupts are always |
| 1487 | * cleared one after the other. |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame] | 1488 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1489 | status &= readl(host->base + MMCIMASK0); |
Jean-Nicolas Graux | 5cad24d | 2017-02-07 12:12:41 +0100 | [diff] [blame] | 1490 | if (host->variant->busy_detect) |
| 1491 | writel(status & ~host->variant->busy_detect_mask, |
| 1492 | host->base + MMCICLEAR); |
| 1493 | else |
| 1494 | writel(status, host->base + MMCICLEAR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1495 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1496 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1497 | |
Ulf Hansson | 7878289 | 2014-06-13 13:21:38 +0200 | [diff] [blame] | 1498 | if (host->variant->reversed_irq_handling) { |
| 1499 | mmci_data_irq(host, host->data, status); |
| 1500 | mmci_cmd_irq(host, host->cmd, status); |
| 1501 | } else { |
| 1502 | mmci_cmd_irq(host, host->cmd, status); |
| 1503 | mmci_data_irq(host, host->data, status); |
| 1504 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1505 | |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1506 | /* |
| 1507 | * Don't poll for busy completion in irq context. |
| 1508 | */ |
| 1509 | if (host->variant->busy_detect && host->busy_status) |
| 1510 | status &= ~host->variant->busy_detect_flag; |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame] | 1511 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1512 | ret = 1; |
| 1513 | } while (status); |
| 1514 | |
| 1515 | spin_unlock(&host->lock); |
| 1516 | |
| 1517 | return IRQ_RETVAL(ret); |
| 1518 | } |
| 1519 | |
| 1520 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) |
| 1521 | { |
| 1522 | struct mmci_host *host = mmc_priv(mmc); |
Linus Walleij | 9e94302 | 2008-10-24 21:17:50 +0100 | [diff] [blame] | 1523 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1524 | |
| 1525 | WARN_ON(host->mrq != NULL); |
| 1526 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 1527 | mrq->cmd->error = mmci_validate_data(host, mrq->data); |
| 1528 | if (mrq->cmd->error) { |
Pierre Ossman | 255d01a | 2007-07-24 20:38:53 +0200 | [diff] [blame] | 1529 | mmc_request_done(mmc, mrq); |
| 1530 | return; |
| 1531 | } |
| 1532 | |
Linus Walleij | 9e94302 | 2008-10-24 21:17:50 +0100 | [diff] [blame] | 1533 | spin_lock_irqsave(&host->lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1534 | |
| 1535 | host->mrq = mrq; |
| 1536 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 1537 | if (mrq->data) |
| 1538 | mmci_get_next_data(host, mrq->data); |
| 1539 | |
Ludovic Barre | d214154 | 2018-10-08 14:08:48 +0200 | [diff] [blame] | 1540 | if (mrq->data && |
| 1541 | (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1542 | mmci_start_data(host, mrq->data); |
| 1543 | |
Ulf Hansson | 024629c | 2013-05-13 15:40:56 +0100 | [diff] [blame] | 1544 | if (mrq->sbc) |
| 1545 | mmci_start_command(host, mrq->sbc, 0); |
| 1546 | else |
| 1547 | mmci_start_command(host, mrq->cmd, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1548 | |
Linus Walleij | 9e94302 | 2008-10-24 21:17:50 +0100 | [diff] [blame] | 1549 | spin_unlock_irqrestore(&host->lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1550 | } |
| 1551 | |
| 1552 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
| 1553 | { |
| 1554 | struct mmci_host *host = mmc_priv(mmc); |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 1555 | struct variant_data *variant = host->variant; |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 1556 | u32 pwr = 0; |
| 1557 | unsigned long flags; |
Lee Jones | db90f91 | 2013-05-03 12:52:12 +0100 | [diff] [blame] | 1558 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1559 | |
Ulf Hansson | bc52181 | 2011-12-13 16:57:55 +0100 | [diff] [blame] | 1560 | if (host->plat->ios_handler && |
| 1561 | host->plat->ios_handler(mmc_dev(mmc), ios)) |
| 1562 | dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); |
| 1563 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1564 | switch (ios->power_mode) { |
| 1565 | case MMC_POWER_OFF: |
Ulf Hansson | 599c1d5 | 2013-01-07 16:22:50 +0100 | [diff] [blame] | 1566 | if (!IS_ERR(mmc->supply.vmmc)) |
| 1567 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); |
Lee Jones | 237fb5e | 2013-01-31 11:27:52 +0000 | [diff] [blame] | 1568 | |
Ulf Hansson | 7c0136e | 2013-05-14 13:53:10 +0100 | [diff] [blame] | 1569 | if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { |
Lee Jones | 237fb5e | 2013-01-31 11:27:52 +0000 | [diff] [blame] | 1570 | regulator_disable(mmc->supply.vqmmc); |
Ulf Hansson | 7c0136e | 2013-05-14 13:53:10 +0100 | [diff] [blame] | 1571 | host->vqmmc_enabled = false; |
| 1572 | } |
Lee Jones | 237fb5e | 2013-01-31 11:27:52 +0000 | [diff] [blame] | 1573 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1574 | break; |
| 1575 | case MMC_POWER_UP: |
Ulf Hansson | 599c1d5 | 2013-01-07 16:22:50 +0100 | [diff] [blame] | 1576 | if (!IS_ERR(mmc->supply.vmmc)) |
| 1577 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); |
| 1578 | |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 1579 | /* |
| 1580 | * The ST Micro variant doesn't have the PL180s MCI_PWR_UP |
| 1581 | * and instead uses MCI_PWR_ON so apply whatever value is |
| 1582 | * configured in the variant data. |
| 1583 | */ |
| 1584 | pwr |= variant->pwrreg_powerup; |
| 1585 | |
| 1586 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1587 | case MMC_POWER_ON: |
Ulf Hansson | 7c0136e | 2013-05-14 13:53:10 +0100 | [diff] [blame] | 1588 | if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { |
Lee Jones | db90f91 | 2013-05-03 12:52:12 +0100 | [diff] [blame] | 1589 | ret = regulator_enable(mmc->supply.vqmmc); |
| 1590 | if (ret < 0) |
| 1591 | dev_err(mmc_dev(mmc), |
| 1592 | "failed to enable vqmmc regulator\n"); |
Ulf Hansson | 7c0136e | 2013-05-14 13:53:10 +0100 | [diff] [blame] | 1593 | else |
| 1594 | host->vqmmc_enabled = true; |
Lee Jones | db90f91 | 2013-05-03 12:52:12 +0100 | [diff] [blame] | 1595 | } |
Lee Jones | 237fb5e | 2013-01-31 11:27:52 +0000 | [diff] [blame] | 1596 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1597 | pwr |= MCI_PWR_ON; |
| 1598 | break; |
| 1599 | } |
| 1600 | |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 1601 | if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { |
| 1602 | /* |
| 1603 | * The ST Micro variant has some additional bits |
| 1604 | * indicating signal direction for the signals in |
| 1605 | * the SD/MMC bus and feedback-clock usage. |
| 1606 | */ |
Ulf Hansson | 4593df2 | 2014-03-21 10:13:05 +0100 | [diff] [blame] | 1607 | pwr |= host->pwr_reg_add; |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 1608 | |
| 1609 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
| 1610 | pwr &= ~MCI_ST_DATA74DIREN; |
| 1611 | else if (ios->bus_width == MMC_BUS_WIDTH_1) |
| 1612 | pwr &= (~MCI_ST_DATA74DIREN & |
| 1613 | ~MCI_ST_DATA31DIREN & |
| 1614 | ~MCI_ST_DATA2DIREN); |
| 1615 | } |
| 1616 | |
Patrice Chotard | f9bb304 | 2018-01-18 15:34:20 +0100 | [diff] [blame] | 1617 | if (variant->opendrain) { |
| 1618 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) |
| 1619 | pwr |= variant->opendrain; |
| 1620 | } else { |
| 1621 | /* |
| 1622 | * If the variant cannot configure the pads by its own, then we |
| 1623 | * expect the pinctrl to be able to do that for us |
| 1624 | */ |
| 1625 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) |
| 1626 | pinctrl_select_state(host->pinctrl, host->pins_opendrain); |
| 1627 | else |
| 1628 | pinctrl_select_state(host->pinctrl, host->pins_default); |
| 1629 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1630 | |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 1631 | /* |
| 1632 | * If clock = 0 and the variant requires the MMCIPOWER to be used for |
| 1633 | * gating the clock, the MCI_PWR_ON bit is cleared. |
| 1634 | */ |
| 1635 | if (!ios->clock && variant->pwrreg_clkgate) |
| 1636 | pwr &= ~MCI_PWR_ON; |
| 1637 | |
Srinivas Kandagatla | 3f4e6f7 | 2014-06-02 10:09:55 +0100 | [diff] [blame] | 1638 | if (host->variant->explicit_mclk_control && |
| 1639 | ios->clock != host->clock_cache) { |
| 1640 | ret = clk_set_rate(host->clk, ios->clock); |
| 1641 | if (ret < 0) |
| 1642 | dev_err(mmc_dev(host->mmc), |
| 1643 | "Error setting clock rate (%d)\n", ret); |
| 1644 | else |
| 1645 | host->mclk = clk_get_rate(host->clk); |
| 1646 | } |
| 1647 | host->clock_cache = ios->clock; |
| 1648 | |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 1649 | spin_lock_irqsave(&host->lock, flags); |
| 1650 | |
Ludovic Barre | cd3ee8c | 2018-10-08 14:08:42 +0200 | [diff] [blame] | 1651 | if (host->ops && host->ops->set_clkreg) |
| 1652 | host->ops->set_clkreg(host, ios->clock); |
| 1653 | else |
| 1654 | mmci_set_clkreg(host, ios->clock); |
| 1655 | |
| 1656 | if (host->ops && host->ops->set_pwrreg) |
| 1657 | host->ops->set_pwrreg(host, pwr); |
| 1658 | else |
| 1659 | mmci_write_pwrreg(host, pwr); |
| 1660 | |
Ulf Hansson | f829c04 | 2013-09-04 09:01:15 +0100 | [diff] [blame] | 1661 | mmci_reg_delay(host); |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 1662 | |
| 1663 | spin_unlock_irqrestore(&host->lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1664 | } |
| 1665 | |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1666 | static int mmci_get_cd(struct mmc_host *mmc) |
| 1667 | { |
| 1668 | struct mmci_host *host = mmc_priv(mmc); |
Rabin Vincent | 2971944 | 2010-08-09 12:54:43 +0100 | [diff] [blame] | 1669 | struct mmci_platform_data *plat = host->plat; |
Ulf Hansson | d276209 | 2014-03-17 13:56:19 +0100 | [diff] [blame] | 1670 | unsigned int status = mmc_gpio_get_cd(mmc); |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1671 | |
Ulf Hansson | d276209 | 2014-03-17 13:56:19 +0100 | [diff] [blame] | 1672 | if (status == -ENOSYS) { |
Rabin Vincent | 4b8caec | 2010-08-09 12:56:40 +0100 | [diff] [blame] | 1673 | if (!plat->status) |
| 1674 | return 1; /* Assume always present */ |
| 1675 | |
Rabin Vincent | 2971944 | 2010-08-09 12:54:43 +0100 | [diff] [blame] | 1676 | status = plat->status(mmc_dev(host->mmc)); |
Ulf Hansson | d276209 | 2014-03-17 13:56:19 +0100 | [diff] [blame] | 1677 | } |
Russell King | 74bc809 | 2010-07-29 15:58:59 +0100 | [diff] [blame] | 1678 | return status; |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1679 | } |
| 1680 | |
Ulf Hansson | 0f3ed7f | 2013-05-15 20:47:33 +0100 | [diff] [blame] | 1681 | static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) |
| 1682 | { |
| 1683 | int ret = 0; |
| 1684 | |
| 1685 | if (!IS_ERR(mmc->supply.vqmmc)) { |
| 1686 | |
Ulf Hansson | 0f3ed7f | 2013-05-15 20:47:33 +0100 | [diff] [blame] | 1687 | switch (ios->signal_voltage) { |
| 1688 | case MMC_SIGNAL_VOLTAGE_330: |
| 1689 | ret = regulator_set_voltage(mmc->supply.vqmmc, |
| 1690 | 2700000, 3600000); |
| 1691 | break; |
| 1692 | case MMC_SIGNAL_VOLTAGE_180: |
| 1693 | ret = regulator_set_voltage(mmc->supply.vqmmc, |
| 1694 | 1700000, 1950000); |
| 1695 | break; |
| 1696 | case MMC_SIGNAL_VOLTAGE_120: |
| 1697 | ret = regulator_set_voltage(mmc->supply.vqmmc, |
| 1698 | 1100000, 1300000); |
| 1699 | break; |
| 1700 | } |
| 1701 | |
| 1702 | if (ret) |
| 1703 | dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); |
Ulf Hansson | 0f3ed7f | 2013-05-15 20:47:33 +0100 | [diff] [blame] | 1704 | } |
| 1705 | |
| 1706 | return ret; |
| 1707 | } |
| 1708 | |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 1709 | static struct mmc_host_ops mmci_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1710 | .request = mmci_request, |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 1711 | .pre_req = mmci_pre_request, |
| 1712 | .post_req = mmci_post_request, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1713 | .set_ios = mmci_set_ios, |
Ulf Hansson | d276209 | 2014-03-17 13:56:19 +0100 | [diff] [blame] | 1714 | .get_ro = mmc_gpio_get_ro, |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1715 | .get_cd = mmci_get_cd, |
Ulf Hansson | 0f3ed7f | 2013-05-15 20:47:33 +0100 | [diff] [blame] | 1716 | .start_signal_voltage_switch = mmci_sig_volt_switch, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1717 | }; |
| 1718 | |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1719 | static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) |
| 1720 | { |
Ulf Hansson | 4593df2 | 2014-03-21 10:13:05 +0100 | [diff] [blame] | 1721 | struct mmci_host *host = mmc_priv(mmc); |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1722 | int ret = mmc_of_parse(mmc); |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1723 | |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1724 | if (ret) |
| 1725 | return ret; |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1726 | |
Ulf Hansson | 4593df2 | 2014-03-21 10:13:05 +0100 | [diff] [blame] | 1727 | if (of_get_property(np, "st,sig-dir-dat0", NULL)) |
| 1728 | host->pwr_reg_add |= MCI_ST_DATA0DIREN; |
| 1729 | if (of_get_property(np, "st,sig-dir-dat2", NULL)) |
| 1730 | host->pwr_reg_add |= MCI_ST_DATA2DIREN; |
| 1731 | if (of_get_property(np, "st,sig-dir-dat31", NULL)) |
| 1732 | host->pwr_reg_add |= MCI_ST_DATA31DIREN; |
| 1733 | if (of_get_property(np, "st,sig-dir-dat74", NULL)) |
| 1734 | host->pwr_reg_add |= MCI_ST_DATA74DIREN; |
| 1735 | if (of_get_property(np, "st,sig-dir-cmd", NULL)) |
| 1736 | host->pwr_reg_add |= MCI_ST_CMDDIREN; |
| 1737 | if (of_get_property(np, "st,sig-pin-fbclk", NULL)) |
| 1738 | host->pwr_reg_add |= MCI_ST_FBCLKEN; |
| 1739 | |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1740 | if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1741 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED; |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1742 | if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1743 | mmc->caps |= MMC_CAP_SD_HIGHSPEED; |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1744 | |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1745 | return 0; |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1746 | } |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1747 | |
Bill Pemberton | c3be1ef | 2012-11-19 13:23:06 -0500 | [diff] [blame] | 1748 | static int mmci_probe(struct amba_device *dev, |
Russell King | aa25afa | 2011-02-19 15:55:00 +0000 | [diff] [blame] | 1749 | const struct amba_id *id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1750 | { |
Linus Walleij | 6ef297f | 2009-09-22 14:29:36 +0100 | [diff] [blame] | 1751 | struct mmci_platform_data *plat = dev->dev.platform_data; |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1752 | struct device_node *np = dev->dev.of_node; |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1753 | struct variant_data *variant = id->data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1754 | struct mmci_host *host; |
| 1755 | struct mmc_host *mmc; |
| 1756 | int ret; |
| 1757 | |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1758 | /* Must have platform data or Device Tree. */ |
| 1759 | if (!plat && !np) { |
| 1760 | dev_err(&dev->dev, "No plat data or DT found\n"); |
| 1761 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1762 | } |
| 1763 | |
Lee Jones | b9b5291 | 2012-06-12 10:49:51 +0100 | [diff] [blame] | 1764 | if (!plat) { |
| 1765 | plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); |
| 1766 | if (!plat) |
| 1767 | return -ENOMEM; |
| 1768 | } |
| 1769 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1770 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); |
Ulf Hansson | ef28998 | 2014-03-17 13:56:32 +0100 | [diff] [blame] | 1771 | if (!mmc) |
| 1772 | return -ENOMEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1773 | |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1774 | ret = mmci_of_parse(np, mmc); |
| 1775 | if (ret) |
| 1776 | goto host_free; |
| 1777 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1778 | host = mmc_priv(mmc); |
Rabin Vincent | 4ea580f | 2009-04-17 08:44:19 +0530 | [diff] [blame] | 1779 | host->mmc = mmc; |
Russell King | 012b7d3 | 2009-07-09 15:13:56 +0100 | [diff] [blame] | 1780 | |
Patrice Chotard | f9bb304 | 2018-01-18 15:34:20 +0100 | [diff] [blame] | 1781 | /* |
| 1782 | * Some variant (STM32) doesn't have opendrain bit, nevertheless |
| 1783 | * pins can be set accordingly using pinctrl |
| 1784 | */ |
| 1785 | if (!variant->opendrain) { |
| 1786 | host->pinctrl = devm_pinctrl_get(&dev->dev); |
| 1787 | if (IS_ERR(host->pinctrl)) { |
| 1788 | dev_err(&dev->dev, "failed to get pinctrl"); |
Wei Yongjun | 310eb25 | 2018-01-23 02:09:13 +0000 | [diff] [blame] | 1789 | ret = PTR_ERR(host->pinctrl); |
Patrice Chotard | f9bb304 | 2018-01-18 15:34:20 +0100 | [diff] [blame] | 1790 | goto host_free; |
| 1791 | } |
| 1792 | |
| 1793 | host->pins_default = pinctrl_lookup_state(host->pinctrl, |
| 1794 | PINCTRL_STATE_DEFAULT); |
| 1795 | if (IS_ERR(host->pins_default)) { |
| 1796 | dev_err(mmc_dev(mmc), "Can't select default pins\n"); |
Wei Yongjun | 310eb25 | 2018-01-23 02:09:13 +0000 | [diff] [blame] | 1797 | ret = PTR_ERR(host->pins_default); |
Patrice Chotard | f9bb304 | 2018-01-18 15:34:20 +0100 | [diff] [blame] | 1798 | goto host_free; |
| 1799 | } |
| 1800 | |
| 1801 | host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, |
| 1802 | MMCI_PINCTRL_STATE_OPENDRAIN); |
| 1803 | if (IS_ERR(host->pins_opendrain)) { |
| 1804 | dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); |
Wei Yongjun | 310eb25 | 2018-01-23 02:09:13 +0000 | [diff] [blame] | 1805 | ret = PTR_ERR(host->pins_opendrain); |
Patrice Chotard | f9bb304 | 2018-01-18 15:34:20 +0100 | [diff] [blame] | 1806 | goto host_free; |
| 1807 | } |
| 1808 | } |
| 1809 | |
Russell King | 012b7d3 | 2009-07-09 15:13:56 +0100 | [diff] [blame] | 1810 | host->hw_designer = amba_manf(dev); |
| 1811 | host->hw_revision = amba_rev(dev); |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1812 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
| 1813 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); |
Russell King | 012b7d3 | 2009-07-09 15:13:56 +0100 | [diff] [blame] | 1814 | |
Ulf Hansson | 665ba56 | 2013-05-13 15:39:17 +0100 | [diff] [blame] | 1815 | host->clk = devm_clk_get(&dev->dev, NULL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1816 | if (IS_ERR(host->clk)) { |
| 1817 | ret = PTR_ERR(host->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1818 | goto host_free; |
| 1819 | } |
| 1820 | |
Julia Lawall | ac94093 | 2012-08-26 16:00:59 +0000 | [diff] [blame] | 1821 | ret = clk_prepare_enable(host->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1822 | if (ret) |
Ulf Hansson | 665ba56 | 2013-05-13 15:39:17 +0100 | [diff] [blame] | 1823 | goto host_free; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1824 | |
Srinivas Kandagatla | 9c34b73 | 2014-06-02 10:10:04 +0100 | [diff] [blame] | 1825 | if (variant->qcom_fifo) |
| 1826 | host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; |
| 1827 | else |
| 1828 | host->get_rx_fifocnt = mmci_get_rx_fifocnt; |
| 1829 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1830 | host->plat = plat; |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1831 | host->variant = variant; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1832 | host->mclk = clk_get_rate(host->clk); |
Linus Walleij | c8df9a5 | 2008-04-29 09:34:07 +0100 | [diff] [blame] | 1833 | /* |
| 1834 | * According to the spec, mclk is max 100 MHz, |
| 1835 | * so we try to adjust the clock down to this, |
| 1836 | * (if possible). |
| 1837 | */ |
Srinivas Kandagatla | dc6500b | 2014-06-02 10:09:47 +0100 | [diff] [blame] | 1838 | if (host->mclk > variant->f_max) { |
| 1839 | ret = clk_set_rate(host->clk, variant->f_max); |
Linus Walleij | c8df9a5 | 2008-04-29 09:34:07 +0100 | [diff] [blame] | 1840 | if (ret < 0) |
| 1841 | goto clk_disable; |
| 1842 | host->mclk = clk_get_rate(host->clk); |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1843 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
| 1844 | host->mclk); |
Linus Walleij | c8df9a5 | 2008-04-29 09:34:07 +0100 | [diff] [blame] | 1845 | } |
Ulf Hansson | ef28998 | 2014-03-17 13:56:32 +0100 | [diff] [blame] | 1846 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 1847 | host->phybase = dev->res.start; |
Ulf Hansson | ef28998 | 2014-03-17 13:56:32 +0100 | [diff] [blame] | 1848 | host->base = devm_ioremap_resource(&dev->dev, &dev->res); |
| 1849 | if (IS_ERR(host->base)) { |
| 1850 | ret = PTR_ERR(host->base); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1851 | goto clk_disable; |
| 1852 | } |
| 1853 | |
Ulf Hansson | ed9067f | 2018-07-13 13:15:23 +0200 | [diff] [blame] | 1854 | if (variant->init) |
| 1855 | variant->init(host); |
| 1856 | |
Linus Walleij | 7f294e4 | 2011-07-08 09:57:15 +0100 | [diff] [blame] | 1857 | /* |
| 1858 | * The ARM and ST versions of the block have slightly different |
| 1859 | * clock divider equations which means that the minimum divider |
| 1860 | * differs too. |
Srinivas Kandagatla | 3f4e6f7 | 2014-06-02 10:09:55 +0100 | [diff] [blame] | 1861 | * on Qualcomm like controllers get the nearest minimum clock to 100Khz |
Linus Walleij | 7f294e4 | 2011-07-08 09:57:15 +0100 | [diff] [blame] | 1862 | */ |
| 1863 | if (variant->st_clkdiv) |
| 1864 | mmc->f_min = DIV_ROUND_UP(host->mclk, 257); |
Srinivas Kandagatla | 3f4e6f7 | 2014-06-02 10:09:55 +0100 | [diff] [blame] | 1865 | else if (variant->explicit_mclk_control) |
| 1866 | mmc->f_min = clk_round_rate(host->clk, 100000); |
Linus Walleij | 7f294e4 | 2011-07-08 09:57:15 +0100 | [diff] [blame] | 1867 | else |
| 1868 | mmc->f_min = DIV_ROUND_UP(host->mclk, 512); |
Linus Walleij | 808d97c | 2010-04-08 07:39:38 +0100 | [diff] [blame] | 1869 | /* |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1870 | * If no maximum operating frequency is supplied, fall back to use |
| 1871 | * the module parameter, which has a (low) default value in case it |
| 1872 | * is not specified. Either value must not exceed the clock rate into |
Ulf Hansson | 5080a08 | 2014-03-21 10:46:39 +0100 | [diff] [blame] | 1873 | * the block, of course. |
Linus Walleij | 808d97c | 2010-04-08 07:39:38 +0100 | [diff] [blame] | 1874 | */ |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1875 | if (mmc->f_max) |
Srinivas Kandagatla | 3f4e6f7 | 2014-06-02 10:09:55 +0100 | [diff] [blame] | 1876 | mmc->f_max = variant->explicit_mclk_control ? |
| 1877 | min(variant->f_max, mmc->f_max) : |
| 1878 | min(host->mclk, mmc->f_max); |
Linus Walleij | 808d97c | 2010-04-08 07:39:38 +0100 | [diff] [blame] | 1879 | else |
Srinivas Kandagatla | 3f4e6f7 | 2014-06-02 10:09:55 +0100 | [diff] [blame] | 1880 | mmc->f_max = variant->explicit_mclk_control ? |
| 1881 | fmax : min(host->mclk, fmax); |
| 1882 | |
| 1883 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1884 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
| 1885 | |
Ludovic Barre | 15878e5 | 2018-10-08 14:08:51 +0200 | [diff] [blame^] | 1886 | host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); |
| 1887 | if (IS_ERR(host->rst)) { |
| 1888 | ret = PTR_ERR(host->rst); |
| 1889 | goto clk_disable; |
| 1890 | } |
| 1891 | |
Ulf Hansson | 599c1d5 | 2013-01-07 16:22:50 +0100 | [diff] [blame] | 1892 | /* Get regulators and the supported OCR mask */ |
Bjorn Andersson | 9369c97 | 2015-03-24 18:39:49 -0700 | [diff] [blame] | 1893 | ret = mmc_regulator_get_supply(mmc); |
Wolfram Sang | 5100695 | 2017-10-14 21:17:14 +0200 | [diff] [blame] | 1894 | if (ret) |
Bjorn Andersson | 9369c97 | 2015-03-24 18:39:49 -0700 | [diff] [blame] | 1895 | goto clk_disable; |
| 1896 | |
Ulf Hansson | 599c1d5 | 2013-01-07 16:22:50 +0100 | [diff] [blame] | 1897 | if (!mmc->ocr_avail) |
Linus Walleij | 34e84f3 | 2009-09-22 14:41:40 +0100 | [diff] [blame] | 1898 | mmc->ocr_avail = plat->ocr_mask; |
Ulf Hansson | 599c1d5 | 2013-01-07 16:22:50 +0100 | [diff] [blame] | 1899 | else if (plat->ocr_mask) |
| 1900 | dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); |
| 1901 | |
Ulf Hansson | 9dd8a8b | 2014-03-19 13:54:18 +0100 | [diff] [blame] | 1902 | /* We support these capabilities. */ |
| 1903 | mmc->caps |= MMC_CAP_CMD23; |
| 1904 | |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1905 | /* |
| 1906 | * Enable busy detection. |
| 1907 | */ |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame] | 1908 | if (variant->busy_detect) { |
| 1909 | mmci_ops.card_busy = mmci_card_busy; |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1910 | /* |
| 1911 | * Not all variants have a flag to enable busy detection |
| 1912 | * in the DPSM, but if they do, set it here. |
| 1913 | */ |
| 1914 | if (variant->busy_dpsm_flag) |
| 1915 | mmci_write_datactrlreg(host, |
| 1916 | host->variant->busy_dpsm_flag); |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame] | 1917 | mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; |
| 1918 | mmc->max_busy_timeout = 0; |
| 1919 | } |
| 1920 | |
| 1921 | mmc->ops = &mmci_ops; |
| 1922 | |
Ulf Hansson | 70be208 | 2013-01-07 15:35:06 +0100 | [diff] [blame] | 1923 | /* We support these PM capabilities. */ |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1924 | mmc->pm_caps |= MMC_PM_KEEP_POWER; |
Ulf Hansson | 70be208 | 2013-01-07 15:35:06 +0100 | [diff] [blame] | 1925 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1926 | /* |
| 1927 | * We can do SGIO |
| 1928 | */ |
Martin K. Petersen | a36274e | 2010-09-10 01:33:59 -0400 | [diff] [blame] | 1929 | mmc->max_segs = NR_SG; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1930 | |
| 1931 | /* |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 1932 | * Since only a certain number of bits are valid in the data length |
| 1933 | * register, we must ensure that we don't exceed 2^num-1 bytes in a |
| 1934 | * single request. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1935 | */ |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 1936 | mmc->max_req_size = (1 << variant->datalength_bits) - 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1937 | |
| 1938 | /* |
| 1939 | * Set the maximum segment size. Since we aren't doing DMA |
| 1940 | * (yet) we are only limited by the data length register. |
| 1941 | */ |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 1942 | mmc->max_seg_size = mmc->max_req_size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1943 | |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 1944 | /* |
| 1945 | * Block size can be up to 2048 bytes, but must be a power of two. |
| 1946 | */ |
Ludovic Barre | c931d49 | 2018-10-08 14:08:43 +0200 | [diff] [blame] | 1947 | mmc->max_blk_size = 1 << variant->datactrl_blocksz; |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 1948 | |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 1949 | /* |
Will Deacon | 8f7f6b7e | 2012-02-24 11:25:21 +0000 | [diff] [blame] | 1950 | * Limit the number of blocks transferred so that we don't overflow |
| 1951 | * the maximum request size. |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 1952 | */ |
Ludovic Barre | c931d49 | 2018-10-08 14:08:43 +0200 | [diff] [blame] | 1953 | mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz; |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 1954 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1955 | spin_lock_init(&host->lock); |
| 1956 | |
| 1957 | writel(0, host->base + MMCIMASK0); |
Patrice Chotard | 6ea9cdf | 2018-01-18 15:34:17 +0100 | [diff] [blame] | 1958 | |
| 1959 | if (variant->mmcimask1) |
| 1960 | writel(0, host->base + MMCIMASK1); |
| 1961 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1962 | writel(0xfff, host->base + MMCICLEAR); |
| 1963 | |
Linus Walleij | ce437aa | 2014-08-27 15:13:54 +0200 | [diff] [blame] | 1964 | /* |
| 1965 | * If: |
| 1966 | * - not using DT but using a descriptor table, or |
| 1967 | * - using a table of descriptors ALONGSIDE DT, or |
| 1968 | * look up these descriptors named "cd" and "wp" right here, fail |
Linus Walleij | 9ef986a | 2018-09-20 16:01:10 -0700 | [diff] [blame] | 1969 | * silently of these do not exist |
Linus Walleij | ce437aa | 2014-08-27 15:13:54 +0200 | [diff] [blame] | 1970 | */ |
| 1971 | if (!np) { |
Linus Walleij | 89168b4 | 2014-10-02 09:08:46 +0200 | [diff] [blame] | 1972 | ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); |
Linus Walleij | 9ef986a | 2018-09-20 16:01:10 -0700 | [diff] [blame] | 1973 | if (ret == -EPROBE_DEFER) |
| 1974 | goto clk_disable; |
Linus Walleij | ce437aa | 2014-08-27 15:13:54 +0200 | [diff] [blame] | 1975 | |
Linus Walleij | 89168b4 | 2014-10-02 09:08:46 +0200 | [diff] [blame] | 1976 | ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); |
Linus Walleij | 9ef986a | 2018-09-20 16:01:10 -0700 | [diff] [blame] | 1977 | if (ret == -EPROBE_DEFER) |
| 1978 | goto clk_disable; |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1979 | } |
| 1980 | |
Ulf Hansson | ef28998 | 2014-03-17 13:56:32 +0100 | [diff] [blame] | 1981 | ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, |
| 1982 | DRIVER_NAME " (cmd)", host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1983 | if (ret) |
Ulf Hansson | ef28998 | 2014-03-17 13:56:32 +0100 | [diff] [blame] | 1984 | goto clk_disable; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1985 | |
Russell King | dfb8518 | 2012-05-03 11:33:15 +0100 | [diff] [blame] | 1986 | if (!dev->irq[1]) |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1987 | host->singleirq = true; |
| 1988 | else { |
Ulf Hansson | ef28998 | 2014-03-17 13:56:32 +0100 | [diff] [blame] | 1989 | ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, |
| 1990 | IRQF_SHARED, DRIVER_NAME " (pio)", host); |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1991 | if (ret) |
Ulf Hansson | ef28998 | 2014-03-17 13:56:32 +0100 | [diff] [blame] | 1992 | goto clk_disable; |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1993 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1994 | |
Ludovic Barre | daf9713 | 2018-10-08 14:08:44 +0200 | [diff] [blame] | 1995 | writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1996 | |
| 1997 | amba_set_drvdata(dev, mmc); |
| 1998 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 1999 | dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", |
| 2000 | mmc_hostname(mmc), amba_part(dev), amba_manf(dev), |
| 2001 | amba_rev(dev), (unsigned long long)dev->res.start, |
| 2002 | dev->irq[0], dev->irq[1]); |
| 2003 | |
| 2004 | mmci_dma_setup(host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2005 | |
Ulf Hansson | 2cd976c | 2011-12-13 17:01:11 +0100 | [diff] [blame] | 2006 | pm_runtime_set_autosuspend_delay(&dev->dev, 50); |
| 2007 | pm_runtime_use_autosuspend(&dev->dev); |
Russell King | 1c3be36 | 2011-08-14 09:17:05 +0100 | [diff] [blame] | 2008 | |
Russell King | 8c11a94 | 2010-12-28 19:40:40 +0000 | [diff] [blame] | 2009 | mmc_add_host(mmc); |
| 2010 | |
Ulf Hansson | 6f2d3c8 | 2014-12-11 14:35:55 +0100 | [diff] [blame] | 2011 | pm_runtime_put(&dev->dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2012 | return 0; |
| 2013 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2014 | clk_disable: |
Julia Lawall | ac94093 | 2012-08-26 16:00:59 +0000 | [diff] [blame] | 2015 | clk_disable_unprepare(host->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2016 | host_free: |
| 2017 | mmc_free_host(mmc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2018 | return ret; |
| 2019 | } |
| 2020 | |
Bill Pemberton | 6e0ee71 | 2012-11-19 13:26:03 -0500 | [diff] [blame] | 2021 | static int mmci_remove(struct amba_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2022 | { |
| 2023 | struct mmc_host *mmc = amba_get_drvdata(dev); |
| 2024 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2025 | if (mmc) { |
| 2026 | struct mmci_host *host = mmc_priv(mmc); |
Patrice Chotard | 6ea9cdf | 2018-01-18 15:34:17 +0100 | [diff] [blame] | 2027 | struct variant_data *variant = host->variant; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2028 | |
Russell King | 1c3be36 | 2011-08-14 09:17:05 +0100 | [diff] [blame] | 2029 | /* |
| 2030 | * Undo pm_runtime_put() in probe. We use the _sync |
| 2031 | * version here so that we can access the primecell. |
| 2032 | */ |
| 2033 | pm_runtime_get_sync(&dev->dev); |
| 2034 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2035 | mmc_remove_host(mmc); |
| 2036 | |
| 2037 | writel(0, host->base + MMCIMASK0); |
Patrice Chotard | 6ea9cdf | 2018-01-18 15:34:17 +0100 | [diff] [blame] | 2038 | |
| 2039 | if (variant->mmcimask1) |
| 2040 | writel(0, host->base + MMCIMASK1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2041 | |
| 2042 | writel(0, host->base + MMCICOMMAND); |
| 2043 | writel(0, host->base + MMCIDATACTRL); |
| 2044 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 2045 | mmci_dma_release(host); |
Julia Lawall | ac94093 | 2012-08-26 16:00:59 +0000 | [diff] [blame] | 2046 | clk_disable_unprepare(host->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2047 | mmc_free_host(mmc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2048 | } |
| 2049 | |
| 2050 | return 0; |
| 2051 | } |
| 2052 | |
Ulf Hansson | 571dce4 | 2014-01-23 00:38:00 +0100 | [diff] [blame] | 2053 | #ifdef CONFIG_PM |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 2054 | static void mmci_save(struct mmci_host *host) |
| 2055 | { |
| 2056 | unsigned long flags; |
| 2057 | |
Ulf Hansson | 42dcc89a | 2014-01-23 00:19:38 +0100 | [diff] [blame] | 2058 | spin_lock_irqsave(&host->lock, flags); |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 2059 | |
Ulf Hansson | 42dcc89a | 2014-01-23 00:19:38 +0100 | [diff] [blame] | 2060 | writel(0, host->base + MMCIMASK0); |
| 2061 | if (host->variant->pwrreg_nopower) { |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 2062 | writel(0, host->base + MMCIDATACTRL); |
| 2063 | writel(0, host->base + MMCIPOWER); |
| 2064 | writel(0, host->base + MMCICLOCK); |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 2065 | } |
Ulf Hansson | 42dcc89a | 2014-01-23 00:19:38 +0100 | [diff] [blame] | 2066 | mmci_reg_delay(host); |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 2067 | |
Ulf Hansson | 42dcc89a | 2014-01-23 00:19:38 +0100 | [diff] [blame] | 2068 | spin_unlock_irqrestore(&host->lock, flags); |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 2069 | } |
| 2070 | |
| 2071 | static void mmci_restore(struct mmci_host *host) |
| 2072 | { |
| 2073 | unsigned long flags; |
| 2074 | |
Ulf Hansson | 42dcc89a | 2014-01-23 00:19:38 +0100 | [diff] [blame] | 2075 | spin_lock_irqsave(&host->lock, flags); |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 2076 | |
Ulf Hansson | 42dcc89a | 2014-01-23 00:19:38 +0100 | [diff] [blame] | 2077 | if (host->variant->pwrreg_nopower) { |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 2078 | writel(host->clk_reg, host->base + MMCICLOCK); |
| 2079 | writel(host->datactrl_reg, host->base + MMCIDATACTRL); |
| 2080 | writel(host->pwr_reg, host->base + MMCIPOWER); |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 2081 | } |
Ludovic Barre | daf9713 | 2018-10-08 14:08:44 +0200 | [diff] [blame] | 2082 | writel(MCI_IRQENABLE | host->variant->start_err, |
| 2083 | host->base + MMCIMASK0); |
Ulf Hansson | 42dcc89a | 2014-01-23 00:19:38 +0100 | [diff] [blame] | 2084 | mmci_reg_delay(host); |
| 2085 | |
| 2086 | spin_unlock_irqrestore(&host->lock, flags); |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 2087 | } |
| 2088 | |
Ulf Hansson | 8259293 | 2013-01-09 11:15:26 +0100 | [diff] [blame] | 2089 | static int mmci_runtime_suspend(struct device *dev) |
| 2090 | { |
| 2091 | struct amba_device *adev = to_amba_device(dev); |
| 2092 | struct mmc_host *mmc = amba_get_drvdata(adev); |
| 2093 | |
| 2094 | if (mmc) { |
| 2095 | struct mmci_host *host = mmc_priv(mmc); |
Ulf Hansson | e36bd9c6 | 2013-09-04 09:00:37 +0100 | [diff] [blame] | 2096 | pinctrl_pm_select_sleep_state(dev); |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 2097 | mmci_save(host); |
Ulf Hansson | 8259293 | 2013-01-09 11:15:26 +0100 | [diff] [blame] | 2098 | clk_disable_unprepare(host->clk); |
| 2099 | } |
| 2100 | |
| 2101 | return 0; |
| 2102 | } |
| 2103 | |
| 2104 | static int mmci_runtime_resume(struct device *dev) |
| 2105 | { |
| 2106 | struct amba_device *adev = to_amba_device(dev); |
| 2107 | struct mmc_host *mmc = amba_get_drvdata(adev); |
| 2108 | |
| 2109 | if (mmc) { |
| 2110 | struct mmci_host *host = mmc_priv(mmc); |
| 2111 | clk_prepare_enable(host->clk); |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 2112 | mmci_restore(host); |
Ulf Hansson | e36bd9c6 | 2013-09-04 09:00:37 +0100 | [diff] [blame] | 2113 | pinctrl_pm_select_default_state(dev); |
Ulf Hansson | 8259293 | 2013-01-09 11:15:26 +0100 | [diff] [blame] | 2114 | } |
| 2115 | |
| 2116 | return 0; |
| 2117 | } |
| 2118 | #endif |
| 2119 | |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 2120 | static const struct dev_pm_ops mmci_dev_pm_ops = { |
Ulf Hansson | f3737fa | 2014-01-23 01:11:33 +0100 | [diff] [blame] | 2121 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
| 2122 | pm_runtime_force_resume) |
Rafael J. Wysocki | 6ed23b8 | 2014-12-04 00:34:11 +0100 | [diff] [blame] | 2123 | SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 2124 | }; |
| 2125 | |
Arvind Yadav | 88411de | 2017-08-23 22:00:49 +0530 | [diff] [blame] | 2126 | static const struct amba_id mmci_ids[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2127 | { |
| 2128 | .id = 0x00041180, |
Pawel Moll | 768fbc1 | 2011-03-11 17:18:07 +0000 | [diff] [blame] | 2129 | .mask = 0xff0fffff, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 2130 | .data = &variant_arm, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2131 | }, |
| 2132 | { |
Pawel Moll | 768fbc1 | 2011-03-11 17:18:07 +0000 | [diff] [blame] | 2133 | .id = 0x01041180, |
| 2134 | .mask = 0xff0fffff, |
| 2135 | .data = &variant_arm_extended_fifo, |
| 2136 | }, |
| 2137 | { |
Pawel Moll | 3a37298 | 2013-01-24 14:12:45 +0100 | [diff] [blame] | 2138 | .id = 0x02041180, |
| 2139 | .mask = 0xff0fffff, |
| 2140 | .data = &variant_arm_extended_fifo_hwfc, |
| 2141 | }, |
| 2142 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2143 | .id = 0x00041181, |
| 2144 | .mask = 0x000fffff, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 2145 | .data = &variant_arm, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2146 | }, |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 2147 | /* ST Micro variants */ |
| 2148 | { |
| 2149 | .id = 0x00180180, |
| 2150 | .mask = 0x00ffffff, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 2151 | .data = &variant_u300, |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 2152 | }, |
| 2153 | { |
Linus Walleij | 34fd421 | 2012-04-10 17:43:59 +0100 | [diff] [blame] | 2154 | .id = 0x10180180, |
| 2155 | .mask = 0xf0ffffff, |
| 2156 | .data = &variant_nomadik, |
| 2157 | }, |
| 2158 | { |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 2159 | .id = 0x00280180, |
| 2160 | .mask = 0x00ffffff, |
Linus Walleij | 0bcb7ef | 2016-01-04 02:21:55 +0100 | [diff] [blame] | 2161 | .data = &variant_nomadik, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 2162 | }, |
| 2163 | { |
| 2164 | .id = 0x00480180, |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 2165 | .mask = 0xf0ffffff, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 2166 | .data = &variant_ux500, |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 2167 | }, |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 2168 | { |
| 2169 | .id = 0x10480180, |
| 2170 | .mask = 0xf0ffffff, |
| 2171 | .data = &variant_ux500v2, |
| 2172 | }, |
Patrice Chotard | 2a9d6c8 | 2018-01-18 15:34:21 +0100 | [diff] [blame] | 2173 | { |
| 2174 | .id = 0x00880180, |
| 2175 | .mask = 0x00ffffff, |
| 2176 | .data = &variant_stm32, |
| 2177 | }, |
Srinivas Kandagatla | 55b604a | 2014-06-02 10:10:13 +0100 | [diff] [blame] | 2178 | /* Qualcomm variants */ |
| 2179 | { |
| 2180 | .id = 0x00051180, |
| 2181 | .mask = 0x000fffff, |
| 2182 | .data = &variant_qcom, |
| 2183 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2184 | { 0, 0 }, |
| 2185 | }; |
| 2186 | |
Dave Martin | 9f99835 | 2011-10-05 15:15:21 +0100 | [diff] [blame] | 2187 | MODULE_DEVICE_TABLE(amba, mmci_ids); |
| 2188 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2189 | static struct amba_driver mmci_driver = { |
| 2190 | .drv = { |
| 2191 | .name = DRIVER_NAME, |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 2192 | .pm = &mmci_dev_pm_ops, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2193 | }, |
| 2194 | .probe = mmci_probe, |
Bill Pemberton | 0433c14 | 2012-11-19 13:20:26 -0500 | [diff] [blame] | 2195 | .remove = mmci_remove, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2196 | .id_table = mmci_ids, |
| 2197 | }; |
| 2198 | |
viresh kumar | 9e5ed09 | 2012-03-15 10:40:38 +0100 | [diff] [blame] | 2199 | module_amba_driver(mmci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2200 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2201 | module_param(fmax, uint, 0444); |
| 2202 | |
| 2203 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); |
| 2204 | MODULE_LICENSE("GPL"); |