blob: 1bb5c6cee3ebb140e30e421c05615bf94b001936 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
Ingo Molnar8f47e162009-01-31 02:03:42 +01004 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
Yinghai Lud4057bd2008-08-19 20:50:38 -070028#include <linux/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029#include <linux/mc146818rtc.h>
30#include <linux/compiler.h>
31#include <linux/acpi.h>
Alexey Dobriyan129f6942005-06-23 00:08:33 -070032#include <linux/module.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033#include <linux/sysdev.h>
Eric W. Biederman3b7d1922006-10-04 02:16:59 -070034#include <linux/msi.h>
Eric W. Biederman95d77882006-10-04 02:17:01 -070035#include <linux/htirq.h>
Nigel Cunningham7dfb7102006-12-06 20:34:23 -080036#include <linux/freezer.h>
Eric W. Biedermanf26d6a22007-05-02 19:27:19 +020037#include <linux/kthread.h>
Ingo Molnar54168ed2008-08-20 09:07:45 +020038#include <linux/jiffies.h> /* time_after() */
Yinghai Lud4057bd2008-08-19 20:50:38 -070039#ifdef CONFIG_ACPI
40#include <acpi/acpi_bus.h>
41#endif
42#include <linux/bootmem.h>
43#include <linux/dmar.h>
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -070044#include <linux/hpet.h>
Ashok Raj54d5d422005-09-06 15:16:15 -070045
Yinghai Lud4057bd2008-08-19 20:50:38 -070046#include <asm/idle.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <asm/io.h>
48#include <asm/smp.h>
Jaswinder Singh Rajput6d652ea2009-01-07 21:38:59 +053049#include <asm/cpu.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070050#include <asm/desc.h>
Yinghai Lud4057bd2008-08-19 20:50:38 -070051#include <asm/proto.h>
52#include <asm/acpi.h>
53#include <asm/dma.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070054#include <asm/timer.h>
Ingo Molnar306e4402005-06-30 02:58:55 -070055#include <asm/i8259.h>
Don Zickus3e4ff112006-06-26 13:57:01 +020056#include <asm/nmi.h>
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -070057#include <asm/msidef.h>
Eric W. Biederman8b955b02006-10-04 02:16:55 -070058#include <asm/hypertransport.h>
Yinghai Lua4dbc342008-07-25 02:14:28 -070059#include <asm/setup.h>
Yinghai Lud4057bd2008-08-19 20:50:38 -070060#include <asm/irq_remapping.h>
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -070061#include <asm/hpet.h>
Dean Nelson4173a0e2008-10-02 12:18:21 -050062#include <asm/uv/uv_hub.h>
63#include <asm/uv/uv_irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070064
Ingo Molnar7b6aa332009-02-17 13:58:15 +010065#include <asm/apic.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070066
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +010067#define __apicdebuginit(type) static type __init
68
Linus Torvalds1da177e2005-04-16 15:20:36 -070069/*
Ingo Molnar54168ed2008-08-20 09:07:45 +020070 * Is the SiS APIC rmw bug present ?
71 * -1 = don't know, 0 = no, 1 = yes
Linus Torvalds1da177e2005-04-16 15:20:36 -070072 */
73int sis_apic_bug = -1;
74
Yinghai Luefa25592008-08-19 20:50:36 -070075static DEFINE_SPINLOCK(ioapic_lock);
76static DEFINE_SPINLOCK(vector_lock);
77
Yinghai Luefa25592008-08-19 20:50:36 -070078/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070079 * # of IRQ routing registers
80 */
81int nr_ioapic_registers[MAX_IO_APICS];
82
Alexey Starikovskiy9f640cc2008-04-04 23:41:13 +040083/* I/O APIC entries */
Jaswinder Singh Rajputb5ba7e62009-01-12 17:46:17 +053084struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
Alexey Starikovskiy9f640cc2008-04-04 23:41:13 +040085int nr_ioapics;
86
Alexey Starikovskiy584f7342008-04-04 23:41:32 +040087/* MP IRQ source entries */
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +053088struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
Alexey Starikovskiy584f7342008-04-04 23:41:32 +040089
90/* # of MP IRQ source entries */
91int mp_irq_entries;
92
Alexey Starikovskiy8732fc42008-05-19 19:47:16 +040093#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
94int mp_bus_id_to_type[MAX_MP_BUSSES];
95#endif
96
97DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
98
Yinghai Luefa25592008-08-19 20:50:36 -070099int skip_ioapic_setup;
100
Ingo Molnar65a4e572009-01-31 03:36:17 +0100101void arch_disable_smp_support(void)
102{
103#ifdef CONFIG_PCI
104 noioapicquirk = 1;
105 noioapicreroute = -1;
106#endif
107 skip_ioapic_setup = 1;
108}
109
Ingo Molnar54168ed2008-08-20 09:07:45 +0200110static int __init parse_noapic(char *str)
Yinghai Luefa25592008-08-19 20:50:36 -0700111{
112 /* disable IO-APIC */
Ingo Molnar65a4e572009-01-31 03:36:17 +0100113 arch_disable_smp_support();
Yinghai Luefa25592008-08-19 20:50:36 -0700114 return 0;
115}
116early_param("noapic", parse_noapic);
Chuck Ebbert66759a02005-09-12 18:49:25 +0200117
Yinghai Lu0f978f42008-08-19 20:50:26 -0700118struct irq_pin_list;
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +0200119
120/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121 * This is performance-critical, we want to do it O(1)
122 *
123 * the indexing order of this array favors 1:1 mappings
124 * between pins and IRQs.
125 */
126
Yinghai Lu0f978f42008-08-19 20:50:26 -0700127struct irq_pin_list {
128 int apic, pin;
129 struct irq_pin_list *next;
130};
Yinghai Lu301e6192008-08-19 20:50:02 -0700131
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800132static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
Yinghai Lu0f978f42008-08-19 20:50:26 -0700133{
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800134 struct irq_pin_list *pin;
135 int node;
Yinghai Lu0f978f42008-08-19 20:50:26 -0700136
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800137 node = cpu_to_node(cpu);
Yinghai Lu0f978f42008-08-19 20:50:26 -0700138
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800139 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
Yinghai Lu0f978f42008-08-19 20:50:26 -0700140
Yinghai Lu0f978f42008-08-19 20:50:26 -0700141 return pin;
142}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800144struct irq_cfg {
145 struct irq_pin_list *irq_2_pin;
Mike Travis22f65d32008-12-16 17:33:56 -0800146 cpumask_var_t domain;
147 cpumask_var_t old_domain;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800148 unsigned move_cleanup_count;
149 u8 vector;
150 u8 move_in_progress : 1;
Yinghai Lu48a1b102008-12-11 00:15:01 -0800151#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
152 u8 move_desc_pending : 1;
153#endif
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800154};
155
156/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
157#ifdef CONFIG_SPARSE_IRQ
158static struct irq_cfg irq_cfgx[] = {
159#else
160static struct irq_cfg irq_cfgx[NR_IRQS] = {
161#endif
Mike Travis22f65d32008-12-16 17:33:56 -0800162 [0] = { .vector = IRQ0_VECTOR, },
163 [1] = { .vector = IRQ1_VECTOR, },
164 [2] = { .vector = IRQ2_VECTOR, },
165 [3] = { .vector = IRQ3_VECTOR, },
166 [4] = { .vector = IRQ4_VECTOR, },
167 [5] = { .vector = IRQ5_VECTOR, },
168 [6] = { .vector = IRQ6_VECTOR, },
169 [7] = { .vector = IRQ7_VECTOR, },
170 [8] = { .vector = IRQ8_VECTOR, },
171 [9] = { .vector = IRQ9_VECTOR, },
172 [10] = { .vector = IRQ10_VECTOR, },
173 [11] = { .vector = IRQ11_VECTOR, },
174 [12] = { .vector = IRQ12_VECTOR, },
175 [13] = { .vector = IRQ13_VECTOR, },
176 [14] = { .vector = IRQ14_VECTOR, },
177 [15] = { .vector = IRQ15_VECTOR, },
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800178};
179
Yinghai Lu13a0c3c2008-12-26 02:05:47 -0800180int __init arch_early_irq_init(void)
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800181{
182 struct irq_cfg *cfg;
183 struct irq_desc *desc;
184 int count;
185 int i;
186
187 cfg = irq_cfgx;
188 count = ARRAY_SIZE(irq_cfgx);
189
190 for (i = 0; i < count; i++) {
191 desc = irq_to_desc(i);
192 desc->chip_data = &cfg[i];
Mike Travis22f65d32008-12-16 17:33:56 -0800193 alloc_bootmem_cpumask_var(&cfg[i].domain);
194 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
195 if (i < NR_IRQS_LEGACY)
196 cpumask_setall(cfg[i].domain);
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800197 }
Yinghai Lu13a0c3c2008-12-26 02:05:47 -0800198
199 return 0;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800200}
201
202#ifdef CONFIG_SPARSE_IRQ
203static struct irq_cfg *irq_cfg(unsigned int irq)
204{
205 struct irq_cfg *cfg = NULL;
206 struct irq_desc *desc;
207
208 desc = irq_to_desc(irq);
209 if (desc)
210 cfg = desc->chip_data;
211
212 return cfg;
213}
214
215static struct irq_cfg *get_one_free_irq_cfg(int cpu)
216{
217 struct irq_cfg *cfg;
218 int node;
219
220 node = cpu_to_node(cpu);
221
222 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
Mike Travis22f65d32008-12-16 17:33:56 -0800223 if (cfg) {
Mike Travis80855f72008-12-31 18:08:47 -0800224 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
Mike Travis22f65d32008-12-16 17:33:56 -0800225 kfree(cfg);
226 cfg = NULL;
Mike Travis80855f72008-12-31 18:08:47 -0800227 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
228 GFP_ATOMIC, node)) {
Mike Travis22f65d32008-12-16 17:33:56 -0800229 free_cpumask_var(cfg->domain);
230 kfree(cfg);
231 cfg = NULL;
232 } else {
233 cpumask_clear(cfg->domain);
234 cpumask_clear(cfg->old_domain);
235 }
236 }
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800237
238 return cfg;
239}
240
Yinghai Lu13a0c3c2008-12-26 02:05:47 -0800241int arch_init_chip_data(struct irq_desc *desc, int cpu)
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800242{
243 struct irq_cfg *cfg;
244
245 cfg = desc->chip_data;
246 if (!cfg) {
247 desc->chip_data = get_one_free_irq_cfg(cpu);
248 if (!desc->chip_data) {
249 printk(KERN_ERR "can not alloc irq_cfg\n");
250 BUG_ON(1);
251 }
252 }
Yinghai Lu13a0c3c2008-12-26 02:05:47 -0800253
254 return 0;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800255}
256
Yinghai Lu48a1b102008-12-11 00:15:01 -0800257#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
258
259static void
260init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
261{
262 struct irq_pin_list *old_entry, *head, *tail, *entry;
263
264 cfg->irq_2_pin = NULL;
265 old_entry = old_cfg->irq_2_pin;
266 if (!old_entry)
267 return;
268
269 entry = get_one_free_irq_2_pin(cpu);
270 if (!entry)
271 return;
272
273 entry->apic = old_entry->apic;
274 entry->pin = old_entry->pin;
275 head = entry;
276 tail = entry;
277 old_entry = old_entry->next;
278 while (old_entry) {
279 entry = get_one_free_irq_2_pin(cpu);
280 if (!entry) {
281 entry = head;
282 while (entry) {
283 head = entry->next;
284 kfree(entry);
285 entry = head;
286 }
287 /* still use the old one */
288 return;
289 }
290 entry->apic = old_entry->apic;
291 entry->pin = old_entry->pin;
292 tail->next = entry;
293 tail = entry;
294 old_entry = old_entry->next;
295 }
296
297 tail->next = NULL;
298 cfg->irq_2_pin = head;
299}
300
301static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
302{
303 struct irq_pin_list *entry, *next;
304
305 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
306 return;
307
308 entry = old_cfg->irq_2_pin;
309
310 while (entry) {
311 next = entry->next;
312 kfree(entry);
313 entry = next;
314 }
315 old_cfg->irq_2_pin = NULL;
316}
317
318void arch_init_copy_chip_data(struct irq_desc *old_desc,
319 struct irq_desc *desc, int cpu)
320{
321 struct irq_cfg *cfg;
322 struct irq_cfg *old_cfg;
323
324 cfg = get_one_free_irq_cfg(cpu);
325
326 if (!cfg)
327 return;
328
329 desc->chip_data = cfg;
330
331 old_cfg = old_desc->chip_data;
332
333 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
334
335 init_copy_irq_2_pin(old_cfg, cfg, cpu);
336}
337
338static void free_irq_cfg(struct irq_cfg *old_cfg)
339{
340 kfree(old_cfg);
341}
342
343void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
344{
345 struct irq_cfg *old_cfg, *cfg;
346
347 old_cfg = old_desc->chip_data;
348 cfg = desc->chip_data;
349
350 if (old_cfg == cfg)
351 return;
352
353 if (old_cfg) {
354 free_irq_2_pin(old_cfg, cfg);
355 free_irq_cfg(old_cfg);
356 old_desc->chip_data = NULL;
357 }
358}
359
Ingo Molnard733e002008-12-17 13:35:51 +0100360static void
361set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
Yinghai Lu48a1b102008-12-11 00:15:01 -0800362{
363 struct irq_cfg *cfg = desc->chip_data;
364
365 if (!cfg->move_in_progress) {
366 /* it means that domain is not changed */
Mike Travis7f7ace02009-01-10 21:58:08 -0800367 if (!cpumask_intersects(desc->affinity, mask))
Yinghai Lu48a1b102008-12-11 00:15:01 -0800368 cfg->move_desc_pending = 1;
369 }
370}
371#endif
372
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800373#else
374static struct irq_cfg *irq_cfg(unsigned int irq)
375{
376 return irq < nr_irqs ? irq_cfgx + irq : NULL;
377}
378
379#endif
380
Yinghai Lu48a1b102008-12-11 00:15:01 -0800381#ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
Mike Travise7986732008-12-16 17:33:52 -0800382static inline void
383set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
Yinghai Lu3145e942008-12-05 18:58:34 -0800384{
385}
Yinghai Lu48a1b102008-12-11 00:15:01 -0800386#endif
Yinghai Lu3145e942008-12-05 18:58:34 -0800387
Linus Torvalds130fe052006-11-01 09:11:00 -0800388struct io_apic {
389 unsigned int index;
390 unsigned int unused[3];
391 unsigned int data;
Suresh Siddha0280f7c2009-03-16 17:05:01 -0700392 unsigned int unused2[11];
393 unsigned int eoi;
Linus Torvalds130fe052006-11-01 09:11:00 -0800394};
395
396static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
397{
398 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
Jaswinder Singh Rajputb5ba7e62009-01-12 17:46:17 +0530399 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
Linus Torvalds130fe052006-11-01 09:11:00 -0800400}
401
Suresh Siddha0280f7c2009-03-16 17:05:01 -0700402static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
403{
404 struct io_apic __iomem *io_apic = io_apic_base(apic);
405 writel(vector, &io_apic->eoi);
406}
407
Linus Torvalds130fe052006-11-01 09:11:00 -0800408static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
409{
410 struct io_apic __iomem *io_apic = io_apic_base(apic);
411 writel(reg, &io_apic->index);
412 return readl(&io_apic->data);
413}
414
415static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
416{
417 struct io_apic __iomem *io_apic = io_apic_base(apic);
418 writel(reg, &io_apic->index);
419 writel(value, &io_apic->data);
420}
421
422/*
423 * Re-write a value: to be used for read-modify-write
424 * cycles where the read already set up the index register.
425 *
426 * Older SiS APIC requires we rewrite the index register
427 */
428static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
429{
Ingo Molnar54168ed2008-08-20 09:07:45 +0200430 struct io_apic __iomem *io_apic = io_apic_base(apic);
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +0200431
432 if (sis_apic_bug)
433 writel(reg, &io_apic->index);
Linus Torvalds130fe052006-11-01 09:11:00 -0800434 writel(value, &io_apic->data);
435}
436
Yinghai Lu3145e942008-12-05 18:58:34 -0800437static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700438{
439 struct irq_pin_list *entry;
440 unsigned long flags;
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700441
442 spin_lock_irqsave(&ioapic_lock, flags);
443 entry = cfg->irq_2_pin;
444 for (;;) {
445 unsigned int reg;
446 int pin;
447
448 if (!entry)
449 break;
450 pin = entry->pin;
451 reg = io_apic_read(entry->apic, 0x10 + pin*2);
452 /* Is the remote IRR bit set? */
453 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
454 spin_unlock_irqrestore(&ioapic_lock, flags);
455 return true;
456 }
457 if (!entry->next)
458 break;
459 entry = entry->next;
460 }
461 spin_unlock_irqrestore(&ioapic_lock, flags);
462
463 return false;
464}
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700465
Andi Kleencf4c6a22006-09-26 10:52:30 +0200466union entry_union {
467 struct { u32 w1, w2; };
468 struct IO_APIC_route_entry entry;
469};
470
471static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
472{
473 union entry_union eu;
474 unsigned long flags;
475 spin_lock_irqsave(&ioapic_lock, flags);
476 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
477 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
478 spin_unlock_irqrestore(&ioapic_lock, flags);
479 return eu.entry;
480}
481
Linus Torvaldsf9dadfa2006-11-01 10:05:35 -0800482/*
483 * When we write a new IO APIC routing entry, we need to write the high
484 * word first! If the mask bit in the low word is clear, we will enable
485 * the interrupt, and we need to make sure the entry is fully populated
486 * before that happens.
487 */
Andi Kleend15512f2006-12-07 02:14:07 +0100488static void
489__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
490{
491 union entry_union eu;
492 eu.entry = e;
493 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
494 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
495}
496
Jeremy Fitzhardingeca97ab92009-02-09 12:05:47 -0800497void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
Andi Kleencf4c6a22006-09-26 10:52:30 +0200498{
499 unsigned long flags;
Andi Kleencf4c6a22006-09-26 10:52:30 +0200500 spin_lock_irqsave(&ioapic_lock, flags);
Andi Kleend15512f2006-12-07 02:14:07 +0100501 __ioapic_write_entry(apic, pin, e);
Linus Torvaldsf9dadfa2006-11-01 10:05:35 -0800502 spin_unlock_irqrestore(&ioapic_lock, flags);
503}
504
505/*
506 * When we mask an IO APIC routing entry, we need to write the low
507 * word first, in order to set the mask bit before we change the
508 * high bits!
509 */
510static void ioapic_mask_entry(int apic, int pin)
511{
512 unsigned long flags;
513 union entry_union eu = { .entry.mask = 1 };
514
515 spin_lock_irqsave(&ioapic_lock, flags);
Andi Kleencf4c6a22006-09-26 10:52:30 +0200516 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
517 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
518 spin_unlock_irqrestore(&ioapic_lock, flags);
519}
520
Yinghai Lu497c9a12008-08-19 20:50:28 -0700521#ifdef CONFIG_SMP
Mike Travis22f65d32008-12-16 17:33:56 -0800522static void send_cleanup_vector(struct irq_cfg *cfg)
523{
524 cpumask_var_t cleanup_mask;
525
526 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
527 unsigned int i;
528 cfg->move_cleanup_count = 0;
529 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
530 cfg->move_cleanup_count++;
531 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
Ingo Molnardac5f412009-01-28 15:42:24 +0100532 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
Mike Travis22f65d32008-12-16 17:33:56 -0800533 } else {
534 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
535 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
Ingo Molnardac5f412009-01-28 15:42:24 +0100536 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
Mike Travis22f65d32008-12-16 17:33:56 -0800537 free_cpumask_var(cleanup_mask);
538 }
539 cfg->move_in_progress = 0;
540}
541
Yinghai Lu3145e942008-12-05 18:58:34 -0800542static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
Yinghai Lu497c9a12008-08-19 20:50:28 -0700543{
544 int apic, pin;
Yinghai Lu497c9a12008-08-19 20:50:28 -0700545 struct irq_pin_list *entry;
Yinghai Lu3145e942008-12-05 18:58:34 -0800546 u8 vector = cfg->vector;
Yinghai Lu497c9a12008-08-19 20:50:28 -0700547
Yinghai Lu497c9a12008-08-19 20:50:28 -0700548 entry = cfg->irq_2_pin;
549 for (;;) {
550 unsigned int reg;
551
552 if (!entry)
553 break;
554
555 apic = entry->apic;
556 pin = entry->pin;
Ingo Molnar54168ed2008-08-20 09:07:45 +0200557 /*
558 * With interrupt-remapping, destination information comes
559 * from interrupt-remapping table entry.
560 */
561 if (!irq_remapped(irq))
562 io_apic_write(apic, 0x11 + pin*2, dest);
Yinghai Lu497c9a12008-08-19 20:50:28 -0700563 reg = io_apic_read(apic, 0x10 + pin*2);
564 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
565 reg |= vector;
Ingo Molnar54168ed2008-08-20 09:07:45 +0200566 io_apic_modify(apic, 0x10 + pin*2, reg);
Yinghai Lu497c9a12008-08-19 20:50:28 -0700567 if (!entry->next)
568 break;
569 entry = entry->next;
570 }
571}
Yinghai Luefa25592008-08-19 20:50:36 -0700572
Mike Travise7986732008-12-16 17:33:52 -0800573static int
574assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
Yinghai Luefa25592008-08-19 20:50:36 -0700575
Mike Travis22f65d32008-12-16 17:33:56 -0800576/*
Ingo Molnardebccb32009-01-28 15:20:18 +0100577 * Either sets desc->affinity to a valid value, and returns
578 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
579 * leaves desc->affinity untouched.
Mike Travis22f65d32008-12-16 17:33:56 -0800580 */
581static unsigned int
582set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
Yinghai Lu497c9a12008-08-19 20:50:28 -0700583{
584 struct irq_cfg *cfg;
Yinghai Lu3145e942008-12-05 18:58:34 -0800585 unsigned int irq;
Yinghai Lu497c9a12008-08-19 20:50:28 -0700586
Rusty Russell0de26522008-12-13 21:20:26 +1030587 if (!cpumask_intersects(mask, cpu_online_mask))
Mike Travis22f65d32008-12-16 17:33:56 -0800588 return BAD_APICID;
Yinghai Lu497c9a12008-08-19 20:50:28 -0700589
Yinghai Lu3145e942008-12-05 18:58:34 -0800590 irq = desc->irq;
591 cfg = desc->chip_data;
592 if (assign_irq_vector(irq, cfg, mask))
Mike Travis22f65d32008-12-16 17:33:56 -0800593 return BAD_APICID;
Yinghai Lu497c9a12008-08-19 20:50:28 -0700594
Yinghai Lufa74c902009-03-24 13:23:16 -0700595 /* check that before desc->addinity get updated */
Yinghai Lu3145e942008-12-05 18:58:34 -0800596 set_extra_move_desc(desc, mask);
Ingo Molnardebccb32009-01-28 15:20:18 +0100597
Rusty Russelle06b1b52009-03-24 14:17:19 -0700598 cpumask_copy(desc->affinity, mask);
599
600 return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
Mike Travis22f65d32008-12-16 17:33:56 -0800601}
Yinghai Lu3145e942008-12-05 18:58:34 -0800602
Mike Travis22f65d32008-12-16 17:33:56 -0800603static void
604set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
Yinghai Lu497c9a12008-08-19 20:50:28 -0700605{
606 struct irq_cfg *cfg;
607 unsigned long flags;
608 unsigned int dest;
Mike Travis22f65d32008-12-16 17:33:56 -0800609 unsigned int irq;
610
611 irq = desc->irq;
612 cfg = desc->chip_data;
Yinghai Lu497c9a12008-08-19 20:50:28 -0700613
614 spin_lock_irqsave(&ioapic_lock, flags);
Mike Travis22f65d32008-12-16 17:33:56 -0800615 dest = set_desc_affinity(desc, mask);
616 if (dest != BAD_APICID) {
617 /* Only the high 8 bits are valid. */
618 dest = SET_APIC_LOGICAL_ID(dest);
619 __target_IO_APIC_irq(irq, dest, cfg);
620 }
Yinghai Lu497c9a12008-08-19 20:50:28 -0700621 spin_unlock_irqrestore(&ioapic_lock, flags);
622}
Yinghai Lu3145e942008-12-05 18:58:34 -0800623
Mike Travis22f65d32008-12-16 17:33:56 -0800624static void
625set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
Yinghai Lu3145e942008-12-05 18:58:34 -0800626{
Yinghai Lu497c9a12008-08-19 20:50:28 -0700627 struct irq_desc *desc;
628
Yinghai Lu497c9a12008-08-19 20:50:28 -0700629 desc = irq_to_desc(irq);
Yinghai Lu3145e942008-12-05 18:58:34 -0800630
631 set_ioapic_affinity_irq_desc(desc, mask);
Yinghai Lu497c9a12008-08-19 20:50:28 -0700632}
Yinghai Lu497c9a12008-08-19 20:50:28 -0700633#endif /* CONFIG_SMP */
634
Linus Torvalds1da177e2005-04-16 15:20:36 -0700635/*
636 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
637 * shared ISA-space IRQs, so we have to support them. We are super
638 * fast in the common case, and fast for shared ISA-space IRQs.
639 */
Yinghai Lu3145e942008-12-05 18:58:34 -0800640static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641{
Yinghai Lu0f978f42008-08-19 20:50:26 -0700642 struct irq_pin_list *entry;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700643
Yinghai Lu0f978f42008-08-19 20:50:26 -0700644 entry = cfg->irq_2_pin;
645 if (!entry) {
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800646 entry = get_one_free_irq_2_pin(cpu);
647 if (!entry) {
648 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
649 apic, pin);
650 return;
651 }
Yinghai Lu0f978f42008-08-19 20:50:26 -0700652 cfg->irq_2_pin = entry;
653 entry->apic = apic;
654 entry->pin = pin;
Yinghai Lu0f978f42008-08-19 20:50:26 -0700655 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700656 }
Yinghai Lu0f978f42008-08-19 20:50:26 -0700657
658 while (entry->next) {
659 /* not again, please */
660 if (entry->apic == apic && entry->pin == pin)
661 return;
662
663 entry = entry->next;
664 }
665
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800666 entry->next = get_one_free_irq_2_pin(cpu);
Yinghai Lu0f978f42008-08-19 20:50:26 -0700667 entry = entry->next;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700668 entry->apic = apic;
669 entry->pin = pin;
670}
671
672/*
673 * Reroute an IRQ to a different pin.
674 */
Yinghai Lu3145e942008-12-05 18:58:34 -0800675static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700676 int oldapic, int oldpin,
677 int newapic, int newpin)
678{
Yinghai Lu0f978f42008-08-19 20:50:26 -0700679 struct irq_pin_list *entry = cfg->irq_2_pin;
680 int replaced = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700681
Yinghai Lu0f978f42008-08-19 20:50:26 -0700682 while (entry) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683 if (entry->apic == oldapic && entry->pin == oldpin) {
684 entry->apic = newapic;
685 entry->pin = newpin;
Yinghai Lu0f978f42008-08-19 20:50:26 -0700686 replaced = 1;
687 /* every one is different, right? */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700688 break;
Yinghai Lu0f978f42008-08-19 20:50:26 -0700689 }
690 entry = entry->next;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700691 }
Yinghai Lu0f978f42008-08-19 20:50:26 -0700692
693 /* why? call replace before add? */
694 if (!replaced)
Yinghai Lu3145e942008-12-05 18:58:34 -0800695 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696}
697
Yinghai Lu3145e942008-12-05 18:58:34 -0800698static inline void io_apic_modify_irq(struct irq_cfg *cfg,
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400699 int mask_and, int mask_or,
700 void (*final)(struct irq_pin_list *entry))
701{
702 int pin;
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400703 struct irq_pin_list *entry;
704
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400705 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
706 unsigned int reg;
707 pin = entry->pin;
708 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
709 reg &= mask_and;
710 reg |= mask_or;
711 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
712 if (final)
713 final(entry);
714 }
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700715}
716
Yinghai Lu3145e942008-12-05 18:58:34 -0800717static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400718{
Yinghai Lu3145e942008-12-05 18:58:34 -0800719 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400720}
Yinghai Lu4e738e22008-08-19 20:50:47 -0700721
722#ifdef CONFIG_X86_64
Jaswinder Singh Rajput7f3e6322008-12-29 20:34:35 +0530723static void io_apic_sync(struct irq_pin_list *entry)
Yinghai Lu4e738e22008-08-19 20:50:47 -0700724{
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400725 /*
726 * Synchronize the IO-APIC and the CPU by doing
727 * a dummy read from the IO-APIC
728 */
729 struct io_apic __iomem *io_apic;
730 io_apic = io_apic_base(entry->apic);
Yinghai Lu4e738e22008-08-19 20:50:47 -0700731 readl(&io_apic->data);
732}
733
Yinghai Lu3145e942008-12-05 18:58:34 -0800734static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400735{
Yinghai Lu3145e942008-12-05 18:58:34 -0800736 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400737}
738#else /* CONFIG_X86_32 */
Yinghai Lu3145e942008-12-05 18:58:34 -0800739static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400740{
Yinghai Lu3145e942008-12-05 18:58:34 -0800741 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400742}
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700743
Yinghai Lu3145e942008-12-05 18:58:34 -0800744static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400745{
Yinghai Lu3145e942008-12-05 18:58:34 -0800746 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400747 IO_APIC_REDIR_MASKED, NULL);
748}
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700749
Yinghai Lu3145e942008-12-05 18:58:34 -0800750static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400751{
Yinghai Lu3145e942008-12-05 18:58:34 -0800752 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400753 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
754}
755#endif /* CONFIG_X86_32 */
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700756
Yinghai Lu3145e942008-12-05 18:58:34 -0800757static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700758{
Yinghai Lu3145e942008-12-05 18:58:34 -0800759 struct irq_cfg *cfg = desc->chip_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700760 unsigned long flags;
761
Yinghai Lu3145e942008-12-05 18:58:34 -0800762 BUG_ON(!cfg);
763
Linus Torvalds1da177e2005-04-16 15:20:36 -0700764 spin_lock_irqsave(&ioapic_lock, flags);
Yinghai Lu3145e942008-12-05 18:58:34 -0800765 __mask_IO_APIC_irq(cfg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700766 spin_unlock_irqrestore(&ioapic_lock, flags);
767}
768
Yinghai Lu3145e942008-12-05 18:58:34 -0800769static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770{
Yinghai Lu3145e942008-12-05 18:58:34 -0800771 struct irq_cfg *cfg = desc->chip_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772 unsigned long flags;
773
774 spin_lock_irqsave(&ioapic_lock, flags);
Yinghai Lu3145e942008-12-05 18:58:34 -0800775 __unmask_IO_APIC_irq(cfg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776 spin_unlock_irqrestore(&ioapic_lock, flags);
777}
778
Yinghai Lu3145e942008-12-05 18:58:34 -0800779static void mask_IO_APIC_irq(unsigned int irq)
780{
781 struct irq_desc *desc = irq_to_desc(irq);
782
783 mask_IO_APIC_irq_desc(desc);
784}
785static void unmask_IO_APIC_irq(unsigned int irq)
786{
787 struct irq_desc *desc = irq_to_desc(irq);
788
789 unmask_IO_APIC_irq_desc(desc);
790}
791
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
793{
794 struct IO_APIC_route_entry entry;
Paolo Ciarrocchi36062442008-06-08 13:07:18 +0200795
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796 /* Check delivery_mode to be sure we're not clearing an SMI pin */
Andi Kleencf4c6a22006-09-26 10:52:30 +0200797 entry = ioapic_read_entry(apic, pin);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798 if (entry.delivery_mode == dest_SMI)
799 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700800 /*
801 * Disable it in the IO-APIC irq-routing table:
802 */
Linus Torvaldsf9dadfa2006-11-01 10:05:35 -0800803 ioapic_mask_entry(apic, pin);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700804}
805
Ingo Molnar54168ed2008-08-20 09:07:45 +0200806static void clear_IO_APIC (void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807{
808 int apic, pin;
809
810 for (apic = 0; apic < nr_ioapics; apic++)
811 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
812 clear_IO_APIC_pin(apic, pin);
813}
814
Ingo Molnar54168ed2008-08-20 09:07:45 +0200815#ifdef CONFIG_X86_32
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816/*
817 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
818 * specific CPU-side IRQs.
819 */
820
821#define MAX_PIRQS 8
Yinghai Lu3bd25d02009-02-15 02:54:03 -0800822static int pirq_entries[MAX_PIRQS] = {
823 [0 ... MAX_PIRQS - 1] = -1
824};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825
Linus Torvalds1da177e2005-04-16 15:20:36 -0700826static int __init ioapic_pirq_setup(char *str)
827{
828 int i, max;
829 int ints[MAX_PIRQS+1];
830
831 get_options(str, ARRAY_SIZE(ints), ints);
832
Linus Torvalds1da177e2005-04-16 15:20:36 -0700833 apic_printk(APIC_VERBOSE, KERN_INFO
834 "PIRQ redirection, working around broken MP-BIOS.\n");
835 max = MAX_PIRQS;
836 if (ints[0] < MAX_PIRQS)
837 max = ints[0];
838
839 for (i = 0; i < max; i++) {
840 apic_printk(APIC_VERBOSE, KERN_DEBUG
841 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
842 /*
843 * PIRQs are mapped upside down, usually.
844 */
845 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
846 }
847 return 1;
848}
849
850__setup("pirq=", ioapic_pirq_setup);
Ingo Molnar54168ed2008-08-20 09:07:45 +0200851#endif /* CONFIG_X86_32 */
852
853#ifdef CONFIG_INTR_REMAP
854/* I/O APIC RTE contents at the OS boot up */
855static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
856
857/*
Suresh Siddha05c3dc22009-03-16 17:05:03 -0700858 * Saves all the IO-APIC RTE's
Ingo Molnar54168ed2008-08-20 09:07:45 +0200859 */
Suresh Siddha05c3dc22009-03-16 17:05:03 -0700860int save_IO_APIC_setup(void)
Ingo Molnar54168ed2008-08-20 09:07:45 +0200861{
862 union IO_APIC_reg_01 reg_01;
863 unsigned long flags;
864 int apic, pin;
865
866 /*
867 * The number of IO-APIC IRQ registers (== #pins):
868 */
869 for (apic = 0; apic < nr_ioapics; apic++) {
870 spin_lock_irqsave(&ioapic_lock, flags);
871 reg_01.raw = io_apic_read(apic, 1);
872 spin_unlock_irqrestore(&ioapic_lock, flags);
873 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
874 }
875
876 for (apic = 0; apic < nr_ioapics; apic++) {
877 early_ioapic_entries[apic] =
878 kzalloc(sizeof(struct IO_APIC_route_entry) *
879 nr_ioapic_registers[apic], GFP_KERNEL);
880 if (!early_ioapic_entries[apic])
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +0400881 goto nomem;
Ingo Molnar54168ed2008-08-20 09:07:45 +0200882 }
883
884 for (apic = 0; apic < nr_ioapics; apic++)
Suresh Siddha05c3dc22009-03-16 17:05:03 -0700885 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
886 early_ioapic_entries[apic][pin] =
Ingo Molnar54168ed2008-08-20 09:07:45 +0200887 ioapic_read_entry(apic, pin);
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +0400888
Ingo Molnar54168ed2008-08-20 09:07:45 +0200889 return 0;
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +0400890
891nomem:
Cyrill Gorcunovc1370b42008-09-23 23:00:02 +0400892 while (apic >= 0)
893 kfree(early_ioapic_entries[apic--]);
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +0400894 memset(early_ioapic_entries, 0,
895 ARRAY_SIZE(early_ioapic_entries));
896
897 return -ENOMEM;
Ingo Molnar54168ed2008-08-20 09:07:45 +0200898}
899
Suresh Siddha05c3dc22009-03-16 17:05:03 -0700900void mask_IO_APIC_setup(void)
901{
902 int apic, pin;
903
904 for (apic = 0; apic < nr_ioapics; apic++) {
905 if (!early_ioapic_entries[apic])
906 break;
907 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
908 struct IO_APIC_route_entry entry;
909
910 entry = early_ioapic_entries[apic][pin];
911 if (!entry.mask) {
912 entry.mask = 1;
913 ioapic_write_entry(apic, pin, entry);
914 }
915 }
916 }
917}
918
Ingo Molnar54168ed2008-08-20 09:07:45 +0200919void restore_IO_APIC_setup(void)
920{
921 int apic, pin;
922
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +0400923 for (apic = 0; apic < nr_ioapics; apic++) {
924 if (!early_ioapic_entries[apic])
925 break;
Ingo Molnar54168ed2008-08-20 09:07:45 +0200926 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
927 ioapic_write_entry(apic, pin,
928 early_ioapic_entries[apic][pin]);
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +0400929 kfree(early_ioapic_entries[apic]);
930 early_ioapic_entries[apic] = NULL;
931 }
Ingo Molnar54168ed2008-08-20 09:07:45 +0200932}
933
934void reinit_intr_remapped_IO_APIC(int intr_remapping)
935{
936 /*
937 * for now plain restore of previous settings.
938 * TBD: In the case of OS enabling interrupt-remapping,
939 * IO-APIC RTE's need to be setup to point to interrupt-remapping
940 * table entries. for now, do a plain restore, and wait for
941 * the setup_IO_APIC_irqs() to do proper initialization.
942 */
943 restore_IO_APIC_setup();
944}
945#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700946
947/*
948 * Find the IRQ entry number of a certain pin.
949 */
950static int find_irq_entry(int apic, int pin, int type)
951{
952 int i;
953
954 for (i = 0; i < mp_irq_entries; i++)
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +0530955 if (mp_irqs[i].irqtype == type &&
956 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
957 mp_irqs[i].dstapic == MP_APIC_ALL) &&
958 mp_irqs[i].dstirq == pin)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700959 return i;
960
961 return -1;
962}
963
964/*
965 * Find the pin to which IRQ[irq] (ISA) is connected
966 */
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -0800967static int __init find_isa_irq_pin(int irq, int type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700968{
969 int i;
970
971 for (i = 0; i < mp_irq_entries; i++) {
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +0530972 int lbus = mp_irqs[i].srcbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700973
Alexey Starikovskiyd27e2b82008-03-20 14:54:18 +0300974 if (test_bit(lbus, mp_bus_not_pci) &&
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +0530975 (mp_irqs[i].irqtype == type) &&
976 (mp_irqs[i].srcbusirq == irq))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700977
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +0530978 return mp_irqs[i].dstirq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700979 }
980 return -1;
981}
982
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -0800983static int __init find_isa_irq_apic(int irq, int type)
984{
985 int i;
986
987 for (i = 0; i < mp_irq_entries; i++) {
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +0530988 int lbus = mp_irqs[i].srcbus;
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -0800989
Alexey Starikovskiy73b29612008-03-20 14:54:24 +0300990 if (test_bit(lbus, mp_bus_not_pci) &&
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +0530991 (mp_irqs[i].irqtype == type) &&
992 (mp_irqs[i].srcbusirq == irq))
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -0800993 break;
994 }
995 if (i < mp_irq_entries) {
996 int apic;
Ingo Molnar54168ed2008-08-20 09:07:45 +0200997 for(apic = 0; apic < nr_ioapics; apic++) {
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +0530998 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -0800999 return apic;
1000 }
1001 }
1002
1003 return -1;
1004}
1005
Linus Torvalds1da177e2005-04-16 15:20:36 -07001006/*
1007 * Find a specific PCI IRQ entry.
1008 * Not an __init, possibly needed by modules
1009 */
1010static int pin_2_irq(int idx, int apic, int pin);
1011
1012int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1013{
1014 int apic, i, best_guess = -1;
1015
Ingo Molnar54168ed2008-08-20 09:07:45 +02001016 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1017 bus, slot, pin);
Alexey Starikovskiyce6444d2008-05-19 19:47:09 +04001018 if (test_bit(bus, mp_bus_not_pci)) {
Ingo Molnar54168ed2008-08-20 09:07:45 +02001019 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001020 return -1;
1021 }
1022 for (i = 0; i < mp_irq_entries; i++) {
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301023 int lbus = mp_irqs[i].srcbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024
1025 for (apic = 0; apic < nr_ioapics; apic++)
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301026 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1027 mp_irqs[i].dstapic == MP_APIC_ALL)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001028 break;
1029
Alexey Starikovskiy47cab822008-03-20 14:54:30 +03001030 if (!test_bit(lbus, mp_bus_not_pci) &&
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301031 !mp_irqs[i].irqtype &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07001032 (bus == lbus) &&
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301033 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1034 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001035
1036 if (!(apic || IO_APIC_IRQ(irq)))
1037 continue;
1038
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301039 if (pin == (mp_irqs[i].srcbusirq & 3))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001040 return irq;
1041 /*
1042 * Use the first all-but-pin matching entry as a
1043 * best-guess fuzzy result for broken mptables.
1044 */
1045 if (best_guess < 0)
1046 best_guess = irq;
1047 }
1048 }
1049 return best_guess;
1050}
Ingo Molnar54168ed2008-08-20 09:07:45 +02001051
Alexey Dobriyan129f6942005-06-23 00:08:33 -07001052EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001053
Alexey Starikovskiyc0a282c2008-03-20 14:55:02 +03001054#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001055/*
1056 * EISA Edge/Level control register, ELCR
1057 */
1058static int EISA_ELCR(unsigned int irq)
1059{
Yinghai Lu99d093d2008-12-05 18:58:32 -08001060 if (irq < NR_IRQS_LEGACY) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001061 unsigned int port = 0x4d0 + (irq >> 3);
1062 return (inb(port) >> (irq & 7)) & 1;
1063 }
1064 apic_printk(APIC_VERBOSE, KERN_INFO
1065 "Broken MPtable reports ISA irq %d\n", irq);
1066 return 0;
1067}
Ingo Molnar54168ed2008-08-20 09:07:45 +02001068
Alexey Starikovskiyc0a282c2008-03-20 14:55:02 +03001069#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001070
Alexey Starikovskiy67288012008-03-20 14:54:36 +03001071/* ISA interrupts are always polarity zero edge triggered,
1072 * when listed as conforming in the MP table. */
1073
1074#define default_ISA_trigger(idx) (0)
1075#define default_ISA_polarity(idx) (0)
1076
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077/* EISA interrupts are always polarity zero and can be edge or level
1078 * trigger depending on the ELCR value. If an interrupt is listed as
1079 * EISA conforming in the MP table, that means its trigger type must
1080 * be read in from the ELCR */
1081
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301082#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
Alexey Starikovskiy67288012008-03-20 14:54:36 +03001083#define default_EISA_polarity(idx) default_ISA_polarity(idx)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001084
1085/* PCI interrupts are always polarity one level triggered,
1086 * when listed as conforming in the MP table. */
1087
1088#define default_PCI_trigger(idx) (1)
1089#define default_PCI_polarity(idx) (1)
1090
1091/* MCA interrupts are always polarity zero level triggered,
1092 * when listed as conforming in the MP table. */
1093
1094#define default_MCA_trigger(idx) (1)
Alexey Starikovskiy67288012008-03-20 14:54:36 +03001095#define default_MCA_polarity(idx) default_ISA_polarity(idx)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001096
Shaohua Li61fd47e2007-11-17 01:05:28 -05001097static int MPBIOS_polarity(int idx)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001098{
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301099 int bus = mp_irqs[idx].srcbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100 int polarity;
1101
1102 /*
1103 * Determine IRQ line polarity (high active or low active):
1104 */
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301105 switch (mp_irqs[idx].irqflag & 3)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001106 {
Ingo Molnar54168ed2008-08-20 09:07:45 +02001107 case 0: /* conforms, ie. bus-type dependent polarity */
1108 if (test_bit(bus, mp_bus_not_pci))
1109 polarity = default_ISA_polarity(idx);
1110 else
1111 polarity = default_PCI_polarity(idx);
1112 break;
1113 case 1: /* high active */
1114 {
1115 polarity = 0;
1116 break;
1117 }
1118 case 2: /* reserved */
1119 {
1120 printk(KERN_WARNING "broken BIOS!!\n");
1121 polarity = 1;
1122 break;
1123 }
1124 case 3: /* low active */
1125 {
1126 polarity = 1;
1127 break;
1128 }
1129 default: /* invalid */
1130 {
1131 printk(KERN_WARNING "broken BIOS!!\n");
1132 polarity = 1;
1133 break;
1134 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001135 }
1136 return polarity;
1137}
1138
1139static int MPBIOS_trigger(int idx)
1140{
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301141 int bus = mp_irqs[idx].srcbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001142 int trigger;
1143
1144 /*
1145 * Determine IRQ trigger mode (edge or level sensitive):
1146 */
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301147 switch ((mp_irqs[idx].irqflag>>2) & 3)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001148 {
Ingo Molnar54168ed2008-08-20 09:07:45 +02001149 case 0: /* conforms, ie. bus-type dependent */
1150 if (test_bit(bus, mp_bus_not_pci))
1151 trigger = default_ISA_trigger(idx);
1152 else
1153 trigger = default_PCI_trigger(idx);
Alexey Starikovskiyc0a282c2008-03-20 14:55:02 +03001154#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
Ingo Molnar54168ed2008-08-20 09:07:45 +02001155 switch (mp_bus_id_to_type[bus]) {
1156 case MP_BUS_ISA: /* ISA pin */
1157 {
1158 /* set before the switch */
1159 break;
1160 }
1161 case MP_BUS_EISA: /* EISA pin */
1162 {
1163 trigger = default_EISA_trigger(idx);
1164 break;
1165 }
1166 case MP_BUS_PCI: /* PCI pin */
1167 {
1168 /* set before the switch */
1169 break;
1170 }
1171 case MP_BUS_MCA: /* MCA pin */
1172 {
1173 trigger = default_MCA_trigger(idx);
1174 break;
1175 }
1176 default:
1177 {
1178 printk(KERN_WARNING "broken BIOS!!\n");
1179 trigger = 1;
1180 break;
1181 }
1182 }
1183#endif
1184 break;
1185 case 1: /* edge */
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02001186 {
Ingo Molnar54168ed2008-08-20 09:07:45 +02001187 trigger = 0;
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02001188 break;
1189 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02001190 case 2: /* reserved */
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02001191 {
1192 printk(KERN_WARNING "broken BIOS!!\n");
1193 trigger = 1;
1194 break;
1195 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02001196 case 3: /* level */
1197 {
1198 trigger = 1;
1199 break;
1200 }
1201 default: /* invalid */
1202 {
1203 printk(KERN_WARNING "broken BIOS!!\n");
1204 trigger = 0;
1205 break;
1206 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001207 }
1208 return trigger;
1209}
1210
1211static inline int irq_polarity(int idx)
1212{
1213 return MPBIOS_polarity(idx);
1214}
1215
1216static inline int irq_trigger(int idx)
1217{
1218 return MPBIOS_trigger(idx);
1219}
1220
Yinghai Luefa25592008-08-19 20:50:36 -07001221int (*ioapic_renumber_irq)(int ioapic, int irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001222static int pin_2_irq(int idx, int apic, int pin)
1223{
1224 int irq, i;
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301225 int bus = mp_irqs[idx].srcbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001226
1227 /*
1228 * Debugging check, we are in big trouble if this message pops up!
1229 */
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301230 if (mp_irqs[idx].dstirq != pin)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001231 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1232
Ingo Molnar54168ed2008-08-20 09:07:45 +02001233 if (test_bit(bus, mp_bus_not_pci)) {
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301234 irq = mp_irqs[idx].srcbusirq;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001235 } else {
Alexey Starikovskiy643befe2008-03-20 14:54:49 +03001236 /*
1237 * PCI IRQs are mapped in order
1238 */
1239 i = irq = 0;
1240 while (i < apic)
1241 irq += nr_ioapic_registers[i++];
1242 irq += pin;
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02001243 /*
Ingo Molnar54168ed2008-08-20 09:07:45 +02001244 * For MPS mode, so far only needed by ES7000 platform
1245 */
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02001246 if (ioapic_renumber_irq)
1247 irq = ioapic_renumber_irq(apic, irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001248 }
1249
Ingo Molnar54168ed2008-08-20 09:07:45 +02001250#ifdef CONFIG_X86_32
Linus Torvalds1da177e2005-04-16 15:20:36 -07001251 /*
1252 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1253 */
1254 if ((pin >= 16) && (pin <= 23)) {
1255 if (pirq_entries[pin-16] != -1) {
1256 if (!pirq_entries[pin-16]) {
1257 apic_printk(APIC_VERBOSE, KERN_DEBUG
1258 "disabling PIRQ%d\n", pin-16);
1259 } else {
1260 irq = pirq_entries[pin-16];
1261 apic_printk(APIC_VERBOSE, KERN_DEBUG
1262 "using PIRQ%d -> IRQ %d\n",
1263 pin-16, irq);
1264 }
1265 }
1266 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02001267#endif
1268
Linus Torvalds1da177e2005-04-16 15:20:36 -07001269 return irq;
1270}
1271
Yinghai Lu497c9a12008-08-19 20:50:28 -07001272void lock_vector_lock(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001273{
Yinghai Lu497c9a12008-08-19 20:50:28 -07001274 /* Used to the online set of cpus does not change
1275 * during assign_irq_vector.
1276 */
1277 spin_lock(&vector_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001278}
1279
Yinghai Lu497c9a12008-08-19 20:50:28 -07001280void unlock_vector_lock(void)
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07001281{
Yinghai Lu497c9a12008-08-19 20:50:28 -07001282 spin_unlock(&vector_lock);
1283}
1284
Mike Travise7986732008-12-16 17:33:52 -08001285static int
1286__assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001287{
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001288 /*
1289 * NOTE! The local APIC isn't very good at handling
1290 * multiple interrupts at the same interrupt level.
1291 * As the interrupt level is determined by taking the
1292 * vector number and shifting that right by 4, we
1293 * want to spread these out a bit so that they don't
1294 * all fall in the same interrupt level.
1295 *
1296 * Also, we've got to be careful not to trash gate
1297 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1298 */
Ingo Molnar54168ed2008-08-20 09:07:45 +02001299 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1300 unsigned int old_vector;
Mike Travis22f65d32008-12-16 17:33:56 -08001301 int cpu, err;
1302 cpumask_var_t tmp_mask;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001303
Ingo Molnar54168ed2008-08-20 09:07:45 +02001304 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1305 return -EBUSY;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001306
Mike Travis22f65d32008-12-16 17:33:56 -08001307 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1308 return -ENOMEM;
Yinghai Lu3145e942008-12-05 18:58:34 -08001309
Ingo Molnar54168ed2008-08-20 09:07:45 +02001310 old_vector = cfg->vector;
1311 if (old_vector) {
Mike Travis22f65d32008-12-16 17:33:56 -08001312 cpumask_and(tmp_mask, mask, cpu_online_mask);
1313 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1314 if (!cpumask_empty(tmp_mask)) {
1315 free_cpumask_var(tmp_mask);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001316 return 0;
Mike Travis22f65d32008-12-16 17:33:56 -08001317 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02001318 }
Yinghai Lu497c9a12008-08-19 20:50:28 -07001319
Mike Travise7986732008-12-16 17:33:52 -08001320 /* Only try and allocate irqs on cpus that are present */
Mike Travis22f65d32008-12-16 17:33:56 -08001321 err = -ENOSPC;
1322 for_each_cpu_and(cpu, mask, cpu_online_mask) {
Ingo Molnar54168ed2008-08-20 09:07:45 +02001323 int new_cpu;
1324 int vector, offset;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001325
Ingo Molnare2d40b12009-01-28 06:50:47 +01001326 apic->vector_allocation_domain(cpu, tmp_mask);
Yinghai Lu497c9a12008-08-19 20:50:28 -07001327
Ingo Molnar54168ed2008-08-20 09:07:45 +02001328 vector = current_vector;
1329 offset = current_offset;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001330next:
Ingo Molnar54168ed2008-08-20 09:07:45 +02001331 vector += 8;
1332 if (vector >= first_system_vector) {
Mike Travise7986732008-12-16 17:33:52 -08001333 /* If out of vectors on large boxen, must share them. */
Ingo Molnar54168ed2008-08-20 09:07:45 +02001334 offset = (offset + 1) % 8;
1335 vector = FIRST_DEVICE_VECTOR + offset;
Yinghai Lu7a959cf2008-08-19 20:50:32 -07001336 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02001337 if (unlikely(current_vector == vector))
1338 continue;
Yinghai Lub77b8812008-12-19 15:23:44 -08001339
1340 if (test_bit(vector, used_vectors))
Ingo Molnar54168ed2008-08-20 09:07:45 +02001341 goto next;
Yinghai Lub77b8812008-12-19 15:23:44 -08001342
Mike Travis22f65d32008-12-16 17:33:56 -08001343 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02001344 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1345 goto next;
1346 /* Found one! */
1347 current_vector = vector;
1348 current_offset = offset;
1349 if (old_vector) {
1350 cfg->move_in_progress = 1;
Mike Travis22f65d32008-12-16 17:33:56 -08001351 cpumask_copy(cfg->old_domain, cfg->domain);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001352 }
Mike Travis22f65d32008-12-16 17:33:56 -08001353 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02001354 per_cpu(vector_irq, new_cpu)[vector] = irq;
1355 cfg->vector = vector;
Mike Travis22f65d32008-12-16 17:33:56 -08001356 cpumask_copy(cfg->domain, tmp_mask);
1357 err = 0;
1358 break;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001359 }
Mike Travis22f65d32008-12-16 17:33:56 -08001360 free_cpumask_var(tmp_mask);
1361 return err;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001362}
1363
Mike Travise7986732008-12-16 17:33:52 -08001364static int
1365assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001366{
1367 int err;
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07001368 unsigned long flags;
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07001369
1370 spin_lock_irqsave(&vector_lock, flags);
Yinghai Lu3145e942008-12-05 18:58:34 -08001371 err = __assign_irq_vector(irq, cfg, mask);
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07001372 spin_unlock_irqrestore(&vector_lock, flags);
Yinghai Lu497c9a12008-08-19 20:50:28 -07001373 return err;
1374}
1375
Yinghai Lu3145e942008-12-05 18:58:34 -08001376static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001377{
Yinghai Lu497c9a12008-08-19 20:50:28 -07001378 int cpu, vector;
1379
Yinghai Lu497c9a12008-08-19 20:50:28 -07001380 BUG_ON(!cfg->vector);
1381
1382 vector = cfg->vector;
Mike Travis22f65d32008-12-16 17:33:56 -08001383 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001384 per_cpu(vector_irq, cpu)[vector] = -1;
1385
1386 cfg->vector = 0;
Mike Travis22f65d32008-12-16 17:33:56 -08001387 cpumask_clear(cfg->domain);
Matthew Wilcox0ca4b6b2008-11-20 14:09:33 -07001388
1389 if (likely(!cfg->move_in_progress))
1390 return;
Mike Travis22f65d32008-12-16 17:33:56 -08001391 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
Matthew Wilcox0ca4b6b2008-11-20 14:09:33 -07001392 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1393 vector++) {
1394 if (per_cpu(vector_irq, cpu)[vector] != irq)
1395 continue;
1396 per_cpu(vector_irq, cpu)[vector] = -1;
1397 break;
1398 }
1399 }
1400 cfg->move_in_progress = 0;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001401}
1402
1403void __setup_vector_irq(int cpu)
1404{
1405 /* Initialize vector_irq on a new cpu */
1406 /* This function must be called with vector_lock held */
1407 int irq, vector;
1408 struct irq_cfg *cfg;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001409 struct irq_desc *desc;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001410
1411 /* Mark the inuse vectors */
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001412 for_each_irq_desc(irq, desc) {
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001413 cfg = desc->chip_data;
Mike Travis22f65d32008-12-16 17:33:56 -08001414 if (!cpumask_test_cpu(cpu, cfg->domain))
Yinghai Lu497c9a12008-08-19 20:50:28 -07001415 continue;
1416 vector = cfg->vector;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001417 per_cpu(vector_irq, cpu)[vector] = irq;
1418 }
1419 /* Mark the free vectors */
1420 for (vector = 0; vector < NR_VECTORS; ++vector) {
1421 irq = per_cpu(vector_irq, cpu)[vector];
1422 if (irq < 0)
1423 continue;
1424
1425 cfg = irq_cfg(irq);
Mike Travis22f65d32008-12-16 17:33:56 -08001426 if (!cpumask_test_cpu(cpu, cfg->domain))
Yinghai Lu497c9a12008-08-19 20:50:28 -07001427 per_cpu(vector_irq, cpu)[vector] = -1;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001428 }
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07001429}
Glauber Costa3fde6902008-05-28 20:34:19 -07001430
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07001431static struct irq_chip ioapic_chip;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001432static struct irq_chip ir_ioapic_chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001433
Ingo Molnar54168ed2008-08-20 09:07:45 +02001434#define IOAPIC_AUTO -1
1435#define IOAPIC_EDGE 0
1436#define IOAPIC_LEVEL 1
Linus Torvalds1da177e2005-04-16 15:20:36 -07001437
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001438#ifdef CONFIG_X86_32
Yinghai Lu1d025192008-08-19 20:50:34 -07001439static inline int IO_APIC_irq_trigger(int irq)
1440{
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02001441 int apic, idx, pin;
Yinghai Lu1d025192008-08-19 20:50:34 -07001442
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02001443 for (apic = 0; apic < nr_ioapics; apic++) {
1444 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1445 idx = find_irq_entry(apic, pin, mp_INT);
1446 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1447 return irq_trigger(idx);
1448 }
1449 }
1450 /*
Ingo Molnar54168ed2008-08-20 09:07:45 +02001451 * nonexistent IRQs are edge default
1452 */
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02001453 return 0;
Yinghai Lu1d025192008-08-19 20:50:34 -07001454}
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001455#else
1456static inline int IO_APIC_irq_trigger(int irq)
1457{
Ingo Molnar54168ed2008-08-20 09:07:45 +02001458 return 1;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001459}
1460#endif
Yinghai Lu1d025192008-08-19 20:50:34 -07001461
Yinghai Lu3145e942008-12-05 18:58:34 -08001462static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001463{
Yinghai Lu199751d2008-08-19 20:50:27 -07001464
Jan Beulich6ebcc002006-06-26 13:56:46 +02001465 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001466 trigger == IOAPIC_LEVEL)
Yinghai Lu08678b02008-08-19 20:50:05 -07001467 desc->status |= IRQ_LEVEL;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001468 else
1469 desc->status &= ~IRQ_LEVEL;
1470
Ingo Molnar54168ed2008-08-20 09:07:45 +02001471 if (irq_remapped(irq)) {
1472 desc->status |= IRQ_MOVE_PCNTXT;
1473 if (trigger)
1474 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1475 handle_fasteoi_irq,
1476 "fasteoi");
1477 else
1478 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1479 handle_edge_irq, "edge");
1480 return;
1481 }
Suresh Siddha29b61be2009-03-16 17:05:02 -07001482
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001483 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1484 trigger == IOAPIC_LEVEL)
Ingo Molnara460e742006-10-17 00:10:03 -07001485 set_irq_chip_and_handler_name(irq, &ioapic_chip,
Ingo Molnar54168ed2008-08-20 09:07:45 +02001486 handle_fasteoi_irq,
1487 "fasteoi");
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001488 else
Ingo Molnara460e742006-10-17 00:10:03 -07001489 set_irq_chip_and_handler_name(irq, &ioapic_chip,
Ingo Molnar54168ed2008-08-20 09:07:45 +02001490 handle_edge_irq, "edge");
Yinghai Lu497c9a12008-08-19 20:50:28 -07001491}
1492
Jeremy Fitzhardingeca97ab92009-02-09 12:05:47 -08001493int setup_ioapic_entry(int apic_id, int irq,
1494 struct IO_APIC_route_entry *entry,
1495 unsigned int destination, int trigger,
Suresh Siddha0280f7c2009-03-16 17:05:01 -07001496 int polarity, int vector, int pin)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001497{
1498 /*
1499 * add it to the IO-APIC irq-routing table:
1500 */
1501 memset(entry,0,sizeof(*entry));
1502
Ingo Molnar54168ed2008-08-20 09:07:45 +02001503 if (intr_remapping_enabled) {
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001504 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001505 struct irte irte;
1506 struct IR_IO_APIC_route_entry *ir_entry =
1507 (struct IR_IO_APIC_route_entry *) entry;
1508 int index;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001509
Ingo Molnar54168ed2008-08-20 09:07:45 +02001510 if (!iommu)
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001511 panic("No mapping iommu for ioapic %d\n", apic_id);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001512
1513 index = alloc_irte(iommu, irq, 1);
1514 if (index < 0)
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001515 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001516
1517 memset(&irte, 0, sizeof(irte));
1518
1519 irte.present = 1;
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01001520 irte.dst_mode = apic->irq_dest_mode;
Suresh Siddha0280f7c2009-03-16 17:05:01 -07001521 /*
1522 * Trigger mode in the IRTE will always be edge, and the
1523 * actual level or edge trigger will be setup in the IO-APIC
1524 * RTE. This will help simplify level triggered irq migration.
1525 * For more details, see the comments above explainig IO-APIC
1526 * irq migration in the presence of interrupt-remapping.
1527 */
1528 irte.trigger_mode = 0;
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01001529 irte.dlvry_mode = apic->irq_delivery_mode;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001530 irte.vector = vector;
1531 irte.dest_id = IRTE_DEST(destination);
1532
1533 modify_irte(irq, &irte);
1534
1535 ir_entry->index2 = (index >> 15) & 0x1;
1536 ir_entry->zero = 0;
1537 ir_entry->format = 1;
1538 ir_entry->index = (index & 0x7fff);
Suresh Siddha0280f7c2009-03-16 17:05:01 -07001539 /*
1540 * IO-APIC RTE will be configured with virtual vector.
1541 * irq handler will do the explicit EOI to the io-apic.
1542 */
1543 ir_entry->vector = pin;
Suresh Siddha29b61be2009-03-16 17:05:02 -07001544 } else {
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01001545 entry->delivery_mode = apic->irq_delivery_mode;
1546 entry->dest_mode = apic->irq_dest_mode;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001547 entry->dest = destination;
Suresh Siddha0280f7c2009-03-16 17:05:01 -07001548 entry->vector = vector;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001549 }
1550
1551 entry->mask = 0; /* enable IRQ */
Yinghai Lu497c9a12008-08-19 20:50:28 -07001552 entry->trigger = trigger;
1553 entry->polarity = polarity;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001554
1555 /* Mask level triggered irqs.
1556 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1557 */
1558 if (trigger)
1559 entry->mask = 1;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001560 return 0;
1561}
1562
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001563static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
Ingo Molnar54168ed2008-08-20 09:07:45 +02001564 int trigger, int polarity)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001565{
1566 struct irq_cfg *cfg;
1567 struct IO_APIC_route_entry entry;
Mike Travis22f65d32008-12-16 17:33:56 -08001568 unsigned int dest;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001569
1570 if (!IO_APIC_IRQ(irq))
1571 return;
1572
Yinghai Lu3145e942008-12-05 18:58:34 -08001573 cfg = desc->chip_data;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001574
Ingo Molnarfe402e12009-01-28 04:32:51 +01001575 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
Yinghai Lu497c9a12008-08-19 20:50:28 -07001576 return;
1577
Ingo Molnardebccb32009-01-28 15:20:18 +01001578 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
Yinghai Lu497c9a12008-08-19 20:50:28 -07001579
1580 apic_printk(APIC_VERBOSE,KERN_DEBUG
1581 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1582 "IRQ %d Mode:%i Active:%i)\n",
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001583 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
Yinghai Lu497c9a12008-08-19 20:50:28 -07001584 irq, trigger, polarity);
1585
1586
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001587 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
Suresh Siddha0280f7c2009-03-16 17:05:01 -07001588 dest, trigger, polarity, cfg->vector, pin)) {
Yinghai Lu497c9a12008-08-19 20:50:28 -07001589 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001590 mp_ioapics[apic_id].apicid, pin);
Yinghai Lu3145e942008-12-05 18:58:34 -08001591 __clear_irq_vector(irq, cfg);
Yinghai Lu497c9a12008-08-19 20:50:28 -07001592 return;
1593 }
1594
Yinghai Lu3145e942008-12-05 18:58:34 -08001595 ioapic_register_intr(irq, desc, trigger);
Yinghai Lu99d093d2008-12-05 18:58:32 -08001596 if (irq < NR_IRQS_LEGACY)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001597 disable_8259A_irq(irq);
1598
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001599 ioapic_write_entry(apic_id, pin, entry);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001600}
1601
1602static void __init setup_IO_APIC_irqs(void)
1603{
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001604 int apic_id, pin, idx, irq;
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001605 int notcon = 0;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001606 struct irq_desc *desc;
Yinghai Lu3145e942008-12-05 18:58:34 -08001607 struct irq_cfg *cfg;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001608 int cpu = boot_cpu_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001609
1610 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1611
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001612 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1613 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001614
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001615 idx = find_irq_entry(apic_id, pin, mp_INT);
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001616 if (idx == -1) {
Cyrill Gorcunov2a554fb2008-09-08 19:38:06 +04001617 if (!notcon) {
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001618 notcon = 1;
Cyrill Gorcunov2a554fb2008-09-08 19:38:06 +04001619 apic_printk(APIC_VERBOSE,
1620 KERN_DEBUG " %d-%d",
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001621 mp_ioapics[apic_id].apicid, pin);
Cyrill Gorcunov2a554fb2008-09-08 19:38:06 +04001622 } else
1623 apic_printk(APIC_VERBOSE, " %d-%d",
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001624 mp_ioapics[apic_id].apicid, pin);
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001625 continue;
1626 }
Cyrill Gorcunov56ffa1a2008-09-13 13:11:16 +04001627 if (notcon) {
1628 apic_printk(APIC_VERBOSE,
1629 " (apicid-pin) not connected\n");
1630 notcon = 0;
1631 }
Yinghai Lu20d225b2007-10-17 18:04:41 +02001632
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001633 irq = pin_2_irq(idx, apic_id, pin);
Ingo Molnar33a201f2009-01-28 07:17:26 +01001634
1635 /*
1636 * Skip the timer IRQ if there's a quirk handler
1637 * installed and if it returns 1:
1638 */
1639 if (apic->multi_timer_check &&
1640 apic->multi_timer_check(apic_id, irq))
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001641 continue;
Ingo Molnar33a201f2009-01-28 07:17:26 +01001642
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001643 desc = irq_to_desc_alloc_cpu(irq, cpu);
1644 if (!desc) {
1645 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1646 continue;
1647 }
Yinghai Lu3145e942008-12-05 18:58:34 -08001648 cfg = desc->chip_data;
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001649 add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02001650
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001651 setup_IO_APIC_irq(apic_id, pin, irq, desc,
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001652 irq_trigger(idx), irq_polarity(idx));
1653 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001654 }
1655
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001656 if (notcon)
1657 apic_printk(APIC_VERBOSE,
Cyrill Gorcunov2a554fb2008-09-08 19:38:06 +04001658 " (apicid-pin) not connected\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001659}
1660
1661/*
Maciej W. Rozyckif7633ce2008-05-27 21:19:34 +01001662 * Set up the timer pin, possibly with the 8259A-master behind.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001663 */
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001664static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
Maciej W. Rozyckif7633ce2008-05-27 21:19:34 +01001665 int vector)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001666{
1667 struct IO_APIC_route_entry entry;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001668
Ingo Molnar54168ed2008-08-20 09:07:45 +02001669 if (intr_remapping_enabled)
1670 return;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001671
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02001672 memset(&entry, 0, sizeof(entry));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001673
1674 /*
1675 * We use logical delivery to get the timer IRQ
1676 * to the first CPU.
1677 */
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01001678 entry.dest_mode = apic->irq_dest_mode;
Yinghai Luf72dcca2009-02-08 16:18:03 -08001679 entry.mask = 0; /* don't mask IRQ for edge */
Ingo Molnardebccb32009-01-28 15:20:18 +01001680 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01001681 entry.delivery_mode = apic->irq_delivery_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001682 entry.polarity = 0;
1683 entry.trigger = 0;
1684 entry.vector = vector;
1685
1686 /*
1687 * The timer IRQ doesn't have to know that behind the
Maciej W. Rozyckif7633ce2008-05-27 21:19:34 +01001688 * scene we may have a 8259A-master in AEOI mode ...
Linus Torvalds1da177e2005-04-16 15:20:36 -07001689 */
Ingo Molnar54168ed2008-08-20 09:07:45 +02001690 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001691
1692 /*
1693 * Add it to the IO-APIC irq-routing table:
1694 */
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001695 ioapic_write_entry(apic_id, pin, entry);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001696}
1697
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +01001698
1699__apicdebuginit(void) print_IO_APIC(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001700{
1701 int apic, i;
1702 union IO_APIC_reg_00 reg_00;
1703 union IO_APIC_reg_01 reg_01;
1704 union IO_APIC_reg_02 reg_02;
1705 union IO_APIC_reg_03 reg_03;
1706 unsigned long flags;
Yinghai Lu0f978f42008-08-19 20:50:26 -07001707 struct irq_cfg *cfg;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001708 struct irq_desc *desc;
Yinghai Lu8f09cd22008-08-19 20:50:51 -07001709 unsigned int irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001710
1711 if (apic_verbosity == APIC_QUIET)
1712 return;
1713
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02001714 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001715 for (i = 0; i < nr_ioapics; i++)
1716 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
Jaswinder Singh Rajputb5ba7e62009-01-12 17:46:17 +05301717 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001718
1719 /*
1720 * We are a bit conservative about what we expect. We have to
1721 * know about every hardware change ASAP.
1722 */
1723 printk(KERN_INFO "testing the IO APIC.......................\n");
1724
1725 for (apic = 0; apic < nr_ioapics; apic++) {
1726
1727 spin_lock_irqsave(&ioapic_lock, flags);
1728 reg_00.raw = io_apic_read(apic, 0);
1729 reg_01.raw = io_apic_read(apic, 1);
1730 if (reg_01.bits.version >= 0x10)
1731 reg_02.raw = io_apic_read(apic, 2);
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02001732 if (reg_01.bits.version >= 0x20)
1733 reg_03.raw = io_apic_read(apic, 3);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001734 spin_unlock_irqrestore(&ioapic_lock, flags);
1735
Ingo Molnar54168ed2008-08-20 09:07:45 +02001736 printk("\n");
Jaswinder Singh Rajputb5ba7e62009-01-12 17:46:17 +05301737 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001738 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1739 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1740 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1741 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001742
Ingo Molnar54168ed2008-08-20 09:07:45 +02001743 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001744 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001745
1746 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1747 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001748
1749 /*
1750 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1751 * but the value of reg_02 is read as the previous read register
1752 * value, so ignore it if reg_02 == reg_01.
1753 */
1754 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1755 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1756 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001757 }
1758
1759 /*
1760 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1761 * or reg_03, but the value of reg_0[23] is read as the previous read
1762 * register value, so ignore it if reg_03 == reg_0[12].
1763 */
1764 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1765 reg_03.raw != reg_01.raw) {
1766 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1767 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001768 }
1769
1770 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1771
Yinghai Lud83e94a2008-08-19 20:50:33 -07001772 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1773 " Stat Dmod Deli Vect: \n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001774
1775 for (i = 0; i <= reg_01.bits.entries; i++) {
1776 struct IO_APIC_route_entry entry;
1777
Andi Kleencf4c6a22006-09-26 10:52:30 +02001778 entry = ioapic_read_entry(apic, i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001779
Ingo Molnar54168ed2008-08-20 09:07:45 +02001780 printk(KERN_DEBUG " %02x %03X ",
1781 i,
1782 entry.dest
1783 );
Linus Torvalds1da177e2005-04-16 15:20:36 -07001784
1785 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1786 entry.mask,
1787 entry.trigger,
1788 entry.irr,
1789 entry.polarity,
1790 entry.delivery_status,
1791 entry.dest_mode,
1792 entry.delivery_mode,
1793 entry.vector
1794 );
1795 }
1796 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001797 printk(KERN_DEBUG "IRQ to pin mappings:\n");
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001798 for_each_irq_desc(irq, desc) {
1799 struct irq_pin_list *entry;
1800
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001801 cfg = desc->chip_data;
1802 entry = cfg->irq_2_pin;
Yinghai Lu0f978f42008-08-19 20:50:26 -07001803 if (!entry)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001804 continue;
Yinghai Lu8f09cd22008-08-19 20:50:51 -07001805 printk(KERN_DEBUG "IRQ%d ", irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001806 for (;;) {
1807 printk("-> %d:%d", entry->apic, entry->pin);
1808 if (!entry->next)
1809 break;
Yinghai Lu0f978f42008-08-19 20:50:26 -07001810 entry = entry->next;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001811 }
1812 printk("\n");
1813 }
1814
1815 printk(KERN_INFO ".................................... done.\n");
1816
1817 return;
1818}
1819
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +01001820__apicdebuginit(void) print_APIC_bitfield(int base)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001821{
1822 unsigned int v;
1823 int i, j;
1824
1825 if (apic_verbosity == APIC_QUIET)
1826 return;
1827
1828 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1829 for (i = 0; i < 8; i++) {
1830 v = apic_read(base + i*0x10);
1831 for (j = 0; j < 32; j++) {
1832 if (v & (1<<j))
1833 printk("1");
1834 else
1835 printk("0");
1836 }
1837 printk("\n");
1838 }
1839}
1840
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +01001841__apicdebuginit(void) print_local_APIC(void *dummy)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001842{
1843 unsigned int v, ver, maxlvt;
Hiroshi Shimamoto7ab6af72008-07-30 17:36:48 -07001844 u64 icr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001845
1846 if (apic_verbosity == APIC_QUIET)
1847 return;
1848
1849 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1850 smp_processor_id(), hard_smp_processor_id());
Andreas Herrmann66823112008-06-05 16:35:10 +02001851 v = apic_read(APIC_ID);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001852 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
Linus Torvalds1da177e2005-04-16 15:20:36 -07001853 v = apic_read(APIC_LVR);
1854 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1855 ver = GET_APIC_VERSION(v);
Thomas Gleixnere05d7232007-02-16 01:27:58 -08001856 maxlvt = lapic_get_maxlvt();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001857
1858 v = apic_read(APIC_TASKPRI);
1859 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1860
Ingo Molnar54168ed2008-08-20 09:07:45 +02001861 if (APIC_INTEGRATED(ver)) { /* !82489DX */
Yinghai Lua11b5ab2008-09-03 16:58:31 -07001862 if (!APIC_XAPIC(ver)) {
1863 v = apic_read(APIC_ARBPRI);
1864 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1865 v & APIC_ARBPRI_MASK);
1866 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001867 v = apic_read(APIC_PROCPRI);
1868 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1869 }
1870
Yinghai Lua11b5ab2008-09-03 16:58:31 -07001871 /*
1872 * Remote read supported only in the 82489DX and local APIC for
1873 * Pentium processors.
1874 */
1875 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1876 v = apic_read(APIC_RRR);
1877 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1878 }
1879
Linus Torvalds1da177e2005-04-16 15:20:36 -07001880 v = apic_read(APIC_LDR);
1881 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
Yinghai Lua11b5ab2008-09-03 16:58:31 -07001882 if (!x2apic_enabled()) {
1883 v = apic_read(APIC_DFR);
1884 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1885 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001886 v = apic_read(APIC_SPIV);
1887 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1888
1889 printk(KERN_DEBUG "... APIC ISR field:\n");
1890 print_APIC_bitfield(APIC_ISR);
1891 printk(KERN_DEBUG "... APIC TMR field:\n");
1892 print_APIC_bitfield(APIC_TMR);
1893 printk(KERN_DEBUG "... APIC IRR field:\n");
1894 print_APIC_bitfield(APIC_IRR);
1895
Ingo Molnar54168ed2008-08-20 09:07:45 +02001896 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1897 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001898 apic_write(APIC_ESR, 0);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001899
Linus Torvalds1da177e2005-04-16 15:20:36 -07001900 v = apic_read(APIC_ESR);
1901 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1902 }
1903
Hiroshi Shimamoto7ab6af72008-07-30 17:36:48 -07001904 icr = apic_icr_read();
Ingo Molnar0c425ce2008-08-18 13:04:26 +02001905 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1906 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001907
1908 v = apic_read(APIC_LVTT);
1909 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1910
1911 if (maxlvt > 3) { /* PC is LVT#4. */
1912 v = apic_read(APIC_LVTPC);
1913 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1914 }
1915 v = apic_read(APIC_LVT0);
1916 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1917 v = apic_read(APIC_LVT1);
1918 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1919
1920 if (maxlvt > 2) { /* ERR is LVT#3. */
1921 v = apic_read(APIC_LVTERR);
1922 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1923 }
1924
1925 v = apic_read(APIC_TMICT);
1926 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1927 v = apic_read(APIC_TMCCT);
1928 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1929 v = apic_read(APIC_TDCR);
1930 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1931 printk("\n");
1932}
1933
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +01001934__apicdebuginit(void) print_all_local_APICs(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001935{
Yinghai Luffd5aae2008-08-19 20:50:50 -07001936 int cpu;
1937
1938 preempt_disable();
1939 for_each_online_cpu(cpu)
1940 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1941 preempt_enable();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001942}
1943
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +01001944__apicdebuginit(void) print_PIC(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001945{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001946 unsigned int v;
1947 unsigned long flags;
1948
1949 if (apic_verbosity == APIC_QUIET)
1950 return;
1951
1952 printk(KERN_DEBUG "\nprinting PIC contents\n");
1953
1954 spin_lock_irqsave(&i8259A_lock, flags);
1955
1956 v = inb(0xa1) << 8 | inb(0x21);
1957 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1958
1959 v = inb(0xa0) << 8 | inb(0x20);
1960 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1961
Ingo Molnar54168ed2008-08-20 09:07:45 +02001962 outb(0x0b,0xa0);
1963 outb(0x0b,0x20);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001964 v = inb(0xa0) << 8 | inb(0x20);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001965 outb(0x0a,0xa0);
1966 outb(0x0a,0x20);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001967
1968 spin_unlock_irqrestore(&i8259A_lock, flags);
1969
1970 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1971
1972 v = inb(0x4d1) << 8 | inb(0x4d0);
1973 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1974}
1975
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +01001976__apicdebuginit(int) print_all_ICs(void)
1977{
1978 print_PIC();
1979 print_all_local_APICs();
1980 print_IO_APIC();
1981
1982 return 0;
1983}
1984
1985fs_initcall(print_all_ICs);
1986
Linus Torvalds1da177e2005-04-16 15:20:36 -07001987
Yinghai Luefa25592008-08-19 20:50:36 -07001988/* Where if anywhere is the i8259 connect in external int mode */
1989static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1990
Ingo Molnar54168ed2008-08-20 09:07:45 +02001991void __init enable_IO_APIC(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001992{
1993 union IO_APIC_reg_01 reg_01;
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08001994 int i8259_apic, i8259_pin;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001995 int apic;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001996 unsigned long flags;
1997
Linus Torvalds1da177e2005-04-16 15:20:36 -07001998 /*
1999 * The number of IO-APIC IRQ registers (== #pins):
2000 */
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002001 for (apic = 0; apic < nr_ioapics; apic++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002002 spin_lock_irqsave(&ioapic_lock, flags);
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002003 reg_01.raw = io_apic_read(apic, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002004 spin_unlock_irqrestore(&ioapic_lock, flags);
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002005 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
2006 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02002007 for(apic = 0; apic < nr_ioapics; apic++) {
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002008 int pin;
2009 /* See if any of the pins is in ExtINT mode */
Eric W. Biederman1008fdd2006-01-11 22:46:06 +01002010 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002011 struct IO_APIC_route_entry entry;
Andi Kleencf4c6a22006-09-26 10:52:30 +02002012 entry = ioapic_read_entry(apic, pin);
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002013
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002014 /* If the interrupt line is enabled and in ExtInt mode
2015 * I have found the pin where the i8259 is connected.
2016 */
2017 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2018 ioapic_i8259.apic = apic;
2019 ioapic_i8259.pin = pin;
2020 goto found_i8259;
2021 }
2022 }
2023 }
2024 found_i8259:
2025 /* Look to see what if the MP table has reported the ExtINT */
2026 /* If we could not find the appropriate pin by looking at the ioapic
2027 * the i8259 probably is not connected the ioapic but give the
2028 * mptable a chance anyway.
2029 */
2030 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
2031 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2032 /* Trust the MP table if nothing is setup in the hardware */
2033 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2034 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2035 ioapic_i8259.pin = i8259_pin;
2036 ioapic_i8259.apic = i8259_apic;
2037 }
2038 /* Complain if the MP table and the hardware disagree */
2039 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2040 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2041 {
2042 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002043 }
2044
2045 /*
2046 * Do not trust the IO-APIC being empty at bootup
2047 */
2048 clear_IO_APIC();
2049}
2050
2051/*
2052 * Not an __init, needed by the reboot code
2053 */
2054void disable_IO_APIC(void)
2055{
2056 /*
2057 * Clear the IO-APIC before rebooting:
2058 */
2059 clear_IO_APIC();
2060
Eric W. Biederman650927e2005-06-25 14:57:44 -07002061 /*
Karsten Wiese0b968d22005-09-09 12:59:04 +02002062 * If the i8259 is routed through an IOAPIC
Eric W. Biederman650927e2005-06-25 14:57:44 -07002063 * Put that IOAPIC in virtual wire mode
Karsten Wiese0b968d22005-09-09 12:59:04 +02002064 * so legacy interrupts can be delivered.
Suresh Siddha7c6d9f92009-03-16 17:04:59 -07002065 *
2066 * With interrupt-remapping, for now we will use virtual wire A mode,
2067 * as virtual wire B is little complex (need to configure both
2068 * IOAPIC RTE aswell as interrupt-remapping table entry).
2069 * As this gets called during crash dump, keep this simple for now.
Eric W. Biederman650927e2005-06-25 14:57:44 -07002070 */
Suresh Siddha7c6d9f92009-03-16 17:04:59 -07002071 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
Eric W. Biederman650927e2005-06-25 14:57:44 -07002072 struct IO_APIC_route_entry entry;
Eric W. Biederman650927e2005-06-25 14:57:44 -07002073
2074 memset(&entry, 0, sizeof(entry));
2075 entry.mask = 0; /* Enabled */
2076 entry.trigger = 0; /* Edge */
2077 entry.irr = 0;
2078 entry.polarity = 0; /* High */
2079 entry.delivery_status = 0;
2080 entry.dest_mode = 0; /* Physical */
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002081 entry.delivery_mode = dest_ExtINT; /* ExtInt */
Eric W. Biederman650927e2005-06-25 14:57:44 -07002082 entry.vector = 0;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002083 entry.dest = read_apic_id();
Eric W. Biederman650927e2005-06-25 14:57:44 -07002084
2085 /*
2086 * Add it to the IO-APIC irq-routing table:
2087 */
Andi Kleencf4c6a22006-09-26 10:52:30 +02002088 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
Eric W. Biederman650927e2005-06-25 14:57:44 -07002089 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02002090
Suresh Siddha7c6d9f92009-03-16 17:04:59 -07002091 /*
2092 * Use virtual wire A mode when interrupt remapping is enabled.
2093 */
2094 disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002095}
2096
Ingo Molnar54168ed2008-08-20 09:07:45 +02002097#ifdef CONFIG_X86_32
Linus Torvalds1da177e2005-04-16 15:20:36 -07002098/*
2099 * function to set the IO-APIC physical IDs based on the
2100 * values stored in the MPC table.
2101 *
2102 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2103 */
2104
Linus Torvalds1da177e2005-04-16 15:20:36 -07002105static void __init setup_ioapic_ids_from_mpc(void)
2106{
2107 union IO_APIC_reg_00 reg_00;
2108 physid_mask_t phys_id_present_map;
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002109 int apic_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002110 int i;
2111 unsigned char old_id;
2112 unsigned long flags;
2113
Yinghai Lua4dbc342008-07-25 02:14:28 -07002114 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
Yinghai Lud49c4282008-06-08 18:31:54 -07002115 return;
Yinghai Lud49c4282008-06-08 18:31:54 -07002116
Linus Torvalds1da177e2005-04-16 15:20:36 -07002117 /*
Natalie Protasevichca05fea2005-06-23 00:08:22 -07002118 * Don't check I/O APIC IDs for xAPIC systems. They have
2119 * no meaning without the serial APIC bus.
2120 */
Shaohua Li7c5c1e42006-03-23 02:59:53 -08002121 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2122 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
Natalie Protasevichca05fea2005-06-23 00:08:22 -07002123 return;
2124 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002125 * This is broken; anything with a real cpu count has to
2126 * circumvent this idiocy regardless.
2127 */
Ingo Molnard190cb82009-01-28 06:50:47 +01002128 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002129
2130 /*
2131 * Set the IOAPIC ID to the value stored in the MPC table.
2132 */
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002133 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002134
2135 /* Read the register 0 value */
2136 spin_lock_irqsave(&ioapic_lock, flags);
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002137 reg_00.raw = io_apic_read(apic_id, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002138 spin_unlock_irqrestore(&ioapic_lock, flags);
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02002139
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002140 old_id = mp_ioapics[apic_id].apicid;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002141
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002142 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002143 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002144 apic_id, mp_ioapics[apic_id].apicid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002145 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2146 reg_00.bits.ID);
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002147 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002148 }
2149
Linus Torvalds1da177e2005-04-16 15:20:36 -07002150 /*
2151 * Sanity check, is the ID really free? Every APIC in a
2152 * system must have a unique ID or we get lots of nice
2153 * 'stuck on smp_invalidate_needed IPI wait' messages.
2154 */
Ingo Molnard1d7cae2009-01-28 05:41:42 +01002155 if (apic->check_apicid_used(phys_id_present_map,
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002156 mp_ioapics[apic_id].apicid)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002157 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002158 apic_id, mp_ioapics[apic_id].apicid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002159 for (i = 0; i < get_physical_broadcast(); i++)
2160 if (!physid_isset(i, phys_id_present_map))
2161 break;
2162 if (i >= get_physical_broadcast())
2163 panic("Max APIC ID exceeded!\n");
2164 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2165 i);
2166 physid_set(i, phys_id_present_map);
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002167 mp_ioapics[apic_id].apicid = i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002168 } else {
2169 physid_mask_t tmp;
Ingo Molnar80587142009-01-28 06:50:47 +01002170 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002171 apic_printk(APIC_VERBOSE, "Setting %d in the "
2172 "phys_id_present_map\n",
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002173 mp_ioapics[apic_id].apicid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002174 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2175 }
2176
2177
2178 /*
2179 * We need to adjust the IRQ routing table
2180 * if the ID changed.
2181 */
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002182 if (old_id != mp_ioapics[apic_id].apicid)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002183 for (i = 0; i < mp_irq_entries; i++)
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05302184 if (mp_irqs[i].dstapic == old_id)
2185 mp_irqs[i].dstapic
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002186 = mp_ioapics[apic_id].apicid;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002187
2188 /*
2189 * Read the right value from the MPC table and
2190 * write it into the ID register.
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02002191 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002192 apic_printk(APIC_VERBOSE, KERN_INFO
2193 "...changing IO-APIC physical APIC ID to %d ...",
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002194 mp_ioapics[apic_id].apicid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002195
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002196 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002197 spin_lock_irqsave(&ioapic_lock, flags);
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002198 io_apic_write(apic_id, 0, reg_00.raw);
Yinghai Lua2d332f2008-08-21 12:56:32 -07002199 spin_unlock_irqrestore(&ioapic_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002200
2201 /*
2202 * Sanity check
2203 */
2204 spin_lock_irqsave(&ioapic_lock, flags);
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002205 reg_00.raw = io_apic_read(apic_id, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002206 spin_unlock_irqrestore(&ioapic_lock, flags);
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002207 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002208 printk("could not set ID!\n");
2209 else
2210 apic_printk(APIC_VERBOSE, " ok.\n");
2211 }
2212}
Ingo Molnar54168ed2008-08-20 09:07:45 +02002213#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002214
Zachary Amsden7ce0bcf2007-02-13 13:26:21 +01002215int no_timer_check __initdata;
Zachary Amsden8542b202006-12-07 02:14:09 +01002216
2217static int __init notimercheck(char *s)
2218{
2219 no_timer_check = 1;
2220 return 1;
2221}
2222__setup("no_timer_check", notimercheck);
2223
Linus Torvalds1da177e2005-04-16 15:20:36 -07002224/*
2225 * There is a nasty bug in some older SMP boards, their mptable lies
2226 * about the timer IRQ. We do the following to work around the situation:
2227 *
2228 * - timer IRQ defaults to IO-APIC IRQ
2229 * - if this function detects that timer IRQs are defunct, then we fall
2230 * back to ISA timer IRQs
2231 */
Adrian Bunkf0a7a5c2007-07-21 17:10:29 +02002232static int __init timer_irq_works(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002233{
2234 unsigned long t1 = jiffies;
Ingo Molnar4aae0702007-12-18 18:05:58 +01002235 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002236
Zachary Amsden8542b202006-12-07 02:14:09 +01002237 if (no_timer_check)
2238 return 1;
2239
Ingo Molnar4aae0702007-12-18 18:05:58 +01002240 local_save_flags(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002241 local_irq_enable();
2242 /* Let ten ticks pass... */
2243 mdelay((10 * 1000) / HZ);
Ingo Molnar4aae0702007-12-18 18:05:58 +01002244 local_irq_restore(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002245
2246 /*
2247 * Expect a few ticks at least, to be sure some possible
2248 * glue logic does not lock up after one or two first
2249 * ticks in a non-ExtINT mode. Also the local APIC
2250 * might have cached one ExtINT interrupt. Finally, at
2251 * least one tick may be lost due to delays.
2252 */
Ingo Molnar54168ed2008-08-20 09:07:45 +02002253
2254 /* jiffies wrap? */
Julia Lawall1d16b532008-01-30 13:32:19 +01002255 if (time_after(jiffies, t1 + 4))
Linus Torvalds1da177e2005-04-16 15:20:36 -07002256 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002257 return 0;
2258}
2259
2260/*
2261 * In the SMP+IOAPIC case it might happen that there are an unspecified
2262 * number of pending IRQ events unhandled. These cases are very rare,
2263 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2264 * better to do it this way as thus we do not have to be aware of
2265 * 'pending' interrupts in the IRQ path, except at this point.
2266 */
2267/*
2268 * Edge triggered needs to resend any interrupt
2269 * that was delayed but this is now handled in the device
2270 * independent code.
2271 */
2272
2273/*
2274 * Starting up a edge-triggered IO-APIC interrupt is
2275 * nasty - we need to make sure that we get the edge.
2276 * If it is already asserted for some reason, we need
2277 * return 1 to indicate that is was pending.
2278 *
2279 * This is not complete - we should be able to fake
2280 * an edge even if it isn't on the 8259A...
2281 */
Ingo Molnar54168ed2008-08-20 09:07:45 +02002282
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07002283static unsigned int startup_ioapic_irq(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002284{
2285 int was_pending = 0;
2286 unsigned long flags;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08002287 struct irq_cfg *cfg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002288
2289 spin_lock_irqsave(&ioapic_lock, flags);
Yinghai Lu99d093d2008-12-05 18:58:32 -08002290 if (irq < NR_IRQS_LEGACY) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002291 disable_8259A_irq(irq);
2292 if (i8259A_irq_pending(irq))
2293 was_pending = 1;
2294 }
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08002295 cfg = irq_cfg(irq);
Yinghai Lu3145e942008-12-05 18:58:34 -08002296 __unmask_IO_APIC_irq(cfg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002297 spin_unlock_irqrestore(&ioapic_lock, flags);
2298
2299 return was_pending;
2300}
2301
Ingo Molnar54168ed2008-08-20 09:07:45 +02002302#ifdef CONFIG_X86_64
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07002303static int ioapic_retrigger_irq(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002304{
Ingo Molnar54168ed2008-08-20 09:07:45 +02002305
2306 struct irq_cfg *cfg = irq_cfg(irq);
2307 unsigned long flags;
2308
2309 spin_lock_irqsave(&vector_lock, flags);
Ingo Molnardac5f412009-01-28 15:42:24 +01002310 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002311 spin_unlock_irqrestore(&vector_lock, flags);
Ingo Molnarc0ad90a2006-06-29 02:24:44 -07002312
2313 return 1;
2314}
Ingo Molnar54168ed2008-08-20 09:07:45 +02002315#else
2316static int ioapic_retrigger_irq(unsigned int irq)
2317{
Ingo Molnardac5f412009-01-28 15:42:24 +01002318 apic->send_IPI_self(irq_cfg(irq)->vector);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002319
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002320 return 1;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002321}
2322#endif
2323
2324/*
2325 * Level and edge triggered IO-APIC interrupts need different handling,
2326 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2327 * handled with the level-triggered descriptor, but that one has slightly
2328 * more overhead. Level-triggered interrupts cannot be handled with the
2329 * edge-triggered handler, without risking IRQ storms and other ugly
2330 * races.
2331 */
Ingo Molnarc0ad90a2006-06-29 02:24:44 -07002332
Yinghai Lu497c9a12008-08-19 20:50:28 -07002333#ifdef CONFIG_SMP
Ingo Molnar54168ed2008-08-20 09:07:45 +02002334
2335#ifdef CONFIG_INTR_REMAP
Ingo Molnar54168ed2008-08-20 09:07:45 +02002336
2337/*
2338 * Migrate the IO-APIC irq in the presence of intr-remapping.
2339 *
Suresh Siddha0280f7c2009-03-16 17:05:01 -07002340 * For both level and edge triggered, irq migration is a simple atomic
2341 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
Ingo Molnar54168ed2008-08-20 09:07:45 +02002342 *
Suresh Siddha0280f7c2009-03-16 17:05:01 -07002343 * For level triggered, we eliminate the io-apic RTE modification (with the
2344 * updated vector information), by using a virtual vector (io-apic pin number).
2345 * Real vector that is used for interrupting cpu will be coming from
2346 * the interrupt-remapping table entry.
Ingo Molnar54168ed2008-08-20 09:07:45 +02002347 */
Mike Travise7986732008-12-16 17:33:52 -08002348static void
2349migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02002350{
2351 struct irq_cfg *cfg;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002352 struct irte irte;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002353 unsigned int dest;
Yinghai Lu3145e942008-12-05 18:58:34 -08002354 unsigned int irq;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002355
Mike Travis22f65d32008-12-16 17:33:56 -08002356 if (!cpumask_intersects(mask, cpu_online_mask))
Ingo Molnar54168ed2008-08-20 09:07:45 +02002357 return;
2358
Yinghai Lu3145e942008-12-05 18:58:34 -08002359 irq = desc->irq;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002360 if (get_irte(irq, &irte))
2361 return;
2362
Yinghai Lu3145e942008-12-05 18:58:34 -08002363 cfg = desc->chip_data;
2364 if (assign_irq_vector(irq, cfg, mask))
Ingo Molnar54168ed2008-08-20 09:07:45 +02002365 return;
2366
Yinghai Lu3145e942008-12-05 18:58:34 -08002367 set_extra_move_desc(desc, mask);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002368
Ingo Molnardebccb32009-01-28 15:20:18 +01002369 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002370
Ingo Molnar54168ed2008-08-20 09:07:45 +02002371 irte.vector = cfg->vector;
2372 irte.dest_id = IRTE_DEST(dest);
2373
2374 /*
2375 * Modified the IRTE and flushes the Interrupt entry cache.
2376 */
2377 modify_irte(irq, &irte);
2378
Mike Travis22f65d32008-12-16 17:33:56 -08002379 if (cfg->move_in_progress)
2380 send_cleanup_vector(cfg);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002381
Mike Travis7f7ace02009-01-10 21:58:08 -08002382 cpumask_copy(desc->affinity, mask);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002383}
2384
Ingo Molnar54168ed2008-08-20 09:07:45 +02002385/*
2386 * Migrates the IRQ destination in the process context.
2387 */
Rusty Russell968ea6d2008-12-13 21:55:51 +10302388static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2389 const struct cpumask *mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02002390{
Yinghai Lu3145e942008-12-05 18:58:34 -08002391 migrate_ioapic_irq_desc(desc, mask);
2392}
Rusty Russell0de26522008-12-13 21:20:26 +10302393static void set_ir_ioapic_affinity_irq(unsigned int irq,
2394 const struct cpumask *mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02002395{
2396 struct irq_desc *desc = irq_to_desc(irq);
2397
Yinghai Lu3145e942008-12-05 18:58:34 -08002398 set_ir_ioapic_affinity_irq_desc(desc, mask);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002399}
Suresh Siddha29b61be2009-03-16 17:05:02 -07002400#else
2401static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2402 const struct cpumask *mask)
2403{
2404}
Ingo Molnar54168ed2008-08-20 09:07:45 +02002405#endif
2406
Yinghai Lu497c9a12008-08-19 20:50:28 -07002407asmlinkage void smp_irq_move_cleanup_interrupt(void)
2408{
2409 unsigned vector, me;
Hiroshi Shimamoto8f2466f2008-12-08 19:19:07 -08002410
Yinghai Lu497c9a12008-08-19 20:50:28 -07002411 ack_APIC_irq();
Ingo Molnar54168ed2008-08-20 09:07:45 +02002412 exit_idle();
Yinghai Lu497c9a12008-08-19 20:50:28 -07002413 irq_enter();
2414
2415 me = smp_processor_id();
2416 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2417 unsigned int irq;
Suresh Siddha68a8ca52009-03-16 17:05:04 -07002418 unsigned int irr;
Yinghai Lu497c9a12008-08-19 20:50:28 -07002419 struct irq_desc *desc;
2420 struct irq_cfg *cfg;
2421 irq = __get_cpu_var(vector_irq)[vector];
2422
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08002423 if (irq == -1)
2424 continue;
2425
Yinghai Lu497c9a12008-08-19 20:50:28 -07002426 desc = irq_to_desc(irq);
2427 if (!desc)
2428 continue;
2429
2430 cfg = irq_cfg(irq);
2431 spin_lock(&desc->lock);
2432 if (!cfg->move_cleanup_count)
2433 goto unlock;
2434
Mike Travis22f65d32008-12-16 17:33:56 -08002435 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
Yinghai Lu497c9a12008-08-19 20:50:28 -07002436 goto unlock;
2437
Suresh Siddha68a8ca52009-03-16 17:05:04 -07002438 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2439 /*
2440 * Check if the vector that needs to be cleanedup is
2441 * registered at the cpu's IRR. If so, then this is not
2442 * the best time to clean it up. Lets clean it up in the
2443 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2444 * to myself.
2445 */
2446 if (irr & (1 << (vector % 32))) {
2447 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2448 goto unlock;
2449 }
Yinghai Lu497c9a12008-08-19 20:50:28 -07002450 __get_cpu_var(vector_irq)[vector] = -1;
2451 cfg->move_cleanup_count--;
2452unlock:
2453 spin_unlock(&desc->lock);
2454 }
2455
2456 irq_exit();
2457}
2458
Yinghai Lu3145e942008-12-05 18:58:34 -08002459static void irq_complete_move(struct irq_desc **descp)
Yinghai Lu497c9a12008-08-19 20:50:28 -07002460{
Yinghai Lu3145e942008-12-05 18:58:34 -08002461 struct irq_desc *desc = *descp;
2462 struct irq_cfg *cfg = desc->chip_data;
Yinghai Lu497c9a12008-08-19 20:50:28 -07002463 unsigned vector, me;
2464
Yinghai Lu48a1b102008-12-11 00:15:01 -08002465 if (likely(!cfg->move_in_progress)) {
2466#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2467 if (likely(!cfg->move_desc_pending))
2468 return;
2469
Yinghai Lub9098952008-12-19 13:48:34 -08002470 /* domain has not changed, but affinity did */
Yinghai Lu48a1b102008-12-11 00:15:01 -08002471 me = smp_processor_id();
Mike Travis7f7ace02009-01-10 21:58:08 -08002472 if (cpumask_test_cpu(me, desc->affinity)) {
Yinghai Lu48a1b102008-12-11 00:15:01 -08002473 *descp = desc = move_irq_desc(desc, me);
2474 /* get the new one */
2475 cfg = desc->chip_data;
2476 cfg->move_desc_pending = 0;
2477 }
2478#endif
Yinghai Lu497c9a12008-08-19 20:50:28 -07002479 return;
Yinghai Lu48a1b102008-12-11 00:15:01 -08002480 }
Yinghai Lu497c9a12008-08-19 20:50:28 -07002481
2482 vector = ~get_irq_regs()->orig_ax;
2483 me = smp_processor_id();
Yinghai Lu10b888d2009-01-31 14:50:07 -08002484
2485 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) {
Yinghai Lu48a1b102008-12-11 00:15:01 -08002486#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2487 *descp = desc = move_irq_desc(desc, me);
2488 /* get the new one */
2489 cfg = desc->chip_data;
2490#endif
Mike Travis22f65d32008-12-16 17:33:56 -08002491 send_cleanup_vector(cfg);
Yinghai Lu10b888d2009-01-31 14:50:07 -08002492 }
Yinghai Lu497c9a12008-08-19 20:50:28 -07002493}
2494#else
Yinghai Lu3145e942008-12-05 18:58:34 -08002495static inline void irq_complete_move(struct irq_desc **descp) {}
Yinghai Lu497c9a12008-08-19 20:50:28 -07002496#endif
Yinghai Lu3145e942008-12-05 18:58:34 -08002497
Ingo Molnar54168ed2008-08-20 09:07:45 +02002498#ifdef CONFIG_INTR_REMAP
Suresh Siddha0280f7c2009-03-16 17:05:01 -07002499static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2500{
2501 int apic, pin;
2502 struct irq_pin_list *entry;
2503
2504 entry = cfg->irq_2_pin;
2505 for (;;) {
2506
2507 if (!entry)
2508 break;
2509
2510 apic = entry->apic;
2511 pin = entry->pin;
2512 io_apic_eoi(apic, pin);
2513 entry = entry->next;
2514 }
2515}
2516
2517static void
2518eoi_ioapic_irq(struct irq_desc *desc)
2519{
2520 struct irq_cfg *cfg;
2521 unsigned long flags;
2522 unsigned int irq;
2523
2524 irq = desc->irq;
2525 cfg = desc->chip_data;
2526
2527 spin_lock_irqsave(&ioapic_lock, flags);
2528 __eoi_ioapic_irq(irq, cfg);
2529 spin_unlock_irqrestore(&ioapic_lock, flags);
2530}
2531
Ingo Molnar54168ed2008-08-20 09:07:45 +02002532static void ack_x2apic_level(unsigned int irq)
2533{
Suresh Siddha0280f7c2009-03-16 17:05:01 -07002534 struct irq_desc *desc = irq_to_desc(irq);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002535 ack_x2APIC_irq();
Suresh Siddha0280f7c2009-03-16 17:05:01 -07002536 eoi_ioapic_irq(desc);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002537}
2538
2539static void ack_x2apic_edge(unsigned int irq)
2540{
2541 ack_x2APIC_irq();
2542}
Yinghai Lu3145e942008-12-05 18:58:34 -08002543
Ingo Molnar54168ed2008-08-20 09:07:45 +02002544#endif
Yinghai Lu497c9a12008-08-19 20:50:28 -07002545
Yinghai Lu1d025192008-08-19 20:50:34 -07002546static void ack_apic_edge(unsigned int irq)
2547{
Yinghai Lu3145e942008-12-05 18:58:34 -08002548 struct irq_desc *desc = irq_to_desc(irq);
2549
2550 irq_complete_move(&desc);
Yinghai Lu1d025192008-08-19 20:50:34 -07002551 move_native_irq(irq);
2552 ack_APIC_irq();
2553}
2554
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002555atomic_t irq_mis_count;
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002556
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002557static void ack_apic_level(unsigned int irq)
2558{
Yinghai Lu3145e942008-12-05 18:58:34 -08002559 struct irq_desc *desc = irq_to_desc(irq);
2560
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002561#ifdef CONFIG_X86_32
2562 unsigned long v;
2563 int i;
2564#endif
Yinghai Lu3145e942008-12-05 18:58:34 -08002565 struct irq_cfg *cfg;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002566 int do_unmask_irq = 0;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002567
Yinghai Lu3145e942008-12-05 18:58:34 -08002568 irq_complete_move(&desc);
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002569#ifdef CONFIG_GENERIC_PENDING_IRQ
Ingo Molnar54168ed2008-08-20 09:07:45 +02002570 /* If we are moving the irq we need to mask it */
Yinghai Lu3145e942008-12-05 18:58:34 -08002571 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
Ingo Molnar54168ed2008-08-20 09:07:45 +02002572 do_unmask_irq = 1;
Yinghai Lu3145e942008-12-05 18:58:34 -08002573 mask_IO_APIC_irq_desc(desc);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002574 }
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002575#endif
2576
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002577#ifdef CONFIG_X86_32
2578 /*
2579 * It appears there is an erratum which affects at least version 0x11
2580 * of I/O APIC (that's the 82093AA and cores integrated into various
2581 * chipsets). Under certain conditions a level-triggered interrupt is
2582 * erroneously delivered as edge-triggered one but the respective IRR
2583 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2584 * message but it will never arrive and further interrupts are blocked
2585 * from the source. The exact reason is so far unknown, but the
2586 * phenomenon was observed when two consecutive interrupt requests
2587 * from a given source get delivered to the same CPU and the source is
2588 * temporarily disabled in between.
2589 *
2590 * A workaround is to simulate an EOI message manually. We achieve it
2591 * by setting the trigger mode to edge and then to level when the edge
2592 * trigger mode gets detected in the TMR of a local APIC for a
2593 * level-triggered interrupt. We mask the source for the time of the
2594 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2595 * The idea is from Manfred Spraul. --macro
2596 */
Yinghai Lu3145e942008-12-05 18:58:34 -08002597 cfg = desc->chip_data;
2598 i = cfg->vector;
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002599
2600 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2601#endif
2602
Ingo Molnar54168ed2008-08-20 09:07:45 +02002603 /*
2604 * We must acknowledge the irq before we move it or the acknowledge will
2605 * not propagate properly.
2606 */
2607 ack_APIC_irq();
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002608
Ingo Molnar54168ed2008-08-20 09:07:45 +02002609 /* Now we can move and renable the irq */
2610 if (unlikely(do_unmask_irq)) {
2611 /* Only migrate the irq if the ack has been received.
2612 *
2613 * On rare occasions the broadcast level triggered ack gets
2614 * delayed going to ioapics, and if we reprogram the
2615 * vector while Remote IRR is still set the irq will never
2616 * fire again.
2617 *
2618 * To prevent this scenario we read the Remote IRR bit
2619 * of the ioapic. This has two effects.
2620 * - On any sane system the read of the ioapic will
2621 * flush writes (and acks) going to the ioapic from
2622 * this cpu.
2623 * - We get to see if the ACK has actually been delivered.
2624 *
2625 * Based on failed experiments of reprogramming the
2626 * ioapic entry from outside of irq context starting
2627 * with masking the ioapic entry and then polling until
2628 * Remote IRR was clear before reprogramming the
2629 * ioapic I don't trust the Remote IRR bit to be
2630 * completey accurate.
2631 *
2632 * However there appears to be no other way to plug
2633 * this race, so if the Remote IRR bit is not
2634 * accurate and is causing problems then it is a hardware bug
2635 * and you can go talk to the chipset vendor about it.
2636 */
Yinghai Lu3145e942008-12-05 18:58:34 -08002637 cfg = desc->chip_data;
2638 if (!io_apic_level_ack_pending(cfg))
Ingo Molnar54168ed2008-08-20 09:07:45 +02002639 move_masked_irq(irq);
Yinghai Lu3145e942008-12-05 18:58:34 -08002640 unmask_IO_APIC_irq_desc(desc);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002641 }
Yinghai Lu1d025192008-08-19 20:50:34 -07002642
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002643#ifdef CONFIG_X86_32
Yinghai Lu1d025192008-08-19 20:50:34 -07002644 if (!(v & (1 << (i & 0x1f)))) {
2645 atomic_inc(&irq_mis_count);
2646 spin_lock(&ioapic_lock);
Yinghai Lu3145e942008-12-05 18:58:34 -08002647 __mask_and_edge_IO_APIC_irq(cfg);
2648 __unmask_and_level_IO_APIC_irq(cfg);
Yinghai Lu1d025192008-08-19 20:50:34 -07002649 spin_unlock(&ioapic_lock);
2650 }
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002651#endif
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002652}
Yinghai Lu1d025192008-08-19 20:50:34 -07002653
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07002654static struct irq_chip ioapic_chip __read_mostly = {
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002655 .name = "IO-APIC",
2656 .startup = startup_ioapic_irq,
2657 .mask = mask_IO_APIC_irq,
2658 .unmask = unmask_IO_APIC_irq,
2659 .ack = ack_apic_edge,
2660 .eoi = ack_apic_level,
Ashok Raj54d5d422005-09-06 15:16:15 -07002661#ifdef CONFIG_SMP
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002662 .set_affinity = set_ioapic_affinity_irq,
Ashok Raj54d5d422005-09-06 15:16:15 -07002663#endif
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07002664 .retrigger = ioapic_retrigger_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002665};
2666
Ingo Molnar54168ed2008-08-20 09:07:45 +02002667static struct irq_chip ir_ioapic_chip __read_mostly = {
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002668 .name = "IR-IO-APIC",
2669 .startup = startup_ioapic_irq,
2670 .mask = mask_IO_APIC_irq,
2671 .unmask = unmask_IO_APIC_irq,
Jaswinder Singh Rajputa1e38ca2009-03-23 02:11:25 +05302672#ifdef CONFIG_INTR_REMAP
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002673 .ack = ack_x2apic_edge,
2674 .eoi = ack_x2apic_level,
Ingo Molnar54168ed2008-08-20 09:07:45 +02002675#ifdef CONFIG_SMP
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002676 .set_affinity = set_ir_ioapic_affinity_irq,
Ingo Molnar54168ed2008-08-20 09:07:45 +02002677#endif
Jaswinder Singh Rajputa1e38ca2009-03-23 02:11:25 +05302678#endif
Ingo Molnar54168ed2008-08-20 09:07:45 +02002679 .retrigger = ioapic_retrigger_irq,
2680};
Linus Torvalds1da177e2005-04-16 15:20:36 -07002681
2682static inline void init_IO_APIC_traps(void)
2683{
2684 int irq;
Yinghai Lu08678b02008-08-19 20:50:05 -07002685 struct irq_desc *desc;
Yinghai Luda51a822008-08-19 20:50:25 -07002686 struct irq_cfg *cfg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002687
2688 /*
2689 * NOTE! The local APIC isn't very good at handling
2690 * multiple interrupts at the same interrupt level.
2691 * As the interrupt level is determined by taking the
2692 * vector number and shifting that right by 4, we
2693 * want to spread these out a bit so that they don't
2694 * all fall in the same interrupt level.
2695 *
2696 * Also, we've got to be careful not to trash gate
2697 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2698 */
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08002699 for_each_irq_desc(irq, desc) {
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08002700 cfg = desc->chip_data;
2701 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002702 /*
2703 * Hmm.. We don't have an entry for this,
2704 * so default to an old-fashioned 8259
2705 * interrupt if we can..
2706 */
Yinghai Lu99d093d2008-12-05 18:58:32 -08002707 if (irq < NR_IRQS_LEGACY)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002708 make_8259A_irq(irq);
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08002709 else
Linus Torvalds1da177e2005-04-16 15:20:36 -07002710 /* Strange. Oh, well.. */
Yinghai Lu08678b02008-08-19 20:50:05 -07002711 desc->chip = &no_irq_chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002712 }
2713 }
2714}
2715
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07002716/*
2717 * The local APIC irq-chip implementation:
2718 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002719
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02002720static void mask_lapic_irq(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002721{
2722 unsigned long v;
2723
2724 v = apic_read(APIC_LVT0);
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +01002725 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002726}
2727
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02002728static void unmask_lapic_irq(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002729{
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07002730 unsigned long v;
2731
2732 v = apic_read(APIC_LVT0);
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +01002733 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002734}
2735
Yinghai Lu3145e942008-12-05 18:58:34 -08002736static void ack_lapic_irq(unsigned int irq)
Yinghai Lu1d025192008-08-19 20:50:34 -07002737{
2738 ack_APIC_irq();
2739}
2740
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07002741static struct irq_chip lapic_chip __read_mostly = {
Maciej W. Rozycki9a1c6192008-05-27 21:19:09 +01002742 .name = "local-APIC",
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07002743 .mask = mask_lapic_irq,
2744 .unmask = unmask_lapic_irq,
Maciej W. Rozyckic88ac1d2008-07-11 19:35:17 +01002745 .ack = ack_lapic_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002746};
2747
Yinghai Lu3145e942008-12-05 18:58:34 -08002748static void lapic_register_intr(int irq, struct irq_desc *desc)
Maciej W. Rozyckic88ac1d2008-07-11 19:35:17 +01002749{
Yinghai Lu08678b02008-08-19 20:50:05 -07002750 desc->status &= ~IRQ_LEVEL;
Maciej W. Rozyckic88ac1d2008-07-11 19:35:17 +01002751 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2752 "edge");
Maciej W. Rozyckic88ac1d2008-07-11 19:35:17 +01002753}
2754
Jan Beuliche9427102008-01-30 13:31:24 +01002755static void __init setup_nmi(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002756{
2757 /*
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02002758 * Dirty trick to enable the NMI watchdog ...
Linus Torvalds1da177e2005-04-16 15:20:36 -07002759 * We put the 8259A master into AEOI mode and
2760 * unmask on all local APICs LVT0 as NMI.
2761 *
2762 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2763 * is from Maciej W. Rozycki - so we do not have to EOI from
2764 * the NMI handler or the timer interrupt.
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02002765 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002766 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2767
Jan Beuliche9427102008-01-30 13:31:24 +01002768 enable_NMI_through_LVT0();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002769
2770 apic_printk(APIC_VERBOSE, " done.\n");
2771}
2772
2773/*
2774 * This looks a bit hackish but it's about the only one way of sending
2775 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2776 * not support the ExtINT mode, unfortunately. We need to send these
2777 * cycles as some i82489DX-based boards have glue logic that keeps the
2778 * 8259A interrupt line asserted until INTA. --macro
2779 */
Jacek Luczak28acf282008-04-12 17:41:12 +02002780static inline void __init unlock_ExtINT_logic(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002781{
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002782 int apic, pin, i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002783 struct IO_APIC_route_entry entry0, entry1;
2784 unsigned char save_control, save_freq_select;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002785
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002786 pin = find_isa_irq_pin(8, mp_INT);
Adrian Bunk956fb532006-12-07 02:14:11 +01002787 if (pin == -1) {
2788 WARN_ON_ONCE(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002789 return;
Adrian Bunk956fb532006-12-07 02:14:11 +01002790 }
2791 apic = find_isa_irq_apic(8, mp_INT);
2792 if (apic == -1) {
2793 WARN_ON_ONCE(1);
2794 return;
2795 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002796
Andi Kleencf4c6a22006-09-26 10:52:30 +02002797 entry0 = ioapic_read_entry(apic, pin);
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002798 clear_IO_APIC_pin(apic, pin);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002799
2800 memset(&entry1, 0, sizeof(entry1));
2801
2802 entry1.dest_mode = 0; /* physical delivery */
2803 entry1.mask = 0; /* unmask IRQ now */
Yinghai Lud83e94a2008-08-19 20:50:33 -07002804 entry1.dest = hard_smp_processor_id();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002805 entry1.delivery_mode = dest_ExtINT;
2806 entry1.polarity = entry0.polarity;
2807 entry1.trigger = 0;
2808 entry1.vector = 0;
2809
Andi Kleencf4c6a22006-09-26 10:52:30 +02002810 ioapic_write_entry(apic, pin, entry1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002811
2812 save_control = CMOS_READ(RTC_CONTROL);
2813 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2814 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2815 RTC_FREQ_SELECT);
2816 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2817
2818 i = 100;
2819 while (i-- > 0) {
2820 mdelay(10);
2821 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2822 i -= 10;
2823 }
2824
2825 CMOS_WRITE(save_control, RTC_CONTROL);
2826 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002827 clear_IO_APIC_pin(apic, pin);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002828
Andi Kleencf4c6a22006-09-26 10:52:30 +02002829 ioapic_write_entry(apic, pin, entry0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002830}
2831
Yinghai Luefa25592008-08-19 20:50:36 -07002832static int disable_timer_pin_1 __initdata;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002833/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
Ingo Molnar54168ed2008-08-20 09:07:45 +02002834static int __init disable_timer_pin_setup(char *arg)
Yinghai Luefa25592008-08-19 20:50:36 -07002835{
2836 disable_timer_pin_1 = 1;
2837 return 0;
2838}
Ingo Molnar54168ed2008-08-20 09:07:45 +02002839early_param("disable_timer_pin_1", disable_timer_pin_setup);
Yinghai Luefa25592008-08-19 20:50:36 -07002840
2841int timer_through_8259 __initdata;
2842
Linus Torvalds1da177e2005-04-16 15:20:36 -07002843/*
2844 * This code may look a bit paranoid, but it's supposed to cooperate with
2845 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2846 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2847 * fanatically on his truly buggy board.
Ingo Molnar54168ed2008-08-20 09:07:45 +02002848 *
2849 * FIXME: really need to revamp this for all platforms.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002850 */
Zachary Amsden8542b202006-12-07 02:14:09 +01002851static inline void __init check_timer(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002852{
Yinghai Lu3145e942008-12-05 18:58:34 -08002853 struct irq_desc *desc = irq_to_desc(0);
2854 struct irq_cfg *cfg = desc->chip_data;
2855 int cpu = boot_cpu_id;
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002856 int apic1, pin1, apic2, pin2;
Ingo Molnar4aae0702007-12-18 18:05:58 +01002857 unsigned long flags;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002858 int no_pin1 = 0;
Ingo Molnar4aae0702007-12-18 18:05:58 +01002859
2860 local_irq_save(flags);
Maciej W. Rozyckid4d25de2007-11-26 20:42:19 +01002861
Linus Torvalds1da177e2005-04-16 15:20:36 -07002862 /*
2863 * get/set the timer IRQ vector:
2864 */
2865 disable_8259A_irq(0);
Ingo Molnarfe402e12009-01-28 04:32:51 +01002866 assign_irq_vector(0, cfg, apic->target_cpus());
Linus Torvalds1da177e2005-04-16 15:20:36 -07002867
2868 /*
Maciej W. Rozyckid11d5792008-05-21 22:09:11 +01002869 * As IRQ0 is to be enabled in the 8259A, the virtual
2870 * wire has to be disabled in the local APIC. Also
2871 * timer interrupts need to be acknowledged manually in
2872 * the 8259A for the i82489DX when using the NMI
2873 * watchdog as that APIC treats NMIs as level-triggered.
2874 * The AEOI mode will finish them in the 8259A
2875 * automatically.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002876 */
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +01002877 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002878 init_8259A(1);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002879#ifdef CONFIG_X86_32
Yinghai Luf72dcca2009-02-08 16:18:03 -08002880 {
2881 unsigned int ver;
2882
2883 ver = apic_read(APIC_LVR);
2884 ver = GET_APIC_VERSION(ver);
2885 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2886 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02002887#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002888
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002889 pin1 = find_isa_irq_pin(0, mp_INT);
2890 apic1 = find_isa_irq_apic(0, mp_INT);
2891 pin2 = ioapic_i8259.pin;
2892 apic2 = ioapic_i8259.apic;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002893
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01002894 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2895 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
Yinghai Lu497c9a12008-08-19 20:50:28 -07002896 cfg->vector, apic1, pin1, apic2, pin2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002897
Maciej W. Rozycki691874f2008-05-27 21:19:51 +01002898 /*
2899 * Some BIOS writers are clueless and report the ExtINTA
2900 * I/O APIC input from the cascaded 8259A as the timer
2901 * interrupt input. So just in case, if only one pin
2902 * was found above, try it both directly and through the
2903 * 8259A.
2904 */
2905 if (pin1 == -1) {
Ingo Molnar54168ed2008-08-20 09:07:45 +02002906 if (intr_remapping_enabled)
2907 panic("BIOS bug: timer not connected to IO-APIC");
Maciej W. Rozycki691874f2008-05-27 21:19:51 +01002908 pin1 = pin2;
2909 apic1 = apic2;
2910 no_pin1 = 1;
2911 } else if (pin2 == -1) {
2912 pin2 = pin1;
2913 apic2 = apic1;
2914 }
2915
Linus Torvalds1da177e2005-04-16 15:20:36 -07002916 if (pin1 != -1) {
2917 /*
2918 * Ok, does IRQ0 through the IOAPIC work?
2919 */
Maciej W. Rozycki691874f2008-05-27 21:19:51 +01002920 if (no_pin1) {
Yinghai Lu3145e942008-12-05 18:58:34 -08002921 add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
Yinghai Lu497c9a12008-08-19 20:50:28 -07002922 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
Yinghai Luf72dcca2009-02-08 16:18:03 -08002923 } else {
2924 /* for edge trigger, setup_IO_APIC_irq already
2925 * leave it unmasked.
2926 * so only need to unmask if it is level-trigger
2927 * do we really have level trigger timer?
2928 */
2929 int idx;
2930 idx = find_irq_entry(apic1, pin1, mp_INT);
2931 if (idx != -1 && irq_trigger(idx))
2932 unmask_IO_APIC_irq_desc(desc);
Maciej W. Rozycki691874f2008-05-27 21:19:51 +01002933 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002934 if (timer_irq_works()) {
2935 if (nmi_watchdog == NMI_IO_APIC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002936 setup_nmi();
2937 enable_8259A_irq(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002938 }
Chuck Ebbert66759a02005-09-12 18:49:25 +02002939 if (disable_timer_pin_1 > 0)
2940 clear_IO_APIC_pin(0, pin1);
Ingo Molnar4aae0702007-12-18 18:05:58 +01002941 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002942 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02002943 if (intr_remapping_enabled)
2944 panic("timer doesn't work through Interrupt-remapped IO-APIC");
Yinghai Luf72dcca2009-02-08 16:18:03 -08002945 local_irq_disable();
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002946 clear_IO_APIC_pin(apic1, pin1);
Maciej W. Rozycki691874f2008-05-27 21:19:51 +01002947 if (!no_pin1)
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01002948 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2949 "8254 timer not connected to IO-APIC\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002950
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01002951 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2952 "(IRQ0) through the 8259A ...\n");
2953 apic_printk(APIC_QUIET, KERN_INFO
2954 "..... (found apic %d pin %d) ...\n", apic2, pin2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002955 /*
2956 * legacy devices should be connected to IO APIC #0
2957 */
Yinghai Lu3145e942008-12-05 18:58:34 -08002958 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
Yinghai Lu497c9a12008-08-19 20:50:28 -07002959 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
Maciej W. Rozyckiecd29472008-05-21 22:09:19 +01002960 enable_8259A_irq(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002961 if (timer_irq_works()) {
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01002962 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
Maciej W. Rozycki35542c52008-05-21 22:10:22 +01002963 timer_through_8259 = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002964 if (nmi_watchdog == NMI_IO_APIC) {
Maciej W. Rozycki60134eb2008-05-21 22:09:34 +01002965 disable_8259A_irq(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002966 setup_nmi();
Maciej W. Rozycki60134eb2008-05-21 22:09:34 +01002967 enable_8259A_irq(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002968 }
Ingo Molnar4aae0702007-12-18 18:05:58 +01002969 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002970 }
2971 /*
2972 * Cleanup, just in case ...
2973 */
Yinghai Luf72dcca2009-02-08 16:18:03 -08002974 local_irq_disable();
Maciej W. Rozyckiecd29472008-05-21 22:09:19 +01002975 disable_8259A_irq(0);
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002976 clear_IO_APIC_pin(apic2, pin2);
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01002977 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002978 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002979
2980 if (nmi_watchdog == NMI_IO_APIC) {
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01002981 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2982 "through the IO-APIC - disabling NMI Watchdog!\n");
Cyrill Gorcunov067fa0f2008-05-29 22:32:30 +04002983 nmi_watchdog = NMI_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002984 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02002985#ifdef CONFIG_X86_32
Maciej W. Rozyckid11d5792008-05-21 22:09:11 +01002986 timer_ack = 0;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002987#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002988
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01002989 apic_printk(APIC_QUIET, KERN_INFO
2990 "...trying to set up timer as Virtual Wire IRQ...\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002991
Yinghai Lu3145e942008-12-05 18:58:34 -08002992 lapic_register_intr(0, desc);
Yinghai Lu497c9a12008-08-19 20:50:28 -07002993 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002994 enable_8259A_irq(0);
2995
2996 if (timer_irq_works()) {
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01002997 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
Ingo Molnar4aae0702007-12-18 18:05:58 +01002998 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002999 }
Yinghai Luf72dcca2009-02-08 16:18:03 -08003000 local_irq_disable();
Maciej W. Rozyckie67465f2008-05-21 22:09:26 +01003001 disable_8259A_irq(0);
Yinghai Lu497c9a12008-08-19 20:50:28 -07003002 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003003 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003004
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003005 apic_printk(APIC_QUIET, KERN_INFO
3006 "...trying to set up timer as ExtINT IRQ...\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003007
Linus Torvalds1da177e2005-04-16 15:20:36 -07003008 init_8259A(0);
3009 make_8259A_irq(0);
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +01003010 apic_write(APIC_LVT0, APIC_DM_EXTINT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003011
3012 unlock_ExtINT_logic();
3013
3014 if (timer_irq_works()) {
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003015 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
Ingo Molnar4aae0702007-12-18 18:05:58 +01003016 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003017 }
Yinghai Luf72dcca2009-02-08 16:18:03 -08003018 local_irq_disable();
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003019 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003020 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003021 "report. Then try booting with the 'noapic' option.\n");
Ingo Molnar4aae0702007-12-18 18:05:58 +01003022out:
3023 local_irq_restore(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003024}
3025
3026/*
Maciej W. Rozyckiaf174782008-07-11 19:35:23 +01003027 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3028 * to devices. However there may be an I/O APIC pin available for
3029 * this interrupt regardless. The pin may be left unconnected, but
3030 * typically it will be reused as an ExtINT cascade interrupt for
3031 * the master 8259A. In the MPS case such a pin will normally be
3032 * reported as an ExtINT interrupt in the MP table. With ACPI
3033 * there is no provision for ExtINT interrupts, and in the absence
3034 * of an override it would be treated as an ordinary ISA I/O APIC
3035 * interrupt, that is edge-triggered and unmasked by default. We
3036 * used to do this, but it caused problems on some systems because
3037 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3038 * the same ExtINT cascade interrupt to drive the local APIC of the
3039 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3040 * the I/O APIC in all cases now. No actual device should request
3041 * it anyway. --macro
Linus Torvalds1da177e2005-04-16 15:20:36 -07003042 */
3043#define PIC_IRQS (1 << PIC_CASCADE_IR)
3044
3045void __init setup_IO_APIC(void)
3046{
Ingo Molnar54168ed2008-08-20 09:07:45 +02003047
Ingo Molnar54168ed2008-08-20 09:07:45 +02003048 /*
3049 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3050 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003051
Maciej W. Rozyckiaf174782008-07-11 19:35:23 +01003052 io_apic_irqs = ~PIC_IRQS;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003053
Ingo Molnar54168ed2008-08-20 09:07:45 +02003054 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02003055 /*
Ingo Molnar54168ed2008-08-20 09:07:45 +02003056 * Set up IO-APIC IRQ routing.
3057 */
3058#ifdef CONFIG_X86_32
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02003059 if (!acpi_ioapic)
3060 setup_ioapic_ids_from_mpc();
Ingo Molnar54168ed2008-08-20 09:07:45 +02003061#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003062 sync_Arb_IDs();
3063 setup_IO_APIC_irqs();
3064 init_IO_APIC_traps();
Linus Torvalds1e4c85f2005-10-31 19:16:17 -08003065 check_timer();
Linus Torvalds1da177e2005-04-16 15:20:36 -07003066}
3067
3068/*
Ingo Molnar54168ed2008-08-20 09:07:45 +02003069 * Called after all the initialization is done. If we didnt find any
3070 * APIC bugs then we can allow the modify fast path
Linus Torvalds1da177e2005-04-16 15:20:36 -07003071 */
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003072
Linus Torvalds1da177e2005-04-16 15:20:36 -07003073static int __init io_apic_bug_finalize(void)
3074{
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02003075 if (sis_apic_bug == -1)
3076 sis_apic_bug = 0;
3077 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003078}
3079
3080late_initcall(io_apic_bug_finalize);
3081
3082struct sysfs_ioapic_data {
3083 struct sys_device dev;
3084 struct IO_APIC_route_entry entry[0];
3085};
Ingo Molnar54168ed2008-08-20 09:07:45 +02003086static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
Linus Torvalds1da177e2005-04-16 15:20:36 -07003087
Pavel Machek438510f2005-04-16 15:25:24 -07003088static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003089{
3090 struct IO_APIC_route_entry *entry;
3091 struct sysfs_ioapic_data *data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003092 int i;
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003093
Linus Torvalds1da177e2005-04-16 15:20:36 -07003094 data = container_of(dev, struct sysfs_ioapic_data, dev);
3095 entry = data->entry;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003096 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3097 *entry = ioapic_read_entry(dev->id, i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003098
3099 return 0;
3100}
3101
3102static int ioapic_resume(struct sys_device *dev)
3103{
3104 struct IO_APIC_route_entry *entry;
3105 struct sysfs_ioapic_data *data;
3106 unsigned long flags;
3107 union IO_APIC_reg_00 reg_00;
3108 int i;
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003109
Linus Torvalds1da177e2005-04-16 15:20:36 -07003110 data = container_of(dev, struct sysfs_ioapic_data, dev);
3111 entry = data->entry;
3112
3113 spin_lock_irqsave(&ioapic_lock, flags);
3114 reg_00.raw = io_apic_read(dev->id, 0);
Jaswinder Singh Rajputb5ba7e62009-01-12 17:46:17 +05303115 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3116 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003117 io_apic_write(dev->id, 0, reg_00.raw);
3118 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003119 spin_unlock_irqrestore(&ioapic_lock, flags);
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003120 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
Andi Kleencf4c6a22006-09-26 10:52:30 +02003121 ioapic_write_entry(dev->id, i, entry[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003122
3123 return 0;
3124}
3125
3126static struct sysdev_class ioapic_sysdev_class = {
Kay Sieversaf5ca3f2007-12-20 02:09:39 +01003127 .name = "ioapic",
Linus Torvalds1da177e2005-04-16 15:20:36 -07003128 .suspend = ioapic_suspend,
3129 .resume = ioapic_resume,
3130};
3131
3132static int __init ioapic_init_sysfs(void)
3133{
Ingo Molnar54168ed2008-08-20 09:07:45 +02003134 struct sys_device * dev;
3135 int i, size, error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003136
3137 error = sysdev_class_register(&ioapic_sysdev_class);
3138 if (error)
3139 return error;
3140
Ingo Molnar54168ed2008-08-20 09:07:45 +02003141 for (i = 0; i < nr_ioapics; i++ ) {
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003142 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
Linus Torvalds1da177e2005-04-16 15:20:36 -07003143 * sizeof(struct IO_APIC_route_entry);
Christophe Jaillet25556c12008-06-22 22:13:48 +02003144 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003145 if (!mp_ioapic_data[i]) {
3146 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3147 continue;
3148 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003149 dev = &mp_ioapic_data[i]->dev;
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003150 dev->id = i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003151 dev->cls = &ioapic_sysdev_class;
3152 error = sysdev_register(dev);
3153 if (error) {
3154 kfree(mp_ioapic_data[i]);
3155 mp_ioapic_data[i] = NULL;
3156 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3157 continue;
3158 }
3159 }
3160
3161 return 0;
3162}
3163
3164device_initcall(ioapic_init_sysfs);
3165
Yinghai Luabcaa2b2009-02-08 16:18:03 -08003166static int nr_irqs_gsi = NR_IRQS_LEGACY;
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003167/*
Eric W. Biederman95d77882006-10-04 02:17:01 -07003168 * Dynamic irq allocate and deallocation
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003169 */
Yinghai Lu199751d2008-08-19 20:50:27 -07003170unsigned int create_irq_nr(unsigned int irq_want)
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003171{
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07003172 /* Allocate an unused irq */
Ingo Molnar54168ed2008-08-20 09:07:45 +02003173 unsigned int irq;
3174 unsigned int new;
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003175 unsigned long flags;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003176 struct irq_cfg *cfg_new = NULL;
3177 int cpu = boot_cpu_id;
3178 struct irq_desc *desc_new = NULL;
Yinghai Lu199751d2008-08-19 20:50:27 -07003179
3180 irq = 0;
Yinghai Luabcaa2b2009-02-08 16:18:03 -08003181 if (irq_want < nr_irqs_gsi)
3182 irq_want = nr_irqs_gsi;
3183
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07003184 spin_lock_irqsave(&vector_lock, flags);
Mike Travis95949492009-01-10 22:24:06 -08003185 for (new = irq_want; new < nr_irqs; new++) {
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003186 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3187 if (!desc_new) {
3188 printk(KERN_INFO "can not get irq_desc for %d\n", new);
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07003189 continue;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003190 }
3191 cfg_new = desc_new->chip_data;
3192
3193 if (cfg_new->vector != 0)
3194 continue;
Ingo Molnarfe402e12009-01-28 04:32:51 +01003195 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07003196 irq = new;
3197 break;
3198 }
3199 spin_unlock_irqrestore(&vector_lock, flags);
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003200
Yinghai Lu199751d2008-08-19 20:50:27 -07003201 if (irq > 0) {
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003202 dynamic_irq_init(irq);
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003203 /* restore it, in case dynamic_irq_init clear it */
3204 if (desc_new)
3205 desc_new->chip_data = cfg_new;
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003206 }
3207 return irq;
3208}
3209
Yinghai Lu199751d2008-08-19 20:50:27 -07003210int create_irq(void)
3211{
Yinghai Lube5d5352008-12-05 18:58:33 -08003212 unsigned int irq_want;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003213 int irq;
3214
Yinghai Lube5d5352008-12-05 18:58:33 -08003215 irq_want = nr_irqs_gsi;
3216 irq = create_irq_nr(irq_want);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003217
3218 if (irq == 0)
3219 irq = -1;
3220
3221 return irq;
Yinghai Lu199751d2008-08-19 20:50:27 -07003222}
3223
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003224void destroy_irq(unsigned int irq)
3225{
3226 unsigned long flags;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003227 struct irq_cfg *cfg;
3228 struct irq_desc *desc;
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003229
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003230 /* store it, in case dynamic_irq_cleanup clear it */
3231 desc = irq_to_desc(irq);
3232 cfg = desc->chip_data;
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003233 dynamic_irq_cleanup(irq);
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003234 /* connect back irq_cfg */
3235 if (desc)
3236 desc->chip_data = cfg;
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003237
Ingo Molnar54168ed2008-08-20 09:07:45 +02003238 free_irte(irq);
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003239 spin_lock_irqsave(&vector_lock, flags);
Yinghai Lu3145e942008-12-05 18:58:34 -08003240 __clear_irq_vector(irq, cfg);
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003241 spin_unlock_irqrestore(&vector_lock, flags);
3242}
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003243
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003244/*
Simon Arlott27b46d72007-10-20 01:13:56 +02003245 * MSI message composition
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003246 */
3247#ifdef CONFIG_PCI_MSI
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003248static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003249{
Yinghai Lu497c9a12008-08-19 20:50:28 -07003250 struct irq_cfg *cfg;
3251 int err;
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003252 unsigned dest;
3253
Jan Beulichf1182632009-01-14 12:27:35 +00003254 if (disable_apic)
3255 return -ENXIO;
3256
Yinghai Lu3145e942008-12-05 18:58:34 -08003257 cfg = irq_cfg(irq);
Ingo Molnarfe402e12009-01-28 04:32:51 +01003258 err = assign_irq_vector(irq, cfg, apic->target_cpus());
Yinghai Lu497c9a12008-08-19 20:50:28 -07003259 if (err)
3260 return err;
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003261
Ingo Molnardebccb32009-01-28 15:20:18 +01003262 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003263
Ingo Molnar54168ed2008-08-20 09:07:45 +02003264 if (irq_remapped(irq)) {
3265 struct irte irte;
3266 int ir_index;
3267 u16 sub_handle;
Yinghai Lu497c9a12008-08-19 20:50:28 -07003268
Ingo Molnar54168ed2008-08-20 09:07:45 +02003269 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3270 BUG_ON(ir_index == -1);
Yinghai Lu497c9a12008-08-19 20:50:28 -07003271
Ingo Molnar54168ed2008-08-20 09:07:45 +02003272 memset (&irte, 0, sizeof(irte));
3273
3274 irte.present = 1;
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01003275 irte.dst_mode = apic->irq_dest_mode;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003276 irte.trigger_mode = 0; /* edge */
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01003277 irte.dlvry_mode = apic->irq_delivery_mode;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003278 irte.vector = cfg->vector;
3279 irte.dest_id = IRTE_DEST(dest);
3280
3281 modify_irte(irq, &irte);
3282
3283 msg->address_hi = MSI_ADDR_BASE_HI;
3284 msg->data = sub_handle;
3285 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3286 MSI_ADDR_IR_SHV |
3287 MSI_ADDR_IR_INDEX1(ir_index) |
3288 MSI_ADDR_IR_INDEX2(ir_index);
Suresh Siddha29b61be2009-03-16 17:05:02 -07003289 } else {
Suresh Siddha9d783ba2009-03-16 17:04:55 -07003290 if (x2apic_enabled())
3291 msg->address_hi = MSI_ADDR_BASE_HI |
3292 MSI_ADDR_EXT_DEST_ID(dest);
3293 else
3294 msg->address_hi = MSI_ADDR_BASE_HI;
3295
Ingo Molnar54168ed2008-08-20 09:07:45 +02003296 msg->address_lo =
3297 MSI_ADDR_BASE_LO |
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01003298 ((apic->irq_dest_mode == 0) ?
Ingo Molnar54168ed2008-08-20 09:07:45 +02003299 MSI_ADDR_DEST_MODE_PHYSICAL:
3300 MSI_ADDR_DEST_MODE_LOGICAL) |
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01003301 ((apic->irq_delivery_mode != dest_LowestPrio) ?
Ingo Molnar54168ed2008-08-20 09:07:45 +02003302 MSI_ADDR_REDIRECTION_CPU:
3303 MSI_ADDR_REDIRECTION_LOWPRI) |
3304 MSI_ADDR_DEST_ID(dest);
3305
3306 msg->data =
3307 MSI_DATA_TRIGGER_EDGE |
3308 MSI_DATA_LEVEL_ASSERT |
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01003309 ((apic->irq_delivery_mode != dest_LowestPrio) ?
Ingo Molnar54168ed2008-08-20 09:07:45 +02003310 MSI_DATA_DELIVERY_FIXED:
3311 MSI_DATA_DELIVERY_LOWPRI) |
3312 MSI_DATA_VECTOR(cfg->vector);
3313 }
Yinghai Lu497c9a12008-08-19 20:50:28 -07003314 return err;
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003315}
3316
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003317#ifdef CONFIG_SMP
Rusty Russell0de26522008-12-13 21:20:26 +10303318static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003319{
Yinghai Lu3145e942008-12-05 18:58:34 -08003320 struct irq_desc *desc = irq_to_desc(irq);
Yinghai Lu497c9a12008-08-19 20:50:28 -07003321 struct irq_cfg *cfg;
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003322 struct msi_msg msg;
3323 unsigned int dest;
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003324
Mike Travis22f65d32008-12-16 17:33:56 -08003325 dest = set_desc_affinity(desc, mask);
3326 if (dest == BAD_APICID)
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003327 return;
3328
Yinghai Lu3145e942008-12-05 18:58:34 -08003329 cfg = desc->chip_data;
Yinghai Lu497c9a12008-08-19 20:50:28 -07003330
Yinghai Lu3145e942008-12-05 18:58:34 -08003331 read_msi_msg_desc(desc, &msg);
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003332
3333 msg.data &= ~MSI_DATA_VECTOR_MASK;
Yinghai Lu497c9a12008-08-19 20:50:28 -07003334 msg.data |= MSI_DATA_VECTOR(cfg->vector);
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003335 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3336 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3337
Yinghai Lu3145e942008-12-05 18:58:34 -08003338 write_msi_msg_desc(desc, &msg);
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003339}
Ingo Molnar54168ed2008-08-20 09:07:45 +02003340#ifdef CONFIG_INTR_REMAP
3341/*
3342 * Migrate the MSI irq to another cpumask. This migration is
3343 * done in the process context using interrupt-remapping hardware.
3344 */
Mike Travise7986732008-12-16 17:33:52 -08003345static void
3346ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02003347{
Yinghai Lu3145e942008-12-05 18:58:34 -08003348 struct irq_desc *desc = irq_to_desc(irq);
Ingo Molnara7883de2008-12-19 00:59:09 +01003349 struct irq_cfg *cfg = desc->chip_data;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003350 unsigned int dest;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003351 struct irte irte;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003352
3353 if (get_irte(irq, &irte))
3354 return;
3355
Mike Travis22f65d32008-12-16 17:33:56 -08003356 dest = set_desc_affinity(desc, mask);
3357 if (dest == BAD_APICID)
Ingo Molnar54168ed2008-08-20 09:07:45 +02003358 return;
3359
Ingo Molnar54168ed2008-08-20 09:07:45 +02003360 irte.vector = cfg->vector;
3361 irte.dest_id = IRTE_DEST(dest);
3362
3363 /*
3364 * atomically update the IRTE with the new destination and vector.
3365 */
3366 modify_irte(irq, &irte);
3367
3368 /*
3369 * After this point, all the interrupts will start arriving
3370 * at the new destination. So, time to cleanup the previous
3371 * vector allocation.
3372 */
Mike Travis22f65d32008-12-16 17:33:56 -08003373 if (cfg->move_in_progress)
3374 send_cleanup_vector(cfg);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003375}
Yinghai Lu3145e942008-12-05 18:58:34 -08003376
Ingo Molnar54168ed2008-08-20 09:07:45 +02003377#endif
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003378#endif /* CONFIG_SMP */
3379
3380/*
3381 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3382 * which implement the MSI or MSI-X Capability Structure.
3383 */
3384static struct irq_chip msi_chip = {
3385 .name = "PCI-MSI",
3386 .unmask = unmask_msi_irq,
3387 .mask = mask_msi_irq,
Yinghai Lu1d025192008-08-19 20:50:34 -07003388 .ack = ack_apic_edge,
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003389#ifdef CONFIG_SMP
3390 .set_affinity = set_msi_irq_affinity,
3391#endif
3392 .retrigger = ioapic_retrigger_irq,
3393};
3394
Ingo Molnar54168ed2008-08-20 09:07:45 +02003395static struct irq_chip msi_ir_chip = {
3396 .name = "IR-PCI-MSI",
3397 .unmask = unmask_msi_irq,
3398 .mask = mask_msi_irq,
Jaswinder Singh Rajputa1e38ca2009-03-23 02:11:25 +05303399#ifdef CONFIG_INTR_REMAP
Ingo Molnar54168ed2008-08-20 09:07:45 +02003400 .ack = ack_x2apic_edge,
3401#ifdef CONFIG_SMP
3402 .set_affinity = ir_set_msi_irq_affinity,
3403#endif
Jaswinder Singh Rajputa1e38ca2009-03-23 02:11:25 +05303404#endif
Ingo Molnar54168ed2008-08-20 09:07:45 +02003405 .retrigger = ioapic_retrigger_irq,
3406};
3407
3408/*
3409 * Map the PCI dev to the corresponding remapping hardware unit
3410 * and allocate 'nvec' consecutive interrupt-remapping table entries
3411 * in it.
3412 */
3413static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3414{
3415 struct intel_iommu *iommu;
3416 int index;
3417
3418 iommu = map_dev_to_ir(dev);
3419 if (!iommu) {
3420 printk(KERN_ERR
3421 "Unable to map PCI %s to iommu\n", pci_name(dev));
3422 return -ENOENT;
3423 }
3424
3425 index = alloc_irte(iommu, irq, nvec);
3426 if (index < 0) {
3427 printk(KERN_ERR
3428 "Unable to allocate %d IRTE for PCI %s\n", nvec,
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02003429 pci_name(dev));
Ingo Molnar54168ed2008-08-20 09:07:45 +02003430 return -ENOSPC;
3431 }
3432 return index;
3433}
Yinghai Lu1d025192008-08-19 20:50:34 -07003434
Yinghai Lu3145e942008-12-05 18:58:34 -08003435static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
Yinghai Lu1d025192008-08-19 20:50:34 -07003436{
3437 int ret;
3438 struct msi_msg msg;
3439
3440 ret = msi_compose_msg(dev, irq, &msg);
3441 if (ret < 0)
3442 return ret;
3443
Yinghai Lu3145e942008-12-05 18:58:34 -08003444 set_irq_msi(irq, msidesc);
Yinghai Lu1d025192008-08-19 20:50:34 -07003445 write_msi_msg(irq, &msg);
3446
Ingo Molnar54168ed2008-08-20 09:07:45 +02003447 if (irq_remapped(irq)) {
3448 struct irq_desc *desc = irq_to_desc(irq);
3449 /*
3450 * irq migration in process context
3451 */
3452 desc->status |= IRQ_MOVE_PCNTXT;
3453 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3454 } else
Ingo Molnar54168ed2008-08-20 09:07:45 +02003455 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
Yinghai Lu1d025192008-08-19 20:50:34 -07003456
Yinghai Luc81bba42008-09-25 11:53:11 -07003457 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3458
Yinghai Lu1d025192008-08-19 20:50:34 -07003459 return 0;
3460}
3461
Yinghai Lu047c8fd2008-08-19 20:50:41 -07003462int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3463{
Ingo Molnar54168ed2008-08-20 09:07:45 +02003464 unsigned int irq;
3465 int ret, sub_handle;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003466 struct msi_desc *msidesc;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003467 unsigned int irq_want;
Dmitri Vorobiev1cc18522009-03-22 19:11:09 +02003468 struct intel_iommu *iommu = NULL;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003469 int index = 0;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003470
Matthew Wilcox1c8d7b02009-03-17 08:54:10 -04003471 /* x86 doesn't support multiple MSI yet */
3472 if (type == PCI_CAP_ID_MSI && nvec > 1)
3473 return 1;
3474
Yinghai Lube5d5352008-12-05 18:58:33 -08003475 irq_want = nr_irqs_gsi;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003476 sub_handle = 0;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003477 list_for_each_entry(msidesc, &dev->msi_list, list) {
3478 irq = create_irq_nr(irq_want);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003479 if (irq == 0)
3480 return -1;
Yinghai Luf1ee5542009-02-08 16:18:03 -08003481 irq_want = irq + 1;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003482 if (!intr_remapping_enabled)
3483 goto no_ir;
3484
3485 if (!sub_handle) {
3486 /*
3487 * allocate the consecutive block of IRTE's
3488 * for 'nvec'
3489 */
3490 index = msi_alloc_irte(dev, irq, nvec);
3491 if (index < 0) {
3492 ret = index;
3493 goto error;
3494 }
3495 } else {
3496 iommu = map_dev_to_ir(dev);
3497 if (!iommu) {
3498 ret = -ENOENT;
3499 goto error;
3500 }
3501 /*
3502 * setup the mapping between the irq and the IRTE
3503 * base index, the sub_handle pointing to the
3504 * appropriate interrupt remap table entry.
3505 */
3506 set_irte_irq(irq, iommu, index, sub_handle);
3507 }
3508no_ir:
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003509 ret = setup_msi_irq(dev, msidesc, irq);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003510 if (ret < 0)
3511 goto error;
3512 sub_handle++;
3513 }
3514 return 0;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07003515
3516error:
Ingo Molnar54168ed2008-08-20 09:07:45 +02003517 destroy_irq(irq);
3518 return ret;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07003519}
3520
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003521void arch_teardown_msi_irq(unsigned int irq)
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003522{
Eric W. Biedermanf7feaca2007-01-28 12:56:37 -07003523 destroy_irq(irq);
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003524}
3525
Suresh Siddha9d783ba2009-03-16 17:04:55 -07003526#if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
Ingo Molnar54168ed2008-08-20 09:07:45 +02003527#ifdef CONFIG_SMP
Mike Travis22f65d32008-12-16 17:33:56 -08003528static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02003529{
Yinghai Lu3145e942008-12-05 18:58:34 -08003530 struct irq_desc *desc = irq_to_desc(irq);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003531 struct irq_cfg *cfg;
3532 struct msi_msg msg;
3533 unsigned int dest;
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003534
Mike Travis22f65d32008-12-16 17:33:56 -08003535 dest = set_desc_affinity(desc, mask);
3536 if (dest == BAD_APICID)
Ingo Molnar54168ed2008-08-20 09:07:45 +02003537 return;
3538
Yinghai Lu3145e942008-12-05 18:58:34 -08003539 cfg = desc->chip_data;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003540
3541 dmar_msi_read(irq, &msg);
3542
3543 msg.data &= ~MSI_DATA_VECTOR_MASK;
3544 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3545 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3546 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3547
3548 dmar_msi_write(irq, &msg);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003549}
Yinghai Lu3145e942008-12-05 18:58:34 -08003550
Ingo Molnar54168ed2008-08-20 09:07:45 +02003551#endif /* CONFIG_SMP */
3552
3553struct irq_chip dmar_msi_type = {
3554 .name = "DMAR_MSI",
3555 .unmask = dmar_msi_unmask,
3556 .mask = dmar_msi_mask,
3557 .ack = ack_apic_edge,
3558#ifdef CONFIG_SMP
3559 .set_affinity = dmar_msi_set_affinity,
3560#endif
3561 .retrigger = ioapic_retrigger_irq,
3562};
3563
3564int arch_setup_dmar_msi(unsigned int irq)
3565{
3566 int ret;
3567 struct msi_msg msg;
3568
3569 ret = msi_compose_msg(NULL, irq, &msg);
3570 if (ret < 0)
3571 return ret;
3572 dmar_msi_write(irq, &msg);
3573 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3574 "edge");
3575 return 0;
3576}
3577#endif
3578
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003579#ifdef CONFIG_HPET_TIMER
3580
3581#ifdef CONFIG_SMP
Mike Travis22f65d32008-12-16 17:33:56 -08003582static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003583{
Yinghai Lu3145e942008-12-05 18:58:34 -08003584 struct irq_desc *desc = irq_to_desc(irq);
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003585 struct irq_cfg *cfg;
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003586 struct msi_msg msg;
3587 unsigned int dest;
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003588
Mike Travis22f65d32008-12-16 17:33:56 -08003589 dest = set_desc_affinity(desc, mask);
3590 if (dest == BAD_APICID)
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003591 return;
3592
Yinghai Lu3145e942008-12-05 18:58:34 -08003593 cfg = desc->chip_data;
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003594
3595 hpet_msi_read(irq, &msg);
3596
3597 msg.data &= ~MSI_DATA_VECTOR_MASK;
3598 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3599 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3600 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3601
3602 hpet_msi_write(irq, &msg);
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003603}
Yinghai Lu3145e942008-12-05 18:58:34 -08003604
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003605#endif /* CONFIG_SMP */
3606
Dmitri Vorobiev1cc18522009-03-22 19:11:09 +02003607static struct irq_chip hpet_msi_type = {
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003608 .name = "HPET_MSI",
3609 .unmask = hpet_msi_unmask,
3610 .mask = hpet_msi_mask,
3611 .ack = ack_apic_edge,
3612#ifdef CONFIG_SMP
3613 .set_affinity = hpet_msi_set_affinity,
3614#endif
3615 .retrigger = ioapic_retrigger_irq,
3616};
3617
3618int arch_setup_hpet_msi(unsigned int irq)
3619{
3620 int ret;
3621 struct msi_msg msg;
3622
3623 ret = msi_compose_msg(NULL, irq, &msg);
3624 if (ret < 0)
3625 return ret;
3626
3627 hpet_msi_write(irq, &msg);
3628 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3629 "edge");
Yinghai Luc81bba42008-09-25 11:53:11 -07003630
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003631 return 0;
3632}
3633#endif
3634
Ingo Molnar54168ed2008-08-20 09:07:45 +02003635#endif /* CONFIG_PCI_MSI */
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003636/*
3637 * Hypertransport interrupt support
3638 */
3639#ifdef CONFIG_HT_IRQ
3640
3641#ifdef CONFIG_SMP
3642
Yinghai Lu497c9a12008-08-19 20:50:28 -07003643static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003644{
Eric W. Biedermanec683072006-11-08 17:44:57 -08003645 struct ht_irq_msg msg;
3646 fetch_ht_irq_msg(irq, &msg);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003647
Yinghai Lu497c9a12008-08-19 20:50:28 -07003648 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
Eric W. Biedermanec683072006-11-08 17:44:57 -08003649 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003650
Yinghai Lu497c9a12008-08-19 20:50:28 -07003651 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
Eric W. Biedermanec683072006-11-08 17:44:57 -08003652 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003653
Eric W. Biedermanec683072006-11-08 17:44:57 -08003654 write_ht_irq_msg(irq, &msg);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003655}
3656
Mike Travis22f65d32008-12-16 17:33:56 -08003657static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003658{
Yinghai Lu3145e942008-12-05 18:58:34 -08003659 struct irq_desc *desc = irq_to_desc(irq);
Yinghai Lu497c9a12008-08-19 20:50:28 -07003660 struct irq_cfg *cfg;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003661 unsigned int dest;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003662
Mike Travis22f65d32008-12-16 17:33:56 -08003663 dest = set_desc_affinity(desc, mask);
3664 if (dest == BAD_APICID)
Yinghai Lu497c9a12008-08-19 20:50:28 -07003665 return;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003666
Yinghai Lu3145e942008-12-05 18:58:34 -08003667 cfg = desc->chip_data;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003668
Yinghai Lu497c9a12008-08-19 20:50:28 -07003669 target_ht_irq(irq, dest, cfg->vector);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003670}
Yinghai Lu3145e942008-12-05 18:58:34 -08003671
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003672#endif
3673
Aneesh Kumar K.Vc37e1082006-10-11 01:20:43 -07003674static struct irq_chip ht_irq_chip = {
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003675 .name = "PCI-HT",
3676 .mask = mask_ht_irq,
3677 .unmask = unmask_ht_irq,
Yinghai Lu1d025192008-08-19 20:50:34 -07003678 .ack = ack_apic_edge,
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003679#ifdef CONFIG_SMP
3680 .set_affinity = set_ht_irq_affinity,
3681#endif
3682 .retrigger = ioapic_retrigger_irq,
3683};
3684
3685int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3686{
Yinghai Lu497c9a12008-08-19 20:50:28 -07003687 struct irq_cfg *cfg;
3688 int err;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003689
Jan Beulichf1182632009-01-14 12:27:35 +00003690 if (disable_apic)
3691 return -ENXIO;
3692
Yinghai Lu3145e942008-12-05 18:58:34 -08003693 cfg = irq_cfg(irq);
Ingo Molnarfe402e12009-01-28 04:32:51 +01003694 err = assign_irq_vector(irq, cfg, apic->target_cpus());
Ingo Molnar54168ed2008-08-20 09:07:45 +02003695 if (!err) {
Eric W. Biedermanec683072006-11-08 17:44:57 -08003696 struct ht_irq_msg msg;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003697 unsigned dest;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003698
Ingo Molnardebccb32009-01-28 15:20:18 +01003699 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3700 apic->target_cpus());
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003701
Eric W. Biedermanec683072006-11-08 17:44:57 -08003702 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003703
Eric W. Biedermanec683072006-11-08 17:44:57 -08003704 msg.address_lo =
3705 HT_IRQ_LOW_BASE |
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003706 HT_IRQ_LOW_DEST_ID(dest) |
Yinghai Lu497c9a12008-08-19 20:50:28 -07003707 HT_IRQ_LOW_VECTOR(cfg->vector) |
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01003708 ((apic->irq_dest_mode == 0) ?
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003709 HT_IRQ_LOW_DM_PHYSICAL :
3710 HT_IRQ_LOW_DM_LOGICAL) |
3711 HT_IRQ_LOW_RQEOI_EDGE |
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01003712 ((apic->irq_delivery_mode != dest_LowestPrio) ?
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003713 HT_IRQ_LOW_MT_FIXED :
3714 HT_IRQ_LOW_MT_ARBITRATED) |
3715 HT_IRQ_LOW_IRQ_MASKED;
3716
Eric W. Biedermanec683072006-11-08 17:44:57 -08003717 write_ht_irq_msg(irq, &msg);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003718
Ingo Molnara460e742006-10-17 00:10:03 -07003719 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3720 handle_edge_irq, "edge");
Yinghai Luc81bba42008-09-25 11:53:11 -07003721
3722 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003723 }
Yinghai Lu497c9a12008-08-19 20:50:28 -07003724 return err;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003725}
3726#endif /* CONFIG_HT_IRQ */
3727
Nick Piggin03b48632009-01-20 04:36:04 +01003728#ifdef CONFIG_X86_UV
Dean Nelson4173a0e2008-10-02 12:18:21 -05003729/*
3730 * Re-target the irq to the specified CPU and enable the specified MMR located
3731 * on the specified blade to allow the sending of MSIs to the specified CPU.
3732 */
3733int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3734 unsigned long mmr_offset)
3735{
Mike Travis22f65d32008-12-16 17:33:56 -08003736 const struct cpumask *eligible_cpu = cpumask_of(cpu);
Dean Nelson4173a0e2008-10-02 12:18:21 -05003737 struct irq_cfg *cfg;
3738 int mmr_pnode;
3739 unsigned long mmr_value;
3740 struct uv_IO_APIC_route_entry *entry;
3741 unsigned long flags;
3742 int err;
3743
Yinghai Lu3145e942008-12-05 18:58:34 -08003744 cfg = irq_cfg(irq);
3745
Mike Travise7986732008-12-16 17:33:52 -08003746 err = assign_irq_vector(irq, cfg, eligible_cpu);
Dean Nelson4173a0e2008-10-02 12:18:21 -05003747 if (err != 0)
3748 return err;
3749
3750 spin_lock_irqsave(&vector_lock, flags);
3751 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3752 irq_name);
3753 spin_unlock_irqrestore(&vector_lock, flags);
3754
Dean Nelson4173a0e2008-10-02 12:18:21 -05003755 mmr_value = 0;
3756 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3757 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3758
3759 entry->vector = cfg->vector;
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01003760 entry->delivery_mode = apic->irq_delivery_mode;
3761 entry->dest_mode = apic->irq_dest_mode;
Dean Nelson4173a0e2008-10-02 12:18:21 -05003762 entry->polarity = 0;
3763 entry->trigger = 0;
3764 entry->mask = 0;
Ingo Molnardebccb32009-01-28 15:20:18 +01003765 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
Dean Nelson4173a0e2008-10-02 12:18:21 -05003766
3767 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3768 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3769
3770 return irq;
3771}
3772
3773/*
3774 * Disable the specified MMR located on the specified blade so that MSIs are
3775 * longer allowed to be sent.
3776 */
3777void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3778{
3779 unsigned long mmr_value;
3780 struct uv_IO_APIC_route_entry *entry;
3781 int mmr_pnode;
3782
3783 mmr_value = 0;
3784 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3785 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3786
3787 entry->mask = 1;
3788
3789 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3790 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3791}
3792#endif /* CONFIG_X86_64 */
3793
Yinghai Lu9d6a4d02008-08-19 20:50:52 -07003794int __init io_apic_get_redir_entries (int ioapic)
3795{
3796 union IO_APIC_reg_01 reg_01;
3797 unsigned long flags;
3798
3799 spin_lock_irqsave(&ioapic_lock, flags);
3800 reg_01.raw = io_apic_read(ioapic, 1);
3801 spin_unlock_irqrestore(&ioapic_lock, flags);
3802
3803 return reg_01.bits.entries;
3804}
3805
Yinghai Lube5d5352008-12-05 18:58:33 -08003806void __init probe_nr_irqs_gsi(void)
Yinghai Lu9d6a4d02008-08-19 20:50:52 -07003807{
Yinghai Lube5d5352008-12-05 18:58:33 -08003808 int nr = 0;
3809
Yinghai Lucc6c5002009-02-08 16:18:03 -08003810 nr = acpi_probe_gsi();
3811 if (nr > nr_irqs_gsi) {
Yinghai Lube5d5352008-12-05 18:58:33 -08003812 nr_irqs_gsi = nr;
Yinghai Lucc6c5002009-02-08 16:18:03 -08003813 } else {
3814 /* for acpi=off or acpi is not compiled in */
3815 int idx;
3816
3817 nr = 0;
3818 for (idx = 0; idx < nr_ioapics; idx++)
3819 nr += io_apic_get_redir_entries(idx) + 1;
3820
3821 if (nr > nr_irqs_gsi)
3822 nr_irqs_gsi = nr;
3823 }
3824
3825 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
Yinghai Lu9d6a4d02008-08-19 20:50:52 -07003826}
3827
Yinghai Lu4a046d12009-01-12 17:39:24 -08003828#ifdef CONFIG_SPARSE_IRQ
3829int __init arch_probe_nr_irqs(void)
3830{
3831 int nr;
3832
Yinghai Luf1ee5542009-02-08 16:18:03 -08003833 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3834 nr_irqs = NR_VECTORS * nr_cpu_ids;
Yinghai Lu4a046d12009-01-12 17:39:24 -08003835
Yinghai Luf1ee5542009-02-08 16:18:03 -08003836 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3837#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3838 /*
3839 * for MSI and HT dyn irq
3840 */
3841 nr += nr_irqs_gsi * 16;
3842#endif
3843 if (nr < nr_irqs)
Yinghai Lu4a046d12009-01-12 17:39:24 -08003844 nr_irqs = nr;
3845
3846 return 0;
3847}
3848#endif
3849
Linus Torvalds1da177e2005-04-16 15:20:36 -07003850/* --------------------------------------------------------------------------
Ingo Molnar54168ed2008-08-20 09:07:45 +02003851 ACPI-based IOAPIC Configuration
Linus Torvalds1da177e2005-04-16 15:20:36 -07003852 -------------------------------------------------------------------------- */
3853
Len Brown888ba6c2005-08-24 12:07:20 -04003854#ifdef CONFIG_ACPI
Linus Torvalds1da177e2005-04-16 15:20:36 -07003855
Ingo Molnar54168ed2008-08-20 09:07:45 +02003856#ifdef CONFIG_X86_32
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003857int __init io_apic_get_unique_id(int ioapic, int apic_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003858{
3859 union IO_APIC_reg_00 reg_00;
3860 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3861 physid_mask_t tmp;
3862 unsigned long flags;
3863 int i = 0;
3864
3865 /*
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003866 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3867 * buses (one for LAPICs, one for IOAPICs), where predecessors only
Linus Torvalds1da177e2005-04-16 15:20:36 -07003868 * supports up to 16 on one shared APIC bus.
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003869 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07003870 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3871 * advantage of new APIC bus architecture.
3872 */
3873
3874 if (physids_empty(apic_id_map))
Ingo Molnard190cb82009-01-28 06:50:47 +01003875 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003876
3877 spin_lock_irqsave(&ioapic_lock, flags);
3878 reg_00.raw = io_apic_read(ioapic, 0);
3879 spin_unlock_irqrestore(&ioapic_lock, flags);
3880
3881 if (apic_id >= get_physical_broadcast()) {
3882 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3883 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3884 apic_id = reg_00.bits.ID;
3885 }
3886
3887 /*
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003888 * Every APIC in a system must have a unique ID or we get lots of nice
Linus Torvalds1da177e2005-04-16 15:20:36 -07003889 * 'stuck on smp_invalidate_needed IPI wait' messages.
3890 */
Ingo Molnard1d7cae2009-01-28 05:41:42 +01003891 if (apic->check_apicid_used(apic_id_map, apic_id)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003892
3893 for (i = 0; i < get_physical_broadcast(); i++) {
Ingo Molnard1d7cae2009-01-28 05:41:42 +01003894 if (!apic->check_apicid_used(apic_id_map, i))
Linus Torvalds1da177e2005-04-16 15:20:36 -07003895 break;
3896 }
3897
3898 if (i == get_physical_broadcast())
3899 panic("Max apic_id exceeded!\n");
3900
3901 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3902 "trying %d\n", ioapic, apic_id, i);
3903
3904 apic_id = i;
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003905 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003906
Ingo Molnar80587142009-01-28 06:50:47 +01003907 tmp = apic->apicid_to_cpu_present(apic_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003908 physids_or(apic_id_map, apic_id_map, tmp);
3909
3910 if (reg_00.bits.ID != apic_id) {
3911 reg_00.bits.ID = apic_id;
3912
3913 spin_lock_irqsave(&ioapic_lock, flags);
3914 io_apic_write(ioapic, 0, reg_00.raw);
3915 reg_00.raw = io_apic_read(ioapic, 0);
3916 spin_unlock_irqrestore(&ioapic_lock, flags);
3917
3918 /* Sanity check */
Andreas Deresch6070f9e2006-02-26 04:18:34 +01003919 if (reg_00.bits.ID != apic_id) {
3920 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3921 return -1;
3922 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003923 }
3924
3925 apic_printk(APIC_VERBOSE, KERN_INFO
3926 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3927
3928 return apic_id;
3929}
3930
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003931int __init io_apic_get_version(int ioapic)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003932{
3933 union IO_APIC_reg_01 reg_01;
3934 unsigned long flags;
3935
3936 spin_lock_irqsave(&ioapic_lock, flags);
3937 reg_01.raw = io_apic_read(ioapic, 1);
3938 spin_unlock_irqrestore(&ioapic_lock, flags);
3939
3940 return reg_01.bits.version;
3941}
Ingo Molnar54168ed2008-08-20 09:07:45 +02003942#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003943
Ingo Molnar54168ed2008-08-20 09:07:45 +02003944int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003945{
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003946 struct irq_desc *desc;
3947 struct irq_cfg *cfg;
3948 int cpu = boot_cpu_id;
3949
Linus Torvalds1da177e2005-04-16 15:20:36 -07003950 if (!IO_APIC_IRQ(irq)) {
Ingo Molnar54168ed2008-08-20 09:07:45 +02003951 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07003952 ioapic);
3953 return -EINVAL;
3954 }
3955
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003956 desc = irq_to_desc_alloc_cpu(irq, cpu);
3957 if (!desc) {
3958 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3959 return 0;
3960 }
3961
Linus Torvalds1da177e2005-04-16 15:20:36 -07003962 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07003963 * IRQs < 16 are already in the irq_2_pin[] map
3964 */
Yinghai Lu99d093d2008-12-05 18:58:32 -08003965 if (irq >= NR_IRQS_LEGACY) {
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003966 cfg = desc->chip_data;
Yinghai Lu3145e942008-12-05 18:58:34 -08003967 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003968 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003969
Yinghai Lu3145e942008-12-05 18:58:34 -08003970 setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003971
3972 return 0;
3973}
3974
Ingo Molnar54168ed2008-08-20 09:07:45 +02003975
Shaohua Li61fd47e2007-11-17 01:05:28 -05003976int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3977{
3978 int i;
3979
3980 if (skip_ioapic_setup)
3981 return -1;
3982
3983 for (i = 0; i < mp_irq_entries; i++)
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05303984 if (mp_irqs[i].irqtype == mp_INT &&
3985 mp_irqs[i].srcbusirq == bus_irq)
Shaohua Li61fd47e2007-11-17 01:05:28 -05003986 break;
3987 if (i >= mp_irq_entries)
3988 return -1;
3989
3990 *trigger = irq_trigger(i);
3991 *polarity = irq_polarity(i);
3992 return 0;
3993}
3994
Len Brown888ba6c2005-08-24 12:07:20 -04003995#endif /* CONFIG_ACPI */
Rusty Russell1a3f2392006-09-26 10:52:32 +02003996
Yinghai Lu497c9a12008-08-19 20:50:28 -07003997/*
3998 * This function currently is only a helper for the i386 smp boot process where
3999 * we need to reprogram the ioredtbls to cater for the cpus which have come online
Ingo Molnarfe402e12009-01-28 04:32:51 +01004000 * so mask in all cases should simply be apic->target_cpus()
Yinghai Lu497c9a12008-08-19 20:50:28 -07004001 */
4002#ifdef CONFIG_SMP
4003void __init setup_ioapic_dest(void)
4004{
4005 int pin, ioapic, irq, irq_entry;
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004006 struct irq_desc *desc;
Yinghai Lu497c9a12008-08-19 20:50:28 -07004007 struct irq_cfg *cfg;
Mike Travis22f65d32008-12-16 17:33:56 -08004008 const struct cpumask *mask;
Yinghai Lu497c9a12008-08-19 20:50:28 -07004009
4010 if (skip_ioapic_setup == 1)
4011 return;
4012
4013 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4014 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4015 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4016 if (irq_entry == -1)
4017 continue;
4018 irq = pin_2_irq(irq_entry, ioapic, pin);
4019
4020 /* setup_IO_APIC_irqs could fail to get vector for some device
4021 * when you have too many devices, because at that time only boot
4022 * cpu is online.
4023 */
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08004024 desc = irq_to_desc(irq);
4025 cfg = desc->chip_data;
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004026 if (!cfg->vector) {
Yinghai Lu3145e942008-12-05 18:58:34 -08004027 setup_IO_APIC_irq(ioapic, pin, irq, desc,
Yinghai Lu497c9a12008-08-19 20:50:28 -07004028 irq_trigger(irq_entry),
4029 irq_polarity(irq_entry));
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004030 continue;
4031
4032 }
4033
4034 /*
4035 * Honour affinities which have been set in early boot
4036 */
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004037 if (desc->status &
4038 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
Mike Travis7f7ace02009-01-10 21:58:08 -08004039 mask = desc->affinity;
Ingo Molnar54168ed2008-08-20 09:07:45 +02004040 else
Ingo Molnarfe402e12009-01-28 04:32:51 +01004041 mask = apic->target_cpus();
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004042
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004043 if (intr_remapping_enabled)
Yinghai Lu3145e942008-12-05 18:58:34 -08004044 set_ir_ioapic_affinity_irq_desc(desc, mask);
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004045 else
Yinghai Lu3145e942008-12-05 18:58:34 -08004046 set_ioapic_affinity_irq_desc(desc, mask);
Yinghai Lu497c9a12008-08-19 20:50:28 -07004047 }
4048
4049 }
4050}
4051#endif
4052
Ingo Molnar54168ed2008-08-20 09:07:45 +02004053#define IOAPIC_RESOURCE_NAME_SIZE 11
4054
4055static struct resource *ioapic_resources;
4056
4057static struct resource * __init ioapic_setup_resources(void)
4058{
4059 unsigned long n;
4060 struct resource *res;
4061 char *mem;
4062 int i;
4063
4064 if (nr_ioapics <= 0)
4065 return NULL;
4066
4067 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4068 n *= nr_ioapics;
4069
4070 mem = alloc_bootmem(n);
4071 res = (void *)mem;
4072
4073 if (mem != NULL) {
4074 mem += sizeof(struct resource) * nr_ioapics;
4075
4076 for (i = 0; i < nr_ioapics; i++) {
4077 res[i].name = mem;
4078 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4079 sprintf(mem, "IOAPIC %u", i);
4080 mem += IOAPIC_RESOURCE_NAME_SIZE;
4081 }
4082 }
4083
4084 ioapic_resources = res;
4085
4086 return res;
4087}
Ingo Molnar54168ed2008-08-20 09:07:45 +02004088
Yinghai Luf3294a32008-06-27 01:41:56 -07004089void __init ioapic_init_mappings(void)
4090{
4091 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
Ingo Molnar54168ed2008-08-20 09:07:45 +02004092 struct resource *ioapic_res;
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02004093 int i;
Yinghai Luf3294a32008-06-27 01:41:56 -07004094
Ingo Molnar54168ed2008-08-20 09:07:45 +02004095 ioapic_res = ioapic_setup_resources();
Yinghai Luf3294a32008-06-27 01:41:56 -07004096 for (i = 0; i < nr_ioapics; i++) {
4097 if (smp_found_config) {
Jaswinder Singh Rajputb5ba7e62009-01-12 17:46:17 +05304098 ioapic_phys = mp_ioapics[i].apicaddr;
Ingo Molnar54168ed2008-08-20 09:07:45 +02004099#ifdef CONFIG_X86_32
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02004100 if (!ioapic_phys) {
4101 printk(KERN_ERR
4102 "WARNING: bogus zero IO-APIC "
4103 "address found in MPTABLE, "
4104 "disabling IO/APIC support!\n");
4105 smp_found_config = 0;
4106 skip_ioapic_setup = 1;
4107 goto fake_ioapic_page;
4108 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02004109#endif
Yinghai Luf3294a32008-06-27 01:41:56 -07004110 } else {
Ingo Molnar54168ed2008-08-20 09:07:45 +02004111#ifdef CONFIG_X86_32
Yinghai Luf3294a32008-06-27 01:41:56 -07004112fake_ioapic_page:
Ingo Molnar54168ed2008-08-20 09:07:45 +02004113#endif
Yinghai Luf3294a32008-06-27 01:41:56 -07004114 ioapic_phys = (unsigned long)
Ingo Molnar54168ed2008-08-20 09:07:45 +02004115 alloc_bootmem_pages(PAGE_SIZE);
Yinghai Luf3294a32008-06-27 01:41:56 -07004116 ioapic_phys = __pa(ioapic_phys);
4117 }
4118 set_fixmap_nocache(idx, ioapic_phys);
Ingo Molnar54168ed2008-08-20 09:07:45 +02004119 apic_printk(APIC_VERBOSE,
4120 "mapped IOAPIC to %08lx (%08lx)\n",
4121 __fix_to_virt(idx), ioapic_phys);
Yinghai Luf3294a32008-06-27 01:41:56 -07004122 idx++;
Ingo Molnar54168ed2008-08-20 09:07:45 +02004123
Ingo Molnar54168ed2008-08-20 09:07:45 +02004124 if (ioapic_res != NULL) {
4125 ioapic_res->start = ioapic_phys;
4126 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4127 ioapic_res++;
4128 }
Yinghai Luf3294a32008-06-27 01:41:56 -07004129 }
4130}
4131
Ingo Molnar54168ed2008-08-20 09:07:45 +02004132static int __init ioapic_insert_resources(void)
4133{
4134 int i;
4135 struct resource *r = ioapic_resources;
4136
4137 if (!r) {
Bartlomiej Zolnierkiewicz04c93ce2009-03-20 21:02:55 +01004138 if (nr_ioapics > 0) {
4139 printk(KERN_ERR
4140 "IO APIC resources couldn't be allocated.\n");
4141 return -1;
4142 }
4143 return 0;
Ingo Molnar54168ed2008-08-20 09:07:45 +02004144 }
4145
4146 for (i = 0; i < nr_ioapics; i++) {
4147 insert_resource(&iomem_resource, r);
4148 r++;
4149 }
4150
4151 return 0;
4152}
4153
4154/* Insert the IO APIC resources after PCI initialization has occured to handle
4155 * IO APICS that are mapped in on a BAR in PCI space. */
4156late_initcall(ioapic_insert_resources);