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Chris Leechc13c8262006-05-23 17:18:44 -07001/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21#ifndef DMAENGINE_H
22#define DMAENGINE_H
David Woodhouse1c0f16e2006-06-27 02:53:56 -070023
Chris Leechc13c8262006-05-23 17:18:44 -070024#include <linux/device.h>
25#include <linux/uio.h>
26#include <linux/kref.h>
27#include <linux/completion.h>
28#include <linux/rcupdate.h>
Dan Williams7405f742007-01-02 11:10:43 -070029#include <linux/dma-mapping.h>
Chris Leechc13c8262006-05-23 17:18:44 -070030
31/**
Dan Williamsd379b012007-07-09 11:56:42 -070032 * enum dma_state_client - state of the channel in the client
33 * @DMA_ACK: client would like to use, or was using this channel
34 * @DMA_DUP: client has already seen this channel, or is not using this channel
35 * @DMA_NAK: client does not want to see any more channels
36 */
37enum dma_state_client {
38 DMA_ACK,
39 DMA_DUP,
40 DMA_NAK,
41};
42
43/**
Randy Dunlapfe4ada22006-07-03 19:44:51 -070044 * typedef dma_cookie_t - an opaque DMA cookie
Chris Leechc13c8262006-05-23 17:18:44 -070045 *
46 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
47 */
48typedef s32 dma_cookie_t;
49
50#define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
51
52/**
53 * enum dma_status - DMA transaction status
54 * @DMA_SUCCESS: transaction completed successfully
55 * @DMA_IN_PROGRESS: transaction not yet processed
56 * @DMA_ERROR: transaction failed
57 */
58enum dma_status {
59 DMA_SUCCESS,
60 DMA_IN_PROGRESS,
61 DMA_ERROR,
62};
63
64/**
Dan Williams7405f742007-01-02 11:10:43 -070065 * enum dma_transaction_type - DMA transaction types/indexes
66 */
67enum dma_transaction_type {
68 DMA_MEMCPY,
69 DMA_XOR,
70 DMA_PQ_XOR,
71 DMA_DUAL_XOR,
72 DMA_PQ_UPDATE,
73 DMA_ZERO_SUM,
74 DMA_PQ_ZERO_SUM,
75 DMA_MEMSET,
76 DMA_MEMCPY_CRC32C,
77 DMA_INTERRUPT,
Dan Williams59b5ec22009-01-06 11:38:15 -070078 DMA_PRIVATE,
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -070079 DMA_SLAVE,
Dan Williams7405f742007-01-02 11:10:43 -070080};
81
82/* last transaction type for creation of the capabilities mask */
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -070083#define DMA_TX_TYPE_END (DMA_SLAVE + 1)
84
Dan Williams7405f742007-01-02 11:10:43 -070085
86/**
Dan Williams636bdea2008-04-17 20:17:26 -070087 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
88 * control completion, and communicate status.
Dan Williamsd4c56f92008-02-02 19:49:58 -070089 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
90 * this transaction
Dan Williams636bdea2008-04-17 20:17:26 -070091 * @DMA_CTRL_ACK - the descriptor cannot be reused until the client
92 * acknowledges receipt, i.e. has has a chance to establish any
93 * dependency chains
Dan Williamse1d181e2008-07-04 00:13:40 -070094 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
95 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
Dan Williamsd4c56f92008-02-02 19:49:58 -070096 */
Dan Williams636bdea2008-04-17 20:17:26 -070097enum dma_ctrl_flags {
Dan Williamsd4c56f92008-02-02 19:49:58 -070098 DMA_PREP_INTERRUPT = (1 << 0),
Dan Williams636bdea2008-04-17 20:17:26 -070099 DMA_CTRL_ACK = (1 << 1),
Dan Williamse1d181e2008-07-04 00:13:40 -0700100 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
101 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
Dan Williamsd4c56f92008-02-02 19:49:58 -0700102};
103
104/**
Dan Williams7405f742007-01-02 11:10:43 -0700105 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
106 * See linux/cpumask.h
107 */
108typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
109
110/**
Chris Leechc13c8262006-05-23 17:18:44 -0700111 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
112 * @refcount: local_t used for open-coded "bigref" counting
113 * @memcpy_count: transaction counter
114 * @bytes_transferred: byte counter
115 */
116
117struct dma_chan_percpu {
Chris Leechc13c8262006-05-23 17:18:44 -0700118 /* stats */
119 unsigned long memcpy_count;
120 unsigned long bytes_transferred;
121};
122
123/**
124 * struct dma_chan - devices supply DMA channels, clients use them
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700125 * @device: ptr to the dma device who supplies this channel, always !%NULL
Chris Leechc13c8262006-05-23 17:18:44 -0700126 * @cookie: last cookie value returned to client
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700127 * @chan_id: channel ID for sysfs
128 * @class_dev: class device for sysfs
Chris Leechc13c8262006-05-23 17:18:44 -0700129 * @refcount: kref, used in "bigref" slow-mode
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700130 * @slow_ref: indicates that the DMA channel is free
131 * @rcu: the DMA channel's RCU head
Chris Leechc13c8262006-05-23 17:18:44 -0700132 * @device_node: used to add this to the device chan list
133 * @local: per-cpu pointer to a struct dma_chan_percpu
Dan Williams7cc5bf92008-07-08 11:58:21 -0700134 * @client-count: how many clients are using this channel
Dan Williamsbec08512009-01-06 11:38:14 -0700135 * @table_count: number of appearances in the mem-to-mem allocation table
Chris Leechc13c8262006-05-23 17:18:44 -0700136 */
137struct dma_chan {
Chris Leechc13c8262006-05-23 17:18:44 -0700138 struct dma_device *device;
139 dma_cookie_t cookie;
140
141 /* sysfs */
142 int chan_id;
Tony Jones891f78e2007-09-25 02:03:03 +0200143 struct device dev;
Chris Leechc13c8262006-05-23 17:18:44 -0700144
145 struct kref refcount;
146 int slow_ref;
147 struct rcu_head rcu;
148
Chris Leechc13c8262006-05-23 17:18:44 -0700149 struct list_head device_node;
150 struct dma_chan_percpu *local;
Dan Williams7cc5bf92008-07-08 11:58:21 -0700151 int client_count;
Dan Williamsbec08512009-01-06 11:38:14 -0700152 int table_count;
Chris Leechc13c8262006-05-23 17:18:44 -0700153};
154
Tony Jones891f78e2007-09-25 02:03:03 +0200155#define to_dma_chan(p) container_of(p, struct dma_chan, dev)
Dan Williamsd379b012007-07-09 11:56:42 -0700156
Chris Leechc13c8262006-05-23 17:18:44 -0700157void dma_chan_cleanup(struct kref *kref);
158
Chris Leechc13c8262006-05-23 17:18:44 -0700159/**
Dan Williams59b5ec22009-01-06 11:38:15 -0700160 * typedef dma_filter_fn - callback filter for dma_request_channel
161 * @chan: channel to be reviewed
162 * @filter_param: opaque parameter passed through dma_request_channel
163 *
164 * When this optional parameter is specified in a call to dma_request_channel a
165 * suitable channel is passed to this routine for further dispositioning before
166 * being returned. Where 'suitable' indicates a non-busy channel that
167 * satisfies the given capability mask.
168 */
169typedef enum dma_state_client (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
170
Dan Williams7405f742007-01-02 11:10:43 -0700171typedef void (*dma_async_tx_callback)(void *dma_async_param);
172/**
173 * struct dma_async_tx_descriptor - async transaction descriptor
174 * ---dma generic offload fields---
175 * @cookie: tracking cookie for this transaction, set to -EBUSY if
176 * this tx is sitting on a dependency list
Dan Williams636bdea2008-04-17 20:17:26 -0700177 * @flags: flags to augment operation preparation, control completion, and
178 * communicate status
Dan Williams7405f742007-01-02 11:10:43 -0700179 * @phys: physical address of the descriptor
180 * @tx_list: driver common field for operations that require multiple
181 * descriptors
182 * @chan: target channel for this operation
183 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
Dan Williams7405f742007-01-02 11:10:43 -0700184 * @callback: routine to call after this operation is complete
185 * @callback_param: general parameter to pass to the callback routine
186 * ---async_tx api specific fields---
Dan Williams19242d72008-04-17 20:17:25 -0700187 * @next: at completion submit this descriptor
Dan Williams7405f742007-01-02 11:10:43 -0700188 * @parent: pointer to the next level up in the dependency chain
Dan Williams19242d72008-04-17 20:17:25 -0700189 * @lock: protect the parent and next pointers
Dan Williams7405f742007-01-02 11:10:43 -0700190 */
191struct dma_async_tx_descriptor {
192 dma_cookie_t cookie;
Dan Williams636bdea2008-04-17 20:17:26 -0700193 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
Dan Williams7405f742007-01-02 11:10:43 -0700194 dma_addr_t phys;
195 struct list_head tx_list;
196 struct dma_chan *chan;
197 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
Dan Williams7405f742007-01-02 11:10:43 -0700198 dma_async_tx_callback callback;
199 void *callback_param;
Dan Williams19242d72008-04-17 20:17:25 -0700200 struct dma_async_tx_descriptor *next;
Dan Williams7405f742007-01-02 11:10:43 -0700201 struct dma_async_tx_descriptor *parent;
202 spinlock_t lock;
203};
204
Chris Leechc13c8262006-05-23 17:18:44 -0700205/**
206 * struct dma_device - info on the entity supplying DMA services
207 * @chancnt: how many DMA channels are supported
208 * @channels: the list of struct dma_chan
209 * @global_node: list_head for global dma_device_list
Dan Williams7405f742007-01-02 11:10:43 -0700210 * @cap_mask: one or more dma_capability flags
211 * @max_xor: maximum number of xor sources, 0 if no capability
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700212 * @refcount: reference count
213 * @done: IO completion struct
214 * @dev_id: unique device ID
Dan Williams7405f742007-01-02 11:10:43 -0700215 * @dev: struct device reference for dma mapping api
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700216 * @device_alloc_chan_resources: allocate resources and return the
217 * number of allocated descriptors
218 * @device_free_chan_resources: release DMA channel's resources
Dan Williams7405f742007-01-02 11:10:43 -0700219 * @device_prep_dma_memcpy: prepares a memcpy operation
220 * @device_prep_dma_xor: prepares a xor operation
221 * @device_prep_dma_zero_sum: prepares a zero_sum operation
222 * @device_prep_dma_memset: prepares a memset operation
223 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700224 * @device_prep_slave_sg: prepares a slave dma operation
225 * @device_terminate_all: terminate all pending operations
Dan Williams7405f742007-01-02 11:10:43 -0700226 * @device_issue_pending: push pending transactions to hardware
Chris Leechc13c8262006-05-23 17:18:44 -0700227 */
228struct dma_device {
229
230 unsigned int chancnt;
231 struct list_head channels;
232 struct list_head global_node;
Dan Williams7405f742007-01-02 11:10:43 -0700233 dma_cap_mask_t cap_mask;
234 int max_xor;
Chris Leechc13c8262006-05-23 17:18:44 -0700235
236 struct kref refcount;
237 struct completion done;
238
239 int dev_id;
Dan Williams7405f742007-01-02 11:10:43 -0700240 struct device *dev;
Chris Leechc13c8262006-05-23 17:18:44 -0700241
Dan Williamsaa1e6f12009-01-06 11:38:17 -0700242 int (*device_alloc_chan_resources)(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700243 void (*device_free_chan_resources)(struct dma_chan *chan);
Dan Williams7405f742007-01-02 11:10:43 -0700244
245 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
Dan Williams00367312008-02-02 19:49:57 -0700246 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700247 size_t len, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700248 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
Dan Williams00367312008-02-02 19:49:57 -0700249 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700250 unsigned int src_cnt, size_t len, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700251 struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)(
Dan Williams00367312008-02-02 19:49:57 -0700252 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700253 size_t len, u32 *result, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700254 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
Dan Williams00367312008-02-02 19:49:57 -0700255 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700256 unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700257 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
Dan Williams636bdea2008-04-17 20:17:26 -0700258 struct dma_chan *chan, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700259
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700260 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
261 struct dma_chan *chan, struct scatterlist *sgl,
262 unsigned int sg_len, enum dma_data_direction direction,
263 unsigned long flags);
264 void (*device_terminate_all)(struct dma_chan *chan);
265
Dan Williams7405f742007-01-02 11:10:43 -0700266 enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700267 dma_cookie_t cookie, dma_cookie_t *last,
268 dma_cookie_t *used);
Dan Williams7405f742007-01-02 11:10:43 -0700269 void (*device_issue_pending)(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700270};
271
272/* --- public DMA engine API --- */
273
Dan Williams209b84a2009-01-06 11:38:17 -0700274void dmaengine_get(void);
275void dmaengine_put(void);
Dan Williams7405f742007-01-02 11:10:43 -0700276dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
277 void *dest, void *src, size_t len);
278dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
279 struct page *page, unsigned int offset, void *kdata, size_t len);
280dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700281 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
Dan Williams7405f742007-01-02 11:10:43 -0700282 unsigned int src_off, size_t len);
283void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
284 struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700285
Dan Williams08398752008-07-17 17:59:56 -0700286static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
Dan Williams7405f742007-01-02 11:10:43 -0700287{
Dan Williams636bdea2008-04-17 20:17:26 -0700288 tx->flags |= DMA_CTRL_ACK;
289}
290
Dan Williams08398752008-07-17 17:59:56 -0700291static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
Dan Williams636bdea2008-04-17 20:17:26 -0700292{
Dan Williams08398752008-07-17 17:59:56 -0700293 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
Chris Leechc13c8262006-05-23 17:18:44 -0700294}
295
Dan Williams7405f742007-01-02 11:10:43 -0700296#define first_dma_cap(mask) __first_dma_cap(&(mask))
297static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
298{
299 return min_t(int, DMA_TX_TYPE_END,
300 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
301}
302
303#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
304static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
305{
306 return min_t(int, DMA_TX_TYPE_END,
307 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
308}
309
310#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
311static inline void
312__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
313{
314 set_bit(tx_type, dstp->bits);
315}
316
Dan Williams33df8ca2009-01-06 11:38:15 -0700317#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
318static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
319{
320 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
321}
322
Dan Williams7405f742007-01-02 11:10:43 -0700323#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
324static inline int
325__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
326{
327 return test_bit(tx_type, srcp->bits);
328}
329
330#define for_each_dma_cap_mask(cap, mask) \
331 for ((cap) = first_dma_cap(mask); \
332 (cap) < DMA_TX_TYPE_END; \
333 (cap) = next_dma_cap((cap), (mask)))
334
Chris Leechc13c8262006-05-23 17:18:44 -0700335/**
Dan Williams7405f742007-01-02 11:10:43 -0700336 * dma_async_issue_pending - flush pending transactions to HW
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700337 * @chan: target DMA channel
Chris Leechc13c8262006-05-23 17:18:44 -0700338 *
339 * This allows drivers to push copies to HW in batches,
340 * reducing MMIO writes where possible.
341 */
Dan Williams7405f742007-01-02 11:10:43 -0700342static inline void dma_async_issue_pending(struct dma_chan *chan)
Chris Leechc13c8262006-05-23 17:18:44 -0700343{
Dan Williamsec8670f2008-03-01 07:51:29 -0700344 chan->device->device_issue_pending(chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700345}
346
Dan Williams7405f742007-01-02 11:10:43 -0700347#define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
348
Chris Leechc13c8262006-05-23 17:18:44 -0700349/**
Dan Williams7405f742007-01-02 11:10:43 -0700350 * dma_async_is_tx_complete - poll for transaction completion
Chris Leechc13c8262006-05-23 17:18:44 -0700351 * @chan: DMA channel
352 * @cookie: transaction identifier to check status of
353 * @last: returns last completed cookie, can be NULL
354 * @used: returns last issued cookie, can be NULL
355 *
356 * If @last and @used are passed in, upon return they reflect the driver
357 * internal state and can be used with dma_async_is_complete() to check
358 * the status of multiple cookies without re-checking hardware state.
359 */
Dan Williams7405f742007-01-02 11:10:43 -0700360static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700361 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
362{
Dan Williams7405f742007-01-02 11:10:43 -0700363 return chan->device->device_is_tx_complete(chan, cookie, last, used);
Chris Leechc13c8262006-05-23 17:18:44 -0700364}
365
Dan Williams7405f742007-01-02 11:10:43 -0700366#define dma_async_memcpy_complete(chan, cookie, last, used)\
367 dma_async_is_tx_complete(chan, cookie, last, used)
368
Chris Leechc13c8262006-05-23 17:18:44 -0700369/**
370 * dma_async_is_complete - test a cookie against chan state
371 * @cookie: transaction identifier to test status of
372 * @last_complete: last know completed transaction
373 * @last_used: last cookie value handed out
374 *
375 * dma_async_is_complete() is used in dma_async_memcpy_complete()
Sebastian Siewior8a5703f2008-04-21 22:38:45 +0000376 * the test logic is separated for lightweight testing of multiple cookies
Chris Leechc13c8262006-05-23 17:18:44 -0700377 */
378static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
379 dma_cookie_t last_complete, dma_cookie_t last_used)
380{
381 if (last_complete <= last_used) {
382 if ((cookie <= last_complete) || (cookie > last_used))
383 return DMA_SUCCESS;
384 } else {
385 if ((cookie <= last_complete) && (cookie > last_used))
386 return DMA_SUCCESS;
387 }
388 return DMA_IN_PROGRESS;
389}
390
Dan Williams7405f742007-01-02 11:10:43 -0700391enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
Dan Williams07f22112009-01-05 17:14:31 -0700392#ifdef CONFIG_DMA_ENGINE
393enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
394#else
395static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
396{
397 return DMA_SUCCESS;
398}
399#endif
Chris Leechc13c8262006-05-23 17:18:44 -0700400
401/* --- DMA device --- */
402
403int dma_async_device_register(struct dma_device *device);
404void dma_async_device_unregister(struct dma_device *device);
Dan Williams07f22112009-01-05 17:14:31 -0700405void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
Dan Williamsbec08512009-01-06 11:38:14 -0700406struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
Dan Williams2ba05622009-01-06 11:38:14 -0700407void dma_issue_pending_all(void);
Dan Williams59b5ec22009-01-06 11:38:15 -0700408#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
409struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
410void dma_release_channel(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700411
Chris Leechde5506e2006-05-23 17:50:37 -0700412/* --- Helper iov-locking functions --- */
413
414struct dma_page_list {
Al Virob2ddb902008-03-29 03:09:38 +0000415 char __user *base_address;
Chris Leechde5506e2006-05-23 17:50:37 -0700416 int nr_pages;
417 struct page **pages;
418};
419
420struct dma_pinned_list {
421 int nr_iovecs;
422 struct dma_page_list page_list[0];
423};
424
425struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
426void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
427
428dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
429 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
430dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
431 struct dma_pinned_list *pinned_list, struct page *page,
432 unsigned int offset, size_t len);
433
Chris Leechc13c8262006-05-23 17:18:44 -0700434#endif /* DMAENGINE_H */