blob: 6dd54f1d3ac9874f6679c9fa99b23d10f051956a [file] [log] [blame]
Russell King96f60e32012-08-15 13:59:49 +01001/*
2 * Copyright (C) 2012 Russell King
3 * Rewritten from the dovefb driver, and Armada510 manuals.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/clk.h>
Russell Kingd8c96082014-04-22 11:10:15 +010010#include <linux/component.h>
11#include <linux/of_device.h>
12#include <linux/platform_device.h>
Russell King96f60e32012-08-15 13:59:49 +010013#include <drm/drmP.h>
14#include <drm/drm_crtc_helper.h>
Daniel Vetter3cb9ae42014-10-29 10:03:57 +010015#include <drm/drm_plane_helper.h>
Dave Airliebcd21a42018-01-05 09:43:46 +100016#include <drm/drm_atomic_helper.h>
Russell King96f60e32012-08-15 13:59:49 +010017#include "armada_crtc.h"
18#include "armada_drm.h"
19#include "armada_fb.h"
20#include "armada_gem.h"
21#include "armada_hw.h"
Russell Kingc8a220c2016-05-17 13:51:08 +010022#include "armada_trace.h"
Russell King96f60e32012-08-15 13:59:49 +010023
Russell King96f60e32012-08-15 13:59:49 +010024enum csc_mode {
25 CSC_AUTO = 0,
26 CSC_YUV_CCIR601 = 1,
27 CSC_YUV_CCIR709 = 2,
28 CSC_RGB_COMPUTER = 1,
29 CSC_RGB_STUDIO = 2,
30};
31
Russell King1c914ce2015-07-15 18:11:24 +010032static const uint32_t armada_primary_formats[] = {
33 DRM_FORMAT_UYVY,
34 DRM_FORMAT_YUYV,
35 DRM_FORMAT_VYUY,
36 DRM_FORMAT_YVYU,
37 DRM_FORMAT_ARGB8888,
38 DRM_FORMAT_ABGR8888,
39 DRM_FORMAT_XRGB8888,
40 DRM_FORMAT_XBGR8888,
41 DRM_FORMAT_RGB888,
42 DRM_FORMAT_BGR888,
43 DRM_FORMAT_ARGB1555,
44 DRM_FORMAT_ABGR1555,
45 DRM_FORMAT_RGB565,
46 DRM_FORMAT_BGR565,
47};
48
Russell King96f60e32012-08-15 13:59:49 +010049/*
50 * A note about interlacing. Let's consider HDMI 1920x1080i.
51 * The timing parameters we have from X are:
52 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
53 * 1920 2448 2492 2640 1080 1084 1094 1125
54 * Which get translated to:
55 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
56 * 1920 2448 2492 2640 540 542 547 562
57 *
58 * This is how it is defined by CEA-861-D - line and pixel numbers are
59 * referenced to the rising edge of VSYNC and HSYNC. Total clocks per
60 * line: 2640. The odd frame, the first active line is at line 21, and
61 * the even frame, the first active line is 584.
62 *
63 * LN: 560 561 562 563 567 568 569
64 * DE: ~~~|____________________________//__________________________
65 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
66 * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
67 * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge).
68 *
69 * LN: 1123 1124 1125 1 5 6 7
70 * DE: ~~~|____________________________//__________________________
71 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
72 * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
73 * 23 blanking lines
74 *
75 * The Armada LCD Controller line and pixel numbers are, like X timings,
76 * referenced to the top left of the active frame.
77 *
78 * So, translating these to our LCD controller:
79 * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
80 * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
81 * Note: Vsync front porch remains constant!
82 *
83 * if (odd_frame) {
84 * vtotal = mode->crtc_vtotal + 1;
85 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
86 * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
87 * } else {
88 * vtotal = mode->crtc_vtotal;
89 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
90 * vhorizpos = mode->crtc_hsync_start;
91 * }
92 * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
93 *
94 * So, we need to reprogram these registers on each vsync event:
95 * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
96 *
97 * Note: we do not use the frame done interrupts because these appear
98 * to happen too early, and lead to jitter on the display (presumably
99 * they occur at the end of the last active line, before the vsync back
100 * porch, which we're reprogramming.)
101 */
102
103void
104armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
105{
106 while (regs->offset != ~0) {
107 void __iomem *reg = dcrtc->base + regs->offset;
108 uint32_t val;
109
110 val = regs->mask;
111 if (val != 0)
112 val &= readl_relaxed(reg);
113 writel_relaxed(val | regs->val, reg);
114 ++regs;
115 }
116}
117
118#define dpms_blanked(dpms) ((dpms) != DRM_MODE_DPMS_ON)
119
120static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
121{
122 uint32_t dumb_ctrl;
123
124 dumb_ctrl = dcrtc->cfg_dumb_ctrl;
125
126 if (!dpms_blanked(dcrtc->dpms))
127 dumb_ctrl |= CFG_DUMB_ENA;
128
129 /*
130 * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
131 * be using SPI or GPIO. If we set this to DUMB_BLANK, we will
132 * force LCD_D[23:0] to output blank color, overriding the GPIO or
133 * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode.
134 */
135 if (dpms_blanked(dcrtc->dpms) &&
136 (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
137 dumb_ctrl &= ~DUMB_MASK;
138 dumb_ctrl |= DUMB_BLANK;
139 }
140
141 /*
142 * The documentation doesn't indicate what the normal state of
143 * the sync signals are. Sebastian Hesselbart kindly probed
144 * these signals on his board to determine their state.
145 *
146 * The non-inverted state of the sync signals is active high.
147 * Setting these bits makes the appropriate signal active low.
148 */
149 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
150 dumb_ctrl |= CFG_INV_CSYNC;
151 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
152 dumb_ctrl |= CFG_INV_HSYNC;
153 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
154 dumb_ctrl |= CFG_INV_VSYNC;
155
156 if (dcrtc->dumb_ctrl != dumb_ctrl) {
157 dcrtc->dumb_ctrl = dumb_ctrl;
158 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
159 }
160}
161
Russell Kingf0b24872016-08-16 22:09:11 +0100162void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb,
163 int x, int y)
164{
Russell Kingd6a48962017-12-08 12:16:22 +0000165 const struct drm_format_info *format = fb->format;
166 unsigned int num_planes = format->num_planes;
Russell Kingf0b24872016-08-16 22:09:11 +0100167 u32 addr = drm_fb_obj(fb)->dev_addr;
Russell Kingf0b24872016-08-16 22:09:11 +0100168 int i;
169
170 if (num_planes > 3)
171 num_planes = 3;
172
Russell Kingde0ea9a2017-12-08 12:16:22 +0000173 addrs[0] = addr + fb->offsets[0] + y * fb->pitches[0] +
174 x * format->cpp[0];
175
176 y /= format->vsub;
177 x /= format->hsub;
178
179 for (i = 1; i < num_planes; i++)
Russell Kingf0b24872016-08-16 22:09:11 +0100180 addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] +
Russell Kingd6a48962017-12-08 12:16:22 +0000181 x * format->cpp[i];
Russell Kingf0b24872016-08-16 22:09:11 +0100182 for (; i < 3; i++)
183 addrs[i] = 0;
184}
185
Russell King96f60e32012-08-15 13:59:49 +0100186static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
187 int x, int y, struct armada_regs *regs, bool interlaced)
188{
Russell King96f60e32012-08-15 13:59:49 +0100189 unsigned pitch = fb->pitches[0];
Russell Kingf0b24872016-08-16 22:09:11 +0100190 u32 addrs[3], addr_odd, addr_even;
Russell King96f60e32012-08-15 13:59:49 +0100191 unsigned i = 0;
192
193 DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
Ville Syrjälä272725c2016-12-14 23:32:20 +0200194 pitch, x, y, fb->format->cpp[0] * 8);
Russell King96f60e32012-08-15 13:59:49 +0100195
Russell Kingf0b24872016-08-16 22:09:11 +0100196 armada_drm_plane_calc_addrs(addrs, fb, x, y);
197
198 addr_odd = addr_even = addrs[0];
Russell King96f60e32012-08-15 13:59:49 +0100199
200 if (interlaced) {
201 addr_even += pitch;
202 pitch *= 2;
203 }
204
205 /* write offset, base, and pitch */
206 armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
207 armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
208 armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
209
210 return i;
211}
212
Russell King2839d452017-07-07 15:56:20 +0100213static void armada_drm_plane_work_call(struct armada_crtc *dcrtc,
214 struct armada_plane_work *work,
215 void (*fn)(struct armada_crtc *, struct armada_plane_work *))
216{
217 struct armada_plane *dplane = drm_to_armada_plane(work->plane);
Russell Kingd9241552017-07-08 10:22:25 +0100218 struct drm_pending_vblank_event *event;
219 struct drm_framebuffer *fb;
Russell King2839d452017-07-07 15:56:20 +0100220
221 if (fn)
222 fn(dcrtc, work);
223 drm_crtc_vblank_put(&dcrtc->crtc);
224
Russell Kingd9241552017-07-08 10:22:25 +0100225 event = work->event;
226 fb = work->old_fb;
Russell Kingeb19be52017-07-08 10:16:53 +0100227 if (event || fb) {
228 struct drm_device *dev = dcrtc->crtc.dev;
229 unsigned long flags;
230
231 spin_lock_irqsave(&dev->event_lock, flags);
232 if (event)
233 drm_crtc_send_vblank_event(&dcrtc->crtc, event);
234 if (fb)
235 __armada_drm_queue_unref_work(dev, fb);
236 spin_unlock_irqrestore(&dev->event_lock, flags);
237 }
Russell Kingb972a802017-07-08 10:16:52 +0100238
Russell Kingd9241552017-07-08 10:22:25 +0100239 if (work->need_kfree)
240 kfree(work);
241
Russell King2839d452017-07-07 15:56:20 +0100242 wake_up(&dplane->frame_wait);
243}
244
Russell King4b5dda82015-08-06 16:37:18 +0100245static void armada_drm_plane_work_run(struct armada_crtc *dcrtc,
Russell Kingec6fb152016-07-25 15:16:11 +0100246 struct drm_plane *plane)
Russell King4b5dda82015-08-06 16:37:18 +0100247{
Russell Kingec6fb152016-07-25 15:16:11 +0100248 struct armada_plane *dplane = drm_to_armada_plane(plane);
249 struct armada_plane_work *work = xchg(&dplane->work, NULL);
Russell King4b5dda82015-08-06 16:37:18 +0100250
251 /* Handle any pending frame work. */
Russell King2839d452017-07-07 15:56:20 +0100252 if (work)
253 armada_drm_plane_work_call(dcrtc, work, work->fn);
Russell King4b5dda82015-08-06 16:37:18 +0100254}
255
256int armada_drm_plane_work_queue(struct armada_crtc *dcrtc,
Russell Kingeaab0132017-07-07 15:55:53 +0100257 struct armada_plane_work *work)
Russell King4b5dda82015-08-06 16:37:18 +0100258{
Russell Kingeaab0132017-07-07 15:55:53 +0100259 struct armada_plane *plane = drm_to_armada_plane(work->plane);
Russell King4b5dda82015-08-06 16:37:18 +0100260 int ret;
261
Gustavo Padovanaccbaf62016-06-06 11:41:40 -0300262 ret = drm_crtc_vblank_get(&dcrtc->crtc);
Russell Kingc93dfdc2017-07-08 10:22:23 +0100263 if (ret)
Russell King4b5dda82015-08-06 16:37:18 +0100264 return ret;
Russell King4b5dda82015-08-06 16:37:18 +0100265
266 ret = cmpxchg(&plane->work, NULL, work) ? -EBUSY : 0;
267 if (ret)
Gustavo Padovanaccbaf62016-06-06 11:41:40 -0300268 drm_crtc_vblank_put(&dcrtc->crtc);
Russell King4b5dda82015-08-06 16:37:18 +0100269
270 return ret;
271}
272
273int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout)
274{
275 return wait_event_timeout(plane->frame_wait, !plane->work, timeout);
276}
277
Russell Kingd3b84212017-07-07 15:55:40 +0100278void armada_drm_plane_work_cancel(struct armada_crtc *dcrtc,
279 struct armada_plane *dplane)
Russell King7c8f7e12015-06-29 17:52:16 +0100280{
Russell Kingd3b84212017-07-07 15:55:40 +0100281 struct armada_plane_work *work = xchg(&dplane->work, NULL);
Russell King7c8f7e12015-06-29 17:52:16 +0100282
Russell King4a8506d2015-08-07 09:33:05 +0100283 if (work)
Russell King2839d452017-07-07 15:56:20 +0100284 armada_drm_plane_work_call(dcrtc, work, work->cancel);
Russell King96f60e32012-08-15 13:59:49 +0100285}
286
Russell King709ffd82015-07-15 18:09:38 +0100287static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc,
Russell King65724a12017-07-07 15:56:24 +0100288 struct armada_plane_work *work)
Russell King96f60e32012-08-15 13:59:49 +0100289{
Russell King709ffd82015-07-15 18:09:38 +0100290 unsigned long flags;
Russell King96f60e32012-08-15 13:59:49 +0100291
Russell King709ffd82015-07-15 18:09:38 +0100292 spin_lock_irqsave(&dcrtc->irq_lock, flags);
Russell Kingeaa66272017-07-08 10:22:10 +0100293 armada_drm_crtc_update_regs(dcrtc, work->regs);
Russell King709ffd82015-07-15 18:09:38 +0100294 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
Russell King65724a12017-07-07 15:56:24 +0100295}
Russell King96f60e32012-08-15 13:59:49 +0100296
Russell King890ca8d2017-07-08 10:22:27 +0100297static void armada_drm_crtc_complete_disable_work(struct armada_crtc *dcrtc,
298 struct armada_plane_work *work)
299{
300 unsigned long flags;
Russell King96f60e32012-08-15 13:59:49 +0100301
Russell King890ca8d2017-07-08 10:22:27 +0100302 if (dcrtc->plane == work->plane)
303 dcrtc->plane = NULL;
304
305 spin_lock_irqsave(&dcrtc->irq_lock, flags);
306 armada_drm_crtc_update_regs(dcrtc, work->regs);
307 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
308}
309
Russell Kingeaa66272017-07-08 10:22:10 +0100310static struct armada_plane_work *
311armada_drm_crtc_alloc_plane_work(struct drm_plane *plane)
Russell King901bb882017-07-07 15:55:45 +0100312{
Russell Kingeaa66272017-07-08 10:22:10 +0100313 struct armada_plane_work *work;
Russell King901bb882017-07-07 15:55:45 +0100314 int i = 0;
315
316 work = kzalloc(sizeof(*work), GFP_KERNEL);
317 if (!work)
318 return NULL;
319
Russell Kingeaa66272017-07-08 10:22:10 +0100320 work->plane = plane;
321 work->fn = armada_drm_crtc_complete_frame_work;
Russell Kingd9241552017-07-08 10:22:25 +0100322 work->need_kfree = true;
Russell King901bb882017-07-07 15:55:45 +0100323 armada_reg_queue_end(work->regs, i);
324
325 return work;
Russell King96f60e32012-08-15 13:59:49 +0100326}
327
328static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
329 struct drm_framebuffer *fb, bool force)
330{
Russell Kingeaa66272017-07-08 10:22:10 +0100331 struct armada_plane_work *work;
Russell King96f60e32012-08-15 13:59:49 +0100332
333 if (!fb)
334 return;
335
336 if (force) {
337 /* Display is disabled, so just drop the old fb */
Haneen Mohammeda52ff2a2017-09-20 12:57:16 -0600338 drm_framebuffer_put(fb);
Russell King96f60e32012-08-15 13:59:49 +0100339 return;
340 }
341
Russell Kingeaa66272017-07-08 10:22:10 +0100342 work = armada_drm_crtc_alloc_plane_work(dcrtc->crtc.primary);
Russell King96f60e32012-08-15 13:59:49 +0100343 if (work) {
Russell King96f60e32012-08-15 13:59:49 +0100344 work->old_fb = fb;
Russell King96f60e32012-08-15 13:59:49 +0100345
Russell Kingeaa66272017-07-08 10:22:10 +0100346 if (armada_drm_plane_work_queue(dcrtc, work) == 0)
Russell King96f60e32012-08-15 13:59:49 +0100347 return;
348
349 kfree(work);
350 }
351
352 /*
353 * Oops - just drop the reference immediately and hope for
354 * the best. The worst that will happen is the buffer gets
355 * reused before it has finished being displayed.
356 */
Haneen Mohammeda52ff2a2017-09-20 12:57:16 -0600357 drm_framebuffer_put(fb);
Russell King96f60e32012-08-15 13:59:49 +0100358}
359
360static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
361{
Russell King96f60e32012-08-15 13:59:49 +0100362 /*
363 * Tell the DRM core that vblank IRQs aren't going to happen for
364 * a while. This cleans up any pending vblank events for us.
365 */
Russell King178e5612014-10-11 23:57:04 +0100366 drm_crtc_vblank_off(&dcrtc->crtc);
Russell Kingec6fb152016-07-25 15:16:11 +0100367 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
Russell King96f60e32012-08-15 13:59:49 +0100368}
369
Russell King96f60e32012-08-15 13:59:49 +0100370/* The mode_config.mutex will be held for this call */
371static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
372{
373 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
374
Russell Kingea908ba2016-10-04 22:19:57 +0100375 if (dpms_blanked(dcrtc->dpms) != dpms_blanked(dpms)) {
Russell King96f60e32012-08-15 13:59:49 +0100376 if (dpms_blanked(dpms))
377 armada_drm_vblank_off(dcrtc);
Russell Kingea908ba2016-10-04 22:19:57 +0100378 else if (!IS_ERR(dcrtc->clk))
379 WARN_ON(clk_prepare_enable(dcrtc->clk));
380 dcrtc->dpms = dpms;
381 armada_drm_crtc_update(dcrtc);
382 if (!dpms_blanked(dpms))
Russell King178e5612014-10-11 23:57:04 +0100383 drm_crtc_vblank_on(&dcrtc->crtc);
Russell Kingea908ba2016-10-04 22:19:57 +0100384 else if (!IS_ERR(dcrtc->clk))
385 clk_disable_unprepare(dcrtc->clk);
386 } else if (dcrtc->dpms != dpms) {
387 dcrtc->dpms = dpms;
Russell King96f60e32012-08-15 13:59:49 +0100388 }
389}
390
391/*
392 * Prepare for a mode set. Turn off overlay to ensure that we don't end
393 * up with the overlay size being bigger than the active screen size.
394 * We rely upon X refreshing this state after the mode set has completed.
395 *
396 * The mode_config.mutex will be held for this call
397 */
398static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
399{
400 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
401 struct drm_plane *plane;
Russell Kingf9a13bb2018-07-30 11:52:34 +0100402 u32 val;
Russell King96f60e32012-08-15 13:59:49 +0100403
404 /*
405 * If we have an overlay plane associated with this CRTC, disable
406 * it before the modeset to avoid its coordinates being outside
Russell Kingf8e14062015-06-29 17:52:42 +0100407 * the new mode parameters.
Russell King96f60e32012-08-15 13:59:49 +0100408 */
409 plane = dcrtc->plane;
Russell King890ca8d2017-07-08 10:22:27 +0100410 if (plane) {
Russell Kingf8e14062015-06-29 17:52:42 +0100411 drm_plane_force_disable(plane);
Russell King890ca8d2017-07-08 10:22:27 +0100412 WARN_ON(!armada_drm_plane_work_wait(drm_to_armada_plane(plane),
413 HZ));
414 }
Russell Kingf9a13bb2018-07-30 11:52:34 +0100415
416 /* Wait for pending flips to complete */
417 armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
418 MAX_SCHEDULE_TIMEOUT);
419
420 drm_crtc_vblank_off(crtc);
421
422 val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
423 if (val != dcrtc->dumb_ctrl) {
424 dcrtc->dumb_ctrl = val;
425 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
426 }
Russell King96f60e32012-08-15 13:59:49 +0100427}
428
429/* The mode_config.mutex will be held for this call */
430static void armada_drm_crtc_commit(struct drm_crtc *crtc)
431{
432 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
433
Russell Kingf9a13bb2018-07-30 11:52:34 +0100434 dcrtc->dpms = DRM_MODE_DPMS_ON;
435 armada_drm_crtc_update(dcrtc);
436 drm_crtc_vblank_on(crtc);
437
438 if (dcrtc->old_modeset_fb)
439 armada_drm_crtc_finish_fb(dcrtc, dcrtc->old_modeset_fb, false);
Russell King96f60e32012-08-15 13:59:49 +0100440}
441
442/* The mode_config.mutex will be held for this call */
443static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
444 const struct drm_display_mode *mode, struct drm_display_mode *adj)
445{
Russell King96f60e32012-08-15 13:59:49 +0100446 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
447 int ret;
448
449 /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
Russell King42e62ba2014-04-22 15:24:03 +0100450 if (!dcrtc->variant->has_spu_adv_reg &&
Russell King96f60e32012-08-15 13:59:49 +0100451 adj->flags & DRM_MODE_FLAG_INTERLACE)
452 return false;
453
454 /* Check whether the display mode is possible */
Russell King42e62ba2014-04-22 15:24:03 +0100455 ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
Russell King96f60e32012-08-15 13:59:49 +0100456 if (ret)
457 return false;
458
459 return true;
460}
461
Shawn Guo5922a7d2017-02-07 17:16:18 +0800462/* These are locked by dev->vbl_lock */
463static void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
464{
465 if (dcrtc->irq_ena & mask) {
466 dcrtc->irq_ena &= ~mask;
467 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
468 }
469}
470
471static void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
472{
473 if ((dcrtc->irq_ena & mask) != mask) {
474 dcrtc->irq_ena |= mask;
475 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
476 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
477 writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
478 }
479}
480
Russell Kinge5d9ddf2014-04-26 15:19:38 +0100481static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
Russell King96f60e32012-08-15 13:59:49 +0100482{
Russell King96f60e32012-08-15 13:59:49 +0100483 void __iomem *base = dcrtc->base;
Russell King4a8506d2015-08-07 09:33:05 +0100484 struct drm_plane *ovl_plane;
Russell King96f60e32012-08-15 13:59:49 +0100485
486 if (stat & DMA_FF_UNDERFLOW)
487 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
488 if (stat & GRA_FF_UNDERFLOW)
489 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
490
491 if (stat & VSYNC_IRQ)
Gustavo Padovan0ac28c52016-07-04 21:04:48 -0300492 drm_crtc_handle_vblank(&dcrtc->crtc);
Russell King96f60e32012-08-15 13:59:49 +0100493
Russell King4a8506d2015-08-07 09:33:05 +0100494 ovl_plane = dcrtc->plane;
Russell Kingec6fb152016-07-25 15:16:11 +0100495 if (ovl_plane)
496 armada_drm_plane_work_run(dcrtc, ovl_plane);
Russell King96f60e32012-08-15 13:59:49 +0100497
Russell Kinga3f6a182017-07-08 10:16:48 +0100498 spin_lock(&dcrtc->irq_lock);
Russell King96f60e32012-08-15 13:59:49 +0100499 if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
500 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
501 uint32_t val;
502
503 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
504 writel_relaxed(dcrtc->v[i].spu_v_h_total,
505 base + LCD_SPUT_V_H_TOTAL);
506
507 val = readl_relaxed(base + LCD_SPU_ADV_REG);
508 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
509 val |= dcrtc->v[i].spu_adv_reg;
Russell King662af0d2013-05-19 10:55:17 +0100510 writel_relaxed(val, base + LCD_SPU_ADV_REG);
Russell King96f60e32012-08-15 13:59:49 +0100511 }
Russell King662af0d2013-05-19 10:55:17 +0100512
513 if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
514 writel_relaxed(dcrtc->cursor_hw_pos,
515 base + LCD_SPU_HWC_OVSA_HPXL_VLN);
516 writel_relaxed(dcrtc->cursor_hw_sz,
517 base + LCD_SPU_HWC_HPXL_VLN);
518 armada_updatel(CFG_HWC_ENA,
519 CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
520 base + LCD_SPU_DMA_CTRL0);
521 dcrtc->cursor_update = false;
522 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
523 }
524
Russell King96f60e32012-08-15 13:59:49 +0100525 spin_unlock(&dcrtc->irq_lock);
526
Russell Kingec6fb152016-07-25 15:16:11 +0100527 if (stat & GRA_FRAME_IRQ)
528 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
Russell King96f60e32012-08-15 13:59:49 +0100529}
530
Russell Kinge5d9ddf2014-04-26 15:19:38 +0100531static irqreturn_t armada_drm_irq(int irq, void *arg)
532{
533 struct armada_crtc *dcrtc = arg;
534 u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
535
536 /*
Russell King92298c12018-06-26 17:06:06 +0100537 * Reading the ISR appears to clear bits provided CLEAN_SPU_IRQ_ISR
538 * is set. Writing has some other effect to acknowledge the IRQ -
539 * without this, we only get a single IRQ.
Russell Kinge5d9ddf2014-04-26 15:19:38 +0100540 */
541 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
542
Russell Kingc8a220c2016-05-17 13:51:08 +0100543 trace_armada_drm_irq(&dcrtc->crtc, stat);
544
Russell Kinge5d9ddf2014-04-26 15:19:38 +0100545 /* Mask out those interrupts we haven't enabled */
546 v = stat & dcrtc->irq_ena;
547
548 if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
549 armada_drm_crtc_irq(dcrtc, stat);
550 return IRQ_HANDLED;
551 }
552 return IRQ_NONE;
553}
554
Russell King96f60e32012-08-15 13:59:49 +0100555static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
556{
557 struct drm_display_mode *adj = &dcrtc->crtc.mode;
558 uint32_t val = 0;
559
560 if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
561 val |= CFG_CSC_YUV_CCIR709;
562 if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
563 val |= CFG_CSC_RGB_STUDIO;
564
565 /*
566 * In auto mode, set the colorimetry, based upon the HDMI spec.
567 * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
568 * ITU601. It may be more appropriate to set this depending on
569 * the source - but what if the graphic frame is YUV and the
570 * video frame is RGB?
571 */
572 if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
573 !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
574 (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
575 if (dcrtc->csc_yuv_mode == CSC_AUTO)
576 val |= CFG_CSC_YUV_CCIR709;
577 }
578
579 /*
580 * We assume we're connected to a TV-like device, so the YUV->RGB
581 * conversion should produce a limited range. We should set this
582 * depending on the connectors attached to this CRTC, and what
583 * kind of device they report being connected.
584 */
585 if (dcrtc->csc_rgb_mode == CSC_AUTO)
586 val |= CFG_CSC_RGB_STUDIO;
587
588 return val;
589}
590
Russell King11df53d2017-07-08 10:22:35 +0100591static void armada_drm_gra_plane_regs(struct armada_regs *regs,
592 struct drm_framebuffer *fb, struct armada_plane_state *state,
593 int x, int y, bool interlaced)
Russell King37af35c2016-08-16 22:09:09 +0100594{
Russell King11df53d2017-07-08 10:22:35 +0100595 unsigned int i;
Russell King2925db02016-08-16 22:09:10 +0100596 u32 ctrl0;
Russell King37af35c2016-08-16 22:09:09 +0100597
Russell King11df53d2017-07-08 10:22:35 +0100598 i = armada_drm_crtc_calc_fb(fb, x, y, regs, interlaced);
Russell King2925db02016-08-16 22:09:10 +0100599 armada_reg_queue_set(regs, i, state->dst_yx, LCD_SPU_GRA_OVSA_HPXL_VLN);
Russell King37af35c2016-08-16 22:09:09 +0100600 armada_reg_queue_set(regs, i, state->src_hw, LCD_SPU_GRA_HPXL_VLN);
601 armada_reg_queue_set(regs, i, state->dst_hw, LCD_SPU_GZM_HPXL_VLN);
602
603 ctrl0 = state->ctrl0;
604 if (interlaced)
605 ctrl0 |= CFG_GRA_FTOGGLE;
606
607 armada_reg_queue_mod(regs, i, ctrl0, CFG_GRAFORMAT |
608 CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
609 CFG_SWAPYU | CFG_YUV2RGB) |
Russell King73c51ab2017-07-08 10:22:19 +0100610 CFG_PALETTE_ENA | CFG_GRA_FTOGGLE |
611 CFG_GRA_HSMOOTH | CFG_GRA_ENA,
Russell King37af35c2016-08-16 22:09:09 +0100612 LCD_SPU_DMA_CTRL0);
613 armada_reg_queue_end(regs, i);
Russell King11df53d2017-07-08 10:22:35 +0100614}
615
Russell Kingcfd1b632018-07-30 11:52:34 +0100616static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
617 struct drm_framebuffer *old_fb);
Russell King37af35c2016-08-16 22:09:09 +0100618
Russell King96f60e32012-08-15 13:59:49 +0100619/* The mode_config.mutex will be held for this call */
620static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
621 struct drm_display_mode *mode, struct drm_display_mode *adj,
622 int x, int y, struct drm_framebuffer *old_fb)
623{
Russell King96f60e32012-08-15 13:59:49 +0100624 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
625 struct armada_regs regs[17];
626 uint32_t lm, rm, tm, bm, val, sclk;
627 unsigned long flags;
628 unsigned i;
629 bool interlaced;
630
Russell Kingcfd1b632018-07-30 11:52:34 +0100631 /* Take a reference on the old fb for armada_drm_crtc_commit() */
632 if (old_fb)
633 drm_framebuffer_get(old_fb);
Russell Kingf9a13bb2018-07-30 11:52:34 +0100634 dcrtc->old_modeset_fb = old_fb;
Russell King96f60e32012-08-15 13:59:49 +0100635
636 interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
637
Russell King37af35c2016-08-16 22:09:09 +0100638 i = 0;
Russell King96f60e32012-08-15 13:59:49 +0100639 rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
640 lm = adj->crtc_htotal - adj->crtc_hsync_end;
641 bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
642 tm = adj->crtc_vtotal - adj->crtc_vsync_end;
643
644 DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
645 adj->crtc_hdisplay,
646 adj->crtc_hsync_start,
647 adj->crtc_hsync_end,
648 adj->crtc_htotal, lm, rm);
649 DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
650 adj->crtc_vdisplay,
651 adj->crtc_vsync_start,
652 adj->crtc_vsync_end,
653 adj->crtc_vtotal, tm, bm);
654
Russell Kinge0ac5e92015-06-29 18:01:38 +0100655 /*
656 * If we are blanked, we would have disabled the clock. Re-enable
657 * it so that compute_clock() does the right thing.
658 */
659 if (!IS_ERR(dcrtc->clk) && dpms_blanked(dcrtc->dpms))
660 WARN_ON(clk_prepare_enable(dcrtc->clk));
661
Russell King96f60e32012-08-15 13:59:49 +0100662 /* Now compute the divider for real */
Russell King42e62ba2014-04-22 15:24:03 +0100663 dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
Russell King96f60e32012-08-15 13:59:49 +0100664
Russell King96f60e32012-08-15 13:59:49 +0100665 armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
666
667 if (interlaced ^ dcrtc->interlaced) {
668 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
Gustavo Padovanaccbaf62016-06-06 11:41:40 -0300669 drm_crtc_vblank_get(&dcrtc->crtc);
Russell King96f60e32012-08-15 13:59:49 +0100670 else
Gustavo Padovanaccbaf62016-06-06 11:41:40 -0300671 drm_crtc_vblank_put(&dcrtc->crtc);
Russell King96f60e32012-08-15 13:59:49 +0100672 dcrtc->interlaced = interlaced;
673 }
674
675 spin_lock_irqsave(&dcrtc->irq_lock, flags);
676
677 /* Even interlaced/progressive frame */
678 dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
679 adj->crtc_htotal;
680 dcrtc->v[1].spu_v_porch = tm << 16 | bm;
681 val = adj->crtc_hsync_start;
Russell King662af0d2013-05-19 10:55:17 +0100682 dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
Russell King42e62ba2014-04-22 15:24:03 +0100683 dcrtc->variant->spu_adv_reg;
Russell King96f60e32012-08-15 13:59:49 +0100684
685 if (interlaced) {
686 /* Odd interlaced frame */
687 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
688 (1 << 16);
689 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
690 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
Russell King662af0d2013-05-19 10:55:17 +0100691 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
Russell King42e62ba2014-04-22 15:24:03 +0100692 dcrtc->variant->spu_adv_reg;
Russell King96f60e32012-08-15 13:59:49 +0100693 } else {
694 dcrtc->v[0] = dcrtc->v[1];
695 }
696
697 val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
698
699 armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
Russell King96f60e32012-08-15 13:59:49 +0100700 armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
701 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
702 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
703 LCD_SPUT_V_H_TOTAL);
704
Russell King42e62ba2014-04-22 15:24:03 +0100705 if (dcrtc->variant->has_spu_adv_reg) {
Russell King96f60e32012-08-15 13:59:49 +0100706 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
707 ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
708 ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
Russell King662af0d2013-05-19 10:55:17 +0100709 }
Russell King96f60e32012-08-15 13:59:49 +0100710
Russell King96f60e32012-08-15 13:59:49 +0100711 val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
712 armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
713
714 val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
715 armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
716 armada_reg_queue_end(regs, i);
717
718 armada_drm_crtc_update_regs(dcrtc, regs);
719 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
720
Russell Kingcfd1b632018-07-30 11:52:34 +0100721 return armada_drm_crtc_mode_set_base(crtc, x, y, old_fb);
Russell King96f60e32012-08-15 13:59:49 +0100722}
723
Russell Kingcfd1b632018-07-30 11:52:34 +0100724static int armada_drm_do_primary_update(struct drm_plane *plane,
725 struct drm_plane_state *state, struct drm_framebuffer *old_fb);
726
Russell King96f60e32012-08-15 13:59:49 +0100727/* The mode_config.mutex will be held for this call */
728static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
729 struct drm_framebuffer *old_fb)
730{
Russell Kingcfd1b632018-07-30 11:52:34 +0100731 struct drm_plane_state state = {
732 .plane = crtc->primary,
733 .crtc = crtc,
734 .fb = crtc->primary->fb,
735 .crtc_x = 0,
736 .crtc_y = 0,
737 .crtc_w = crtc->mode.hdisplay,
738 .crtc_h = crtc->mode.vdisplay,
739 .src_x = x << 16,
740 .src_y = y << 16,
741 .src_w = crtc->mode.hdisplay << 16,
742 .src_h = crtc->mode.vdisplay << 16,
743 .rotation = DRM_MODE_ROTATE_0,
744 };
Russell King96f60e32012-08-15 13:59:49 +0100745
Russell Kingcfd1b632018-07-30 11:52:34 +0100746 armada_drm_do_primary_update(crtc->primary, &state, old_fb);
Russell King96f60e32012-08-15 13:59:49 +0100747
748 return 0;
749}
750
Russell King96f60e32012-08-15 13:59:49 +0100751/* The mode_config.mutex will be held for this call */
752static void armada_drm_crtc_disable(struct drm_crtc *crtc)
753{
Russell King96f60e32012-08-15 13:59:49 +0100754 armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
Russell King28b30432017-07-08 10:16:40 +0100755
756 /* Disable our primary plane when we disable the CRTC. */
757 crtc->primary->funcs->disable_plane(crtc->primary, NULL);
Russell King96f60e32012-08-15 13:59:49 +0100758}
759
760static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
761 .dpms = armada_drm_crtc_dpms,
762 .prepare = armada_drm_crtc_prepare,
763 .commit = armada_drm_crtc_commit,
764 .mode_fixup = armada_drm_crtc_mode_fixup,
765 .mode_set = armada_drm_crtc_mode_set,
766 .mode_set_base = armada_drm_crtc_mode_set_base,
Russell King96f60e32012-08-15 13:59:49 +0100767 .disable = armada_drm_crtc_disable,
768};
769
Russell King662af0d2013-05-19 10:55:17 +0100770static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
771 unsigned stride, unsigned width, unsigned height)
772{
773 uint32_t addr;
774 unsigned y;
775
776 addr = SRAM_HWC32_RAM1;
777 for (y = 0; y < height; y++) {
778 uint32_t *p = &pix[y * stride];
779 unsigned x;
780
781 for (x = 0; x < width; x++, p++) {
782 uint32_t val = *p;
783
784 val = (val & 0xff00ff00) |
785 (val & 0x000000ff) << 16 |
786 (val & 0x00ff0000) >> 16;
787
788 writel_relaxed(val,
789 base + LCD_SPU_SRAM_WRDAT);
790 writel_relaxed(addr | SRAM_WRITE,
791 base + LCD_SPU_SRAM_CTRL);
Russell Kingc39b0692014-04-07 12:00:17 +0100792 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
Russell King662af0d2013-05-19 10:55:17 +0100793 addr += 1;
794 if ((addr & 0x00ff) == 0)
795 addr += 0xf00;
796 if ((addr & 0x30ff) == 0)
797 addr = SRAM_HWC32_RAM2;
798 }
799 }
800}
801
802static void armada_drm_crtc_cursor_tran(void __iomem *base)
803{
804 unsigned addr;
805
806 for (addr = 0; addr < 256; addr++) {
807 /* write the default value */
808 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
809 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
810 base + LCD_SPU_SRAM_CTRL);
811 }
812}
813
814static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
815{
816 uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
817 uint32_t yoff, yscr, h = dcrtc->cursor_h;
818 uint32_t para1;
819
820 /*
821 * Calculate the visible width and height of the cursor,
822 * screen position, and the position in the cursor bitmap.
823 */
824 if (dcrtc->cursor_x < 0) {
825 xoff = -dcrtc->cursor_x;
826 xscr = 0;
827 w -= min(xoff, w);
828 } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
829 xoff = 0;
830 xscr = dcrtc->cursor_x;
831 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
832 } else {
833 xoff = 0;
834 xscr = dcrtc->cursor_x;
835 }
836
837 if (dcrtc->cursor_y < 0) {
838 yoff = -dcrtc->cursor_y;
839 yscr = 0;
840 h -= min(yoff, h);
841 } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
842 yoff = 0;
843 yscr = dcrtc->cursor_y;
844 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
845 } else {
846 yoff = 0;
847 yscr = dcrtc->cursor_y;
848 }
849
850 /* On interlaced modes, the vertical cursor size must be halved */
851 s = dcrtc->cursor_w;
852 if (dcrtc->interlaced) {
853 s *= 2;
854 yscr /= 2;
855 h /= 2;
856 }
857
858 if (!dcrtc->cursor_obj || !h || !w) {
859 spin_lock_irq(&dcrtc->irq_lock);
860 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
861 dcrtc->cursor_update = false;
862 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
863 spin_unlock_irq(&dcrtc->irq_lock);
864 return 0;
865 }
866
Russell King214612f2017-07-08 10:22:15 +0100867 spin_lock_irq(&dcrtc->irq_lock);
Russell King662af0d2013-05-19 10:55:17 +0100868 para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
869 armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
870 dcrtc->base + LCD_SPU_SRAM_PARA1);
Russell King214612f2017-07-08 10:22:15 +0100871 spin_unlock_irq(&dcrtc->irq_lock);
Russell King662af0d2013-05-19 10:55:17 +0100872
873 /*
874 * Initialize the transparency if the SRAM was powered down.
875 * We must also reload the cursor data as well.
876 */
877 if (!(para1 & CFG_CSB_256x32)) {
878 armada_drm_crtc_cursor_tran(dcrtc->base);
879 reload = true;
880 }
881
882 if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
883 spin_lock_irq(&dcrtc->irq_lock);
884 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
885 dcrtc->cursor_update = false;
886 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
887 spin_unlock_irq(&dcrtc->irq_lock);
888 reload = true;
889 }
890 if (reload) {
891 struct armada_gem_object *obj = dcrtc->cursor_obj;
892 uint32_t *pix;
893 /* Set the top-left corner of the cursor image */
894 pix = obj->addr;
895 pix += yoff * s + xoff;
896 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
897 }
898
899 /* Reload the cursor position, size and enable in the IRQ handler */
900 spin_lock_irq(&dcrtc->irq_lock);
901 dcrtc->cursor_hw_pos = yscr << 16 | xscr;
902 dcrtc->cursor_hw_sz = h << 16 | w;
903 dcrtc->cursor_update = true;
904 armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
905 spin_unlock_irq(&dcrtc->irq_lock);
906
907 return 0;
908}
909
910static void cursor_update(void *data)
911{
912 armada_drm_crtc_cursor_update(data, true);
913}
914
915static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
916 struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
917{
Russell King662af0d2013-05-19 10:55:17 +0100918 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
Russell King662af0d2013-05-19 10:55:17 +0100919 struct armada_gem_object *obj = NULL;
920 int ret;
921
922 /* If no cursor support, replicate drm's return value */
Russell King42e62ba2014-04-22 15:24:03 +0100923 if (!dcrtc->variant->has_spu_adv_reg)
Russell King662af0d2013-05-19 10:55:17 +0100924 return -ENXIO;
925
926 if (handle && w > 0 && h > 0) {
927 /* maximum size is 64x32 or 32x64 */
928 if (w > 64 || h > 64 || (w > 32 && h > 32))
929 return -ENOMEM;
930
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100931 obj = armada_gem_object_lookup(file, handle);
Russell King662af0d2013-05-19 10:55:17 +0100932 if (!obj)
933 return -ENOENT;
934
935 /* Must be a kernel-mapped object */
936 if (!obj->addr) {
Haneen Mohammed4c3cf372017-09-20 12:54:48 -0600937 drm_gem_object_put_unlocked(&obj->obj);
Russell King662af0d2013-05-19 10:55:17 +0100938 return -EINVAL;
939 }
940
941 if (obj->obj.size < w * h * 4) {
942 DRM_ERROR("buffer is too small\n");
Haneen Mohammed4c3cf372017-09-20 12:54:48 -0600943 drm_gem_object_put_unlocked(&obj->obj);
Russell King662af0d2013-05-19 10:55:17 +0100944 return -ENOMEM;
945 }
946 }
947
Russell King662af0d2013-05-19 10:55:17 +0100948 if (dcrtc->cursor_obj) {
949 dcrtc->cursor_obj->update = NULL;
950 dcrtc->cursor_obj->update_data = NULL;
Haneen Mohammed4c3cf372017-09-20 12:54:48 -0600951 drm_gem_object_put_unlocked(&dcrtc->cursor_obj->obj);
Russell King662af0d2013-05-19 10:55:17 +0100952 }
953 dcrtc->cursor_obj = obj;
954 dcrtc->cursor_w = w;
955 dcrtc->cursor_h = h;
956 ret = armada_drm_crtc_cursor_update(dcrtc, true);
957 if (obj) {
958 obj->update_data = dcrtc;
959 obj->update = cursor_update;
960 }
Russell King662af0d2013-05-19 10:55:17 +0100961
962 return ret;
963}
964
965static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
966{
Russell King662af0d2013-05-19 10:55:17 +0100967 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
Russell King662af0d2013-05-19 10:55:17 +0100968 int ret;
969
970 /* If no cursor support, replicate drm's return value */
Russell King42e62ba2014-04-22 15:24:03 +0100971 if (!dcrtc->variant->has_spu_adv_reg)
Russell King662af0d2013-05-19 10:55:17 +0100972 return -EFAULT;
973
Russell King662af0d2013-05-19 10:55:17 +0100974 dcrtc->cursor_x = x;
975 dcrtc->cursor_y = y;
976 ret = armada_drm_crtc_cursor_update(dcrtc, false);
Russell King662af0d2013-05-19 10:55:17 +0100977
978 return ret;
979}
980
Russell King96f60e32012-08-15 13:59:49 +0100981static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
982{
983 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
984 struct armada_private *priv = crtc->dev->dev_private;
985
Russell King662af0d2013-05-19 10:55:17 +0100986 if (dcrtc->cursor_obj)
Haneen Mohammed4c3cf372017-09-20 12:54:48 -0600987 drm_gem_object_put_unlocked(&dcrtc->cursor_obj->obj);
Russell King662af0d2013-05-19 10:55:17 +0100988
Russell King96f60e32012-08-15 13:59:49 +0100989 priv->dcrtc[dcrtc->num] = NULL;
990 drm_crtc_cleanup(&dcrtc->crtc);
991
992 if (!IS_ERR(dcrtc->clk))
993 clk_disable_unprepare(dcrtc->clk);
994
Russell Kinge5d9ddf2014-04-26 15:19:38 +0100995 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
996
Russell King9611cb92014-06-15 11:21:23 +0100997 of_node_put(dcrtc->crtc.port);
998
Russell King96f60e32012-08-15 13:59:49 +0100999 kfree(dcrtc);
1000}
1001
1002/*
1003 * The mode_config lock is held here, to prevent races between this
1004 * and a mode_set.
1005 */
1006static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
Daniel Vetter41292b1f2017-03-22 22:50:50 +01001007 struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags,
1008 struct drm_modeset_acquire_ctx *ctx)
Russell King96f60e32012-08-15 13:59:49 +01001009{
1010 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
Russell Kingeaa66272017-07-08 10:22:10 +01001011 struct armada_plane_work *work;
Russell King96f60e32012-08-15 13:59:49 +01001012 unsigned i;
1013 int ret;
1014
Russell Kingeaa66272017-07-08 10:22:10 +01001015 work = armada_drm_crtc_alloc_plane_work(dcrtc->crtc.primary);
Russell King96f60e32012-08-15 13:59:49 +01001016 if (!work)
1017 return -ENOMEM;
1018
1019 work->event = event;
Matt Roperf4510a22014-04-01 15:22:40 -07001020 work->old_fb = dcrtc->crtc.primary->fb;
Russell King96f60e32012-08-15 13:59:49 +01001021
1022 i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
1023 dcrtc->interlaced);
1024 armada_reg_queue_end(work->regs, i);
1025
1026 /*
Russell Kingc5488302014-10-11 23:53:35 +01001027 * Ensure that we hold a reference on the new framebuffer.
1028 * This has to match the behaviour in mode_set.
Russell King96f60e32012-08-15 13:59:49 +01001029 */
Haneen Mohammeda52ff2a2017-09-20 12:57:16 -06001030 drm_framebuffer_get(fb);
Russell King96f60e32012-08-15 13:59:49 +01001031
Russell Kingeaa66272017-07-08 10:22:10 +01001032 ret = armada_drm_plane_work_queue(dcrtc, work);
Russell King96f60e32012-08-15 13:59:49 +01001033 if (ret) {
Russell Kingc5488302014-10-11 23:53:35 +01001034 /* Undo our reference above */
Haneen Mohammeda52ff2a2017-09-20 12:57:16 -06001035 drm_framebuffer_put(fb);
Russell King96f60e32012-08-15 13:59:49 +01001036 kfree(work);
1037 return ret;
1038 }
1039
1040 /*
Russell King96f60e32012-08-15 13:59:49 +01001041 * Finally, if the display is blanked, we won't receive an
1042 * interrupt, so complete it now.
1043 */
Russell King4b5dda82015-08-06 16:37:18 +01001044 if (dpms_blanked(dcrtc->dpms))
Russell Kingec6fb152016-07-25 15:16:11 +01001045 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
Russell King96f60e32012-08-15 13:59:49 +01001046
1047 return 0;
1048}
1049
1050static int
1051armada_drm_crtc_set_property(struct drm_crtc *crtc,
1052 struct drm_property *property, uint64_t val)
1053{
1054 struct armada_private *priv = crtc->dev->dev_private;
1055 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1056 bool update_csc = false;
1057
1058 if (property == priv->csc_yuv_prop) {
1059 dcrtc->csc_yuv_mode = val;
1060 update_csc = true;
1061 } else if (property == priv->csc_rgb_prop) {
1062 dcrtc->csc_rgb_mode = val;
1063 update_csc = true;
1064 }
1065
1066 if (update_csc) {
1067 uint32_t val;
1068
1069 val = dcrtc->spu_iopad_ctrl |
1070 armada_drm_crtc_calculate_csc(dcrtc);
1071 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1072 }
1073
1074 return 0;
1075}
1076
Shawn Guo5922a7d2017-02-07 17:16:18 +08001077/* These are called under the vbl_lock. */
1078static int armada_drm_crtc_enable_vblank(struct drm_crtc *crtc)
1079{
1080 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
Russell King92298c12018-06-26 17:06:06 +01001081 unsigned long flags;
Shawn Guo5922a7d2017-02-07 17:16:18 +08001082
Russell King92298c12018-06-26 17:06:06 +01001083 spin_lock_irqsave(&dcrtc->irq_lock, flags);
Shawn Guo5922a7d2017-02-07 17:16:18 +08001084 armada_drm_crtc_enable_irq(dcrtc, VSYNC_IRQ_ENA);
Russell King92298c12018-06-26 17:06:06 +01001085 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
Shawn Guo5922a7d2017-02-07 17:16:18 +08001086 return 0;
1087}
1088
1089static void armada_drm_crtc_disable_vblank(struct drm_crtc *crtc)
1090{
1091 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
Russell King92298c12018-06-26 17:06:06 +01001092 unsigned long flags;
Shawn Guo5922a7d2017-02-07 17:16:18 +08001093
Russell King92298c12018-06-26 17:06:06 +01001094 spin_lock_irqsave(&dcrtc->irq_lock, flags);
Shawn Guo5922a7d2017-02-07 17:16:18 +08001095 armada_drm_crtc_disable_irq(dcrtc, VSYNC_IRQ_ENA);
Russell King92298c12018-06-26 17:06:06 +01001096 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
Shawn Guo5922a7d2017-02-07 17:16:18 +08001097}
1098
Ville Syrjäläa02fb902015-12-15 12:20:59 +01001099static const struct drm_crtc_funcs armada_crtc_funcs = {
Russell King662af0d2013-05-19 10:55:17 +01001100 .cursor_set = armada_drm_crtc_cursor_set,
1101 .cursor_move = armada_drm_crtc_cursor_move,
Russell King96f60e32012-08-15 13:59:49 +01001102 .destroy = armada_drm_crtc_destroy,
1103 .set_config = drm_crtc_helper_set_config,
1104 .page_flip = armada_drm_crtc_page_flip,
1105 .set_property = armada_drm_crtc_set_property,
Shawn Guo5922a7d2017-02-07 17:16:18 +08001106 .enable_vblank = armada_drm_crtc_enable_vblank,
1107 .disable_vblank = armada_drm_crtc_disable_vblank,
Russell King96f60e32012-08-15 13:59:49 +01001108};
1109
Russell King950bc132017-07-08 10:22:37 +01001110static void armada_drm_primary_update_state(struct drm_plane_state *state,
1111 struct armada_regs *regs)
1112{
1113 struct armada_plane *dplane = drm_to_armada_plane(state->plane);
1114 struct armada_crtc *dcrtc = drm_to_armada_crtc(state->crtc);
1115 struct armada_framebuffer *dfb = drm_fb_to_armada_fb(state->fb);
1116 bool was_disabled;
1117 unsigned int idx = 0;
1118 u32 val;
1119
1120 val = CFG_GRA_FMT(dfb->fmt) | CFG_GRA_MOD(dfb->mod);
1121 if (dfb->fmt > CFG_420)
1122 val |= CFG_PALETTE_ENA;
1123 if (state->visible)
1124 val |= CFG_GRA_ENA;
1125 if (drm_rect_width(&state->src) >> 16 != drm_rect_width(&state->dst))
1126 val |= CFG_GRA_HSMOOTH;
1127
1128 was_disabled = !(dplane->state.ctrl0 & CFG_GRA_ENA);
1129 if (was_disabled)
1130 armada_reg_queue_mod(regs, idx,
1131 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
1132
1133 dplane->state.ctrl0 = val;
Russell King02395202018-07-30 11:52:34 +01001134 dplane->state.src_hw = armada_rect_hw_fp(&state->src);
1135 dplane->state.dst_hw = armada_rect_hw(&state->dst);
1136 dplane->state.dst_yx = armada_rect_yx(&state->dst);
Russell King950bc132017-07-08 10:22:37 +01001137
1138 armada_drm_gra_plane_regs(regs + idx, &dfb->fb, &dplane->state,
1139 state->src.x1 >> 16, state->src.y1 >> 16,
1140 dcrtc->interlaced);
1141
1142 dplane->state.vsync_update = !was_disabled;
1143 dplane->state.changed = true;
1144}
1145
Russell Kingcfd1b632018-07-30 11:52:34 +01001146static int armada_drm_do_primary_update(struct drm_plane *plane,
1147 struct drm_plane_state *state, struct drm_framebuffer *old_fb)
Russell King950bc132017-07-08 10:22:37 +01001148{
1149 struct armada_plane *dplane = drm_to_armada_plane(plane);
Russell Kingcfd1b632018-07-30 11:52:34 +01001150 struct armada_crtc *dcrtc = drm_to_armada_crtc(state->crtc);
Russell King950bc132017-07-08 10:22:37 +01001151 struct armada_plane_work *work;
Ville Syrjälä57270b82018-01-23 19:08:55 +02001152 struct drm_crtc_state crtc_state = {
Russell Kingcfd1b632018-07-30 11:52:34 +01001153 .crtc = state->crtc,
1154 .enable = state->crtc->enabled,
1155 .mode = state->crtc->mode,
Ville Syrjälä57270b82018-01-23 19:08:55 +02001156 };
Russell King950bc132017-07-08 10:22:37 +01001157 int ret;
1158
Russell Kingcfd1b632018-07-30 11:52:34 +01001159 ret = drm_atomic_helper_check_plane_state(state, &crtc_state, 0,
Dave Airliebcd21a42018-01-05 09:43:46 +10001160 INT_MAX, true, false);
Russell King950bc132017-07-08 10:22:37 +01001161 if (ret)
1162 return ret;
1163
1164 work = &dplane->works[dplane->next_work];
1165 work->fn = armada_drm_crtc_complete_frame_work;
1166
Russell Kingcfd1b632018-07-30 11:52:34 +01001167 if (old_fb != state->fb) {
Russell King950bc132017-07-08 10:22:37 +01001168 /*
1169 * Take a reference on the new framebuffer - we want to
1170 * hold on to it while the hardware is displaying it.
1171 */
Russell Kingcfd1b632018-07-30 11:52:34 +01001172 drm_framebuffer_reference(state->fb);
Russell King950bc132017-07-08 10:22:37 +01001173
Russell Kingcfd1b632018-07-30 11:52:34 +01001174 work->old_fb = old_fb;
Russell King950bc132017-07-08 10:22:37 +01001175 } else {
1176 work->old_fb = NULL;
1177 }
1178
Russell Kingcfd1b632018-07-30 11:52:34 +01001179 armada_drm_primary_update_state(state, work->regs);
Russell King950bc132017-07-08 10:22:37 +01001180
1181 if (!dplane->state.changed)
1182 return 0;
1183
1184 /* Wait for pending work to complete */
1185 if (armada_drm_plane_work_wait(dplane, HZ / 10) == 0)
1186 armada_drm_plane_work_cancel(dcrtc, dplane);
1187
1188 if (!dplane->state.vsync_update) {
1189 work->fn(dcrtc, work);
1190 if (work->old_fb)
1191 drm_framebuffer_unreference(work->old_fb);
1192 return 0;
1193 }
1194
1195 /* Queue it for update on the next interrupt if we are enabled */
1196 ret = armada_drm_plane_work_queue(dcrtc, work);
1197 if (ret) {
1198 work->fn(dcrtc, work);
1199 if (work->old_fb)
1200 drm_framebuffer_unreference(work->old_fb);
1201 }
1202
1203 dplane->next_work = !dplane->next_work;
1204
1205 return 0;
1206}
1207
Russell Kingcfd1b632018-07-30 11:52:34 +01001208static int armada_drm_primary_update(struct drm_plane *plane,
1209 struct drm_crtc *crtc, struct drm_framebuffer *fb,
1210 int crtc_x, int crtc_y, unsigned int crtc_w, unsigned int crtc_h,
1211 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h,
1212 struct drm_modeset_acquire_ctx *ctx)
1213{
1214 struct drm_plane_state state = {
1215 .plane = plane,
1216 .crtc = crtc,
1217 .fb = fb,
1218 .src_x = src_x,
1219 .src_y = src_y,
1220 .src_w = src_w,
1221 .src_h = src_h,
1222 .crtc_x = crtc_x,
1223 .crtc_y = crtc_y,
1224 .crtc_w = crtc_w,
1225 .crtc_h = crtc_h,
1226 .rotation = DRM_MODE_ROTATE_0,
1227 };
1228
1229 return armada_drm_do_primary_update(plane, &state, plane->fb);
1230}
1231
Russell Kingf1f1bffc2017-07-08 10:16:42 +01001232int armada_drm_plane_disable(struct drm_plane *plane,
1233 struct drm_modeset_acquire_ctx *ctx)
Russell King28b30432017-07-08 10:16:40 +01001234{
1235 struct armada_plane *dplane = drm_to_armada_plane(plane);
Russell Kingf1f1bffc2017-07-08 10:16:42 +01001236 struct armada_crtc *dcrtc;
Russell King890ca8d2017-07-08 10:22:27 +01001237 struct armada_plane_work *work;
1238 unsigned int idx = 0;
Russell Kingd76dcc72017-07-08 10:16:47 +01001239 u32 sram_para1, enable_mask;
Russell King28b30432017-07-08 10:16:40 +01001240
Russell Kingf1f1bffc2017-07-08 10:16:42 +01001241 if (!plane->crtc)
1242 return 0;
1243
Russell King28b30432017-07-08 10:16:40 +01001244 /*
Russell King890ca8d2017-07-08 10:22:27 +01001245 * Arrange to power down most RAMs and FIFOs if this is the primary
1246 * plane, otherwise just the YUV FIFOs for the overlay plane.
Russell King28b30432017-07-08 10:16:40 +01001247 */
Russell King28b30432017-07-08 10:16:40 +01001248 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
1249 sram_para1 = CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1250 CFG_PDWN32x32 | CFG_PDWN64x66;
Russell Kingd76dcc72017-07-08 10:16:47 +01001251 enable_mask = CFG_GRA_ENA;
Russell King28b30432017-07-08 10:16:40 +01001252 } else {
Russell King28b30432017-07-08 10:16:40 +01001253 sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66;
Russell Kingd76dcc72017-07-08 10:16:47 +01001254 enable_mask = CFG_DMA_ENA;
Russell King28b30432017-07-08 10:16:40 +01001255 }
1256
Russell Kingd76dcc72017-07-08 10:16:47 +01001257 dplane->state.ctrl0 &= ~enable_mask;
1258
Russell Kingf1f1bffc2017-07-08 10:16:42 +01001259 dcrtc = drm_to_armada_crtc(plane->crtc);
1260
Russell King890ca8d2017-07-08 10:22:27 +01001261 /*
1262 * Try to disable the plane and drop our ref on the framebuffer
1263 * at the next frame update. If we fail for any reason, disable
1264 * the plane immediately.
1265 */
1266 work = &dplane->works[dplane->next_work];
1267 work->fn = armada_drm_crtc_complete_disable_work;
1268 work->cancel = armada_drm_crtc_complete_disable_work;
1269 work->old_fb = plane->fb;
1270
1271 armada_reg_queue_mod(work->regs, idx,
1272 0, enable_mask, LCD_SPU_DMA_CTRL0);
1273 armada_reg_queue_mod(work->regs, idx,
1274 sram_para1, 0, LCD_SPU_SRAM_PARA1);
1275 armada_reg_queue_end(work->regs, idx);
1276
Russell King28b30432017-07-08 10:16:40 +01001277 /* Wait for any preceding work to complete, but don't wedge */
1278 if (WARN_ON(!armada_drm_plane_work_wait(dplane, HZ)))
1279 armada_drm_plane_work_cancel(dcrtc, dplane);
1280
Russell King890ca8d2017-07-08 10:22:27 +01001281 if (armada_drm_plane_work_queue(dcrtc, work)) {
1282 work->fn(dcrtc, work);
1283 if (work->old_fb)
1284 drm_framebuffer_unreference(work->old_fb);
1285 }
1286
1287 dplane->next_work = !dplane->next_work;
Russell King28b30432017-07-08 10:16:40 +01001288
Russell King28b30432017-07-08 10:16:40 +01001289 return 0;
1290}
1291
Russell Kingde323012015-07-15 18:11:24 +01001292static const struct drm_plane_funcs armada_primary_plane_funcs = {
Russell King950bc132017-07-08 10:22:37 +01001293 .update_plane = armada_drm_primary_update,
Russell Kingf1f1bffc2017-07-08 10:16:42 +01001294 .disable_plane = armada_drm_plane_disable,
Russell Kingde323012015-07-15 18:11:24 +01001295 .destroy = drm_primary_helper_destroy,
1296};
1297
Russell King5740d272015-07-15 18:11:25 +01001298int armada_drm_plane_init(struct armada_plane *plane)
1299{
Russell Kingd9241552017-07-08 10:22:25 +01001300 unsigned int i;
1301
1302 for (i = 0; i < ARRAY_SIZE(plane->works); i++)
1303 plane->works[i].plane = &plane->base;
1304
Russell King5740d272015-07-15 18:11:25 +01001305 init_waitqueue_head(&plane->frame_wait);
1306
1307 return 0;
1308}
1309
Arvind Yadavaaaf2f12017-07-01 15:30:15 +05301310static const struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
Russell King96f60e32012-08-15 13:59:49 +01001311 { CSC_AUTO, "Auto" },
1312 { CSC_YUV_CCIR601, "CCIR601" },
1313 { CSC_YUV_CCIR709, "CCIR709" },
1314};
1315
Arvind Yadavaaaf2f12017-07-01 15:30:15 +05301316static const struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
Russell King96f60e32012-08-15 13:59:49 +01001317 { CSC_AUTO, "Auto" },
1318 { CSC_RGB_COMPUTER, "Computer system" },
1319 { CSC_RGB_STUDIO, "Studio" },
1320};
1321
1322static int armada_drm_crtc_create_properties(struct drm_device *dev)
1323{
1324 struct armada_private *priv = dev->dev_private;
1325
1326 if (priv->csc_yuv_prop)
1327 return 0;
1328
1329 priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
1330 "CSC_YUV", armada_drm_csc_yuv_enum_list,
1331 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
1332 priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
1333 "CSC_RGB", armada_drm_csc_rgb_enum_list,
1334 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
1335
1336 if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
1337 return -ENOMEM;
1338
1339 return 0;
1340}
1341
Russell King0fb29702015-06-06 21:46:53 +01001342static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
Russell King9611cb92014-06-15 11:21:23 +01001343 struct resource *res, int irq, const struct armada_variant *variant,
1344 struct device_node *port)
Russell King96f60e32012-08-15 13:59:49 +01001345{
Russell Kingd8c96082014-04-22 11:10:15 +01001346 struct armada_private *priv = drm->dev_private;
Russell King96f60e32012-08-15 13:59:49 +01001347 struct armada_crtc *dcrtc;
Russell Kingde323012015-07-15 18:11:24 +01001348 struct armada_plane *primary;
Russell King96f60e32012-08-15 13:59:49 +01001349 void __iomem *base;
1350 int ret;
1351
Russell Kingd8c96082014-04-22 11:10:15 +01001352 ret = armada_drm_crtc_create_properties(drm);
Russell King96f60e32012-08-15 13:59:49 +01001353 if (ret)
1354 return ret;
1355
Linus Torvaldsa7d7a142014-08-07 17:36:12 -07001356 base = devm_ioremap_resource(dev, res);
Jingoo Hanc9d53c02014-06-11 14:00:05 +09001357 if (IS_ERR(base))
1358 return PTR_ERR(base);
Russell King96f60e32012-08-15 13:59:49 +01001359
1360 dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
1361 if (!dcrtc) {
1362 DRM_ERROR("failed to allocate Armada crtc\n");
1363 return -ENOMEM;
1364 }
1365
Russell Kingd8c96082014-04-22 11:10:15 +01001366 if (dev != drm->dev)
1367 dev_set_drvdata(dev, dcrtc);
1368
Russell King42e62ba2014-04-22 15:24:03 +01001369 dcrtc->variant = variant;
Russell King96f60e32012-08-15 13:59:49 +01001370 dcrtc->base = base;
Russell Kingd8c96082014-04-22 11:10:15 +01001371 dcrtc->num = drm->mode_config.num_crtc;
Russell King96f60e32012-08-15 13:59:49 +01001372 dcrtc->clk = ERR_PTR(-EINVAL);
1373 dcrtc->csc_yuv_mode = CSC_AUTO;
1374 dcrtc->csc_rgb_mode = CSC_AUTO;
1375 dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
1376 dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
1377 spin_lock_init(&dcrtc->irq_lock);
1378 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
Russell King96f60e32012-08-15 13:59:49 +01001379
1380 /* Initialize some registers which we don't otherwise set */
1381 writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
1382 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
1383 writel_relaxed(dcrtc->spu_iopad_ctrl,
1384 dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1385 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
1386 writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1387 CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
1388 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
1389 writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
Russell Kinge5d9ddf2014-04-26 15:19:38 +01001390 writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
Russell King92298c12018-06-26 17:06:06 +01001391 readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
Russell Kinge5d9ddf2014-04-26 15:19:38 +01001392 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
Russell King96f60e32012-08-15 13:59:49 +01001393
Russell Kinge5d9ddf2014-04-26 15:19:38 +01001394 ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
1395 dcrtc);
Russell King33cd3c02017-12-08 12:16:22 +00001396 if (ret < 0)
1397 goto err_crtc;
Russell King96f60e32012-08-15 13:59:49 +01001398
Russell King42e62ba2014-04-22 15:24:03 +01001399 if (dcrtc->variant->init) {
Russell Kingd8c96082014-04-22 11:10:15 +01001400 ret = dcrtc->variant->init(dcrtc, dev);
Russell King33cd3c02017-12-08 12:16:22 +00001401 if (ret)
1402 goto err_crtc;
Russell King96f60e32012-08-15 13:59:49 +01001403 }
1404
1405 /* Ensure AXI pipeline is enabled */
1406 armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
1407
1408 priv->dcrtc[dcrtc->num] = dcrtc;
1409
Russell King9611cb92014-06-15 11:21:23 +01001410 dcrtc->crtc.port = port;
Russell King1c914ce2015-07-15 18:11:24 +01001411
Russell Kingde323012015-07-15 18:11:24 +01001412 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
Russell King33cd3c02017-12-08 12:16:22 +00001413 if (!primary) {
1414 ret = -ENOMEM;
1415 goto err_crtc;
1416 }
Russell King1c914ce2015-07-15 18:11:24 +01001417
Russell King5740d272015-07-15 18:11:25 +01001418 ret = armada_drm_plane_init(primary);
1419 if (ret) {
1420 kfree(primary);
Russell King33cd3c02017-12-08 12:16:22 +00001421 goto err_crtc;
Russell King5740d272015-07-15 18:11:25 +01001422 }
1423
Russell Kingde323012015-07-15 18:11:24 +01001424 ret = drm_universal_plane_init(drm, &primary->base, 0,
1425 &armada_primary_plane_funcs,
1426 armada_primary_formats,
1427 ARRAY_SIZE(armada_primary_formats),
Ben Widawskye6fc3b62017-07-23 20:46:38 -07001428 NULL,
Ville Syrjäläb0b3b792015-12-09 16:19:55 +02001429 DRM_PLANE_TYPE_PRIMARY, NULL);
Russell Kingde323012015-07-15 18:11:24 +01001430 if (ret) {
1431 kfree(primary);
Russell King33cd3c02017-12-08 12:16:22 +00001432 goto err_crtc;
Russell Kingde323012015-07-15 18:11:24 +01001433 }
1434
1435 ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL,
Ville Syrjäläf9882872015-12-09 16:19:31 +02001436 &armada_crtc_funcs, NULL);
Russell King1c914ce2015-07-15 18:11:24 +01001437 if (ret)
1438 goto err_crtc_init;
1439
Russell King96f60e32012-08-15 13:59:49 +01001440 drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
1441
1442 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
1443 dcrtc->csc_yuv_mode);
1444 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
1445 dcrtc->csc_rgb_mode);
1446
Russell Kingd8c96082014-04-22 11:10:15 +01001447 return armada_overlay_plane_create(drm, 1 << dcrtc->num);
Russell King1c914ce2015-07-15 18:11:24 +01001448
1449err_crtc_init:
Russell Kingde323012015-07-15 18:11:24 +01001450 primary->base.funcs->destroy(&primary->base);
Russell King33cd3c02017-12-08 12:16:22 +00001451err_crtc:
1452 kfree(dcrtc);
1453
Russell King1c914ce2015-07-15 18:11:24 +01001454 return ret;
Russell King96f60e32012-08-15 13:59:49 +01001455}
Russell Kingd8c96082014-04-22 11:10:15 +01001456
1457static int
1458armada_lcd_bind(struct device *dev, struct device *master, void *data)
1459{
1460 struct platform_device *pdev = to_platform_device(dev);
1461 struct drm_device *drm = data;
1462 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1463 int irq = platform_get_irq(pdev, 0);
1464 const struct armada_variant *variant;
Russell King9611cb92014-06-15 11:21:23 +01001465 struct device_node *port = NULL;
Russell Kingd8c96082014-04-22 11:10:15 +01001466
1467 if (irq < 0)
1468 return irq;
1469
1470 if (!dev->of_node) {
1471 const struct platform_device_id *id;
1472
1473 id = platform_get_device_id(pdev);
1474 if (!id)
1475 return -ENXIO;
1476
1477 variant = (const struct armada_variant *)id->driver_data;
1478 } else {
1479 const struct of_device_id *match;
Russell King9611cb92014-06-15 11:21:23 +01001480 struct device_node *np, *parent = dev->of_node;
Russell Kingd8c96082014-04-22 11:10:15 +01001481
1482 match = of_match_device(dev->driver->of_match_table, dev);
1483 if (!match)
1484 return -ENXIO;
1485
Russell King9611cb92014-06-15 11:21:23 +01001486 np = of_get_child_by_name(parent, "ports");
1487 if (np)
1488 parent = np;
1489 port = of_get_child_by_name(parent, "port");
1490 of_node_put(np);
1491 if (!port) {
Rob Herring4bf99142017-07-18 16:43:04 -05001492 dev_err(dev, "no port node found in %pOF\n", parent);
Russell King9611cb92014-06-15 11:21:23 +01001493 return -ENXIO;
1494 }
1495
Russell Kingd8c96082014-04-22 11:10:15 +01001496 variant = match->data;
1497 }
1498
Russell King9611cb92014-06-15 11:21:23 +01001499 return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
Russell Kingd8c96082014-04-22 11:10:15 +01001500}
1501
1502static void
1503armada_lcd_unbind(struct device *dev, struct device *master, void *data)
1504{
1505 struct armada_crtc *dcrtc = dev_get_drvdata(dev);
1506
1507 armada_drm_crtc_destroy(&dcrtc->crtc);
1508}
1509
1510static const struct component_ops armada_lcd_ops = {
1511 .bind = armada_lcd_bind,
1512 .unbind = armada_lcd_unbind,
1513};
1514
1515static int armada_lcd_probe(struct platform_device *pdev)
1516{
1517 return component_add(&pdev->dev, &armada_lcd_ops);
1518}
1519
1520static int armada_lcd_remove(struct platform_device *pdev)
1521{
1522 component_del(&pdev->dev, &armada_lcd_ops);
1523 return 0;
1524}
1525
Arvind Yadav85909712017-06-20 10:44:33 +05301526static const struct of_device_id armada_lcd_of_match[] = {
Russell Kingd8c96082014-04-22 11:10:15 +01001527 {
1528 .compatible = "marvell,dove-lcd",
1529 .data = &armada510_ops,
1530 },
1531 {}
1532};
1533MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
1534
1535static const struct platform_device_id armada_lcd_platform_ids[] = {
1536 {
1537 .name = "armada-lcd",
1538 .driver_data = (unsigned long)&armada510_ops,
1539 }, {
1540 .name = "armada-510-lcd",
1541 .driver_data = (unsigned long)&armada510_ops,
1542 },
1543 { },
1544};
1545MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
1546
1547struct platform_driver armada_lcd_platform_driver = {
1548 .probe = armada_lcd_probe,
1549 .remove = armada_lcd_remove,
1550 .driver = {
1551 .name = "armada-lcd",
1552 .owner = THIS_MODULE,
1553 .of_match_table = armada_lcd_of_match,
1554 },
1555 .id_table = armada_lcd_platform_ids,
1556};