James Schulman | 6ba9dd6 | 2019-02-07 12:12:15 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * cs35l36.h -- CS35L36 ALSA SoC audio driver |
| 4 | * |
| 5 | * Copyright 2018 Cirrus Logic, Inc. |
| 6 | * |
| 7 | * Author: James Schulman <james.schulman@cirrus.com> |
| 8 | * |
| 9 | */ |
| 10 | |
| 11 | #ifndef __CS35L36_H__ |
| 12 | #define __CS35L36_H__ |
| 13 | |
| 14 | #include <linux/regmap.h> |
| 15 | |
| 16 | #define CS35L36_FIRSTREG 0x00000000 |
| 17 | #define CS35L36_LASTREG 0x00E037FC |
| 18 | #define CS35L36_SW_RESET 0x00000000 |
| 19 | #define CS35L36_SW_REV 0x00000004 |
| 20 | #define CS35L36_HW_REV 0x00000008 |
| 21 | #define CS35L36_TESTKEY_CTRL 0x00000020 |
| 22 | #define CS35L36_USERKEY_CTL 0x00000024 |
| 23 | #define CS35L36_OTP_MEM30 0x00000478 |
| 24 | #define CS35L36_OTP_CTRL1 0x00000500 |
| 25 | #define CS35L36_OTP_CTRL2 0x00000504 |
| 26 | #define CS35L36_OTP_CTRL3 0x00000508 |
| 27 | #define CS35L36_OTP_CTRL4 0x0000050C |
| 28 | #define CS35L36_OTP_CTRL5 0x00000510 |
| 29 | #define CS35L36_PAC_CTL1 0x00000C00 |
| 30 | #define CS35L36_PAC_CTL2 0x00000C04 |
| 31 | #define CS35L36_PAC_CTL3 0x00000C08 |
| 32 | #define CS35L36_DEVICE_ID 0x00002004 |
| 33 | #define CS35L36_FAB_ID 0x00002008 |
| 34 | #define CS35L36_REV_ID 0x0000200C |
| 35 | #define CS35L36_PWR_CTRL1 0x00002014 |
| 36 | #define CS35L36_PWR_CTRL2 0x00002018 |
| 37 | #define CS35L36_PWR_CTRL3 0x0000201C |
| 38 | #define CS35L36_CTRL_OVRRIDE 0x00002020 |
| 39 | #define CS35L36_AMP_OUT_MUTE 0x00002024 |
| 40 | #define CS35L36_OTP_TRIM_STATUS 0x00002028 |
| 41 | #define CS35L36_DISCH_FILT 0x0000202C |
| 42 | #define CS35L36_OSC_TRIM 0x00002030 |
| 43 | #define CS35L36_PROTECT_REL_ERR 0x00002034 |
| 44 | #define CS35L36_PAD_INTERFACE 0x00002400 |
| 45 | #define CS35L36_PLL_CLK_CTRL 0x00002C04 |
| 46 | #define CS35L36_GLOBAL_CLK_CTRL 0x00002C0C |
| 47 | #define CS35L36_ADC_CLK_CTRL 0x00002C10 |
| 48 | #define CS35L36_SWIRE_CLK_CTRL 0x00002C14 |
| 49 | #define CS35L36_SP_SCLK_CLK_CTRL 0x00002D00 |
| 50 | #define CS35L36_TST_FS_MON0 0x00002D10 |
| 51 | #define CS35L36_PLL_LOOP_PARAMS 0x00003008 |
| 52 | #define CS35L36_DCO_CTRL 0x00003010 |
| 53 | #define CS35L36_MISC_CTRL 0x00003014 |
| 54 | #define CS35L36_MDSYNC_EN 0x00003404 |
| 55 | #define CS35L36_MDSYNC_TX_ID 0x00003408 |
| 56 | #define CS35L36_MDSYNC_PWR_CTRL 0x0000340C |
| 57 | #define CS35L36_MDSYNC_DATA_TX 0x00003410 |
| 58 | #define CS35L36_MDSYNC_TX_STATUS 0x0000341C |
| 59 | #define CS35L36_MDSYNC_RX_STATUS 0x00003420 |
| 60 | #define CS35L36_MDSYNC_ERR_STATUS 0x00003424 |
| 61 | #define CS35L36_BSTCVRT_VCTRL1 0x00003800 |
| 62 | #define CS35L36_BSTCVRT_VCTRL2 0x00003804 |
| 63 | #define CS35L36_BSTCVRT_PEAK_CUR 0x00003808 |
| 64 | #define CS35L36_BSTCVRT_SFT_RAMP 0x0000380C |
| 65 | #define CS35L36_BSTCVRT_COEFF 0x00003810 |
| 66 | #define CS35L36_BSTCVRT_SLOPE_LBST 0x00003814 |
| 67 | #define CS35L36_BSTCVRT_SW_FREQ 0x00003818 |
| 68 | #define CS35L36_BSTCVRT_DCM_CTRL 0x0000381C |
| 69 | #define CS35L36_BSTCVRT_DCM_MODE_FORCE 0x00003820 |
| 70 | #define CS35L36_BSTCVRT_OVERVOLT_CTRL 0x00003830 |
| 71 | #define CS35L36_BST_TST_MANUAL 0x0000393C |
| 72 | #define CS35L36_BST_ANA2_TEST 0x0000394C |
| 73 | #define CS35L36_VPI_LIMIT_MODE 0x00003C04 |
| 74 | #define CS35L36_VPI_LIMIT_MINMAX 0x00003C08 |
| 75 | #define CS35L36_VPI_VP_THLD 0x00003C0C |
| 76 | #define CS35L36_VPI_TRACK_CTRL 0x00003C10 |
| 77 | #define CS35L36_VPI_TRIG_MODE_CTRL 0x00003C14 |
| 78 | #define CS35L36_VPI_TRIG_STEPS 0x00003C18 |
| 79 | #define CS35L36_VI_SPKMON_FILT 0x00004004 |
| 80 | #define CS35L36_VI_SPKMON_GAIN 0x00004008 |
| 81 | #define CS35L36_VI_SPKMON_IP_SEL 0x00004100 |
| 82 | #define CS35L36_DTEMP_WARN_THLD 0x00004220 |
| 83 | #define CS35L36_DTEMP_STATUS 0x00004300 |
| 84 | #define CS35L36_VPVBST_FS_SEL 0x00004400 |
| 85 | #define CS35L36_VPVBST_VP_CTRL 0x00004440 |
| 86 | #define CS35L36_VPVBST_VBST_CTRL 0x00004444 |
| 87 | #define CS35L36_ASP_TX_PIN_CTRL 0x00004800 |
| 88 | #define CS35L36_ASP_RATE_CTRL 0x00004804 |
| 89 | #define CS35L36_ASP_FORMAT 0x00004808 |
| 90 | #define CS35L36_ASP_FRAME_CTRL 0x00004818 |
| 91 | #define CS35L36_ASP_TX1_TX2_SLOT 0x0000481C |
| 92 | #define CS35L36_ASP_TX3_TX4_SLOT 0x00004820 |
| 93 | #define CS35L36_ASP_TX5_TX6_SLOT 0x00004824 |
| 94 | #define CS35L36_ASP_TX7_TX8_SLOT 0x00004828 |
| 95 | #define CS35L36_ASP_RX1_SLOT 0x0000482C |
| 96 | #define CS35L36_ASP_RX_TX_EN 0x0000483C |
| 97 | #define CS35L36_ASP_RX1_SEL 0x00004C00 |
| 98 | #define CS35L36_ASP_TX1_SEL 0x00004C20 |
| 99 | #define CS35L36_ASP_TX2_SEL 0x00004C24 |
| 100 | #define CS35L36_ASP_TX3_SEL 0x00004C28 |
| 101 | #define CS35L36_ASP_TX4_SEL 0x00004C2C |
| 102 | #define CS35L36_ASP_TX5_SEL 0x00004C30 |
| 103 | #define CS35L36_ASP_TX6_SEL 0x00004C34 |
| 104 | #define CS35L36_SWIRE_P1_TX1_SEL 0x00004C40 |
| 105 | #define CS35L36_SWIRE_P1_TX2_SEL 0x00004C44 |
| 106 | #define CS35L36_SWIRE_P2_TX1_SEL 0x00004C60 |
| 107 | #define CS35L36_SWIRE_P2_TX2_SEL 0x00004C64 |
| 108 | #define CS35L36_SWIRE_P2_TX3_SEL 0x00004C68 |
| 109 | #define CS35L36_SWIRE_DP1_FIFO_CFG 0x00005000 |
| 110 | #define CS35L36_SWIRE_DP2_FIFO_CFG 0x00005004 |
| 111 | #define CS35L36_SWIRE_DP3_FIFO_CFG 0x00005008 |
| 112 | #define CS35L36_SWIRE_PCM_RX_DATA 0x0000500C |
| 113 | #define CS35L36_SWIRE_FS_SEL 0x00005010 |
| 114 | #define CS35L36_SPARE_CP_BITS 0x00005C00 |
| 115 | #define CS35L36_AMP_DIG_VOL_CTRL 0x00006000 |
| 116 | #define CS35L36_VPBR_CFG 0x00006404 |
| 117 | #define CS35L36_VBBR_CFG 0x00006408 |
| 118 | #define CS35L36_VPBR_STATUS 0x0000640C |
| 119 | #define CS35L36_VBBR_STATUS 0x00006410 |
| 120 | #define CS35L36_OVERTEMP_CFG 0x00006414 |
| 121 | #define CS35L36_AMP_ERR_VOL 0x00006418 |
| 122 | #define CS35L36_CLASSH_CFG 0x00006800 |
| 123 | #define CS35L36_CLASSH_FET_DRV_CFG 0x00006804 |
| 124 | #define CS35L36_NG_CFG 0x00006808 |
| 125 | #define CS35L36_AMP_GAIN_CTRL 0x00006C04 |
| 126 | #define CS35L36_PWM_MOD_IO_CTRL 0x0000706C |
| 127 | #define CS35L36_PWM_MOD_STATUS 0x00007070 |
| 128 | #define CS35L36_DAC_MSM_CFG 0x00007400 |
| 129 | #define CS35L36_AMP_SLOPE_CTRL 0x00007410 |
| 130 | #define CS35L36_AMP_PDM_VOLUME 0x00007E04 |
| 131 | #define CS35L36_AMP_PDM_RATE_CTRL 0x00007E08 |
| 132 | #define CS35L36_PDM_CH_SEL 0x00007E10 |
| 133 | #define CS35L36_AMP_NG_CTRL 0x00007E14 |
| 134 | #define CS35L36_PDM_HIGHFILT_CTRL 0x00007E3C |
| 135 | #define CS35L36_INT1_STATUS 0x00D00000 |
| 136 | #define CS35L36_INT2_STATUS 0x00D00004 |
| 137 | #define CS35L36_INT3_STATUS 0x00D00008 |
| 138 | #define CS35L36_INT4_STATUS 0x00D0000C |
| 139 | #define CS35L36_INT1_RAW_STATUS 0x00D00020 |
| 140 | #define CS35L36_INT2_RAW_STATUS 0x00D00024 |
| 141 | #define CS35L36_INT3_RAW_STATUS 0x00D00028 |
| 142 | #define CS35L36_INT4_RAW_STATUS 0x00D0002C |
| 143 | #define CS35L36_INT1_MASK 0x00D00040 |
| 144 | #define CS35L36_INT2_MASK 0x00D00044 |
| 145 | #define CS35L36_INT3_MASK 0x00D00048 |
| 146 | #define CS35L36_INT4_MASK 0x00D0004C |
| 147 | #define CS35L36_INT1_EDGE_LVL_CTRL 0x00D00060 |
| 148 | #define CS35L36_INT3_EDGE_LVL_CTRL 0x00D00068 |
| 149 | #define CS35L36_PAC_INT_STATUS 0x00D00200 |
| 150 | #define CS35L36_PAC_INT_RAW_STATUS 0x00D00210 |
| 151 | #define CS35L36_PAC_INT_FLUSH_CTRL 0x00D00218 |
| 152 | #define CS35L36_PAC_INT0_CTRL 0x00D00220 |
| 153 | #define CS35L36_PAC_INT1_CTRL 0x00D00224 |
| 154 | #define CS35L36_PAC_INT2_CTRL 0x00D00228 |
| 155 | #define CS35L36_PAC_INT3_CTRL 0x00D0022C |
| 156 | #define CS35L36_PAC_INT4_CTRL 0x00D00230 |
| 157 | #define CS35L36_PAC_INT5_CTRL 0x00D00234 |
| 158 | #define CS35L36_PAC_INT6_CTRL 0x00D00238 |
| 159 | #define CS35L36_PAC_INT7_CTRL 0x00D0023C |
| 160 | #define CS35L36_PAC_PMEM_WORD0 0x00E02800 |
| 161 | #define CS35L36_PAC_PMEM_WORD1 0x00E02804 |
| 162 | #define CS35L36_PAC_PMEM_WORD1023 0x00E037FC |
| 163 | |
| 164 | #define CS35L36_INTPAC_REG_COUNT 25 |
| 165 | #define CS35L36_CHIP_ID 0x00035A36 |
| 166 | |
| 167 | #define CS35L36_INT_OUTPUT_EN_MASK 0x01 |
| 168 | #define CS35L36_INT_GPIO_SEL_MASK 0x02 |
| 169 | #define CS35L36_INT_GPIO_SEL_SHIFT 1 |
| 170 | #define CS35L36_INT_POL_SEL_MASK 0x04 |
| 171 | #define CS35L36_INT_POL_SEL_SHIFT 2 |
| 172 | #define CS35L36_INT_DRV_SEL_MASK 0x20 |
| 173 | #define CS35L36_INT_DRV_SEL_SHIFT 5 |
| 174 | #define CS35L36_IRQ_SRC_MASK 0x08 |
| 175 | #define CS35L36_IRQ_SRC_SHIFT 3 |
| 176 | |
| 177 | #define CS35L36_SCLK_MSTR_MASK 0x40 |
| 178 | #define CS35L36_SCLK_MSTR_SHIFT 6 |
| 179 | #define CS35L36_LRCLK_MSTR_MASK 0x01 |
| 180 | #define CS35L36_LRCLK_MSTR_SHIFT 0 |
| 181 | #define CS35L36_SCLK_INV_MASK 0x100 |
| 182 | #define CS35L36_SCLK_INV_SHIFT 8 |
| 183 | #define CS35L36_LRCLK_INV_MASK 0x04 |
| 184 | #define CS35L36_LRCLK_INV_SHIFT 2 |
| 185 | #define CS35L36_SCLK_FRC_MASK 0x80 |
| 186 | #define CS35L36_SCLK_FRC_SHIFT 7 |
| 187 | #define CS35L36_LRCLK_FRC_MASK 0x02 |
| 188 | #define CS35L36_LRCLK_FRC_SHIFT 1 |
| 189 | |
| 190 | #define CS35L36_PDM_MODE_MASK 0x01 |
| 191 | #define CS35L36_PDM_MODE_SHIFT 0 |
| 192 | |
| 193 | #define CS35L36_ASP_FMT_MASK 0x07 |
| 194 | #define CS35L36_ASP_FMT_SHIFT 0 |
| 195 | |
| 196 | #define CS35L36_ASP_RX_WIDTH_MASK 0xFF0000 |
| 197 | #define CS35L36_ASP_RX_WIDTH_SHIFT 16 |
| 198 | #define CS35L36_ASP_TX_WIDTH_MASK 0xFF |
| 199 | #define CS35L36_ASP_TX_WIDTH_SHIFT 0 |
| 200 | #define CS35L36_ASP_WIDTH_16 0x10 |
| 201 | #define CS35L36_ASP_WIDTH_24 0x18 |
| 202 | #define CS35L36_ASP_WIDTH_32 0x20 |
| 203 | |
| 204 | #define CS35L36_ASP_RX1_SLOT_MASK 0x3F |
| 205 | #define CS35L36_ASP_RX1_EN_MASK 0x00010000 |
| 206 | #define CS35L36_ASP_RX1_EN_SHIFT 16 |
| 207 | |
| 208 | #define CS35L36_ASP_TX1_SLOT_MASK 0x3F |
| 209 | #define CS35L36_ASP_TX2_SLOT_MASK 0x3F0000 |
| 210 | #define CS35L36_ASP_TX2_SLOT_SHIFT 16 |
| 211 | #define CS35L36_ASP_TX3_SLOT_MASK 0x3F |
| 212 | #define CS35L36_ASP_TX4_SLOT_MASK 0x3F0000 |
| 213 | #define CS35L36_ASP_TX4_SLOT_SHIFT 16 |
| 214 | #define CS35L36_ASP_TX5_SLOT_MASK 0x3F |
| 215 | #define CS35L36_ASP_TX6_SLOT_MASK 0x3F0000 |
| 216 | #define CS35L36_ASP_TX6_SLOT_SHIFT 16 |
| 217 | #define CS35L36_ASP_TX7_SLOT_MASK 0x3F |
| 218 | #define CS35L36_ASP_TX8_SLOT_MASK 0x3F0000 |
| 219 | #define CS35L36_ASP_TX8_SLOT_SHIFT 16 |
| 220 | #define CS35L36_ASP_TX_HIZ_MASK 0x200000 |
| 221 | |
| 222 | #define CS35L36_APS_TX_SEL_MASK 0x7F |
| 223 | |
| 224 | #define CS35L36_ASP_TX1_EN_MASK 0x01 |
| 225 | #define CS35L36_ASP_TX2_EN_MASK 0x02 |
| 226 | #define CS35L36_ASP_TX2_EN_SHIFT 1 |
| 227 | #define CS35L36_ASP_TX3_EN_MASK 0x04 |
| 228 | #define CS35L36_ASP_TX3_EN_SHIFT 2 |
| 229 | #define CS35L36_ASP_TX4_EN_MASK 0x08 |
| 230 | #define CS35L36_ASP_TX4_EN_SHIFT 3 |
| 231 | #define CS35L36_ASP_TX5_EN_MASK 0x10 |
| 232 | #define CS35L36_ASP_TX5_EN_SHIFT 4 |
| 233 | #define CS35L36_ASP_TX6_EN_MASK 0x20 |
| 234 | #define CS35L36_ASP_TX6_EN_SHIFT 5 |
| 235 | #define CS35L36_ASP_TX7_EN_MASK 0x40 |
| 236 | #define CS35L36_ASP_TX7_EN_SHIFT 6 |
| 237 | #define CS35L36_ASP_TX8_EN_MASK 0x80 |
| 238 | #define CS35L36_ASP_TX8_EN_SHIFT 7 |
| 239 | |
| 240 | |
| 241 | #define CS35L36_PLL_CLK_SEL_MASK 0x07 |
| 242 | #define CS35L36_PLL_CLK_SEL_SHIFT 0 |
| 243 | #define CS35L36_PLLSRC_SCLK 0 |
| 244 | #define CS35L36_PLLSRC_LRCLK 1 |
| 245 | #define CS35L36_PLLSRC_SELF 3 |
| 246 | #define CS35L36_PLLSRC_PDMCLK 4 |
| 247 | #define CS35L36_PLLSRC_MCLK 5 |
| 248 | #define CS35L36_PLLSRC_SWIRE 7 |
| 249 | #define CS35L36_REFCLK_FREQ_MASK 0x7E0 |
| 250 | #define CS35L36_REFCLK_FREQ_SHIFT 5 |
| 251 | #define CS35L36_PLL_OPENLOOP_MASK 0x800 |
| 252 | #define CS35L36_PLL_OPENLOOP_SHIFT 11 |
| 253 | #define CS35L36_PLL_REFCLK_EN_MASK 0x10 |
| 254 | #define CS35L36_PLL_REFCLK_EN_SHIFT 4 |
| 255 | |
| 256 | |
| 257 | #define CS35L36_GLOBAL_FS_MASK 0x1F |
| 258 | #define CS35L36_GLOBAL_FS_SHIFT 0 |
| 259 | |
| 260 | #define CS35L36_HPF_PCM_EN_MASK 0x800 |
| 261 | #define CS35L36_HPF_PCM_EN_SHIFT 15 |
| 262 | #define CS35L36_PCM_RX_SEL_MASK 0x7F |
| 263 | #define CS35L36_PCM_RX_SEL_SHIFT 0 |
| 264 | |
| 265 | #define CS35L36_PCM_RX_SEL_ZERO 0x00 |
| 266 | #define CS35L36_PCM_RX_SEL_PCM 0x08 |
| 267 | #define CS35L36_PCM_RX_SEL_SWIRE 0x10 |
| 268 | #define CS35L36_PCM_RX_SEL_DIAG 0x04 |
| 269 | |
| 270 | #define CS35L36_GLOBAL_EN_MASK 0x01 |
| 271 | #define CS35L36_GLOBAL_EN_SHIFT 0x00 |
| 272 | |
| 273 | #define CS35L36_AMP_PCM_INV_MASK 0x4000 |
| 274 | #define CS35L36_AMP_PCM_INV_SHIFT 14 |
| 275 | |
| 276 | #define CS35L36_AMP_VOL_PCM_MASK 0x3FF8 |
| 277 | #define CS35L36_AMP_VOL_PCM_SHIFT 3 |
| 278 | #define CS35L36_DIGITAL_MUTE 0x04CF |
| 279 | |
| 280 | #define CS35L36_AMP_RAMP_MASK 0x0007 |
| 281 | #define CS35L36_AMP_RAMP_SHIFT 0 |
| 282 | |
| 283 | #define CS35L36_AMP_MUTE_MASK 0x0010 |
| 284 | #define CS35L36_AMP_MUTE_SHIFT 4 |
| 285 | |
| 286 | #define CS35L36_GLOBAL_RESYNC_FS1_MASK 0x00000200 |
| 287 | #define CS35L36_GLOBAL_RESYNC_FS2_MASK 0x00000400 |
| 288 | #define CS35L36_SYNC_GLOBAL_OVR_MASK 0x00000002 |
| 289 | #define CS35L36_SYNC_GLOBAL_OVR_SHIFT 1 |
| 290 | |
| 291 | #define CS35L36_REFCLK_IN_MASK 0x00100000 |
| 292 | #define CS35L36_PLL_UNLOCK_MASK 0x00002000 |
| 293 | |
| 294 | #define CS35L36_ASP_RX_UDF_MASK 0x00000040 |
| 295 | #define CS35L36_ASP_RX_OVF_MASK 0x00000080 |
| 296 | |
| 297 | #define CS35L36_IMON_POL_MASK 0x02 |
| 298 | #define CS35L36_IMON_POL_SHIFT 1 |
| 299 | |
| 300 | #define CS35L36_VMON_POL_MASK 0x01 |
| 301 | #define CS35L36_VMON_POL_SHIFT 0 |
| 302 | |
| 303 | #define CS35L36_PDN_DONE 0x40 |
| 304 | #define CS35L36_PDN_DONE_SHIFT 6 |
| 305 | #define CS35L36_PUP_DONE 0x80 |
| 306 | #define CS35L36_PUP_DONE_SHIFT 7 |
| 307 | #define CS35L36_GLOBAL_EN_ASSRT 0x20 |
| 308 | #define CS35L36_PUP_DONE_IRQ_UNMASK 0x7F |
| 309 | #define CS35L36_PUP_DONE_IRQ_MASK 0xBF |
| 310 | |
| 311 | #define CS35L36_FS1_WINDOW_MASK 0x000007FF |
| 312 | #define CS35L36_FS2_WINDOW_MASK 0x00FFF800 |
| 313 | #define CS35L36_FS2_WINDOW_SHIFT 12 |
| 314 | |
| 315 | #define CS35L36_PLL_FFL_IGAIN_MASK 0x0F |
| 316 | #define CS35L36_PLL_IGAIN_MASK 0x3F0 |
| 317 | #define CS35L36_PLL_IGAIN_SHIFT 4 |
| 318 | #define CS35L36_PLL_IGAIN 0x04 |
| 319 | |
| 320 | #define CS35L36_BST_EN_MASK 0x30 |
| 321 | #define CS35L36_BST_EN 0x02 |
| 322 | #define CS35L36_BST_DIS_VP 0x01 |
| 323 | #define CS35L36_BST_DIS_EXTN 0x00 |
| 324 | #define CS35L36_BST_EN_SHIFT 4 |
| 325 | #define CS35L36_BST_MAN_IPKCOMP_MASK 0x200 |
| 326 | #define CS35L36_BST_MAN_IPKCOMP_SHIFT 9 |
| 327 | |
| 328 | #define CS35L36_BST_MAN_IPKCOMP_EN_MASK 0x100 |
| 329 | #define CS35L36_BST_MAN_IPKCOMP_EN_SHIFT 8 |
| 330 | |
| 331 | #define CS35L36_BST_IPK_MASK 0x7F |
| 332 | #define CS35L36_BST_OVP_THLD_MASK 0x3F |
| 333 | #define CS35L36_BST_OVP_THLD_11V 0x10 |
| 334 | #define CS35L36_BST_OVP_TRIM_MASK 0x00078000 |
| 335 | #define CS35L36_BST_OVP_TRIM_SHIFT 15 |
| 336 | #define CS35L36_BST_OVP_TRIM_11V 0x0C |
| 337 | #define CS35L36_BST_CTRL_LIM_MASK 0x04 |
| 338 | #define CS35L36_BST_CTRL_LIM_SHIFT 2 |
| 339 | #define CS35L36_BST_CTRL_10V_CLAMP 0x96 |
| 340 | |
| 341 | #define CS35L36_NG_AMP_EN_MASK 0x3F00 |
| 342 | #define CS35L36_NG_DELAY_MASK 0x70 |
| 343 | #define CS35L36_NG_DELAY_SHIFT 4 |
| 344 | #define CS35L36_AMP_ZC_SHIFT 10 |
| 345 | #define CS35L36_PDM_LDM_ENTER_SHIFT 3 |
| 346 | #define CS35L36_PDM_LDM_EXIT_SHIFT 4 |
| 347 | |
| 348 | #define CS35L36_BSTCVRT_K1_MASK 0xFF |
| 349 | #define CS35L36_BSTCVRT_K2_MASK 0xFF00 |
| 350 | #define CS35L36_BSTCVRT_K2_SHIFT 8 |
| 351 | #define CS35L36_BSTCVRT_SLOPE_MASK 0xFF00 |
| 352 | #define CS35L36_BSTCVRT_SLOPE_SHIFT 8 |
| 353 | #define CS35L36_BSTCVRT_CCMFREQ_MASK 0x0F |
| 354 | #define CS35L36_BSTCVRT_LBSTVAL_MASK 0x03 |
| 355 | #define CS35L35_BSTCVRT_CTL_MASK 0xFF |
| 356 | #define CS35L35_BSTCVRT_CTL_SEL_MASK 0x03 |
| 357 | #define CS35L36_DCM_AUTO_MASK 0x01 |
| 358 | |
| 359 | #define CS35L36_INT1_MASK_DEFAULT 0xF9BA7FFF |
| 360 | #define CS35L36_INT1_MASK_RESET 0xFFFFFFFF |
| 361 | #define CS35L36_INT3_MASK_DEFAULT 0xFFFFEFFF |
| 362 | #define CS35L36_INT3_MASK_RESET 0xFFFFFFFF |
| 363 | |
| 364 | |
| 365 | #define CS35L36_AMP_SHORT_ERR 0x1000 |
| 366 | #define CS35L36_BST_SHORT_ERR 0x40000 |
| 367 | #define CS35L36_TEMP_WARN 0x2000000 |
| 368 | #define CS35L36_TEMP_ERR 0x4000000 |
| 369 | #define CS35L36_BST_OVP_ERR 0x10000 |
| 370 | #define CS35L36_BST_DCM_UVP_ERR 0x20000 |
| 371 | |
| 372 | #define CS35L36_AMP_SHORT_ERR_RLS 0x02 |
| 373 | #define CS35L36_BST_SHORT_ERR_RLS 0x04 |
| 374 | #define CS35L36_BST_OVP_ERR_RLS 0x08 |
| 375 | #define CS35L36_BST_UVP_ERR_RLS 0x10 |
| 376 | #define CS35L36_TEMP_WARN_ERR_RLS 0x20 |
| 377 | #define CS35L36_TEMP_ERR_RLS 0x40 |
| 378 | #define CS35L36_TEMP_THLD_MASK 0x03 |
| 379 | |
| 380 | #define CS35L36_REV_B0 0xb0 |
| 381 | #define CS35L36_REV_A0 0xa0 |
| 382 | #define CS35L36_B0_PAC_PATCH 0x00DD0102 |
| 383 | |
| 384 | #define CS35L36_OTP_ECC_EN_MASK 0x400 |
| 385 | #define CS35L36_OTP_ECC_EN_SHIFT 10 |
| 386 | #define CS35L36_OTP_RUN_BOOT_MASK 0x01 |
| 387 | #define CS35L36_OTP_BOOT_DONE 0x2000000 |
| 388 | #define CS35L36_PAC_RESET_MASK 0x04 |
| 389 | #define CS35L36_PAC_RESET_SHIFT 2 |
| 390 | #define CS35L36_PAC_STALL_MASK 0x02 |
| 391 | #define CS35L36_PAC_STALL_SHIFT 1 |
| 392 | #define CS35L36_PAC_ENABLE_MASK 0x00000001 |
| 393 | #define CS35L36_PAC_MEM_ACCESS 0x01 |
| 394 | #define CS35L36_PAC_MEM_ACCESS_CLR 0 |
| 395 | #define CS35L36_SOFT_RESET 0x5AAA |
| 396 | #define CS35L36_MCU_BOOT_COMPLETE 0x02 |
| 397 | #define CS35L36_MCU_CONFIG_UNMASK 0x00FEFFFF |
| 398 | #define CS35L36_MCU_CONFIG_CLR 0x00010000 |
| 399 | #define CS35L36_MCU_CONFIG_MASK 0x00FFFFFF |
| 400 | #define CS35L36_GPIO_INT_SEL_MASK 0x0000003B |
| 401 | #define CS35L36_GPIO_INT_SEL_UNMASK 0x0000003A |
| 402 | #define CS35L36_PAC_RESET 0x00000000 |
| 403 | #define CS35L36_OTP_REV_MASK 0x00FF0000 |
| 404 | #define CS35L36_OTP_REV_L37 0x00CC0000 |
| 405 | #define CS35L36_12V_L37 37 |
| 406 | #define CS35L36_10V_L36 36 |
| 407 | |
| 408 | #define CS35L36_VPBR_EN_MASK 0x00001000 |
| 409 | #define CS35L36_VPBR_EN_SHIFT 12 |
| 410 | |
| 411 | #define CS35L36_VPBR_THLD_MASK 0x0000001F |
| 412 | #define CS35L36_VPBR_THLD_SHIFT 0 |
| 413 | #define CS35L36_VPBR_MAX_ATTN_MASK 0x00000F00 |
| 414 | #define CS35L36_VPBR_MAX_ATTN_SHIFT 8 |
| 415 | #define CS35L36_VPBR_ATK_VOL_MASK 0x0000F000 |
| 416 | #define CS35L36_VPBR_ATK_VOL_SHIFT 12 |
| 417 | #define CS35L36_VPBR_ATK_RATE_MASK 0x00070000 |
| 418 | #define CS35L36_VPBR_ATK_RATE_SHIFT 16 |
| 419 | #define CS35L36_VPBR_WAIT_MASK 0x00180000 |
| 420 | #define CS35L36_VPBR_WAIT_SHIFT 19 |
| 421 | #define CS35L36_VPBR_REL_RATE_MASK 0x00E00000 |
| 422 | #define CS35L36_VPBR_REL_RATE_SHIFT 21 |
| 423 | #define CS35L36_VPBR_MUTE_EN_MASK 0x01000000 |
| 424 | #define CS35L36_VPBR_MUTE_EN_SHIFT 24 |
| 425 | |
| 426 | #define CS35L36_OSC_FREQ_TRIM_MASK 0x070 |
| 427 | #define CS35L36_OSC_TRIM_DONE 0x08 |
| 428 | |
| 429 | #define CS35L36_FS1_DEFAULT_VAL 16 |
| 430 | #define CS35L36_FS2_DEFAULT_VAL 36 |
| 431 | #define CS35L36_FS_NOM_6MHZ 6000000 |
| 432 | |
| 433 | #define CS35L36_TEST_UNLOCK1 0x00005555 |
| 434 | #define CS35L36_TEST_UNLOCK2 0x0000AAAA |
| 435 | #define CS35L36_TEST_LOCK1 0x0000CCCC |
| 436 | #define CS35L36_TEST_LOCK2 0x00003333 |
| 437 | |
| 438 | #define CS35L36_PAC_PROG_MEM 512 |
| 439 | |
| 440 | #define CS35L36_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) |
| 441 | #define CS35L36_TX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE \ |
| 442 | | SNDRV_PCM_FMTBIT_S32_LE) |
| 443 | |
| 444 | extern const int cs35l36_a0_pac_patch[CS35L36_PAC_PROG_MEM]; |
| 445 | |
| 446 | #endif |