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Arto Merilainen0ae797a2016-12-14 13:16:13 +02001/*
2 * Copyright (c) 2015, NVIDIA Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef TEGRA_VIC_H
10#define TEGRA_VIC_H
11
12/* VIC methods */
13
14#define VIC_SET_APPLICATION_ID 0x00000200
15#define VIC_SET_FCE_UCODE_SIZE 0x0000071C
16#define VIC_SET_FCE_UCODE_OFFSET 0x0000072C
17
18/* VIC registers */
19
Thierry Redingf3779cb2019-02-01 14:28:36 +010020#define VIC_THI_STREAMID0 0x00000030
21#define VIC_THI_STREAMID1 0x00000034
22
Arto Merilainen0ae797a2016-12-14 13:16:13 +020023#define NV_PVIC_MISC_PRI_VIC_CG 0x000016d0
24#define CG_IDLE_CG_DLY_CNT(val) ((val & 0x3f) << 0)
25#define CG_IDLE_CG_EN (1 << 6)
26#define CG_WAKEUP_DLY_CNT(val) ((val & 0xf) << 16)
27
Thierry Redingf3779cb2019-02-01 14:28:36 +010028#define VIC_TFBIF_TRANSCFG 0x00002044
29#define TRANSCFG_ATT(i, v) (((v) & 0x3) << (i * 4))
30#define TRANSCFG_SID_HW 0
31#define TRANSCFG_SID_PHY 1
32#define TRANSCFG_SID_FALCON 2
33
Arto Merilainen0ae797a2016-12-14 13:16:13 +020034/* Firmware offsets */
35
36#define VIC_UCODE_FCE_HEADER_OFFSET (6*4)
37#define VIC_UCODE_FCE_DATA_OFFSET (7*4)
38#define FCE_UCODE_SIZE_OFFSET (2*4)
39
40#endif /* TEGRA_VIC_H */