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Rene Bolldorf4ff40d52011-11-17 14:25:09 +00001/*
Gabor Juhose9b62e82012-03-14 10:36:14 +01002 * Atheros AR724X PCI host controller driver
Rene Bolldorf4ff40d52011-11-17 14:25:09 +00003 *
4 * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
Gabor Juhose9b62e82012-03-14 10:36:14 +01005 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
Rene Bolldorf4ff40d52011-11-17 14:25:09 +00006 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
Gabor Juhos4c07c7d2012-03-14 10:36:07 +010012#include <linux/irq.h>
Rene Bolldorf4ff40d52011-11-17 14:25:09 +000013#include <linux/pci.h>
Paul Gortmaker27220902016-08-21 15:58:16 -040014#include <linux/init.h>
Mathias Kresin0316b052018-07-20 13:58:25 +020015#include <linux/delay.h>
Gabor Juhos58d2e9b2013-02-02 11:40:42 +000016#include <linux/platform_device.h>
Gabor Juhos6015a852012-03-14 10:36:05 +010017#include <asm/mach-ath79/ath79.h>
Gabor Juhos4c07c7d2012-03-14 10:36:07 +010018#include <asm/mach-ath79/ar71xx_regs.h>
Rene Bolldorf4ff40d52011-11-17 14:25:09 +000019
Mathias Kresin0316b052018-07-20 13:58:25 +020020#define AR724X_PCI_REG_APP 0x00
Gabor Juhosa1dca312012-08-23 15:35:26 +020021#define AR724X_PCI_REG_RESET 0x18
Gabor Juhos4c07c7d2012-03-14 10:36:07 +010022#define AR724X_PCI_REG_INT_STATUS 0x4c
23#define AR724X_PCI_REG_INT_MASK 0x50
24
Mathias Kresin0316b052018-07-20 13:58:25 +020025#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
26
Gabor Juhosa1dca312012-08-23 15:35:26 +020027#define AR724X_PCI_RESET_LINK_UP BIT(0)
28
Gabor Juhos4c07c7d2012-03-14 10:36:07 +010029#define AR724X_PCI_INT_DEV0 BIT(14)
30
31#define AR724X_PCI_IRQ_COUNT 1
32
Gabor Juhos6015a852012-03-14 10:36:05 +010033#define AR7240_BAR0_WAR_VALUE 0xffff
34
Gabor Juhos12401fc2013-02-03 14:52:47 +000035#define AR724X_PCI_CMD_INIT (PCI_COMMAND_MEMORY | \
36 PCI_COMMAND_MASTER | \
37 PCI_COMMAND_INVALIDATE | \
38 PCI_COMMAND_PARITY | \
39 PCI_COMMAND_SERR | \
40 PCI_COMMAND_FAST_BACK)
41
Gabor Juhos908339e2013-02-03 09:58:38 +000042struct ar724x_pci_controller {
43 void __iomem *devcfg_base;
44 void __iomem *ctrl_base;
Gabor Juhos12401fc2013-02-03 14:52:47 +000045 void __iomem *crp_base;
Rene Bolldorf4ff40d52011-11-17 14:25:09 +000046
Gabor Juhos908339e2013-02-03 09:58:38 +000047 int irq;
Gabor Juhos8b66d462013-02-03 10:00:16 +000048 int irq_base;
Gabor Juhosa1dca312012-08-23 15:35:26 +020049
Gabor Juhos908339e2013-02-03 09:58:38 +000050 bool link_up;
51 bool bar0_is_cached;
52 u32 bar0_value;
53
Gabor Juhos908339e2013-02-03 09:58:38 +000054 struct pci_controller pci_controller;
Gabor Juhos34b134a2013-02-03 09:59:45 +000055 struct resource io_res;
56 struct resource mem_res;
Gabor Juhos908339e2013-02-03 09:58:38 +000057};
58
59static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
Gabor Juhosa1dca312012-08-23 15:35:26 +020060{
61 u32 reset;
62
Gabor Juhos908339e2013-02-03 09:58:38 +000063 reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET);
Gabor Juhosa1dca312012-08-23 15:35:26 +020064 return reset & AR724X_PCI_RESET_LINK_UP;
65}
Gabor Juhos6015a852012-03-14 10:36:05 +010066
Gabor Juhos908339e2013-02-03 09:58:38 +000067static inline struct ar724x_pci_controller *
68pci_bus_to_ar724x_controller(struct pci_bus *bus)
69{
70 struct pci_controller *hose;
71
72 hose = (struct pci_controller *) bus->sysdata;
73 return container_of(hose, struct ar724x_pci_controller, pci_controller);
74}
75
Gabor Juhos12401fc2013-02-03 14:52:47 +000076static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
77 int where, int size, u32 value)
78{
Gabor Juhos12401fc2013-02-03 14:52:47 +000079 void __iomem *base;
80 u32 data;
81 int s;
82
83 WARN_ON(where & (size - 1));
84
85 if (!apc->link_up)
86 return PCIBIOS_DEVICE_NOT_FOUND;
87
88 base = apc->crp_base;
Gabor Juhos12401fc2013-02-03 14:52:47 +000089 data = __raw_readl(base + (where & ~3));
90
91 switch (size) {
92 case 1:
93 s = ((where & 3) * 8);
94 data &= ~(0xff << s);
95 data |= ((value & 0xff) << s);
96 break;
97 case 2:
98 s = ((where & 2) * 8);
99 data &= ~(0xffff << s);
100 data |= ((value & 0xffff) << s);
101 break;
102 case 4:
103 data = value;
104 break;
105 default:
Gabor Juhos12401fc2013-02-03 14:52:47 +0000106 return PCIBIOS_BAD_REGISTER_NUMBER;
107 }
108
109 __raw_writel(data, base + (where & ~3));
110 /* flush write */
111 __raw_readl(base + (where & ~3));
Gabor Juhos12401fc2013-02-03 14:52:47 +0000112
113 return PCIBIOS_SUCCESSFUL;
114}
115
Gabor Juhosd624bd32012-03-14 10:29:26 +0100116static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000117 int size, uint32_t *value)
118{
Gabor Juhos908339e2013-02-03 09:58:38 +0000119 struct ar724x_pci_controller *apc;
Gabor Juhosc1984412012-03-14 10:29:27 +0100120 void __iomem *base;
Gabor Juhos64adb6b2012-03-14 10:36:04 +0100121 u32 data;
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000122
Gabor Juhos908339e2013-02-03 09:58:38 +0000123 apc = pci_bus_to_ar724x_controller(bus);
124 if (!apc->link_up)
Gabor Juhosa1dca312012-08-23 15:35:26 +0200125 return PCIBIOS_DEVICE_NOT_FOUND;
126
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000127 if (devfn)
128 return PCIBIOS_DEVICE_NOT_FOUND;
129
Gabor Juhos908339e2013-02-03 09:58:38 +0000130 base = apc->devcfg_base;
Gabor Juhos64adb6b2012-03-14 10:36:04 +0100131 data = __raw_readl(base + (where & ~3));
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000132
133 switch (size) {
134 case 1:
Gabor Juhos64adb6b2012-03-14 10:36:04 +0100135 if (where & 1)
136 data >>= 8;
137 if (where & 2)
138 data >>= 16;
139 data &= 0xff;
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000140 break;
141 case 2:
Gabor Juhos64adb6b2012-03-14 10:36:04 +0100142 if (where & 2)
143 data >>= 16;
144 data &= 0xffff;
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000145 break;
146 case 4:
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000147 break;
148 default:
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000149 return PCIBIOS_BAD_REGISTER_NUMBER;
150 }
151
Gabor Juhos6015a852012-03-14 10:36:05 +0100152 if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
Gabor Juhos908339e2013-02-03 09:58:38 +0000153 apc->bar0_is_cached) {
Gabor Juhos6015a852012-03-14 10:36:05 +0100154 /* use the cached value */
Gabor Juhos908339e2013-02-03 09:58:38 +0000155 *value = apc->bar0_value;
Gabor Juhos6015a852012-03-14 10:36:05 +0100156 } else {
157 *value = data;
158 }
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000159
160 return PCIBIOS_SUCCESSFUL;
161}
162
Gabor Juhosd624bd32012-03-14 10:29:26 +0100163static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000164 int size, uint32_t value)
165{
Gabor Juhos908339e2013-02-03 09:58:38 +0000166 struct ar724x_pci_controller *apc;
Gabor Juhosc1984412012-03-14 10:29:27 +0100167 void __iomem *base;
Gabor Juhos64adb6b2012-03-14 10:36:04 +0100168 u32 data;
169 int s;
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000170
Gabor Juhos908339e2013-02-03 09:58:38 +0000171 apc = pci_bus_to_ar724x_controller(bus);
172 if (!apc->link_up)
Gabor Juhosa1dca312012-08-23 15:35:26 +0200173 return PCIBIOS_DEVICE_NOT_FOUND;
174
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000175 if (devfn)
176 return PCIBIOS_DEVICE_NOT_FOUND;
177
Gabor Juhos6015a852012-03-14 10:36:05 +0100178 if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) {
179 if (value != 0xffffffff) {
180 /*
181 * WAR for a hw issue. If the BAR0 register of the
182 * device is set to the proper base address, the
183 * memory space of the device is not accessible.
184 *
185 * Cache the intended value so it can be read back,
186 * and write a SoC specific constant value to the
187 * BAR0 register in order to make the device memory
188 * accessible.
189 */
Gabor Juhos908339e2013-02-03 09:58:38 +0000190 apc->bar0_is_cached = true;
191 apc->bar0_value = value;
Gabor Juhos6015a852012-03-14 10:36:05 +0100192
193 value = AR7240_BAR0_WAR_VALUE;
194 } else {
Gabor Juhos908339e2013-02-03 09:58:38 +0000195 apc->bar0_is_cached = false;
Gabor Juhos6015a852012-03-14 10:36:05 +0100196 }
197 }
198
Gabor Juhos908339e2013-02-03 09:58:38 +0000199 base = apc->devcfg_base;
Gabor Juhos64adb6b2012-03-14 10:36:04 +0100200 data = __raw_readl(base + (where & ~3));
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000201
202 switch (size) {
203 case 1:
Gabor Juhos64adb6b2012-03-14 10:36:04 +0100204 s = ((where & 3) * 8);
205 data &= ~(0xff << s);
206 data |= ((value & 0xff) << s);
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000207 break;
208 case 2:
Gabor Juhos64adb6b2012-03-14 10:36:04 +0100209 s = ((where & 2) * 8);
210 data &= ~(0xffff << s);
211 data |= ((value & 0xffff) << s);
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000212 break;
213 case 4:
Gabor Juhos64adb6b2012-03-14 10:36:04 +0100214 data = value;
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000215 break;
216 default:
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000217 return PCIBIOS_BAD_REGISTER_NUMBER;
218 }
219
Gabor Juhos64adb6b2012-03-14 10:36:04 +0100220 __raw_writel(data, base + (where & ~3));
221 /* flush write */
222 __raw_readl(base + (where & ~3));
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000223
224 return PCIBIOS_SUCCESSFUL;
225}
226
Gabor Juhosd624bd32012-03-14 10:29:26 +0100227static struct pci_ops ar724x_pci_ops = {
228 .read = ar724x_pci_read,
229 .write = ar724x_pci_write,
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000230};
231
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200232static void ar724x_pci_irq_handler(struct irq_desc *desc)
Rene Bolldorf4ff40d52011-11-17 14:25:09 +0000233{
Gabor Juhos908339e2013-02-03 09:58:38 +0000234 struct ar724x_pci_controller *apc;
Gabor Juhos4c07c7d2012-03-14 10:36:07 +0100235 void __iomem *base;
236 u32 pending;
237
Jiang Liu25aae562015-05-20 17:59:51 +0800238 apc = irq_desc_get_handler_data(desc);
Gabor Juhos908339e2013-02-03 09:58:38 +0000239 base = apc->ctrl_base;
Gabor Juhos4c07c7d2012-03-14 10:36:07 +0100240
241 pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
242 __raw_readl(base + AR724X_PCI_REG_INT_MASK);
243
244 if (pending & AR724X_PCI_INT_DEV0)
Gabor Juhos8b66d462013-02-03 10:00:16 +0000245 generic_handle_irq(apc->irq_base + 0);
Gabor Juhos4c07c7d2012-03-14 10:36:07 +0100246
247 else
248 spurious_interrupt();
249}
250
251static void ar724x_pci_irq_unmask(struct irq_data *d)
252{
Gabor Juhos908339e2013-02-03 09:58:38 +0000253 struct ar724x_pci_controller *apc;
Gabor Juhos4c07c7d2012-03-14 10:36:07 +0100254 void __iomem *base;
Gabor Juhos8b66d462013-02-03 10:00:16 +0000255 int offset;
Gabor Juhos4c07c7d2012-03-14 10:36:07 +0100256 u32 t;
257
Gabor Juhos908339e2013-02-03 09:58:38 +0000258 apc = irq_data_get_irq_chip_data(d);
259 base = apc->ctrl_base;
Gabor Juhos8b66d462013-02-03 10:00:16 +0000260 offset = apc->irq_base - d->irq;
Gabor Juhos4c07c7d2012-03-14 10:36:07 +0100261
Gabor Juhos8b66d462013-02-03 10:00:16 +0000262 switch (offset) {
263 case 0:
Gabor Juhos4c07c7d2012-03-14 10:36:07 +0100264 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
265 __raw_writel(t | AR724X_PCI_INT_DEV0,
266 base + AR724X_PCI_REG_INT_MASK);
267 /* flush write */
268 __raw_readl(base + AR724X_PCI_REG_INT_MASK);
269 }
270}
271
272static void ar724x_pci_irq_mask(struct irq_data *d)
273{
Gabor Juhos908339e2013-02-03 09:58:38 +0000274 struct ar724x_pci_controller *apc;
Gabor Juhos4c07c7d2012-03-14 10:36:07 +0100275 void __iomem *base;
Gabor Juhos8b66d462013-02-03 10:00:16 +0000276 int offset;
Gabor Juhos4c07c7d2012-03-14 10:36:07 +0100277 u32 t;
278
Gabor Juhos908339e2013-02-03 09:58:38 +0000279 apc = irq_data_get_irq_chip_data(d);
280 base = apc->ctrl_base;
Gabor Juhos8b66d462013-02-03 10:00:16 +0000281 offset = apc->irq_base - d->irq;
Gabor Juhos4c07c7d2012-03-14 10:36:07 +0100282
Gabor Juhos8b66d462013-02-03 10:00:16 +0000283 switch (offset) {
284 case 0:
Gabor Juhos4c07c7d2012-03-14 10:36:07 +0100285 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
286 __raw_writel(t & ~AR724X_PCI_INT_DEV0,
287 base + AR724X_PCI_REG_INT_MASK);
288
289 /* flush write */
290 __raw_readl(base + AR724X_PCI_REG_INT_MASK);
291
292 t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
293 __raw_writel(t | AR724X_PCI_INT_DEV0,
294 base + AR724X_PCI_REG_INT_STATUS);
295
296 /* flush write */
297 __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
298 }
299}
300
301static struct irq_chip ar724x_pci_irq_chip = {
302 .name = "AR724X PCI ",
303 .irq_mask = ar724x_pci_irq_mask,
304 .irq_unmask = ar724x_pci_irq_unmask,
305 .irq_mask_ack = ar724x_pci_irq_mask,
306};
307
Gabor Juhos8b66d462013-02-03 10:00:16 +0000308static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
309 int id)
Gabor Juhos4c07c7d2012-03-14 10:36:07 +0100310{
311 void __iomem *base;
312 int i;
313
Gabor Juhos908339e2013-02-03 09:58:38 +0000314 base = apc->ctrl_base;
Gabor Juhos4c07c7d2012-03-14 10:36:07 +0100315
316 __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
317 __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
318
Gabor Juhos8b66d462013-02-03 10:00:16 +0000319 apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
Gabor Juhos4c07c7d2012-03-14 10:36:07 +0100320
Gabor Juhos8b66d462013-02-03 10:00:16 +0000321 for (i = apc->irq_base;
322 i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
Gabor Juhos4c07c7d2012-03-14 10:36:07 +0100323 irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
324 handle_level_irq);
Gabor Juhos908339e2013-02-03 09:58:38 +0000325 irq_set_chip_data(i, apc);
326 }
Gabor Juhos4c07c7d2012-03-14 10:36:07 +0100327
Thomas Gleixner4d3f77d2015-07-13 20:45:56 +0000328 irq_set_chained_handler_and_data(apc->irq, ar724x_pci_irq_handler,
329 apc);
Gabor Juhos4c07c7d2012-03-14 10:36:07 +0100330}
331
Mathias Kresin0316b052018-07-20 13:58:25 +0200332static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc)
333{
334 u32 ppl, app;
335 int wait = 0;
336
337 /* deassert PCIe host controller and PCIe PHY reset */
338 ath79_device_reset_clear(AR724X_RESET_PCIE);
339 ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
340
341 /* remove the reset of the PCIE PLL */
342 ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
343 ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
344 ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
345
346 /* deassert bypass for the PCIE PLL */
347 ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
348 ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
349 ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
350
351 /* set PCIE Application Control to ready */
352 app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
353 app |= AR724X_PCI_APP_LTSSM_ENABLE;
354 __raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP);
355
356 /* wait up to 100ms for PHY link up */
357 do {
358 mdelay(10);
359 wait++;
360 } while (wait < 10 && !ar724x_pci_check_link(apc));
361}
362
Gabor Juhos58d2e9b2013-02-02 11:40:42 +0000363static int ar724x_pci_probe(struct platform_device *pdev)
364{
Gabor Juhos908339e2013-02-03 09:58:38 +0000365 struct ar724x_pci_controller *apc;
Gabor Juhos58d2e9b2013-02-02 11:40:42 +0000366 struct resource *res;
Gabor Juhos8b66d462013-02-03 10:00:16 +0000367 int id;
368
369 id = pdev->id;
370 if (id == -1)
371 id = 0;
Gabor Juhos908339e2013-02-03 09:58:38 +0000372
373 apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
374 GFP_KERNEL);
375 if (!apc)
376 return -ENOMEM;
Gabor Juhos58d2e9b2013-02-02 11:40:42 +0000377
378 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
Silviu-Mihai Popescuf560fab2013-03-12 10:30:05 +0000379 apc->ctrl_base = devm_ioremap_resource(&pdev->dev, res);
380 if (IS_ERR(apc->ctrl_base))
381 return PTR_ERR(apc->ctrl_base);
Gabor Juhos58d2e9b2013-02-02 11:40:42 +0000382
383 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
Silviu-Mihai Popescuf560fab2013-03-12 10:30:05 +0000384 apc->devcfg_base = devm_ioremap_resource(&pdev->dev, res);
385 if (IS_ERR(apc->devcfg_base))
386 return PTR_ERR(apc->devcfg_base);
Gabor Juhos58d2e9b2013-02-02 11:40:42 +0000387
Gabor Juhos12401fc2013-02-03 14:52:47 +0000388 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base");
Silviu-Mihai Popescuf560fab2013-03-12 10:30:05 +0000389 apc->crp_base = devm_ioremap_resource(&pdev->dev, res);
390 if (IS_ERR(apc->crp_base))
391 return PTR_ERR(apc->crp_base);
Gabor Juhos12401fc2013-02-03 14:52:47 +0000392
Gabor Juhos908339e2013-02-03 09:58:38 +0000393 apc->irq = platform_get_irq(pdev, 0);
394 if (apc->irq < 0)
Gabor Juhos58d2e9b2013-02-02 11:40:42 +0000395 return -EINVAL;
396
Gabor Juhos34b134a2013-02-03 09:59:45 +0000397 res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
398 if (!res)
399 return -EINVAL;
400
401 apc->io_res.parent = res;
402 apc->io_res.name = "PCI IO space";
403 apc->io_res.start = res->start;
404 apc->io_res.end = res->end;
405 apc->io_res.flags = IORESOURCE_IO;
406
407 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
408 if (!res)
409 return -EINVAL;
410
411 apc->mem_res.parent = res;
412 apc->mem_res.name = "PCI memory space";
413 apc->mem_res.start = res->start;
414 apc->mem_res.end = res->end;
415 apc->mem_res.flags = IORESOURCE_MEM;
416
Gabor Juhos908339e2013-02-03 09:58:38 +0000417 apc->pci_controller.pci_ops = &ar724x_pci_ops;
Gabor Juhos34b134a2013-02-03 09:59:45 +0000418 apc->pci_controller.io_resource = &apc->io_res;
419 apc->pci_controller.mem_resource = &apc->mem_res;
Gabor Juhos908339e2013-02-03 09:58:38 +0000420
Mathias Kresin0316b052018-07-20 13:58:25 +0200421 /*
422 * Do the full PCIE Root Complex Initialization Sequence if the PCIe
423 * host controller is in reset.
424 */
425 if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
426 ar724x_pci_hw_init(apc);
427
Gabor Juhos908339e2013-02-03 09:58:38 +0000428 apc->link_up = ar724x_pci_check_link(apc);
429 if (!apc->link_up)
Gabor Juhos58d2e9b2013-02-02 11:40:42 +0000430 dev_warn(&pdev->dev, "PCIe link is down\n");
431
Gabor Juhos8b66d462013-02-03 10:00:16 +0000432 ar724x_pci_irq_init(apc, id);
Gabor Juhos58d2e9b2013-02-02 11:40:42 +0000433
Gabor Juhos12401fc2013-02-03 14:52:47 +0000434 ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT);
435
Gabor Juhos908339e2013-02-03 09:58:38 +0000436 register_pci_controller(&apc->pci_controller);
Gabor Juhos58d2e9b2013-02-02 11:40:42 +0000437
438 return 0;
439}
440
441static struct platform_driver ar724x_pci_driver = {
442 .probe = ar724x_pci_probe,
443 .driver = {
444 .name = "ar724x-pci",
Gabor Juhos58d2e9b2013-02-02 11:40:42 +0000445 },
446};
447
448static int __init ar724x_pci_init(void)
449{
450 return platform_driver_register(&ar724x_pci_driver);
451}
452
453postcore_initcall(ar724x_pci_init);