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Boris BREZILLON1fef62c2014-10-21 15:08:41 +02001/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
3 *
4 * Derived from:
5 * https://github.com/yuq/sunxi-nfc-mtd
6 * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
7 *
8 * https://github.com/hno/Allwinner-Info
9 * Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
10 *
11 * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
12 * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 */
24
25#include <linux/dma-mapping.h>
26#include <linux/slab.h>
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/platform_device.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
32#include <linux/of_gpio.h>
33#include <linux/of_mtd.h>
34#include <linux/mtd/mtd.h>
35#include <linux/mtd/nand.h>
36#include <linux/mtd/partitions.h>
37#include <linux/clk.h>
38#include <linux/delay.h>
39#include <linux/dmaengine.h>
40#include <linux/gpio.h>
41#include <linux/interrupt.h>
42#include <linux/io.h>
43
44#define NFC_REG_CTL 0x0000
45#define NFC_REG_ST 0x0004
46#define NFC_REG_INT 0x0008
47#define NFC_REG_TIMING_CTL 0x000C
48#define NFC_REG_TIMING_CFG 0x0010
49#define NFC_REG_ADDR_LOW 0x0014
50#define NFC_REG_ADDR_HIGH 0x0018
51#define NFC_REG_SECTOR_NUM 0x001C
52#define NFC_REG_CNT 0x0020
53#define NFC_REG_CMD 0x0024
54#define NFC_REG_RCMD_SET 0x0028
55#define NFC_REG_WCMD_SET 0x002C
56#define NFC_REG_IO_DATA 0x0030
57#define NFC_REG_ECC_CTL 0x0034
58#define NFC_REG_ECC_ST 0x0038
59#define NFC_REG_DEBUG 0x003C
60#define NFC_REG_ECC_CNT0 0x0040
61#define NFC_REG_ECC_CNT1 0x0044
62#define NFC_REG_ECC_CNT2 0x0048
63#define NFC_REG_ECC_CNT3 0x004c
64#define NFC_REG_USER_DATA_BASE 0x0050
65#define NFC_REG_SPARE_AREA 0x00A0
66#define NFC_RAM0_BASE 0x0400
67#define NFC_RAM1_BASE 0x0800
68
69/* define bit use in NFC_CTL */
70#define NFC_EN BIT(0)
71#define NFC_RESET BIT(1)
72#define NFC_BUS_WIDYH BIT(2)
73#define NFC_RB_SEL BIT(3)
74#define NFC_CE_SEL GENMASK(26, 24)
75#define NFC_CE_CTL BIT(6)
76#define NFC_CE_CTL1 BIT(7)
77#define NFC_PAGE_SIZE GENMASK(11, 8)
78#define NFC_SAM BIT(12)
79#define NFC_RAM_METHOD BIT(14)
80#define NFC_DEBUG_CTL BIT(31)
81
82/* define bit use in NFC_ST */
83#define NFC_RB_B2R BIT(0)
84#define NFC_CMD_INT_FLAG BIT(1)
85#define NFC_DMA_INT_FLAG BIT(2)
86#define NFC_CMD_FIFO_STATUS BIT(3)
87#define NFC_STA BIT(4)
88#define NFC_NATCH_INT_FLAG BIT(5)
89#define NFC_RB_STATE0 BIT(8)
90#define NFC_RB_STATE1 BIT(9)
91#define NFC_RB_STATE2 BIT(10)
92#define NFC_RB_STATE3 BIT(11)
93
94/* define bit use in NFC_INT */
95#define NFC_B2R_INT_ENABLE BIT(0)
96#define NFC_CMD_INT_ENABLE BIT(1)
97#define NFC_DMA_INT_ENABLE BIT(2)
98#define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
99 NFC_CMD_INT_ENABLE | \
100 NFC_DMA_INT_ENABLE)
101
Roy Splietd052e502015-06-26 11:00:11 +0200102/* define bit use in NFC_TIMING_CTL */
103#define NFC_TIMING_CTL_EDO BIT(8)
104
Roy Spliet9c618292015-06-26 11:00:10 +0200105/* define NFC_TIMING_CFG register layout */
106#define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \
107 (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \
108 (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \
109 (((tCAD) & 0x7) << 8))
110
Boris BREZILLON1fef62c2014-10-21 15:08:41 +0200111/* define bit use in NFC_CMD */
112#define NFC_CMD_LOW_BYTE GENMASK(7, 0)
113#define NFC_CMD_HIGH_BYTE GENMASK(15, 8)
114#define NFC_ADR_NUM GENMASK(18, 16)
115#define NFC_SEND_ADR BIT(19)
116#define NFC_ACCESS_DIR BIT(20)
117#define NFC_DATA_TRANS BIT(21)
118#define NFC_SEND_CMD1 BIT(22)
119#define NFC_WAIT_FLAG BIT(23)
120#define NFC_SEND_CMD2 BIT(24)
121#define NFC_SEQ BIT(25)
122#define NFC_DATA_SWAP_METHOD BIT(26)
123#define NFC_ROW_AUTO_INC BIT(27)
124#define NFC_SEND_CMD3 BIT(28)
125#define NFC_SEND_CMD4 BIT(29)
126#define NFC_CMD_TYPE GENMASK(31, 30)
127
128/* define bit use in NFC_RCMD_SET */
129#define NFC_READ_CMD GENMASK(7, 0)
130#define NFC_RANDOM_READ_CMD0 GENMASK(15, 8)
131#define NFC_RANDOM_READ_CMD1 GENMASK(23, 16)
132
133/* define bit use in NFC_WCMD_SET */
134#define NFC_PROGRAM_CMD GENMASK(7, 0)
135#define NFC_RANDOM_WRITE_CMD GENMASK(15, 8)
136#define NFC_READ_CMD0 GENMASK(23, 16)
137#define NFC_READ_CMD1 GENMASK(31, 24)
138
139/* define bit use in NFC_ECC_CTL */
140#define NFC_ECC_EN BIT(0)
141#define NFC_ECC_PIPELINE BIT(3)
142#define NFC_ECC_EXCEPTION BIT(4)
143#define NFC_ECC_BLOCK_SIZE BIT(5)
144#define NFC_RANDOM_EN BIT(9)
145#define NFC_RANDOM_DIRECTION BIT(10)
146#define NFC_ECC_MODE_SHIFT 12
147#define NFC_ECC_MODE GENMASK(15, 12)
148#define NFC_RANDOM_SEED GENMASK(30, 16)
149
Boris BREZILLON03a0e8a2015-09-14 10:41:03 +0200150/* NFC_USER_DATA helper macros */
151#define NFC_BUF_TO_USER_DATA(buf) ((buf)[0] | ((buf)[1] << 8) | \
152 ((buf)[2] << 16) | ((buf)[3] << 24))
153
Boris BREZILLON1fef62c2014-10-21 15:08:41 +0200154#define NFC_DEFAULT_TIMEOUT_MS 1000
155
156#define NFC_SRAM_SIZE 1024
157
158#define NFC_MAX_CS 7
159
160/*
161 * Ready/Busy detection type: describes the Ready/Busy detection modes
162 *
163 * @RB_NONE: no external detection available, rely on STATUS command
164 * and software timeouts
165 * @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy
166 * pin of the NAND flash chip must be connected to one of the
167 * native NAND R/B pins (those which can be muxed to the NAND
168 * Controller)
169 * @RB_GPIO: use a simple GPIO to handle Ready/Busy status. The Ready/Busy
170 * pin of the NAND flash chip must be connected to a GPIO capable
171 * pin.
172 */
173enum sunxi_nand_rb_type {
174 RB_NONE,
175 RB_NATIVE,
176 RB_GPIO,
177};
178
179/*
180 * Ready/Busy structure: stores information related to Ready/Busy detection
181 *
182 * @type: the Ready/Busy detection mode
183 * @info: information related to the R/B detection mode. Either a gpio
184 * id or a native R/B id (those supported by the NAND controller).
185 */
186struct sunxi_nand_rb {
187 enum sunxi_nand_rb_type type;
188 union {
189 int gpio;
190 int nativeid;
191 } info;
192};
193
194/*
195 * Chip Select structure: stores information related to NAND Chip Select
196 *
197 * @cs: the NAND CS id used to communicate with a NAND Chip
198 * @rb: the Ready/Busy description
199 */
200struct sunxi_nand_chip_sel {
201 u8 cs;
202 struct sunxi_nand_rb rb;
203};
204
205/*
206 * sunxi HW ECC infos: stores information related to HW ECC support
207 *
208 * @mode: the sunxi ECC mode field deduced from ECC requirements
209 * @layout: the OOB layout depending on the ECC requirements and the
210 * selected ECC mode
211 */
212struct sunxi_nand_hw_ecc {
213 int mode;
214 struct nand_ecclayout layout;
215};
216
217/*
218 * NAND chip structure: stores NAND chip device related information
219 *
220 * @node: used to store NAND chips into a list
221 * @nand: base NAND chip structure
222 * @mtd: base MTD structure
223 * @clk_rate: clk_rate required for this NAND chip
Roy Spliet9c618292015-06-26 11:00:10 +0200224 * @timing_cfg TIMING_CFG register value for this NAND chip
Boris BREZILLON1fef62c2014-10-21 15:08:41 +0200225 * @selected: current active CS
226 * @nsels: number of CS lines required by the NAND chip
227 * @sels: array of CS lines descriptions
228 */
229struct sunxi_nand_chip {
230 struct list_head node;
231 struct nand_chip nand;
232 struct mtd_info mtd;
233 unsigned long clk_rate;
Roy Spliet9c618292015-06-26 11:00:10 +0200234 u32 timing_cfg;
Roy Splietd052e502015-06-26 11:00:11 +0200235 u32 timing_ctl;
Boris BREZILLON1fef62c2014-10-21 15:08:41 +0200236 int selected;
237 int nsels;
238 struct sunxi_nand_chip_sel sels[0];
239};
240
241static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
242{
243 return container_of(nand, struct sunxi_nand_chip, nand);
244}
245
246/*
247 * NAND Controller structure: stores sunxi NAND controller information
248 *
249 * @controller: base controller structure
250 * @dev: parent device (used to print error messages)
251 * @regs: NAND controller registers
252 * @ahb_clk: NAND Controller AHB clock
253 * @mod_clk: NAND Controller mod clock
254 * @assigned_cs: bitmask describing already assigned CS lines
255 * @clk_rate: NAND controller current clock rate
256 * @chips: a list containing all the NAND chips attached to
257 * this NAND controller
258 * @complete: a completion object used to wait for NAND
259 * controller events
260 */
261struct sunxi_nfc {
262 struct nand_hw_control controller;
263 struct device *dev;
264 void __iomem *regs;
265 struct clk *ahb_clk;
266 struct clk *mod_clk;
267 unsigned long assigned_cs;
268 unsigned long clk_rate;
269 struct list_head chips;
270 struct completion complete;
271};
272
273static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
274{
275 return container_of(ctrl, struct sunxi_nfc, controller);
276}
277
278static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id)
279{
280 struct sunxi_nfc *nfc = dev_id;
281 u32 st = readl(nfc->regs + NFC_REG_ST);
282 u32 ien = readl(nfc->regs + NFC_REG_INT);
283
284 if (!(ien & st))
285 return IRQ_NONE;
286
287 if ((ien & st) == ien)
288 complete(&nfc->complete);
289
290 writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
291 writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
292
293 return IRQ_HANDLED;
294}
295
296static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
297 unsigned int timeout_ms)
298{
299 init_completion(&nfc->complete);
300
301 writel(flags, nfc->regs + NFC_REG_INT);
302
303 if (!timeout_ms)
304 timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
305
306 if (!wait_for_completion_timeout(&nfc->complete,
307 msecs_to_jiffies(timeout_ms))) {
308 dev_err(nfc->dev, "wait interrupt timedout\n");
309 return -ETIMEDOUT;
310 }
311
312 return 0;
313}
314
315static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
316{
317 unsigned long timeout = jiffies +
318 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS);
319
320 do {
321 if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
322 return 0;
323 } while (time_before(jiffies, timeout));
324
325 dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
326 return -ETIMEDOUT;
327}
328
329static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
330{
331 unsigned long timeout = jiffies +
332 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS);
333
334 writel(0, nfc->regs + NFC_REG_ECC_CTL);
335 writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
336
337 do {
338 if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET))
339 return 0;
340 } while (time_before(jiffies, timeout));
341
342 dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
343 return -ETIMEDOUT;
344}
345
346static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
347{
348 struct nand_chip *nand = mtd->priv;
349 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
350 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
351 struct sunxi_nand_rb *rb;
352 unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
353 int ret;
354
355 if (sunxi_nand->selected < 0)
356 return 0;
357
358 rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
359
360 switch (rb->type) {
361 case RB_NATIVE:
362 ret = !!(readl(nfc->regs + NFC_REG_ST) &
363 (NFC_RB_STATE0 << rb->info.nativeid));
364 if (ret)
365 break;
366
367 sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
368 ret = !!(readl(nfc->regs + NFC_REG_ST) &
369 (NFC_RB_STATE0 << rb->info.nativeid));
370 break;
371 case RB_GPIO:
372 ret = gpio_get_value(rb->info.gpio);
373 break;
374 case RB_NONE:
375 default:
376 ret = 0;
377 dev_err(nfc->dev, "cannot check R/B NAND status!\n");
378 break;
379 }
380
381 return ret;
382}
383
384static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
385{
386 struct nand_chip *nand = mtd->priv;
387 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
388 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
389 struct sunxi_nand_chip_sel *sel;
390 u32 ctl;
391
392 if (chip > 0 && chip >= sunxi_nand->nsels)
393 return;
394
395 if (chip == sunxi_nand->selected)
396 return;
397
398 ctl = readl(nfc->regs + NFC_REG_CTL) &
399 ~(NFC_CE_SEL | NFC_RB_SEL | NFC_EN);
400
401 if (chip >= 0) {
402 sel = &sunxi_nand->sels[chip];
403
404 ctl |= (sel->cs << 24) | NFC_EN |
405 (((nand->page_shift - 10) & 0xf) << 8);
406 if (sel->rb.type == RB_NONE) {
407 nand->dev_ready = NULL;
408 } else {
409 nand->dev_ready = sunxi_nfc_dev_ready;
410 if (sel->rb.type == RB_NATIVE)
411 ctl |= (sel->rb.info.nativeid << 3);
412 }
413
414 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
415
416 if (nfc->clk_rate != sunxi_nand->clk_rate) {
417 clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
418 nfc->clk_rate = sunxi_nand->clk_rate;
419 }
420 }
421
Roy Splietd052e502015-06-26 11:00:11 +0200422 writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
Roy Spliet9c618292015-06-26 11:00:10 +0200423 writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
Boris BREZILLON1fef62c2014-10-21 15:08:41 +0200424 writel(ctl, nfc->regs + NFC_REG_CTL);
425
426 sunxi_nand->selected = chip;
427}
428
429static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
430{
431 struct nand_chip *nand = mtd->priv;
432 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
433 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
434 int ret;
435 int cnt;
436 int offs = 0;
437 u32 tmp;
438
439 while (len > offs) {
440 cnt = min(len - offs, NFC_SRAM_SIZE);
441
442 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
443 if (ret)
444 break;
445
446 writel(cnt, nfc->regs + NFC_REG_CNT);
447 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
448 writel(tmp, nfc->regs + NFC_REG_CMD);
449
450 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
451 if (ret)
452 break;
453
454 if (buf)
455 memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
456 cnt);
457 offs += cnt;
458 }
459}
460
461static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
462 int len)
463{
464 struct nand_chip *nand = mtd->priv;
465 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
466 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
467 int ret;
468 int cnt;
469 int offs = 0;
470 u32 tmp;
471
472 while (len > offs) {
473 cnt = min(len - offs, NFC_SRAM_SIZE);
474
475 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
476 if (ret)
477 break;
478
479 writel(cnt, nfc->regs + NFC_REG_CNT);
480 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
481 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
482 NFC_ACCESS_DIR;
483 writel(tmp, nfc->regs + NFC_REG_CMD);
484
485 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
486 if (ret)
487 break;
488
489 offs += cnt;
490 }
491}
492
493static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
494{
495 uint8_t ret;
496
497 sunxi_nfc_read_buf(mtd, &ret, 1);
498
499 return ret;
500}
501
502static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
503 unsigned int ctrl)
504{
505 struct nand_chip *nand = mtd->priv;
506 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
507 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
508 int ret;
509 u32 tmp;
510
511 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
512 if (ret)
513 return;
514
515 if (ctrl & NAND_CTRL_CHANGE) {
516 tmp = readl(nfc->regs + NFC_REG_CTL);
517 if (ctrl & NAND_NCE)
518 tmp |= NFC_CE_CTL;
519 else
520 tmp &= ~NFC_CE_CTL;
521 writel(tmp, nfc->regs + NFC_REG_CTL);
522 }
523
524 if (dat == NAND_CMD_NONE)
525 return;
526
527 if (ctrl & NAND_CLE) {
528 writel(NFC_SEND_CMD1 | dat, nfc->regs + NFC_REG_CMD);
529 } else {
530 writel(dat, nfc->regs + NFC_REG_ADDR_LOW);
531 writel(NFC_SEND_ADR, nfc->regs + NFC_REG_CMD);
532 }
533
534 sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
535}
536
537static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
538 struct nand_chip *chip, uint8_t *buf,
539 int oob_required, int page)
540{
541 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
542 struct nand_ecc_ctrl *ecc = &chip->ecc;
543 struct nand_ecclayout *layout = ecc->layout;
544 struct sunxi_nand_hw_ecc *data = ecc->priv;
545 unsigned int max_bitflips = 0;
546 int offset;
547 int ret;
548 u32 tmp;
549 int i;
550 int cnt;
551
552 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
553 tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE);
554 tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) |
555 NFC_ECC_EXCEPTION;
556
557 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
558
559 for (i = 0; i < ecc->steps; i++) {
560 if (i)
561 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i * ecc->size, -1);
562
563 offset = mtd->writesize + layout->eccpos[i * ecc->bytes] - 4;
564
565 chip->read_buf(mtd, NULL, ecc->size);
566
567 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
568
569 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
570 if (ret)
571 return ret;
572
573 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | (1 << 30);
574 writel(tmp, nfc->regs + NFC_REG_CMD);
575
576 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
577 if (ret)
578 return ret;
579
580 memcpy_fromio(buf + (i * ecc->size),
581 nfc->regs + NFC_RAM0_BASE, ecc->size);
582
583 if (readl(nfc->regs + NFC_REG_ECC_ST) & 0x1) {
584 mtd->ecc_stats.failed++;
585 } else {
586 tmp = readl(nfc->regs + NFC_REG_ECC_CNT0) & 0xff;
587 mtd->ecc_stats.corrected += tmp;
588 max_bitflips = max_t(unsigned int, max_bitflips, tmp);
589 }
590
591 if (oob_required) {
592 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
593
594 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
595 if (ret)
596 return ret;
597
598 offset -= mtd->writesize;
599 chip->read_buf(mtd, chip->oob_poi + offset,
600 ecc->bytes + 4);
601 }
602 }
603
604 if (oob_required) {
605 cnt = ecc->layout->oobfree[ecc->steps].length;
606 if (cnt > 0) {
607 offset = mtd->writesize +
608 ecc->layout->oobfree[ecc->steps].offset;
609 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
610 offset -= mtd->writesize;
611 chip->read_buf(mtd, chip->oob_poi + offset, cnt);
612 }
613 }
614
615 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
616 tmp &= ~NFC_ECC_EN;
617
618 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
619
620 return max_bitflips;
621}
622
623static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
624 struct nand_chip *chip,
625 const uint8_t *buf, int oob_required)
626{
627 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
628 struct nand_ecc_ctrl *ecc = &chip->ecc;
629 struct nand_ecclayout *layout = ecc->layout;
630 struct sunxi_nand_hw_ecc *data = ecc->priv;
631 int offset;
632 int ret;
633 u32 tmp;
634 int i;
635 int cnt;
636
637 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
638 tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE);
639 tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) |
640 NFC_ECC_EXCEPTION;
641
642 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
643
644 for (i = 0; i < ecc->steps; i++) {
645 if (i)
646 chip->cmdfunc(mtd, NAND_CMD_RNDIN, i * ecc->size, -1);
647
648 chip->write_buf(mtd, buf + (i * ecc->size), ecc->size);
649
650 offset = layout->eccpos[i * ecc->bytes] - 4 + mtd->writesize;
651
652 /* Fill OOB data in */
Boris BREZILLON03a0e8a2015-09-14 10:41:03 +0200653 writel(NFC_BUF_TO_USER_DATA(chip->oob_poi +
654 layout->oobfree[i].offset),
655 nfc->regs + NFC_REG_USER_DATA_BASE);
Boris BREZILLON1fef62c2014-10-21 15:08:41 +0200656
657 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1);
658
659 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
660 if (ret)
661 return ret;
662
663 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ACCESS_DIR |
664 (1 << 30);
665 writel(tmp, nfc->regs + NFC_REG_CMD);
666 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
667 if (ret)
668 return ret;
669 }
670
671 if (oob_required) {
672 cnt = ecc->layout->oobfree[i].length;
673 if (cnt > 0) {
674 offset = mtd->writesize +
675 ecc->layout->oobfree[i].offset;
676 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1);
677 offset -= mtd->writesize;
678 chip->write_buf(mtd, chip->oob_poi + offset, cnt);
679 }
680 }
681
682 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
683 tmp &= ~NFC_ECC_EN;
684
685 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
686
687 return 0;
688}
689
690static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
691 struct nand_chip *chip,
692 uint8_t *buf, int oob_required,
693 int page)
694{
695 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
696 struct nand_ecc_ctrl *ecc = &chip->ecc;
697 struct sunxi_nand_hw_ecc *data = ecc->priv;
698 unsigned int max_bitflips = 0;
699 uint8_t *oob = chip->oob_poi;
700 int offset = 0;
701 int ret;
702 int cnt;
703 u32 tmp;
704 int i;
705
706 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
707 tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE);
708 tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) |
709 NFC_ECC_EXCEPTION;
710
711 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
712
713 for (i = 0; i < ecc->steps; i++) {
714 chip->read_buf(mtd, NULL, ecc->size);
715
716 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | (1 << 30);
717 writel(tmp, nfc->regs + NFC_REG_CMD);
718
719 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
720 if (ret)
721 return ret;
722
723 memcpy_fromio(buf, nfc->regs + NFC_RAM0_BASE, ecc->size);
724 buf += ecc->size;
725 offset += ecc->size;
726
727 if (readl(nfc->regs + NFC_REG_ECC_ST) & 0x1) {
728 mtd->ecc_stats.failed++;
729 } else {
730 tmp = readl(nfc->regs + NFC_REG_ECC_CNT0) & 0xff;
731 mtd->ecc_stats.corrected += tmp;
732 max_bitflips = max_t(unsigned int, max_bitflips, tmp);
733 }
734
735 if (oob_required) {
736 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
737 chip->read_buf(mtd, oob, ecc->bytes + ecc->prepad);
738 oob += ecc->bytes + ecc->prepad;
739 }
740
741 offset += ecc->bytes + ecc->prepad;
742 }
743
744 if (oob_required) {
745 cnt = mtd->oobsize - (oob - chip->oob_poi);
746 if (cnt > 0) {
747 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
748 chip->read_buf(mtd, oob, cnt);
749 }
750 }
751
752 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
753 nfc->regs + NFC_REG_ECC_CTL);
754
755 return max_bitflips;
756}
757
758static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
759 struct nand_chip *chip,
760 const uint8_t *buf,
761 int oob_required)
762{
763 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
764 struct nand_ecc_ctrl *ecc = &chip->ecc;
765 struct sunxi_nand_hw_ecc *data = ecc->priv;
766 uint8_t *oob = chip->oob_poi;
767 int offset = 0;
768 int ret;
769 int cnt;
770 u32 tmp;
771 int i;
772
773 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
774 tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE);
775 tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) |
776 NFC_ECC_EXCEPTION;
777
778 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
779
780 for (i = 0; i < ecc->steps; i++) {
781 chip->write_buf(mtd, buf + (i * ecc->size), ecc->size);
782 offset += ecc->size;
783
784 /* Fill OOB data in */
Boris BREZILLON03a0e8a2015-09-14 10:41:03 +0200785 writel(NFC_BUF_TO_USER_DATA(oob),
786 nfc->regs + NFC_REG_USER_DATA_BASE);
Boris BREZILLON1fef62c2014-10-21 15:08:41 +0200787
788 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ACCESS_DIR |
789 (1 << 30);
790 writel(tmp, nfc->regs + NFC_REG_CMD);
791
792 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
793 if (ret)
794 return ret;
795
796 offset += ecc->bytes + ecc->prepad;
797 oob += ecc->bytes + ecc->prepad;
798 }
799
800 if (oob_required) {
801 cnt = mtd->oobsize - (oob - chip->oob_poi);
802 if (cnt > 0) {
803 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1);
804 chip->write_buf(mtd, oob, cnt);
805 }
806 }
807
808 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
809 tmp &= ~NFC_ECC_EN;
810
811 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
812
813 return 0;
814}
815
Roy Spliet9c618292015-06-26 11:00:10 +0200816static const s32 tWB_lut[] = {6, 12, 16, 20};
817static const s32 tRHW_lut[] = {4, 8, 12, 20};
818
819static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
820 u32 clk_period)
821{
822 u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
823 int i;
824
825 for (i = 0; i < lut_size; i++) {
826 if (clk_cycles <= lut[i])
827 return i;
828 }
829
830 /* Doesn't fit */
831 return -EINVAL;
832}
833
834#define sunxi_nand_lookup_timing(l, p, c) \
835 _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
836
Boris BREZILLON1fef62c2014-10-21 15:08:41 +0200837static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
838 const struct nand_sdr_timings *timings)
839{
Roy Spliet9c618292015-06-26 11:00:10 +0200840 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->nand.controller);
Boris BREZILLON1fef62c2014-10-21 15:08:41 +0200841 u32 min_clk_period = 0;
Roy Spliet9c618292015-06-26 11:00:10 +0200842 s32 tWB, tADL, tWHR, tRHW, tCAD;
Boris BREZILLON1fef62c2014-10-21 15:08:41 +0200843
844 /* T1 <=> tCLS */
845 if (timings->tCLS_min > min_clk_period)
846 min_clk_period = timings->tCLS_min;
847
848 /* T2 <=> tCLH */
849 if (timings->tCLH_min > min_clk_period)
850 min_clk_period = timings->tCLH_min;
851
852 /* T3 <=> tCS */
853 if (timings->tCS_min > min_clk_period)
854 min_clk_period = timings->tCS_min;
855
856 /* T4 <=> tCH */
857 if (timings->tCH_min > min_clk_period)
858 min_clk_period = timings->tCH_min;
859
860 /* T5 <=> tWP */
861 if (timings->tWP_min > min_clk_period)
862 min_clk_period = timings->tWP_min;
863
864 /* T6 <=> tWH */
865 if (timings->tWH_min > min_clk_period)
866 min_clk_period = timings->tWH_min;
867
868 /* T7 <=> tALS */
869 if (timings->tALS_min > min_clk_period)
870 min_clk_period = timings->tALS_min;
871
872 /* T8 <=> tDS */
873 if (timings->tDS_min > min_clk_period)
874 min_clk_period = timings->tDS_min;
875
876 /* T9 <=> tDH */
877 if (timings->tDH_min > min_clk_period)
878 min_clk_period = timings->tDH_min;
879
880 /* T10 <=> tRR */
881 if (timings->tRR_min > (min_clk_period * 3))
882 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
883
884 /* T11 <=> tALH */
885 if (timings->tALH_min > min_clk_period)
886 min_clk_period = timings->tALH_min;
887
888 /* T12 <=> tRP */
889 if (timings->tRP_min > min_clk_period)
890 min_clk_period = timings->tRP_min;
891
892 /* T13 <=> tREH */
893 if (timings->tREH_min > min_clk_period)
894 min_clk_period = timings->tREH_min;
895
896 /* T14 <=> tRC */
897 if (timings->tRC_min > (min_clk_period * 2))
898 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
899
900 /* T15 <=> tWC */
901 if (timings->tWC_min > (min_clk_period * 2))
902 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
903
Roy Spliet9c618292015-06-26 11:00:10 +0200904 /* T16 - T19 + tCAD */
905 tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
906 min_clk_period);
907 if (tWB < 0) {
908 dev_err(nfc->dev, "unsupported tWB\n");
909 return tWB;
910 }
911
912 tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
913 if (tADL > 3) {
914 dev_err(nfc->dev, "unsupported tADL\n");
915 return -EINVAL;
916 }
917
918 tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
919 if (tWHR > 3) {
920 dev_err(nfc->dev, "unsupported tWHR\n");
921 return -EINVAL;
922 }
923
924 tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
925 min_clk_period);
926 if (tRHW < 0) {
927 dev_err(nfc->dev, "unsupported tRHW\n");
928 return tRHW;
929 }
930
931 /*
932 * TODO: according to ONFI specs this value only applies for DDR NAND,
933 * but Allwinner seems to set this to 0x7. Mimic them for now.
934 */
935 tCAD = 0x7;
936
937 /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
938 chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
Boris BREZILLON1fef62c2014-10-21 15:08:41 +0200939
Roy Splietd052e502015-06-26 11:00:11 +0200940 /*
941 * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
942 * output cycle timings shall be used if the host drives tRC less than
943 * 30 ns.
944 */
945 chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0;
946
Boris BREZILLON1fef62c2014-10-21 15:08:41 +0200947 /* Convert min_clk_period from picoseconds to nanoseconds */
948 min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
949
950 /*
951 * Convert min_clk_period into a clk frequency, then get the
952 * appropriate rate for the NAND controller IP given this formula
953 * (specified in the datasheet):
954 * nand clk_rate = 2 * min_clk_rate
955 */
956 chip->clk_rate = (2 * NSEC_PER_SEC) / min_clk_period;
957
Boris BREZILLON1fef62c2014-10-21 15:08:41 +0200958 return 0;
959}
960
961static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
962 struct device_node *np)
963{
964 const struct nand_sdr_timings *timings;
965 int ret;
966 int mode;
967
968 mode = onfi_get_async_timing_mode(&chip->nand);
969 if (mode == ONFI_TIMING_MODE_UNKNOWN) {
970 mode = chip->nand.onfi_timing_mode_default;
971 } else {
972 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
Stefan Roese7eadd472015-08-28 14:45:21 +0200973 int i;
Boris BREZILLON1fef62c2014-10-21 15:08:41 +0200974
975 mode = fls(mode) - 1;
976 if (mode < 0)
977 mode = 0;
978
979 feature[0] = mode;
Stefan Roese7eadd472015-08-28 14:45:21 +0200980 for (i = 0; i < chip->nsels; i++) {
981 chip->nand.select_chip(&chip->mtd, i);
982 ret = chip->nand.onfi_set_features(&chip->mtd,
983 &chip->nand,
Boris BREZILLON1fef62c2014-10-21 15:08:41 +0200984 ONFI_FEATURE_ADDR_TIMING_MODE,
985 feature);
Stefan Roese7eadd472015-08-28 14:45:21 +0200986 chip->nand.select_chip(&chip->mtd, -1);
987 if (ret)
988 return ret;
989 }
Boris BREZILLON1fef62c2014-10-21 15:08:41 +0200990 }
991
992 timings = onfi_async_timing_mode_to_sdr_timings(mode);
993 if (IS_ERR(timings))
994 return PTR_ERR(timings);
995
996 return sunxi_nand_chip_set_timings(chip, timings);
997}
998
999static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
1000 struct nand_ecc_ctrl *ecc,
1001 struct device_node *np)
1002{
1003 static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
1004 struct nand_chip *nand = mtd->priv;
1005 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1006 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
1007 struct sunxi_nand_hw_ecc *data;
1008 struct nand_ecclayout *layout;
1009 int nsectors;
1010 int ret;
1011 int i;
1012
1013 data = kzalloc(sizeof(*data), GFP_KERNEL);
1014 if (!data)
1015 return -ENOMEM;
1016
1017 /* Add ECC info retrieval from DT */
1018 for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1019 if (ecc->strength <= strengths[i])
1020 break;
1021 }
1022
1023 if (i >= ARRAY_SIZE(strengths)) {
1024 dev_err(nfc->dev, "unsupported strength\n");
1025 ret = -ENOTSUPP;
1026 goto err;
1027 }
1028
1029 data->mode = i;
1030
1031 /* HW ECC always request ECC bytes for 1024 bytes blocks */
1032 ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
1033
1034 /* HW ECC always work with even numbers of ECC bytes */
1035 ecc->bytes = ALIGN(ecc->bytes, 2);
1036
1037 layout = &data->layout;
1038 nsectors = mtd->writesize / ecc->size;
1039
1040 if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
1041 ret = -EINVAL;
1042 goto err;
1043 }
1044
1045 layout->eccbytes = (ecc->bytes * nsectors);
1046
1047 ecc->layout = layout;
1048 ecc->priv = data;
1049
1050 return 0;
1051
1052err:
1053 kfree(data);
1054
1055 return ret;
1056}
1057
1058static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
1059{
1060 kfree(ecc->priv);
1061}
1062
1063static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
1064 struct nand_ecc_ctrl *ecc,
1065 struct device_node *np)
1066{
1067 struct nand_ecclayout *layout;
1068 int nsectors;
1069 int i, j;
1070 int ret;
1071
1072 ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1073 if (ret)
1074 return ret;
1075
1076 ecc->read_page = sunxi_nfc_hw_ecc_read_page;
1077 ecc->write_page = sunxi_nfc_hw_ecc_write_page;
1078 layout = ecc->layout;
1079 nsectors = mtd->writesize / ecc->size;
1080
1081 for (i = 0; i < nsectors; i++) {
1082 if (i) {
1083 layout->oobfree[i].offset =
1084 layout->oobfree[i - 1].offset +
1085 layout->oobfree[i - 1].length +
1086 ecc->bytes;
1087 layout->oobfree[i].length = 4;
1088 } else {
1089 /*
1090 * The first 2 bytes are used for BB markers, hence we
1091 * only have 2 bytes available in the first user data
1092 * section.
1093 */
1094 layout->oobfree[i].length = 2;
1095 layout->oobfree[i].offset = 2;
1096 }
1097
1098 for (j = 0; j < ecc->bytes; j++)
1099 layout->eccpos[(ecc->bytes * i) + j] =
1100 layout->oobfree[i].offset +
1101 layout->oobfree[i].length + j;
1102 }
1103
1104 if (mtd->oobsize > (ecc->bytes + 4) * nsectors) {
1105 layout->oobfree[nsectors].offset =
1106 layout->oobfree[nsectors - 1].offset +
1107 layout->oobfree[nsectors - 1].length +
1108 ecc->bytes;
1109 layout->oobfree[nsectors].length = mtd->oobsize -
1110 ((ecc->bytes + 4) * nsectors);
1111 }
1112
1113 return 0;
1114}
1115
1116static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
1117 struct nand_ecc_ctrl *ecc,
1118 struct device_node *np)
1119{
1120 struct nand_ecclayout *layout;
1121 int nsectors;
1122 int i;
1123 int ret;
1124
1125 ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1126 if (ret)
1127 return ret;
1128
1129 ecc->prepad = 4;
1130 ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
1131 ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
1132
1133 layout = ecc->layout;
1134 nsectors = mtd->writesize / ecc->size;
1135
1136 for (i = 0; i < (ecc->bytes * nsectors); i++)
1137 layout->eccpos[i] = i;
1138
1139 layout->oobfree[0].length = mtd->oobsize - i;
1140 layout->oobfree[0].offset = i;
1141
1142 return 0;
1143}
1144
1145static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
1146{
1147 switch (ecc->mode) {
1148 case NAND_ECC_HW:
1149 case NAND_ECC_HW_SYNDROME:
1150 sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
1151 break;
1152 case NAND_ECC_NONE:
1153 kfree(ecc->layout);
1154 default:
1155 break;
1156 }
1157}
1158
1159static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
1160 struct device_node *np)
1161{
1162 struct nand_chip *nand = mtd->priv;
Boris BREZILLON1fef62c2014-10-21 15:08:41 +02001163 int ret;
1164
Boris BREZILLONa3d22a52015-09-02 10:30:25 +02001165 if (!ecc->size) {
Boris BREZILLON1fef62c2014-10-21 15:08:41 +02001166 ecc->size = nand->ecc_step_ds;
1167 ecc->strength = nand->ecc_strength_ds;
1168 }
1169
1170 if (!ecc->size || !ecc->strength)
1171 return -EINVAL;
1172
Boris BREZILLON1fef62c2014-10-21 15:08:41 +02001173 switch (ecc->mode) {
1174 case NAND_ECC_SOFT_BCH:
Boris BREZILLON1fef62c2014-10-21 15:08:41 +02001175 break;
1176 case NAND_ECC_HW:
1177 ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np);
1178 if (ret)
1179 return ret;
1180 break;
1181 case NAND_ECC_HW_SYNDROME:
1182 ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc, np);
1183 if (ret)
1184 return ret;
1185 break;
1186 case NAND_ECC_NONE:
1187 ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
1188 if (!ecc->layout)
1189 return -ENOMEM;
1190 ecc->layout->oobfree[0].length = mtd->oobsize;
1191 case NAND_ECC_SOFT:
1192 break;
1193 default:
1194 return -EINVAL;
1195 }
1196
1197 return 0;
1198}
1199
1200static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
1201 struct device_node *np)
1202{
1203 const struct nand_sdr_timings *timings;
1204 struct sunxi_nand_chip *chip;
1205 struct mtd_part_parser_data ppdata;
1206 struct mtd_info *mtd;
1207 struct nand_chip *nand;
1208 int nsels;
1209 int ret;
1210 int i;
1211 u32 tmp;
1212
1213 if (!of_get_property(np, "reg", &nsels))
1214 return -EINVAL;
1215
1216 nsels /= sizeof(u32);
1217 if (!nsels) {
1218 dev_err(dev, "invalid reg property size\n");
1219 return -EINVAL;
1220 }
1221
1222 chip = devm_kzalloc(dev,
1223 sizeof(*chip) +
1224 (nsels * sizeof(struct sunxi_nand_chip_sel)),
1225 GFP_KERNEL);
1226 if (!chip) {
1227 dev_err(dev, "could not allocate chip\n");
1228 return -ENOMEM;
1229 }
1230
1231 chip->nsels = nsels;
1232 chip->selected = -1;
1233
1234 for (i = 0; i < nsels; i++) {
1235 ret = of_property_read_u32_index(np, "reg", i, &tmp);
1236 if (ret) {
1237 dev_err(dev, "could not retrieve reg property: %d\n",
1238 ret);
1239 return ret;
1240 }
1241
1242 if (tmp > NFC_MAX_CS) {
1243 dev_err(dev,
1244 "invalid reg value: %u (max CS = 7)\n",
1245 tmp);
1246 return -EINVAL;
1247 }
1248
1249 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1250 dev_err(dev, "CS %d already assigned\n", tmp);
1251 return -EINVAL;
1252 }
1253
1254 chip->sels[i].cs = tmp;
1255
1256 if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) &&
1257 tmp < 2) {
1258 chip->sels[i].rb.type = RB_NATIVE;
1259 chip->sels[i].rb.info.nativeid = tmp;
1260 } else {
1261 ret = of_get_named_gpio(np, "rb-gpios", i);
1262 if (ret >= 0) {
1263 tmp = ret;
1264 chip->sels[i].rb.type = RB_GPIO;
1265 chip->sels[i].rb.info.gpio = tmp;
1266 ret = devm_gpio_request(dev, tmp, "nand-rb");
1267 if (ret)
1268 return ret;
1269
1270 ret = gpio_direction_input(tmp);
1271 if (ret)
1272 return ret;
1273 } else {
1274 chip->sels[i].rb.type = RB_NONE;
1275 }
1276 }
1277 }
1278
1279 timings = onfi_async_timing_mode_to_sdr_timings(0);
1280 if (IS_ERR(timings)) {
1281 ret = PTR_ERR(timings);
1282 dev_err(dev,
1283 "could not retrieve timings for ONFI mode 0: %d\n",
1284 ret);
1285 return ret;
1286 }
1287
1288 ret = sunxi_nand_chip_set_timings(chip, timings);
1289 if (ret) {
1290 dev_err(dev, "could not configure chip timings: %d\n", ret);
1291 return ret;
1292 }
1293
1294 nand = &chip->nand;
1295 /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
1296 nand->chip_delay = 200;
1297 nand->controller = &nfc->controller;
Boris BREZILLONa3d22a52015-09-02 10:30:25 +02001298 /*
1299 * Set the ECC mode to the default value in case nothing is specified
1300 * in the DT.
1301 */
1302 nand->ecc.mode = NAND_ECC_HW;
1303 nand->flash_node = np;
Boris BREZILLON1fef62c2014-10-21 15:08:41 +02001304 nand->select_chip = sunxi_nfc_select_chip;
1305 nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
1306 nand->read_buf = sunxi_nfc_read_buf;
1307 nand->write_buf = sunxi_nfc_write_buf;
1308 nand->read_byte = sunxi_nfc_read_byte;
1309
Boris BREZILLON1fef62c2014-10-21 15:08:41 +02001310 mtd = &chip->mtd;
1311 mtd->dev.parent = dev;
1312 mtd->priv = nand;
1313 mtd->owner = THIS_MODULE;
1314
1315 ret = nand_scan_ident(mtd, nsels, NULL);
1316 if (ret)
1317 return ret;
1318
Boris BREZILLONa3d22a52015-09-02 10:30:25 +02001319 if (nand->bbt_options & NAND_BBT_USE_FLASH)
1320 nand->bbt_options |= NAND_BBT_NO_OOB;
1321
Boris BREZILLON1fef62c2014-10-21 15:08:41 +02001322 ret = sunxi_nand_chip_init_timings(chip, np);
1323 if (ret) {
1324 dev_err(dev, "could not configure chip timings: %d\n", ret);
1325 return ret;
1326 }
1327
1328 ret = sunxi_nand_ecc_init(mtd, &nand->ecc, np);
1329 if (ret) {
1330 dev_err(dev, "ECC init failed: %d\n", ret);
1331 return ret;
1332 }
1333
1334 ret = nand_scan_tail(mtd);
1335 if (ret) {
1336 dev_err(dev, "nand_scan_tail failed: %d\n", ret);
1337 return ret;
1338 }
1339
1340 ppdata.of_node = np;
1341 ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
1342 if (ret) {
1343 dev_err(dev, "failed to register mtd device: %d\n", ret);
1344 nand_release(mtd);
1345 return ret;
1346 }
1347
1348 list_add_tail(&chip->node, &nfc->chips);
1349
1350 return 0;
1351}
1352
1353static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
1354{
1355 struct device_node *np = dev->of_node;
1356 struct device_node *nand_np;
1357 int nchips = of_get_child_count(np);
1358 int ret;
1359
1360 if (nchips > 8) {
1361 dev_err(dev, "too many NAND chips: %d (max = 8)\n", nchips);
1362 return -EINVAL;
1363 }
1364
1365 for_each_child_of_node(np, nand_np) {
1366 ret = sunxi_nand_chip_init(dev, nfc, nand_np);
1367 if (ret)
1368 return ret;
1369 }
1370
1371 return 0;
1372}
1373
1374static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
1375{
1376 struct sunxi_nand_chip *chip;
1377
1378 while (!list_empty(&nfc->chips)) {
1379 chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
1380 node);
1381 nand_release(&chip->mtd);
1382 sunxi_nand_ecc_cleanup(&chip->nand.ecc);
Boris BREZILLON8e375cc2015-09-13 18:14:43 +02001383 list_del(&chip->node);
Boris BREZILLON1fef62c2014-10-21 15:08:41 +02001384 }
1385}
1386
1387static int sunxi_nfc_probe(struct platform_device *pdev)
1388{
1389 struct device *dev = &pdev->dev;
1390 struct resource *r;
1391 struct sunxi_nfc *nfc;
1392 int irq;
1393 int ret;
1394
1395 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1396 if (!nfc)
1397 return -ENOMEM;
1398
1399 nfc->dev = dev;
1400 spin_lock_init(&nfc->controller.lock);
1401 init_waitqueue_head(&nfc->controller.wq);
1402 INIT_LIST_HEAD(&nfc->chips);
1403
1404 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1405 nfc->regs = devm_ioremap_resource(dev, r);
1406 if (IS_ERR(nfc->regs))
1407 return PTR_ERR(nfc->regs);
1408
1409 irq = platform_get_irq(pdev, 0);
1410 if (irq < 0) {
1411 dev_err(dev, "failed to retrieve irq\n");
1412 return irq;
1413 }
1414
1415 nfc->ahb_clk = devm_clk_get(dev, "ahb");
1416 if (IS_ERR(nfc->ahb_clk)) {
1417 dev_err(dev, "failed to retrieve ahb clk\n");
1418 return PTR_ERR(nfc->ahb_clk);
1419 }
1420
1421 ret = clk_prepare_enable(nfc->ahb_clk);
1422 if (ret)
1423 return ret;
1424
1425 nfc->mod_clk = devm_clk_get(dev, "mod");
1426 if (IS_ERR(nfc->mod_clk)) {
1427 dev_err(dev, "failed to retrieve mod clk\n");
1428 ret = PTR_ERR(nfc->mod_clk);
1429 goto out_ahb_clk_unprepare;
1430 }
1431
1432 ret = clk_prepare_enable(nfc->mod_clk);
1433 if (ret)
1434 goto out_ahb_clk_unprepare;
1435
1436 ret = sunxi_nfc_rst(nfc);
1437 if (ret)
1438 goto out_mod_clk_unprepare;
1439
1440 writel(0, nfc->regs + NFC_REG_INT);
1441 ret = devm_request_irq(dev, irq, sunxi_nfc_interrupt,
1442 0, "sunxi-nand", nfc);
1443 if (ret)
1444 goto out_mod_clk_unprepare;
1445
1446 platform_set_drvdata(pdev, nfc);
1447
Boris BREZILLON1fef62c2014-10-21 15:08:41 +02001448 ret = sunxi_nand_chips_init(dev, nfc);
1449 if (ret) {
1450 dev_err(dev, "failed to init nand chips\n");
1451 goto out_mod_clk_unprepare;
1452 }
1453
1454 return 0;
1455
1456out_mod_clk_unprepare:
1457 clk_disable_unprepare(nfc->mod_clk);
1458out_ahb_clk_unprepare:
1459 clk_disable_unprepare(nfc->ahb_clk);
1460
1461 return ret;
1462}
1463
1464static int sunxi_nfc_remove(struct platform_device *pdev)
1465{
1466 struct sunxi_nfc *nfc = platform_get_drvdata(pdev);
1467
1468 sunxi_nand_chips_cleanup(nfc);
1469
1470 return 0;
1471}
1472
1473static const struct of_device_id sunxi_nfc_ids[] = {
1474 { .compatible = "allwinner,sun4i-a10-nand" },
1475 { /* sentinel */ }
1476};
1477MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
1478
1479static struct platform_driver sunxi_nfc_driver = {
1480 .driver = {
1481 .name = "sunxi_nand",
1482 .of_match_table = sunxi_nfc_ids,
1483 },
1484 .probe = sunxi_nfc_probe,
1485 .remove = sunxi_nfc_remove,
1486};
1487module_platform_driver(sunxi_nfc_driver);
1488
1489MODULE_LICENSE("GPL v2");
1490MODULE_AUTHOR("Boris BREZILLON");
1491MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
1492MODULE_ALIAS("platform:sunxi_nand");