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Gabor Juhos8efaef42011-01-04 21:28:22 +01001/*
2 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
3 *
4 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This driver has been based on the spi-gpio.c:
7 * Copyright (C) 2006,2008 David Brownell
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#include <linux/kernel.h>
Gabor Juhos807cc4b2011-11-16 20:01:43 +010016#include <linux/module.h>
Gabor Juhos8efaef42011-01-04 21:28:22 +010017#include <linux/delay.h>
18#include <linux/spinlock.h>
Gabor Juhos8efaef42011-01-04 21:28:22 +010019#include <linux/platform_device.h>
20#include <linux/io.h>
21#include <linux/spi/spi.h>
22#include <linux/spi/spi_bitbang.h>
23#include <linux/bitops.h>
Gabor Juhos440114f2012-12-27 10:42:24 +010024#include <linux/clk.h>
25#include <linux/err.h>
Gabor Juhos8efaef42011-01-04 21:28:22 +010026
27#include <asm/mach-ath79/ar71xx_regs.h>
28#include <asm/mach-ath79/ath79_spi_platform.h>
29
30#define DRV_NAME "ath79-spi"
31
Gabor Juhos440114f2012-12-27 10:42:24 +010032#define ATH79_SPI_RRW_DELAY_FACTOR 12000
33#define MHZ (1000 * 1000)
34
Gabor Juhos8efaef42011-01-04 21:28:22 +010035struct ath79_spi {
36 struct spi_bitbang bitbang;
37 u32 ioc_base;
38 u32 reg_ctrl;
39 void __iomem *base;
Gabor Juhos440114f2012-12-27 10:42:24 +010040 struct clk *clk;
Aravind Thokalada470d62017-06-27 22:01:11 +053041 unsigned int rrw_delay;
Gabor Juhos8efaef42011-01-04 21:28:22 +010042};
43
Aravind Thokalada470d62017-06-27 22:01:11 +053044static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg)
Gabor Juhos8efaef42011-01-04 21:28:22 +010045{
46 return ioread32(sp->base + reg);
47}
48
Aravind Thokalada470d62017-06-27 22:01:11 +053049static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val)
Gabor Juhos8efaef42011-01-04 21:28:22 +010050{
51 iowrite32(val, sp->base + reg);
52}
53
54static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
55{
56 return spi_master_get_devdata(spi->master);
57}
58
Aravind Thokalada470d62017-06-27 22:01:11 +053059static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs)
Gabor Juhos440114f2012-12-27 10:42:24 +010060{
61 if (nsecs > sp->rrw_delay)
62 ndelay(nsecs - sp->rrw_delay);
63}
64
Gabor Juhos8efaef42011-01-04 21:28:22 +010065static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
66{
67 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
68 int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
Alban Bedel797622d2019-01-16 19:55:45 +010069 u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
Gabor Juhos8efaef42011-01-04 21:28:22 +010070
Alban Bedel797622d2019-01-16 19:55:45 +010071 if (cs_high)
72 sp->ioc_base |= cs_bit;
73 else
74 sp->ioc_base &= ~cs_bit;
Gabor Juhos8efaef42011-01-04 21:28:22 +010075
Alban Bedel797622d2019-01-16 19:55:45 +010076 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
Gabor Juhos8efaef42011-01-04 21:28:22 +010077}
78
Gabor Juhosc4a31f42012-12-27 10:42:28 +010079static void ath79_spi_enable(struct ath79_spi *sp)
Gabor Juhos8efaef42011-01-04 21:28:22 +010080{
Gabor Juhos8efaef42011-01-04 21:28:22 +010081 /* enable GPIO mode */
82 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
83
84 /* save CTRL register */
85 sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
86 sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
87
Alban Bedel797622d2019-01-16 19:55:45 +010088 /* clear clk and mosi in the base state */
89 sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK);
90
Gabor Juhos8efaef42011-01-04 21:28:22 +010091 /* TODO: setup speed? */
92 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
Gabor Juhosc4a31f42012-12-27 10:42:28 +010093}
94
95static void ath79_spi_disable(struct ath79_spi *sp)
96{
97 /* restore CTRL register */
98 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
99 /* disable GPIO mode */
100 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
101}
102
103static int ath79_spi_setup_cs(struct spi_device *spi)
104{
Alban Bedel83f0f392015-04-24 16:19:24 +0200105 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
Gabor Juhosc4a31f42012-12-27 10:42:28 +0100106
Linus Walleij8db79542019-01-07 16:51:51 +0100107 if (!spi->cs_gpiod) {
Felix Fietkau22c76322016-12-09 20:48:52 +0100108 u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
109
Alban Bedel83f0f392015-04-24 16:19:24 +0200110 if (spi->mode & SPI_CS_HIGH)
Felix Fietkau22c76322016-12-09 20:48:52 +0100111 sp->ioc_base &= ~cs_bit;
Alban Bedel83f0f392015-04-24 16:19:24 +0200112 else
Felix Fietkau22c76322016-12-09 20:48:52 +0100113 sp->ioc_base |= cs_bit;
Alban Bedel83f0f392015-04-24 16:19:24 +0200114
115 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
Gabor Juhos8efaef42011-01-04 21:28:22 +0100116 }
117
Linus Walleij8db79542019-01-07 16:51:51 +0100118 return 0;
Gabor Juhos8efaef42011-01-04 21:28:22 +0100119}
120
121static int ath79_spi_setup(struct spi_device *spi)
122{
123 int status = 0;
124
Gabor Juhos8efaef42011-01-04 21:28:22 +0100125 if (!spi->controller_state) {
126 status = ath79_spi_setup_cs(spi);
127 if (status)
128 return status;
129 }
130
131 status = spi_bitbang_setup(spi);
Gabor Juhos8efaef42011-01-04 21:28:22 +0100132
133 return status;
134}
135
136static void ath79_spi_cleanup(struct spi_device *spi)
137{
Gabor Juhos8efaef42011-01-04 21:28:22 +0100138 spi_bitbang_cleanup(spi);
139}
140
Aravind Thokalada470d62017-06-27 22:01:11 +0530141static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs,
Lorenzo Bianconi304d3432018-07-28 10:19:13 +0200142 u32 word, u8 bits, unsigned flags)
Gabor Juhos8efaef42011-01-04 21:28:22 +0100143{
144 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
145 u32 ioc = sp->ioc_base;
146
147 /* clock starts at inactive polarity */
148 for (word <<= (32 - bits); likely(bits); bits--) {
149 u32 out;
150
151 if (word & (1 << 31))
152 out = ioc | AR71XX_SPI_IOC_DO;
153 else
154 out = ioc & ~AR71XX_SPI_IOC_DO;
155
156 /* setup MSB (to slave) on trailing edge */
157 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
Gabor Juhos440114f2012-12-27 10:42:24 +0100158 ath79_spi_delay(sp, nsecs);
Gabor Juhos8efaef42011-01-04 21:28:22 +0100159 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
Gabor Juhos440114f2012-12-27 10:42:24 +0100160 ath79_spi_delay(sp, nsecs);
Gabor Juhos72611db2012-12-27 10:42:25 +0100161 if (bits == 1)
162 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
Gabor Juhos8efaef42011-01-04 21:28:22 +0100163
164 word <<= 1;
165 }
166
167 return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
168}
169
Grant Likelyfd4a3192012-12-07 16:57:14 +0000170static int ath79_spi_probe(struct platform_device *pdev)
Gabor Juhos8efaef42011-01-04 21:28:22 +0100171{
172 struct spi_master *master;
173 struct ath79_spi *sp;
174 struct ath79_spi_platform_data *pdata;
175 struct resource *r;
Gabor Juhos440114f2012-12-27 10:42:24 +0100176 unsigned long rate;
Gabor Juhos8efaef42011-01-04 21:28:22 +0100177 int ret;
178
179 master = spi_alloc_master(&pdev->dev, sizeof(*sp));
180 if (master == NULL) {
181 dev_err(&pdev->dev, "failed to allocate spi master\n");
182 return -ENOMEM;
183 }
184
185 sp = spi_master_get_devdata(master);
Alban Bedel85f62472015-04-24 16:19:22 +0200186 master->dev.of_node = pdev->dev.of_node;
Gabor Juhos8efaef42011-01-04 21:28:22 +0100187 platform_set_drvdata(pdev, sp);
188
Jingoo Han8074cf02013-07-30 16:58:59 +0900189 pdata = dev_get_platdata(&pdev->dev);
Gabor Juhos8efaef42011-01-04 21:28:22 +0100190
Linus Walleij8db79542019-01-07 16:51:51 +0100191 master->use_gpio_descriptors = true;
Stephen Warren24778be2013-05-21 20:36:35 -0600192 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
Gabor Juhos8efaef42011-01-04 21:28:22 +0100193 master->setup = ath79_spi_setup;
194 master->cleanup = ath79_spi_cleanup;
195 if (pdata) {
196 master->bus_num = pdata->bus_num;
197 master->num_chipselect = pdata->num_chipselect;
Gabor Juhos8efaef42011-01-04 21:28:22 +0100198 }
199
Axel Lin94c69f72013-09-10 15:43:41 +0800200 sp->bitbang.master = master;
Gabor Juhos8efaef42011-01-04 21:28:22 +0100201 sp->bitbang.chipselect = ath79_spi_chipselect;
202 sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
203 sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
204 sp->bitbang.flags = SPI_CS_HIGH;
205
206 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Heiner Kallweitb7a2a1c2015-09-27 18:47:35 +0200207 sp->base = devm_ioremap_resource(&pdev->dev, r);
208 if (IS_ERR(sp->base)) {
209 ret = PTR_ERR(sp->base);
Gabor Juhos8efaef42011-01-04 21:28:22 +0100210 goto err_put_master;
211 }
212
Jingoo Hana6f4c8e2013-12-09 19:14:58 +0900213 sp->clk = devm_clk_get(&pdev->dev, "ahb");
Gabor Juhos440114f2012-12-27 10:42:24 +0100214 if (IS_ERR(sp->clk)) {
215 ret = PTR_ERR(sp->clk);
Jingoo Hana6f4c8e2013-12-09 19:14:58 +0900216 goto err_put_master;
Gabor Juhos440114f2012-12-27 10:42:24 +0100217 }
218
Alban Bedel3e19acd2015-04-24 16:19:23 +0200219 ret = clk_prepare_enable(sp->clk);
Gabor Juhos440114f2012-12-27 10:42:24 +0100220 if (ret)
Jingoo Hana6f4c8e2013-12-09 19:14:58 +0900221 goto err_put_master;
Gabor Juhos440114f2012-12-27 10:42:24 +0100222
223 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
224 if (!rate) {
225 ret = -EINVAL;
226 goto err_clk_disable;
227 }
228
229 sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
230 dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
231 sp->rrw_delay);
232
Gabor Juhosc4a31f42012-12-27 10:42:28 +0100233 ath79_spi_enable(sp);
Gabor Juhos8efaef42011-01-04 21:28:22 +0100234 ret = spi_bitbang_start(&sp->bitbang);
235 if (ret)
Gabor Juhosc4a31f42012-12-27 10:42:28 +0100236 goto err_disable;
Gabor Juhos8efaef42011-01-04 21:28:22 +0100237
238 return 0;
239
Gabor Juhosc4a31f42012-12-27 10:42:28 +0100240err_disable:
241 ath79_spi_disable(sp);
Gabor Juhos440114f2012-12-27 10:42:24 +0100242err_clk_disable:
Alban Bedel3e19acd2015-04-24 16:19:23 +0200243 clk_disable_unprepare(sp->clk);
Gabor Juhos8efaef42011-01-04 21:28:22 +0100244err_put_master:
Gabor Juhos8efaef42011-01-04 21:28:22 +0100245 spi_master_put(sp->bitbang.master);
246
247 return ret;
248}
249
Grant Likelyfd4a3192012-12-07 16:57:14 +0000250static int ath79_spi_remove(struct platform_device *pdev)
Gabor Juhos8efaef42011-01-04 21:28:22 +0100251{
252 struct ath79_spi *sp = platform_get_drvdata(pdev);
253
254 spi_bitbang_stop(&sp->bitbang);
Gabor Juhosc4a31f42012-12-27 10:42:28 +0100255 ath79_spi_disable(sp);
Alban Bedel3e19acd2015-04-24 16:19:23 +0200256 clk_disable_unprepare(sp->clk);
Gabor Juhos8efaef42011-01-04 21:28:22 +0100257 spi_master_put(sp->bitbang.master);
258
259 return 0;
260}
261
Gabor Juhos7410e842013-02-05 20:57:55 +0100262static void ath79_spi_shutdown(struct platform_device *pdev)
263{
264 ath79_spi_remove(pdev);
265}
266
Alban Bedel85f62472015-04-24 16:19:22 +0200267static const struct of_device_id ath79_spi_of_match[] = {
268 { .compatible = "qca,ar7100-spi", },
269 { },
270};
Javier Martinez Canillasd7a32392016-11-23 13:37:11 -0300271MODULE_DEVICE_TABLE(of, ath79_spi_of_match);
Alban Bedel85f62472015-04-24 16:19:22 +0200272
Gabor Juhos8efaef42011-01-04 21:28:22 +0100273static struct platform_driver ath79_spi_driver = {
274 .probe = ath79_spi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +0000275 .remove = ath79_spi_remove,
Gabor Juhos7410e842013-02-05 20:57:55 +0100276 .shutdown = ath79_spi_shutdown,
Gabor Juhos8efaef42011-01-04 21:28:22 +0100277 .driver = {
278 .name = DRV_NAME,
Alban Bedel85f62472015-04-24 16:19:22 +0200279 .of_match_table = ath79_spi_of_match,
Gabor Juhos8efaef42011-01-04 21:28:22 +0100280 },
281};
Grant Likely940ab882011-10-05 11:29:49 -0600282module_platform_driver(ath79_spi_driver);
Gabor Juhos8efaef42011-01-04 21:28:22 +0100283
284MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
285MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
286MODULE_LICENSE("GPL v2");
287MODULE_ALIAS("platform:" DRV_NAME);