blob: 6aefef99f935e5d3aee23481c2b9c0ff370773f1 [file] [log] [blame]
Fabrice Gasnier1add69882016-11-15 16:30:57 +01001/*
2 * This file is part of STM32 ADC driver
3 *
4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
5 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
6 *
7 * Inspired from: fsl-imx25-tsadc
8 *
9 * License type: GPLv2
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published by
13 * the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 * or FITNESS FOR A PARTICULAR PURPOSE.
18 * See the GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program. If not, see <http://www.gnu.org/licenses/>.
22 */
23
24#include <linux/clk.h>
25#include <linux/interrupt.h>
26#include <linux/irqchip/chained_irq.h>
27#include <linux/irqdesc.h>
28#include <linux/irqdomain.h>
29#include <linux/module.h>
30#include <linux/of_device.h>
31#include <linux/regulator/consumer.h>
32#include <linux/slab.h>
33
34#include "stm32-adc-core.h"
35
36/* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
37#define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
38#define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04)
39
40/* STM32F4_ADC_CSR - bit fields */
41#define STM32F4_EOC3 BIT(17)
42#define STM32F4_EOC2 BIT(9)
43#define STM32F4_EOC1 BIT(1)
44
45/* STM32F4_ADC_CCR - bit fields */
46#define STM32F4_ADC_ADCPRE_SHIFT 16
47#define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16)
48
49/* STM32 F4 maximum analog clock rate (from datasheet) */
50#define STM32F4_ADC_MAX_CLK_RATE 36000000
51
Fabrice Gasnier95e339b2017-05-29 11:28:20 +020052/* STM32H7 - common registers for all ADC instances */
53#define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
54#define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
55
56/* STM32H7_ADC_CSR - bit fields */
57#define STM32H7_EOC_SLV BIT(18)
58#define STM32H7_EOC_MST BIT(2)
59
60/* STM32H7_ADC_CCR - bit fields */
61#define STM32H7_PRESC_SHIFT 18
62#define STM32H7_PRESC_MASK GENMASK(21, 18)
63#define STM32H7_CKMODE_SHIFT 16
64#define STM32H7_CKMODE_MASK GENMASK(17, 16)
65
66/* STM32 H7 maximum analog clock rate (from datasheet) */
Fabrice Gasnier50dbe1f2017-07-24 18:10:38 +020067#define STM32H7_ADC_MAX_CLK_RATE 36000000
Fabrice Gasnier95e339b2017-05-29 11:28:20 +020068
Fabrice Gasnier1add69882016-11-15 16:30:57 +010069/**
Fabrice Gasnier64ad7f62017-05-29 11:28:18 +020070 * stm32_adc_common_regs - stm32 common registers, compatible dependent data
71 * @csr: common status register offset
72 * @eoc1: adc1 end of conversion flag in @csr
73 * @eoc2: adc2 end of conversion flag in @csr
74 * @eoc3: adc3 end of conversion flag in @csr
75 */
76struct stm32_adc_common_regs {
77 u32 csr;
78 u32 eoc1_msk;
79 u32 eoc2_msk;
80 u32 eoc3_msk;
81};
82
83struct stm32_adc_priv;
84
85/**
86 * stm32_adc_priv_cfg - stm32 core compatible configuration data
87 * @regs: common registers for all instances
88 * @clk_sel: clock selection routine
89 */
90struct stm32_adc_priv_cfg {
91 const struct stm32_adc_common_regs *regs;
92 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
93};
94
95/**
Fabrice Gasnier1add69882016-11-15 16:30:57 +010096 * struct stm32_adc_priv - stm32 ADC core private data
97 * @irq: irq for ADC block
98 * @domain: irq domain reference
99 * @aclk: clock reference for the analog circuitry
Fabrice Gasnier95e339b2017-05-29 11:28:20 +0200100 * @bclk: bus clock common for all ADCs, depends on part used
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100101 * @vref: regulator reference
Fabrice Gasnier64ad7f62017-05-29 11:28:18 +0200102 * @cfg: compatible configuration data
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100103 * @common: common data for all ADC instances
104 */
105struct stm32_adc_priv {
106 int irq;
107 struct irq_domain *domain;
108 struct clk *aclk;
Fabrice Gasnier95e339b2017-05-29 11:28:20 +0200109 struct clk *bclk;
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100110 struct regulator *vref;
Fabrice Gasnier64ad7f62017-05-29 11:28:18 +0200111 const struct stm32_adc_priv_cfg *cfg;
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100112 struct stm32_adc_common common;
113};
114
115static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
116{
117 return container_of(com, struct stm32_adc_priv, common);
118}
119
120/* STM32F4 ADC internal common clock prescaler division ratios */
121static int stm32f4_pclk_div[] = {2, 4, 6, 8};
122
123/**
124 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
125 * @priv: stm32 ADC core private data
126 * Select clock prescaler used for analog conversions, before using ADC.
127 */
128static int stm32f4_adc_clk_sel(struct platform_device *pdev,
129 struct stm32_adc_priv *priv)
130{
131 unsigned long rate;
132 u32 val;
133 int i;
134
Fabrice Gasnier9fd243c2017-05-29 11:28:17 +0200135 /* stm32f4 has one clk input for analog (mandatory), enforce it here */
136 if (!priv->aclk) {
137 dev_err(&pdev->dev, "No 'adc' clock found\n");
138 return -ENOENT;
139 }
140
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100141 rate = clk_get_rate(priv->aclk);
Fabrice Gasnierf66f18e2017-10-18 13:40:12 +0200142 if (!rate) {
143 dev_err(&pdev->dev, "Invalid clock rate: 0\n");
144 return -EINVAL;
145 }
146
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100147 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
148 if ((rate / stm32f4_pclk_div[i]) <= STM32F4_ADC_MAX_CLK_RATE)
149 break;
150 }
Fabrice Gasnier9fd243c2017-05-29 11:28:17 +0200151 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
152 dev_err(&pdev->dev, "adc clk selection failed\n");
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100153 return -EINVAL;
Fabrice Gasnier9fd243c2017-05-29 11:28:17 +0200154 }
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100155
Fabrice Gasnier50dbe1f2017-07-24 18:10:38 +0200156 priv->common.rate = rate / stm32f4_pclk_div[i];
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100157 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
158 val &= ~STM32F4_ADC_ADCPRE_MASK;
159 val |= i << STM32F4_ADC_ADCPRE_SHIFT;
160 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
161
162 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
Fabrice Gasnier50dbe1f2017-07-24 18:10:38 +0200163 priv->common.rate / 1000);
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100164
165 return 0;
166}
167
Fabrice Gasnier95e339b2017-05-29 11:28:20 +0200168/**
169 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
170 * @ckmode: ADC clock mode, Async or sync with prescaler.
171 * @presc: prescaler bitfield for async clock mode
172 * @div: prescaler division ratio
173 */
174struct stm32h7_adc_ck_spec {
175 u32 ckmode;
176 u32 presc;
177 int div;
178};
179
Colin Ian King004123f2017-06-28 14:06:50 +0100180static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
Fabrice Gasnier95e339b2017-05-29 11:28:20 +0200181 /* 00: CK_ADC[1..3]: Asynchronous clock modes */
182 { 0, 0, 1 },
183 { 0, 1, 2 },
184 { 0, 2, 4 },
185 { 0, 3, 6 },
186 { 0, 4, 8 },
187 { 0, 5, 10 },
188 { 0, 6, 12 },
189 { 0, 7, 16 },
190 { 0, 8, 32 },
191 { 0, 9, 64 },
192 { 0, 10, 128 },
193 { 0, 11, 256 },
194 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
195 { 1, 0, 1 },
196 { 2, 0, 2 },
197 { 3, 0, 4 },
198};
199
200static int stm32h7_adc_clk_sel(struct platform_device *pdev,
201 struct stm32_adc_priv *priv)
202{
203 u32 ckmode, presc, val;
204 unsigned long rate;
205 int i, div;
206
207 /* stm32h7 bus clock is common for all ADC instances (mandatory) */
208 if (!priv->bclk) {
209 dev_err(&pdev->dev, "No 'bus' clock found\n");
210 return -ENOENT;
211 }
212
213 /*
214 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
215 * So, choice is to have bus clock mandatory and adc clock optional.
216 * If optional 'adc' clock has been found, then try to use it first.
217 */
218 if (priv->aclk) {
219 /*
220 * Asynchronous clock modes (e.g. ckmode == 0)
221 * From spec: PLL output musn't exceed max rate
222 */
223 rate = clk_get_rate(priv->aclk);
Fabrice Gasnierf66f18e2017-10-18 13:40:12 +0200224 if (!rate) {
225 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
226 return -EINVAL;
227 }
Fabrice Gasnier95e339b2017-05-29 11:28:20 +0200228
229 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
230 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
231 presc = stm32h7_adc_ckmodes_spec[i].presc;
232 div = stm32h7_adc_ckmodes_spec[i].div;
233
234 if (ckmode)
235 continue;
236
237 if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
238 goto out;
239 }
240 }
241
242 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
243 rate = clk_get_rate(priv->bclk);
Fabrice Gasnierf66f18e2017-10-18 13:40:12 +0200244 if (!rate) {
245 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
246 return -EINVAL;
247 }
Fabrice Gasnier95e339b2017-05-29 11:28:20 +0200248
249 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
250 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
251 presc = stm32h7_adc_ckmodes_spec[i].presc;
252 div = stm32h7_adc_ckmodes_spec[i].div;
253
254 if (!ckmode)
255 continue;
256
257 if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
258 goto out;
259 }
260
261 dev_err(&pdev->dev, "adc clk selection failed\n");
262 return -EINVAL;
263
264out:
265 /* rate used later by each ADC instance to control BOOST mode */
Fabrice Gasnier50dbe1f2017-07-24 18:10:38 +0200266 priv->common.rate = rate / div;
Fabrice Gasnier95e339b2017-05-29 11:28:20 +0200267
268 /* Set common clock mode and prescaler */
269 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
270 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
271 val |= ckmode << STM32H7_CKMODE_SHIFT;
272 val |= presc << STM32H7_PRESC_SHIFT;
273 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
274
275 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
Fabrice Gasnier50dbe1f2017-07-24 18:10:38 +0200276 ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
Fabrice Gasnier95e339b2017-05-29 11:28:20 +0200277
278 return 0;
279}
280
Fabrice Gasnier64ad7f62017-05-29 11:28:18 +0200281/* STM32F4 common registers definitions */
282static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
283 .csr = STM32F4_ADC_CSR,
284 .eoc1_msk = STM32F4_EOC1,
285 .eoc2_msk = STM32F4_EOC2,
286 .eoc3_msk = STM32F4_EOC3,
287};
288
Fabrice Gasnier95e339b2017-05-29 11:28:20 +0200289/* STM32H7 common registers definitions */
290static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
291 .csr = STM32H7_ADC_CSR,
292 .eoc1_msk = STM32H7_EOC_MST,
293 .eoc2_msk = STM32H7_EOC_SLV,
294};
295
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100296/* ADC common interrupt for all instances */
297static void stm32_adc_irq_handler(struct irq_desc *desc)
298{
299 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
300 struct irq_chip *chip = irq_desc_get_chip(desc);
301 u32 status;
302
303 chained_irq_enter(chip, desc);
Fabrice Gasnier64ad7f62017-05-29 11:28:18 +0200304 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100305
Fabrice Gasnier64ad7f62017-05-29 11:28:18 +0200306 if (status & priv->cfg->regs->eoc1_msk)
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100307 generic_handle_irq(irq_find_mapping(priv->domain, 0));
308
Fabrice Gasnier64ad7f62017-05-29 11:28:18 +0200309 if (status & priv->cfg->regs->eoc2_msk)
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100310 generic_handle_irq(irq_find_mapping(priv->domain, 1));
311
Fabrice Gasnier64ad7f62017-05-29 11:28:18 +0200312 if (status & priv->cfg->regs->eoc3_msk)
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100313 generic_handle_irq(irq_find_mapping(priv->domain, 2));
314
315 chained_irq_exit(chip, desc);
316};
317
318static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
319 irq_hw_number_t hwirq)
320{
321 irq_set_chip_data(irq, d->host_data);
322 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
323
324 return 0;
325}
326
327static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
328{
329 irq_set_chip_and_handler(irq, NULL, NULL);
330 irq_set_chip_data(irq, NULL);
331}
332
333static const struct irq_domain_ops stm32_adc_domain_ops = {
334 .map = stm32_adc_domain_map,
335 .unmap = stm32_adc_domain_unmap,
336 .xlate = irq_domain_xlate_onecell,
337};
338
339static int stm32_adc_irq_probe(struct platform_device *pdev,
340 struct stm32_adc_priv *priv)
341{
342 struct device_node *np = pdev->dev.of_node;
343
344 priv->irq = platform_get_irq(pdev, 0);
345 if (priv->irq < 0) {
346 dev_err(&pdev->dev, "failed to get irq\n");
347 return priv->irq;
348 }
349
350 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
351 &stm32_adc_domain_ops,
352 priv);
353 if (!priv->domain) {
354 dev_err(&pdev->dev, "Failed to add irq domain\n");
355 return -ENOMEM;
356 }
357
358 irq_set_chained_handler(priv->irq, stm32_adc_irq_handler);
359 irq_set_handler_data(priv->irq, priv);
360
361 return 0;
362}
363
364static void stm32_adc_irq_remove(struct platform_device *pdev,
365 struct stm32_adc_priv *priv)
366{
367 int hwirq;
368
369 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
370 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
371 irq_domain_remove(priv->domain);
372 irq_set_chained_handler(priv->irq, NULL);
373}
374
375static int stm32_adc_probe(struct platform_device *pdev)
376{
377 struct stm32_adc_priv *priv;
Fabrice Gasnier64ad7f62017-05-29 11:28:18 +0200378 struct device *dev = &pdev->dev;
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100379 struct device_node *np = pdev->dev.of_node;
380 struct resource *res;
381 int ret;
382
383 if (!pdev->dev.of_node)
384 return -ENODEV;
385
386 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
387 if (!priv)
388 return -ENOMEM;
389
Fabrice Gasnier64ad7f62017-05-29 11:28:18 +0200390 priv->cfg = (const struct stm32_adc_priv_cfg *)
391 of_match_device(dev->driver->of_match_table, dev)->data;
392
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100393 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
394 priv->common.base = devm_ioremap_resource(&pdev->dev, res);
395 if (IS_ERR(priv->common.base))
396 return PTR_ERR(priv->common.base);
Fabrice Gasnier2763ea02017-01-26 15:28:33 +0100397 priv->common.phys_base = res->start;
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100398
399 priv->vref = devm_regulator_get(&pdev->dev, "vref");
400 if (IS_ERR(priv->vref)) {
401 ret = PTR_ERR(priv->vref);
402 dev_err(&pdev->dev, "vref get failed, %d\n", ret);
403 return ret;
404 }
405
406 ret = regulator_enable(priv->vref);
407 if (ret < 0) {
408 dev_err(&pdev->dev, "vref enable failed\n");
409 return ret;
410 }
411
412 ret = regulator_get_voltage(priv->vref);
413 if (ret < 0) {
414 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
415 goto err_regulator_disable;
416 }
417 priv->common.vref_mv = ret / 1000;
418 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
419
420 priv->aclk = devm_clk_get(&pdev->dev, "adc");
421 if (IS_ERR(priv->aclk)) {
422 ret = PTR_ERR(priv->aclk);
Fabrice Gasnier9fd243c2017-05-29 11:28:17 +0200423 if (ret == -ENOENT) {
424 priv->aclk = NULL;
425 } else {
426 dev_err(&pdev->dev, "Can't get 'adc' clock\n");
427 goto err_regulator_disable;
428 }
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100429 }
430
Fabrice Gasnier9fd243c2017-05-29 11:28:17 +0200431 if (priv->aclk) {
432 ret = clk_prepare_enable(priv->aclk);
433 if (ret < 0) {
434 dev_err(&pdev->dev, "adc clk enable failed\n");
435 goto err_regulator_disable;
436 }
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100437 }
438
Fabrice Gasnier95e339b2017-05-29 11:28:20 +0200439 priv->bclk = devm_clk_get(&pdev->dev, "bus");
440 if (IS_ERR(priv->bclk)) {
441 ret = PTR_ERR(priv->bclk);
442 if (ret == -ENOENT) {
443 priv->bclk = NULL;
444 } else {
445 dev_err(&pdev->dev, "Can't get 'bus' clock\n");
446 goto err_aclk_disable;
447 }
448 }
449
450 if (priv->bclk) {
451 ret = clk_prepare_enable(priv->bclk);
452 if (ret < 0) {
453 dev_err(&pdev->dev, "adc clk enable failed\n");
454 goto err_aclk_disable;
455 }
456 }
457
Fabrice Gasnier64ad7f62017-05-29 11:28:18 +0200458 ret = priv->cfg->clk_sel(pdev, priv);
Fabrice Gasnier9fd243c2017-05-29 11:28:17 +0200459 if (ret < 0)
Fabrice Gasnier95e339b2017-05-29 11:28:20 +0200460 goto err_bclk_disable;
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100461
462 ret = stm32_adc_irq_probe(pdev, priv);
463 if (ret < 0)
Fabrice Gasnier95e339b2017-05-29 11:28:20 +0200464 goto err_bclk_disable;
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100465
466 platform_set_drvdata(pdev, &priv->common);
467
468 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
469 if (ret < 0) {
470 dev_err(&pdev->dev, "failed to populate DT children\n");
471 goto err_irq_remove;
472 }
473
474 return 0;
475
476err_irq_remove:
477 stm32_adc_irq_remove(pdev, priv);
478
Fabrice Gasnier95e339b2017-05-29 11:28:20 +0200479err_bclk_disable:
480 if (priv->bclk)
481 clk_disable_unprepare(priv->bclk);
482
483err_aclk_disable:
Fabrice Gasnier9fd243c2017-05-29 11:28:17 +0200484 if (priv->aclk)
485 clk_disable_unprepare(priv->aclk);
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100486
487err_regulator_disable:
488 regulator_disable(priv->vref);
489
490 return ret;
491}
492
493static int stm32_adc_remove(struct platform_device *pdev)
494{
495 struct stm32_adc_common *common = platform_get_drvdata(pdev);
496 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
497
498 of_platform_depopulate(&pdev->dev);
499 stm32_adc_irq_remove(pdev, priv);
Fabrice Gasnier95e339b2017-05-29 11:28:20 +0200500 if (priv->bclk)
501 clk_disable_unprepare(priv->bclk);
Fabrice Gasnier9fd243c2017-05-29 11:28:17 +0200502 if (priv->aclk)
503 clk_disable_unprepare(priv->aclk);
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100504 regulator_disable(priv->vref);
505
506 return 0;
507}
508
Fabrice Gasnier64ad7f62017-05-29 11:28:18 +0200509static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
510 .regs = &stm32f4_adc_common_regs,
511 .clk_sel = stm32f4_adc_clk_sel,
512};
513
Fabrice Gasnier95e339b2017-05-29 11:28:20 +0200514static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
515 .regs = &stm32h7_adc_common_regs,
516 .clk_sel = stm32h7_adc_clk_sel,
517};
518
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100519static const struct of_device_id stm32_adc_of_match[] = {
Fabrice Gasnier64ad7f62017-05-29 11:28:18 +0200520 {
521 .compatible = "st,stm32f4-adc-core",
522 .data = (void *)&stm32f4_adc_priv_cfg
523 }, {
Fabrice Gasnier95e339b2017-05-29 11:28:20 +0200524 .compatible = "st,stm32h7-adc-core",
525 .data = (void *)&stm32h7_adc_priv_cfg
526 }, {
Fabrice Gasnier64ad7f62017-05-29 11:28:18 +0200527 },
Fabrice Gasnier1add69882016-11-15 16:30:57 +0100528};
529MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
530
531static struct platform_driver stm32_adc_driver = {
532 .probe = stm32_adc_probe,
533 .remove = stm32_adc_remove,
534 .driver = {
535 .name = "stm32-adc-core",
536 .of_match_table = stm32_adc_of_match,
537 },
538};
539module_platform_driver(stm32_adc_driver);
540
541MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
542MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
543MODULE_LICENSE("GPL v2");
544MODULE_ALIAS("platform:stm32-adc-core");