blob: e6220809ca11730061320fe500d9cd424faa683e [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/init.h>
18
19#include <linux/mm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020#include <linux/delay.h>
21#include <linux/bootmem.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <linux/interrupt.h>
23#include <linux/mc146818rtc.h>
24#include <linux/kernel_stat.h>
25#include <linux/sysdev.h>
Aaron Durbin39928722006-12-07 02:14:01 +010026#include <linux/ioport.h>
Yinghai Lu773763d2008-08-24 02:01:52 -070027#include <linux/cpu.h>
Thomas Gleixnerba7eda42007-10-12 23:04:07 +020028#include <linux/clockchips.h>
Thomas Gleixner70a20022008-01-30 13:30:18 +010029#include <linux/acpi_pmtmr.h>
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +010030#include <linux/module.h>
Yinghai Lu773763d2008-08-24 02:01:52 -070031#include <linux/dmi.h>
Suresh Siddha6e1cb382008-07-10 11:16:58 -070032#include <linux/dmar.h>
Frederic Weisbeckerbcbc4f22008-12-09 23:54:20 +010033#include <linux/ftrace.h>
Jaswinder Singh Rajpute423e332009-01-04 16:16:25 +053034#include <linux/smp.h>
35#include <linux/nmi.h>
36#include <linux/timex.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
38#include <asm/atomic.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#include <asm/mtrr.h>
40#include <asm/mpspec.h>
Yinghai Luefa25592008-08-19 20:50:36 -070041#include <asm/desc.h>
Yinghai Lu773763d2008-08-24 02:01:52 -070042#include <asm/arch_hooks.h>
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +010043#include <asm/hpet.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070044#include <asm/pgalloc.h>
Yinghai Lu773763d2008-08-24 02:01:52 -070045#include <asm/i8253.h>
Andi Kleen95833c82006-01-11 22:44:36 +010046#include <asm/idle.h>
Andi Kleen73dea472006-02-03 21:50:50 +010047#include <asm/proto.h>
Andi Kleen2c8c0e62006-09-26 10:52:32 +020048#include <asm/apic.h>
Suresh Siddha6e1cb382008-07-10 11:16:58 -070049#include <asm/i8259.h>
Jaswinder Singh Rajput2bc13792009-01-11 20:34:47 +053050#include <asm/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
Glauber Costadd46e3c2008-03-25 18:10:46 -030052#include <mach_apic.h>
Yinghai Lu773763d2008-08-24 02:01:52 -070053#include <mach_ipi.h>
Glauber Costa5af55732008-03-25 13:28:56 -030054
Cyrill Gorcunov80e56092008-08-24 02:01:42 -070055/*
56 * Sanity check
57 */
58#if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
59# error SPURIOUS_APIC_VECTOR definition error
60#endif
61
Brian Gerstec70de82009-01-27 12:56:47 +090062unsigned int num_processors;
63unsigned disabled_cpus __cpuinitdata;
64/* Processor that is doing the boot up */
65unsigned int boot_cpu_physical_apicid = -1U;
66EXPORT_SYMBOL(boot_cpu_physical_apicid);
67unsigned int max_physical_apicid;
68
69/* Bitmask of physically existing CPUs */
70physid_mask_t phys_cpu_present_map;
71
72/*
73 * Map cpu index to physical APIC ID
74 */
75DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
76DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
77EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
78EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
79
Yinghai Lub3c51172008-08-24 02:01:46 -070080#ifdef CONFIG_X86_32
81/*
82 * Knob to control our willingness to enable the local APIC.
83 *
84 * +1=force-enable
85 */
86static int force_enable_local_apic;
87/*
88 * APIC command line parameters
89 */
90static int __init parse_lapic(char *arg)
91{
92 force_enable_local_apic = 1;
93 return 0;
94}
95early_param("lapic", parse_lapic);
Yinghai Luf28c0ae2008-08-24 02:01:49 -070096/* Local APIC was disabled by the BIOS and enabled by the kernel */
97static int enabled_via_apicbase;
98
Yinghai Lub3c51172008-08-24 02:01:46 -070099#endif
100
101#ifdef CONFIG_X86_64
Chris Wrightbc1d99c2007-10-12 23:04:23 +0200102static int apic_calibrate_pmtmr __initdata;
Yinghai Lub3c51172008-08-24 02:01:46 -0700103static __init int setup_apicpmtimer(char *s)
104{
105 apic_calibrate_pmtmr = 1;
106 notsc_setup(NULL);
107 return 0;
108}
109__setup("apicpmtimer", setup_apicpmtimer);
110#endif
111
Yinghai Lu49899ea2008-08-24 02:01:47 -0700112#ifdef CONFIG_X86_64
113#define HAVE_X2APIC
114#endif
115
116#ifdef HAVE_X2APIC
Suresh Siddha89027d32008-07-10 11:16:56 -0700117int x2apic;
Suresh Siddha6e1cb382008-07-10 11:16:58 -0700118/* x2apic enabled before OS handover */
Jaswinder Singhb6b301a2008-12-23 21:52:33 +0530119static int x2apic_preenabled;
120static int disable_x2apic;
Yinghai Lu49899ea2008-08-24 02:01:47 -0700121static __init int setup_nox2apic(char *str)
122{
123 disable_x2apic = 1;
124 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
125 return 0;
126}
127early_param("nox2apic", setup_nox2apic);
128#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129
Yinghai Lub3c51172008-08-24 02:01:46 -0700130unsigned long mp_lapic_addr;
131int disable_apic;
132/* Disable local APIC timer from the kernel commandline or via dmi quirk */
133static int disable_apic_timer __cpuinitdata;
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +0100134/* Local APIC timer works in C2 */
Linus Torvalds2e7c2832007-03-23 11:32:31 -0700135int local_apic_timer_c2_ok;
136EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
137
Yinghai Luefa25592008-08-19 20:50:36 -0700138int first_system_vector = 0xfe;
139
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +0100140/*
141 * Debug level, exported for io_apic.c
142 */
Maciej W. Rozyckibaa13182008-07-14 18:44:51 +0100143unsigned int apic_verbosity;
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +0100144
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -0700145int pic_mode;
146
Alexey Starikovskiybab4b272008-05-19 19:47:03 +0400147/* Have we found an MP table */
148int smp_found_config;
149
Aaron Durbin39928722006-12-07 02:14:01 +0100150static struct resource lapic_resource = {
151 .name = "Local APIC",
152 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
153};
154
Thomas Gleixnerd03030e2007-10-12 23:04:06 +0200155static unsigned int calibration_result;
156
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200157static int lapic_next_event(unsigned long delta,
158 struct clock_event_device *evt);
159static void lapic_timer_setup(enum clock_event_mode mode,
160 struct clock_event_device *evt);
Mike Travis96289372008-12-31 18:08:46 -0800161static void lapic_timer_broadcast(const struct cpumask *mask);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100162static void apic_pm_activate(void);
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200163
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400164/*
165 * The local apic timer can be used for any function which is CPU local.
166 */
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200167static struct clock_event_device lapic_clockevent = {
168 .name = "lapic",
169 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
170 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
171 .shift = 32,
172 .set_mode = lapic_timer_setup,
173 .set_next_event = lapic_next_event,
174 .broadcast = lapic_timer_broadcast,
175 .rating = 100,
176 .irq = -1,
177};
178static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
179
Andi Kleend3432892008-01-30 13:33:17 +0100180static unsigned long apic_phys;
181
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100182/*
183 * Get the LAPIC version
184 */
185static inline int lapic_get_version(void)
186{
187 return GET_APIC_VERSION(apic_read(APIC_LVR));
188}
189
190/*
Cyrill Gorcunov9c803862008-08-16 23:21:54 +0400191 * Check, if the APIC is integrated or a separate chip
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100192 */
193static inline int lapic_is_integrated(void)
194{
Cyrill Gorcunov9c803862008-08-16 23:21:54 +0400195#ifdef CONFIG_X86_64
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100196 return 1;
Cyrill Gorcunov9c803862008-08-16 23:21:54 +0400197#else
198 return APIC_INTEGRATED(lapic_get_version());
199#endif
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100200}
201
202/*
203 * Check, whether this is a modern or a first generation APIC
204 */
205static int modern_apic(void)
206{
207 /* AMD systems use old APIC versions, so check the CPU */
208 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
209 boot_cpu_data.x86 >= 0xf)
210 return 1;
211 return lapic_get_version() >= 0x14;
212}
213
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400214/*
215 * Paravirt kernels also might be using these below ops. So we still
216 * use generic apic_read()/apic_write(), which might be pointing to different
217 * ops in PARAVIRT case.
218 */
Suresh Siddha1b374e42008-07-10 11:16:49 -0700219void xapic_wait_icr_idle(void)
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100220{
221 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
222 cpu_relax();
223}
224
Suresh Siddha1b374e42008-07-10 11:16:49 -0700225u32 safe_xapic_wait_icr_idle(void)
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100226{
227 u32 send_status;
228 int timeout;
229
230 timeout = 0;
231 do {
232 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
233 if (!send_status)
234 break;
235 udelay(100);
236 } while (timeout++ < 1000);
237
238 return send_status;
239}
240
Suresh Siddha1b374e42008-07-10 11:16:49 -0700241void xapic_icr_write(u32 low, u32 id)
242{
Cyrill Gorcunoved4e5ec2008-08-15 13:51:20 +0200243 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
Suresh Siddha1b374e42008-07-10 11:16:49 -0700244 apic_write(APIC_ICR, low);
245}
246
Jaswinder Singh Rajputec8c8422008-12-30 22:46:36 +0530247static u64 xapic_icr_read(void)
Suresh Siddha1b374e42008-07-10 11:16:49 -0700248{
249 u32 icr1, icr2;
250
251 icr2 = apic_read(APIC_ICR2);
252 icr1 = apic_read(APIC_ICR);
253
Cyrill Gorcunovcf9768d72008-08-16 23:21:55 +0400254 return icr1 | ((u64)icr2 << 32);
Suresh Siddha1b374e42008-07-10 11:16:49 -0700255}
256
257static struct apic_ops xapic_ops = {
258 .read = native_apic_mem_read,
259 .write = native_apic_mem_write,
Suresh Siddha1b374e42008-07-10 11:16:49 -0700260 .icr_read = xapic_icr_read,
261 .icr_write = xapic_icr_write,
262 .wait_icr_idle = xapic_wait_icr_idle,
263 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
264};
265
266struct apic_ops __read_mostly *apic_ops = &xapic_ops;
Suresh Siddha1b374e42008-07-10 11:16:49 -0700267EXPORT_SYMBOL_GPL(apic_ops);
268
Yinghai Lu49899ea2008-08-24 02:01:47 -0700269#ifdef HAVE_X2APIC
Suresh Siddha13c88fb52008-07-10 11:16:52 -0700270static void x2apic_wait_icr_idle(void)
271{
272 /* no need to wait for icr idle in x2apic */
273 return;
274}
275
276static u32 safe_x2apic_wait_icr_idle(void)
277{
278 /* no need to wait for icr idle in x2apic */
279 return 0;
280}
281
282void x2apic_icr_write(u32 low, u32 id)
283{
284 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
285}
286
Jaswinder Singh Rajputec8c8422008-12-30 22:46:36 +0530287static u64 x2apic_icr_read(void)
Suresh Siddha13c88fb52008-07-10 11:16:52 -0700288{
289 unsigned long val;
290
291 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
292 return val;
293}
294
295static struct apic_ops x2apic_ops = {
296 .read = native_apic_msr_read,
297 .write = native_apic_msr_write,
Suresh Siddha13c88fb52008-07-10 11:16:52 -0700298 .icr_read = x2apic_icr_read,
299 .icr_write = x2apic_icr_write,
300 .wait_icr_idle = x2apic_wait_icr_idle,
301 .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
302};
Yinghai Lu49899ea2008-08-24 02:01:47 -0700303#endif
Suresh Siddha13c88fb52008-07-10 11:16:52 -0700304
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100305/**
306 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
307 */
Jan Beuliche9427102008-01-30 13:31:24 +0100308void __cpuinit enable_NMI_through_LVT0(void)
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100309{
310 unsigned int v;
311
312 /* unmask and set to NMI */
313 v = APIC_DM_NMI;
Cyrill Gorcunovd4c63ec2008-07-24 13:52:29 +0200314
315 /* Level triggered for 82489DX (32bit mode) */
316 if (!lapic_is_integrated())
317 v |= APIC_LVT_LEVEL_TRIGGER;
318
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100319 apic_write(APIC_LVT0, v);
320}
321
Cyrill Gorcunov7c37e482008-08-24 02:01:40 -0700322#ifdef CONFIG_X86_32
323/**
324 * get_physical_broadcast - Get number of physical broadcast IDs
325 */
326int get_physical_broadcast(void)
327{
328 return modern_apic() ? 0xff : 0xf;
329}
330#endif
331
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100332/**
333 * lapic_get_maxlvt - get the maximum number of local vector table entries
334 */
335int lapic_get_maxlvt(void)
336{
Cyrill Gorcunov36a028d2008-07-24 13:52:28 +0200337 unsigned int v;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100338
339 v = apic_read(APIC_LVR);
Cyrill Gorcunov36a028d2008-07-24 13:52:28 +0200340 /*
341 * - we always have APIC integrated on 64bit mode
342 * - 82489DXs do not report # of LVT entries
343 */
344 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100345}
346
347/*
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400348 * Local APIC timer
349 */
350
Cyrill Gorcunovc40aaec2008-08-18 20:45:55 +0400351/* Clock divisor */
Cyrill Gorcunovc40aaec2008-08-18 20:45:55 +0400352#define APIC_DIVISOR 16
Cyrill Gorcunovf07f4f92008-08-15 13:51:21 +0200353
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100354/*
355 * This function sets up the local APIC timer, with a timeout of
356 * 'clocks' APIC bus clock. During calibration we actually call
357 * this function twice on the boot CPU, once with a bogus timeout
358 * value, second time for real. The other (noncalibrating) CPUs
359 * call this function only once, with the real, calibrated value.
360 *
361 * We do reads before writes even if unnecessary, to get around the
362 * P5 APIC double write bug.
363 */
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100364static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
365{
366 unsigned int lvtt_value, tmp_value;
367
368 lvtt_value = LOCAL_TIMER_VECTOR;
369 if (!oneshot)
370 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
Cyrill Gorcunovf07f4f92008-08-15 13:51:21 +0200371 if (!lapic_is_integrated())
372 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
373
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100374 if (!irqen)
375 lvtt_value |= APIC_LVT_MASKED;
376
377 apic_write(APIC_LVTT, lvtt_value);
378
379 /*
380 * Divide PICLK by 16
381 */
382 tmp_value = apic_read(APIC_TDCR);
Cyrill Gorcunovc40aaec2008-08-18 20:45:55 +0400383 apic_write(APIC_TDCR,
384 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
385 APIC_TDR_DIV_16);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100386
387 if (!oneshot)
Cyrill Gorcunovf07f4f92008-08-15 13:51:21 +0200388 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100389}
390
391/*
Robert Richter7b83dae2008-01-30 13:30:40 +0100392 * Setup extended LVT, AMD specific (K8, family 10h)
393 *
394 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
395 * MCE interrupts are supported. Thus MCE offset must be set to 0.
Robert Richter286f5712008-07-22 21:08:46 +0200396 *
397 * If mask=1, the LVT entry does not generate interrupts while mask=0
398 * enables the vector. See also the BKDGs.
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100399 */
Robert Richter7b83dae2008-01-30 13:30:40 +0100400
401#define APIC_EILVT_LVTOFF_MCE 0
402#define APIC_EILVT_LVTOFF_IBS 1
403
404static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100405{
Robert Richter7b83dae2008-01-30 13:30:40 +0100406 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100407 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
408
409 apic_write(reg, v);
410}
411
Robert Richter7b83dae2008-01-30 13:30:40 +0100412u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
413{
414 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
415 return APIC_EILVT_LVTOFF_MCE;
416}
417
418u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
419{
420 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
421 return APIC_EILVT_LVTOFF_IBS;
422}
Robert Richter6aa360e2008-07-23 15:28:14 +0200423EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
Robert Richter7b83dae2008-01-30 13:30:40 +0100424
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100425/*
426 * Program the next event, relative to now
427 */
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200428static int lapic_next_event(unsigned long delta,
429 struct clock_event_device *evt)
430{
431 apic_write(APIC_TMICT, delta);
432 return 0;
433}
434
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100435/*
436 * Setup the lapic timer in periodic or oneshot mode
437 */
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200438static void lapic_timer_setup(enum clock_event_mode mode,
439 struct clock_event_device *evt)
440{
441 unsigned long flags;
442 unsigned int v;
443
444 /* Lapic used as dummy for broadcast ? */
445 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
446 return;
447
448 local_irq_save(flags);
449
450 switch (mode) {
451 case CLOCK_EVT_MODE_PERIODIC:
452 case CLOCK_EVT_MODE_ONESHOT:
453 __setup_APIC_LVTT(calibration_result,
454 mode != CLOCK_EVT_MODE_PERIODIC, 1);
455 break;
456 case CLOCK_EVT_MODE_UNUSED:
457 case CLOCK_EVT_MODE_SHUTDOWN:
458 v = apic_read(APIC_LVTT);
459 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
460 apic_write(APIC_LVTT, v);
Thomas Gleixnera98f8fd2008-11-06 01:13:39 +0100461 apic_write(APIC_TMICT, 0xffffffff);
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200462 break;
463 case CLOCK_EVT_MODE_RESUME:
464 /* Nothing to do here */
465 break;
466 }
467
468 local_irq_restore(flags);
469}
470
471/*
472 * Local APIC timer broadcast function
473 */
Mike Travis96289372008-12-31 18:08:46 -0800474static void lapic_timer_broadcast(const struct cpumask *mask)
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200475{
476#ifdef CONFIG_SMP
Ingo Molnardac5f412009-01-28 15:42:24 +0100477 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200478#endif
479}
480
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100481/*
482 * Setup the local APIC timer for this CPU. Copy the initilized values
483 * of the boot CPU and register the clock event in the framework.
484 */
Cyrill Gorcunovdb4b5522008-08-24 02:01:39 -0700485static void __cpuinit setup_APIC_timer(void)
Fernando Luis VazquezCao8339e9f2007-05-02 19:27:17 +0200486{
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100487 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
488
489 memcpy(levt, &lapic_clockevent, sizeof(*levt));
Rusty Russell320ab2b2008-12-13 21:20:26 +1030490 levt->cpumask = cpumask_of(smp_processor_id());
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100491
492 clockevents_register_device(levt);
Fernando Luis VazquezCao8339e9f2007-05-02 19:27:17 +0200493}
494
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700495/*
496 * In this functions we calibrate APIC bus clocks to the external timer.
497 *
498 * We want to do the calibration only once since we want to have local timer
499 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
500 * frequency.
501 *
502 * This was previously done by reading the PIT/HPET and waiting for a wrap
503 * around to find out, that a tick has elapsed. I have a box, where the PIT
504 * readout is broken, so it never gets out of the wait loop again. This was
505 * also reported by others.
506 *
507 * Monitoring the jiffies value is inaccurate and the clockevents
508 * infrastructure allows us to do a simple substitution of the interrupt
509 * handler.
510 *
511 * The calibration routine also uses the pm_timer when possible, as the PIT
512 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
513 * back to normal later in the boot process).
514 */
515
516#define LAPIC_CAL_LOOPS (HZ/10)
517
518static __initdata int lapic_cal_loops = -1;
519static __initdata long lapic_cal_t1, lapic_cal_t2;
520static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
521static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
522static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
523
524/*
525 * Temporary interrupt handler.
526 */
527static void __init lapic_cal_handler(struct clock_event_device *dev)
528{
529 unsigned long long tsc = 0;
530 long tapic = apic_read(APIC_TMCCT);
531 unsigned long pm = acpi_pm_read_early();
532
533 if (cpu_has_tsc)
534 rdtscll(tsc);
535
536 switch (lapic_cal_loops++) {
537 case 0:
538 lapic_cal_t1 = tapic;
539 lapic_cal_tsc1 = tsc;
540 lapic_cal_pm1 = pm;
541 lapic_cal_j1 = jiffies;
542 break;
543
544 case LAPIC_CAL_LOOPS:
545 lapic_cal_t2 = tapic;
546 lapic_cal_tsc2 = tsc;
547 if (pm < lapic_cal_pm1)
548 pm += ACPI_PM_OVRRUN;
549 lapic_cal_pm2 = pm;
550 lapic_cal_j2 = jiffies;
551 break;
552 }
553}
554
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400555static int __init calibrate_by_pmtimer(long deltapm, long *delta)
556{
557 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
558 const long pm_thresh = pm_100ms / 100;
559 unsigned long mult;
560 u64 res;
561
562#ifndef CONFIG_X86_PM_TIMER
563 return -1;
564#endif
565
566 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
567
568 /* Check, if the PM timer is available */
569 if (!deltapm)
570 return -1;
571
572 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
573
574 if (deltapm > (pm_100ms - pm_thresh) &&
575 deltapm < (pm_100ms + pm_thresh)) {
576 apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
577 } else {
578 res = (((u64)deltapm) * mult) >> 22;
579 do_div(res, 1000000);
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100580 pr_warning("APIC calibration not consistent "
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400581 "with PM Timer: %ldms instead of 100ms\n",
582 (long)res);
583 /* Correct the lapic counter value */
584 res = (((u64)(*delta)) * pm_100ms);
585 do_div(res, deltapm);
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100586 pr_info("APIC delta adjusted to PM-Timer: "
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400587 "%lu (%ld)\n", (unsigned long)res, *delta);
588 *delta = (long)res;
589 }
590
591 return 0;
592}
593
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700594static int __init calibrate_APIC_clock(void)
595{
596 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700597 void (*real_handler)(struct clock_event_device *dev);
598 unsigned long deltaj;
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400599 long delta;
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700600 int pm_referenced = 0;
601
602 local_irq_disable();
603
604 /* Replace the global interrupt handler */
605 real_handler = global_clock_event->event_handler;
606 global_clock_event->event_handler = lapic_cal_handler;
607
608 /*
Cyrill Gorcunov81608f32008-10-10 19:00:17 +0400609 * Setup the APIC counter to maximum. There is no way the lapic
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700610 * can underflow in the 100ms detection time frame
611 */
Cyrill Gorcunov81608f32008-10-10 19:00:17 +0400612 __setup_APIC_LVTT(0xffffffff, 0, 0);
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700613
614 /* Let the interrupts run */
615 local_irq_enable();
616
617 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
618 cpu_relax();
619
620 local_irq_disable();
621
622 /* Restore the real event handler */
623 global_clock_event->event_handler = real_handler;
624
625 /* Build delta t1-t2 as apic timer counts down */
626 delta = lapic_cal_t1 - lapic_cal_t2;
627 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
628
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400629 /* we trust the PM based calibration if possible */
630 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
631 &delta);
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700632
633 /* Calculate the scaled math multiplication factor */
634 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
635 lapic_clockevent.shift);
636 lapic_clockevent.max_delta_ns =
637 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
638 lapic_clockevent.min_delta_ns =
639 clockevent_delta2ns(0xF, &lapic_clockevent);
640
641 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
642
643 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
644 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
645 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
646 calibration_result);
647
648 if (cpu_has_tsc) {
649 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
650 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
651 "%ld.%04ld MHz.\n",
652 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
653 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
654 }
655
656 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
657 "%u.%04u MHz.\n",
658 calibration_result / (1000000 / HZ),
659 calibration_result % (1000000 / HZ));
660
661 /*
662 * Do a sanity check on the APIC calibration result
663 */
664 if (calibration_result < (1000000 / HZ)) {
665 local_irq_enable();
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100666 pr_warning("APIC frequency too slow, disabling apic timer\n");
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700667 return -1;
668 }
669
670 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
671
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400672 /*
673 * PM timer calibration failed or not turned on
674 * so lets try APIC timer based calibration
675 */
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700676 if (!pm_referenced) {
677 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
678
679 /*
680 * Setup the apic timer manually
681 */
682 levt->event_handler = lapic_cal_handler;
683 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
684 lapic_cal_loops = -1;
685
686 /* Let the interrupts run */
687 local_irq_enable();
688
689 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
690 cpu_relax();
691
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700692 /* Stop the lapic timer */
693 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
694
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700695 /* Jiffies delta */
696 deltaj = lapic_cal_j2 - lapic_cal_j1;
697 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
698
699 /* Check, if the jiffies result is consistent */
700 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
701 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
702 else
703 levt->features |= CLOCK_EVT_FEAT_DUMMY;
704 } else
705 local_irq_enable();
706
707 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
Jaswinder Singh Rajpute423e332009-01-04 16:16:25 +0530708 pr_warning("APIC timer disabled due to verification failure\n");
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700709 return -1;
710 }
711
712 return 0;
713}
714
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +0100715/*
716 * Setup the boot APIC
717 *
718 * Calibrate and verify the result.
719 */
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100720void __init setup_boot_APIC_clock(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721{
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100722 /*
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400723 * The local apic timer can be disabled via the kernel
724 * commandline or from the CPU detection code. Register the lapic
725 * timer as a dummy clock event source on SMP systems, so the
726 * broadcast mechanism is used. On UP systems simply ignore it.
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100727 */
728 if (disable_apic_timer) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100729 pr_info("Disabling APIC timer\n");
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100730 /* No broadcast on UP ! */
Thomas Gleixner9d099512008-01-30 13:33:04 +0100731 if (num_possible_cpus() > 1) {
732 lapic_clockevent.mult = 1;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100733 setup_APIC_timer();
Thomas Gleixner9d099512008-01-30 13:33:04 +0100734 }
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100735 return;
736 }
Thomas Gleixner6935d1f2007-07-21 17:10:17 +0200737
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400738 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
739 "calibrating APIC timer ...\n");
740
Cyrill Gorcunov89b3b1f2008-07-15 21:02:54 +0400741 if (calibrate_APIC_clock()) {
Thomas Gleixnerc2b84b32008-01-30 13:33:04 +0100742 /* No broadcast on UP ! */
743 if (num_possible_cpus() > 1)
744 setup_APIC_timer();
745 return;
746 }
747
748 /*
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100749 * If nmi_watchdog is set to IO_APIC, we need the
750 * PIT/HPET going. Otherwise register lapic as a dummy
751 * device.
752 */
753 if (nmi_watchdog != NMI_IO_APIC)
754 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
755 else
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100756 pr_warning("APIC timer registered as dummy,"
Cyrill Gorcunov116f5702008-06-24 22:52:04 +0200757 " due to nmi_watchdog=%d!\n", nmi_watchdog);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100758
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400759 /* Setup the lapic or request the broadcast */
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100760 setup_APIC_timer();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761}
762
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100763void __cpuinit setup_secondary_APIC_clock(void)
764{
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100765 setup_APIC_timer();
766}
767
768/*
769 * The guts of the apic timer interrupt
770 */
771static void local_apic_timer_interrupt(void)
772{
773 int cpu = smp_processor_id();
774 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
775
776 /*
777 * Normally we should not be here till LAPIC has been initialized but
778 * in some cases like kdump, its possible that there is a pending LAPIC
779 * timer interrupt from previous kernel's context and is delivered in
780 * new kernel the moment interrupts are enabled.
781 *
782 * Interrupts are enabled early and LAPIC is setup much later, hence
783 * its possible that when we get here evt->event_handler is NULL.
784 * Check for event_handler being NULL and discard the interrupt as
785 * spurious.
786 */
787 if (!evt->event_handler) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100788 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100789 /* Switch it off */
790 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
791 return;
792 }
793
794 /*
795 * the NMI deadlock-detector uses this.
796 */
Hiroshi Shimamoto915b0d02008-12-08 19:19:26 -0800797 inc_irq_stat(apic_timer_irqs);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100798
799 evt->event_handler(evt);
800}
801
802/*
803 * Local APIC timer interrupt. This is the most natural way for doing
804 * local interrupts, but local timer interrupts can be emulated by
805 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
806 *
807 * [ if a single-CPU system runs an SMP kernel then we call the local
808 * interrupt as well. Thus we cannot inline the local irq ... ]
809 */
Frederic Weisbeckerbcbc4f22008-12-09 23:54:20 +0100810void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100811{
812 struct pt_regs *old_regs = set_irq_regs(regs);
813
814 /*
815 * NOTE! We'd better ACK the irq immediately,
816 * because timer handling can be slow.
817 */
818 ack_APIC_irq();
819 /*
820 * update_process_times() expects us to have done irq_enter().
821 * Besides, if we don't timer interrupts ignore the global
822 * interrupt lock, which is the WrongThing (tm) to do.
823 */
824 exit_idle();
825 irq_enter();
826 local_apic_timer_interrupt();
827 irq_exit();
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400828
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100829 set_irq_regs(old_regs);
830}
831
832int setup_profiling_timer(unsigned int multiplier)
833{
834 return -EINVAL;
835}
836
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100837/*
838 * Local APIC start and shutdown
839 */
840
841/**
842 * clear_local_APIC - shutdown the local APIC
843 *
844 * This is called, when a CPU is disabled and before rebooting, so the state of
845 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
846 * leftovers during boot.
847 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700848void clear_local_APIC(void)
849{
Chuck Ebbert2584a822008-05-20 18:18:12 -0400850 int maxlvt;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100851 u32 v;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700852
Andi Kleend3432892008-01-30 13:33:17 +0100853 /* APIC hasn't been mapped yet */
854 if (!apic_phys)
855 return;
856
857 maxlvt = lapic_get_maxlvt();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858 /*
Siddha, Suresh B704fc592006-06-26 13:59:53 +0200859 * Masking an LVT entry can trigger a local APIC error
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860 * if the vector is zero. Mask LVTERR first to prevent this.
861 */
862 if (maxlvt >= 3) {
863 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
Andi Kleen11a8e772006-01-11 22:46:51 +0100864 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865 }
866 /*
867 * Careful: we have to set masks only first to deassert
868 * any level-triggered sources.
869 */
870 v = apic_read(APIC_LVTT);
Andi Kleen11a8e772006-01-11 22:46:51 +0100871 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700872 v = apic_read(APIC_LVT0);
Andi Kleen11a8e772006-01-11 22:46:51 +0100873 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874 v = apic_read(APIC_LVT1);
Andi Kleen11a8e772006-01-11 22:46:51 +0100875 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876 if (maxlvt >= 4) {
877 v = apic_read(APIC_LVTPC);
Andi Kleen11a8e772006-01-11 22:46:51 +0100878 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700879 }
880
Cyrill Gorcunov67640142008-08-16 23:21:50 +0400881 /* lets not touch this if we didn't frob it */
882#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
883 if (maxlvt >= 5) {
884 v = apic_read(APIC_LVTTHMR);
885 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
886 }
887#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700888 /*
889 * Clean APIC state for other OSs:
890 */
Andi Kleen11a8e772006-01-11 22:46:51 +0100891 apic_write(APIC_LVTT, APIC_LVT_MASKED);
892 apic_write(APIC_LVT0, APIC_LVT_MASKED);
893 apic_write(APIC_LVT1, APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700894 if (maxlvt >= 3)
Andi Kleen11a8e772006-01-11 22:46:51 +0100895 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896 if (maxlvt >= 4)
Andi Kleen11a8e772006-01-11 22:46:51 +0100897 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
Cyrill Gorcunov67640142008-08-16 23:21:50 +0400898
899 /* Integrated APIC (!82489DX) ? */
900 if (lapic_is_integrated()) {
901 if (maxlvt > 3)
902 /* Clear ESR due to Pentium errata 3AP and 11AP */
903 apic_write(APIC_ESR, 0);
904 apic_read(APIC_ESR);
905 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700906}
907
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100908/**
909 * disable_local_APIC - clear and disable the local APIC
910 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700911void disable_local_APIC(void)
912{
913 unsigned int value;
914
Jan Beulicha08c4742009-01-14 12:28:51 +0000915 /* APIC hasn't been mapped yet */
916 if (!apic_phys)
917 return;
918
Linus Torvalds1da177e2005-04-16 15:20:36 -0700919 clear_local_APIC();
920
921 /*
922 * Disable APIC (implies clearing of registers
923 * for 82489DX!).
924 */
925 value = apic_read(APIC_SPIV);
926 value &= ~APIC_SPIV_APIC_ENABLED;
Andi Kleen11a8e772006-01-11 22:46:51 +0100927 apic_write(APIC_SPIV, value);
Cyrill Gorcunov990b1832008-08-18 20:45:51 +0400928
929#ifdef CONFIG_X86_32
930 /*
931 * When LAPIC was disabled by the BIOS and enabled by the kernel,
932 * restore the disabled state.
933 */
934 if (enabled_via_apicbase) {
935 unsigned int l, h;
936
937 rdmsr(MSR_IA32_APICBASE, l, h);
938 l &= ~MSR_IA32_APICBASE_ENABLE;
939 wrmsr(MSR_IA32_APICBASE, l, h);
940 }
941#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700942}
943
Cyrill Gorcunovfe4024d2008-08-18 20:45:52 +0400944/*
945 * If Linux enabled the LAPIC against the BIOS default disable it down before
946 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
947 * not power-off. Additionally clear all LVT entries before disable_local_APIC
948 * for the case where Linux didn't enable the LAPIC.
949 */
Hiroshi Shimamoto9b7711f2007-10-19 18:21:11 -0700950void lapic_shutdown(void)
951{
952 unsigned long flags;
953
954 if (!cpu_has_apic)
955 return;
956
957 local_irq_save(flags);
958
Cyrill Gorcunovfe4024d2008-08-18 20:45:52 +0400959#ifdef CONFIG_X86_32
960 if (!enabled_via_apicbase)
961 clear_local_APIC();
962 else
963#endif
964 disable_local_APIC();
965
Hiroshi Shimamoto9b7711f2007-10-19 18:21:11 -0700966
967 local_irq_restore(flags);
968}
969
Linus Torvalds1da177e2005-04-16 15:20:36 -0700970/*
971 * This is to verify that we're looking at a real local APIC.
972 * Check these against your board if the CPUs aren't getting
973 * started for no apparent reason.
974 */
975int __init verify_local_APIC(void)
976{
977 unsigned int reg0, reg1;
978
979 /*
980 * The version register is read-only in a real APIC.
981 */
982 reg0 = apic_read(APIC_LVR);
983 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
984 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
985 reg1 = apic_read(APIC_LVR);
986 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
987
988 /*
989 * The two version reads above should print the same
990 * numbers. If the second one is different, then we
991 * poke at a non-APIC.
992 */
993 if (reg1 != reg0)
994 return 0;
995
996 /*
997 * Check if the version looks reasonably.
998 */
999 reg1 = GET_APIC_VERSION(reg0);
1000 if (reg1 == 0x00 || reg1 == 0xff)
1001 return 0;
Thomas Gleixner37e650c2008-01-30 13:30:14 +01001002 reg1 = lapic_get_maxlvt();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001003 if (reg1 < 0x02 || reg1 == 0xff)
1004 return 0;
1005
1006 /*
1007 * The ID register is read/write in a real APIC.
1008 */
Suresh Siddha2d7a66d2008-07-11 14:24:19 -07001009 reg0 = apic_read(APIC_ID);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001010 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
Ingo Molnar5b812722009-01-28 14:59:17 +01001011 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
Suresh Siddha2d7a66d2008-07-11 14:24:19 -07001012 reg1 = apic_read(APIC_ID);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001013 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1014 apic_write(APIC_ID, reg0);
Ingo Molnar5b812722009-01-28 14:59:17 +01001015 if (reg1 != (reg0 ^ apic->apic_id_mask))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001016 return 0;
1017
1018 /*
1019 * The next two are just to see if we have sane values.
1020 * They're only really relevant if we're in Virtual Wire
1021 * compatibility mode, but most boxes are anymore.
1022 */
1023 reg0 = apic_read(APIC_LVT0);
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001024 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001025 reg1 = apic_read(APIC_LVT1);
1026 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1027
1028 return 1;
1029}
1030
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001031/**
1032 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1033 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001034void __init sync_Arb_IDs(void)
1035{
Cyrill Gorcunov296cb952008-08-15 13:51:23 +02001036 /*
1037 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1038 * needed on AMD.
1039 */
1040 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001041 return;
1042
1043 /*
1044 * Wait for idle.
1045 */
1046 apic_wait_icr_idle();
1047
1048 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
Cyrill Gorcunov6f6da972008-08-15 23:05:19 +04001049 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1050 APIC_INT_LEVELTRIG | APIC_DM_INIT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001051}
1052
Linus Torvalds1da177e2005-04-16 15:20:36 -07001053/*
1054 * An initial setup of the virtual wire mode.
1055 */
1056void __init init_bsp_APIC(void)
1057{
Andi Kleen11a8e772006-01-11 22:46:51 +01001058 unsigned int value;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001059
1060 /*
1061 * Don't do the setup now if we have a SMP BIOS as the
1062 * through-I/O-APIC virtual wire mode might be active.
1063 */
1064 if (smp_found_config || !cpu_has_apic)
1065 return;
1066
Linus Torvalds1da177e2005-04-16 15:20:36 -07001067 /*
1068 * Do not trust the local APIC being empty at bootup.
1069 */
1070 clear_local_APIC();
1071
1072 /*
1073 * Enable APIC.
1074 */
1075 value = apic_read(APIC_SPIV);
1076 value &= ~APIC_VECTOR_MASK;
1077 value |= APIC_SPIV_APIC_ENABLED;
Cyrill Gorcunov638c0412008-08-15 23:05:18 +04001078
1079#ifdef CONFIG_X86_32
1080 /* This bit is reserved on P4/Xeon and should be cleared */
1081 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1082 (boot_cpu_data.x86 == 15))
1083 value &= ~APIC_SPIV_FOCUS_DISABLED;
1084 else
1085#endif
1086 value |= APIC_SPIV_FOCUS_DISABLED;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001087 value |= SPURIOUS_APIC_VECTOR;
Andi Kleen11a8e772006-01-11 22:46:51 +01001088 apic_write(APIC_SPIV, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001089
1090 /*
1091 * Set up the virtual wire mode.
1092 */
Andi Kleen11a8e772006-01-11 22:46:51 +01001093 apic_write(APIC_LVT0, APIC_DM_EXTINT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001094 value = APIC_DM_NMI;
Cyrill Gorcunov638c0412008-08-15 23:05:18 +04001095 if (!lapic_is_integrated()) /* 82489DX */
1096 value |= APIC_LVT_LEVEL_TRIGGER;
Andi Kleen11a8e772006-01-11 22:46:51 +01001097 apic_write(APIC_LVT1, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001098}
1099
Cyrill Gorcunovc43da2f2008-08-18 20:45:54 +04001100static void __cpuinit lapic_setup_esr(void)
1101{
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001102 unsigned int oldvalue, value, maxlvt;
Cyrill Gorcunovc43da2f2008-08-18 20:45:54 +04001103
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001104 if (!lapic_is_integrated()) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001105 pr_info("No ESR for 82489DX.\n");
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001106 return;
Cyrill Gorcunovc43da2f2008-08-18 20:45:54 +04001107 }
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001108
Ingo Molnar08125d32009-01-28 05:08:44 +01001109 if (apic->disable_esr) {
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001110 /*
1111 * Something untraceable is creating bad interrupts on
1112 * secondary quads ... for the moment, just leave the
1113 * ESR disabled - we can't do anything useful with the
1114 * errors anyway - mbligh
1115 */
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001116 pr_info("Leaving ESR disabled.\n");
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001117 return;
1118 }
1119
1120 maxlvt = lapic_get_maxlvt();
1121 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1122 apic_write(APIC_ESR, 0);
1123 oldvalue = apic_read(APIC_ESR);
1124
1125 /* enables sending errors */
1126 value = ERROR_APIC_VECTOR;
1127 apic_write(APIC_LVTERR, value);
1128
1129 /*
1130 * spec says clear errors after enabling vector.
1131 */
1132 if (maxlvt > 3)
1133 apic_write(APIC_ESR, 0);
1134 value = apic_read(APIC_ESR);
1135 if (value != oldvalue)
1136 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1137 "vector: 0x%08x after: 0x%08x\n",
1138 oldvalue, value);
Cyrill Gorcunovc43da2f2008-08-18 20:45:54 +04001139}
1140
1141
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001142/**
1143 * setup_local_APIC - setup the local APIC
1144 */
1145void __cpuinit setup_local_APIC(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001146{
Andi Kleen739f33b2008-01-30 13:30:40 +01001147 unsigned int value;
Vivek Goyalda7ed9f2006-03-25 16:31:16 +01001148 int i, j;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001149
Jan Beulichf1182632009-01-14 12:27:35 +00001150 if (disable_apic) {
Ingo Molnar5cdc5e9e2009-01-19 20:49:37 +01001151#ifdef CONFIG_X86_IO_APIC
Jan Beulichf1182632009-01-14 12:27:35 +00001152 disable_ioapic_setup();
Ingo Molnar5cdc5e9e2009-01-19 20:49:37 +01001153#endif
Jan Beulichf1182632009-01-14 12:27:35 +00001154 return;
1155 }
1156
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001157#ifdef CONFIG_X86_32
1158 /* Pound the ESR really hard over the head with a big hammer - mbligh */
Ingo Molnar08125d32009-01-28 05:08:44 +01001159 if (lapic_is_integrated() && apic->disable_esr) {
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001160 apic_write(APIC_ESR, 0);
1161 apic_write(APIC_ESR, 0);
1162 apic_write(APIC_ESR, 0);
1163 apic_write(APIC_ESR, 0);
1164 }
1165#endif
1166
Jack Steinerac23d4e2008-03-28 14:12:16 -05001167 preempt_disable();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001168
Linus Torvalds1da177e2005-04-16 15:20:36 -07001169 /*
1170 * Double-check whether this APIC is really registered.
1171 * This is meaningless in clustered apic mode, so we skip it.
1172 */
Ingo Molnar7ed248d2009-01-28 03:43:47 +01001173 if (!apic->apic_id_registered())
Linus Torvalds1da177e2005-04-16 15:20:36 -07001174 BUG();
1175
1176 /*
1177 * Intel recommends to set DFR, LDR and TPR before enabling
1178 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1179 * document number 292116). So here it goes...
1180 */
Ingo Molnara5c43292009-01-28 06:50:47 +01001181 apic->init_apic_ldr();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001182
1183 /*
1184 * Set Task Priority to 'accept all'. We never change this
1185 * later on.
1186 */
1187 value = apic_read(APIC_TASKPRI);
1188 value &= ~APIC_TPRI_MASK;
Andi Kleen11a8e772006-01-11 22:46:51 +01001189 apic_write(APIC_TASKPRI, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001190
1191 /*
Vivek Goyalda7ed9f2006-03-25 16:31:16 +01001192 * After a crash, we no longer service the interrupts and a pending
1193 * interrupt from previous kernel might still have ISR bit set.
1194 *
1195 * Most probably by now CPU has serviced that pending interrupt and
1196 * it might not have done the ack_APIC_irq() because it thought,
1197 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1198 * does not clear the ISR bit and cpu thinks it has already serivced
1199 * the interrupt. Hence a vector might get locked. It was noticed
1200 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1201 */
1202 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1203 value = apic_read(APIC_ISR + i*0x10);
1204 for (j = 31; j >= 0; j--) {
1205 if (value & (1<<j))
1206 ack_APIC_irq();
1207 }
1208 }
1209
1210 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001211 * Now that we are all set up, enable the APIC
1212 */
1213 value = apic_read(APIC_SPIV);
1214 value &= ~APIC_VECTOR_MASK;
1215 /*
1216 * Enable APIC
1217 */
1218 value |= APIC_SPIV_APIC_ENABLED;
1219
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001220#ifdef CONFIG_X86_32
1221 /*
1222 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1223 * certain networking cards. If high frequency interrupts are
1224 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1225 * entry is masked/unmasked at a high rate as well then sooner or
1226 * later IOAPIC line gets 'stuck', no more interrupts are received
1227 * from the device. If focus CPU is disabled then the hang goes
1228 * away, oh well :-(
1229 *
1230 * [ This bug can be reproduced easily with a level-triggered
1231 * PCI Ne2000 networking cards and PII/PIII processors, dual
1232 * BX chipset. ]
1233 */
1234 /*
1235 * Actually disabling the focus CPU check just makes the hang less
1236 * frequent as it makes the interrupt distributon model be more
1237 * like LRU than MRU (the short-term load is more even across CPUs).
1238 * See also the comment in end_level_ioapic_irq(). --macro
1239 */
1240
1241 /*
1242 * - enable focus processor (bit==0)
1243 * - 64bit mode always use processor focus
1244 * so no need to set it
1245 */
1246 value &= ~APIC_SPIV_FOCUS_DISABLED;
1247#endif
Andi Kleen3f14c742006-09-26 10:52:29 +02001248
Linus Torvalds1da177e2005-04-16 15:20:36 -07001249 /*
1250 * Set spurious IRQ vector
1251 */
1252 value |= SPURIOUS_APIC_VECTOR;
Andi Kleen11a8e772006-01-11 22:46:51 +01001253 apic_write(APIC_SPIV, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001254
1255 /*
1256 * Set up LVT0, LVT1:
1257 *
1258 * set up through-local-APIC on the BP's LINT0. This is not
1259 * strictly necessary in pure symmetric-IO mode, but sometimes
1260 * we delegate interrupts to the 8259A.
1261 */
1262 /*
1263 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1264 */
1265 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001266 if (!smp_processor_id() && (pic_mode || !value)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001267 value = APIC_DM_EXTINT;
Chris Wrightbc1d99c2007-10-12 23:04:23 +02001268 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001269 smp_processor_id());
Linus Torvalds1da177e2005-04-16 15:20:36 -07001270 } else {
1271 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
Chris Wrightbc1d99c2007-10-12 23:04:23 +02001272 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001273 smp_processor_id());
Linus Torvalds1da177e2005-04-16 15:20:36 -07001274 }
Andi Kleen11a8e772006-01-11 22:46:51 +01001275 apic_write(APIC_LVT0, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001276
1277 /*
1278 * only the BP should see the LINT1 NMI signal, obviously.
1279 */
1280 if (!smp_processor_id())
1281 value = APIC_DM_NMI;
1282 else
1283 value = APIC_DM_NMI | APIC_LVT_MASKED;
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001284 if (!lapic_is_integrated()) /* 82489DX */
1285 value |= APIC_LVT_LEVEL_TRIGGER;
Andi Kleen11a8e772006-01-11 22:46:51 +01001286 apic_write(APIC_LVT1, value);
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001287
Jack Steinerac23d4e2008-03-28 14:12:16 -05001288 preempt_enable();
Andi Kleen739f33b2008-01-30 13:30:40 +01001289}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001290
Andi Kleen739f33b2008-01-30 13:30:40 +01001291void __cpuinit end_local_APIC_setup(void)
1292{
1293 lapic_setup_esr();
Cyrill Gorcunovfa6b95f2008-08-18 20:45:58 +04001294
1295#ifdef CONFIG_X86_32
Cyrill Gorcunov1b4ee4e2008-08-18 23:12:33 +04001296 {
1297 unsigned int value;
1298 /* Disable the local apic timer */
1299 value = apic_read(APIC_LVTT);
1300 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1301 apic_write(APIC_LVTT, value);
1302 }
Cyrill Gorcunovfa6b95f2008-08-18 20:45:58 +04001303#endif
1304
Don Zickusf2802e72006-09-26 10:52:26 +02001305 setup_apic_nmi_watchdog(NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001306 apic_pm_activate();
1307}
1308
Yinghai Lu49899ea2008-08-24 02:01:47 -07001309#ifdef HAVE_X2APIC
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001310void check_x2apic(void)
1311{
1312 int msr, msr2;
1313
1314 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1315
1316 if (msr & X2APIC_ENABLE) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001317 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001318 x2apic_preenabled = x2apic = 1;
1319 apic_ops = &x2apic_ops;
1320 }
1321}
1322
1323void enable_x2apic(void)
1324{
1325 int msr, msr2;
1326
1327 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1328 if (!(msr & X2APIC_ENABLE)) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001329 pr_info("Enabling x2apic\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001330 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1331 }
1332}
1333
Al Viro2236d252008-11-22 17:37:34 +00001334void __init enable_IR_x2apic(void)
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001335{
1336#ifdef CONFIG_INTR_REMAP
1337 int ret;
1338 unsigned long flags;
1339
1340 if (!cpu_has_x2apic)
1341 return;
1342
1343 if (!x2apic_preenabled && disable_x2apic) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001344 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1345 "because of nox2apic\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001346 return;
1347 }
1348
1349 if (x2apic_preenabled && disable_x2apic)
1350 panic("Bios already enabled x2apic, can't enforce nox2apic");
1351
1352 if (!x2apic_preenabled && skip_ioapic_setup) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001353 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1354 "because of skipping io-apic setup\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001355 return;
1356 }
1357
1358 ret = dmar_table_init();
1359 if (ret) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001360 pr_info("dmar_table_init() failed with %d:\n", ret);
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001361
1362 if (x2apic_preenabled)
1363 panic("x2apic enabled by bios. But IR enabling failed");
1364 else
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001365 pr_info("Not enabling x2apic,Intr-remapping\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001366 return;
1367 }
1368
1369 local_irq_save(flags);
1370 mask_8259A();
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +04001371
1372 ret = save_mask_IO_APIC_setup();
1373 if (ret) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001374 pr_info("Saving IO-APIC state failed: %d\n", ret);
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +04001375 goto end;
1376 }
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001377
1378 ret = enable_intr_remapping(1);
1379
1380 if (ret && x2apic_preenabled) {
1381 local_irq_restore(flags);
1382 panic("x2apic enabled by bios. But IR enabling failed");
1383 }
1384
1385 if (ret)
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +04001386 goto end_restore;
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001387
1388 if (!x2apic) {
1389 x2apic = 1;
1390 apic_ops = &x2apic_ops;
1391 enable_x2apic();
1392 }
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +04001393
1394end_restore:
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001395 if (ret)
1396 /*
1397 * IR enabling failed
1398 */
1399 restore_IO_APIC_setup();
1400 else
1401 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1402
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +04001403end:
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001404 unmask_8259A();
1405 local_irq_restore(flags);
1406
1407 if (!ret) {
1408 if (!x2apic_preenabled)
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001409 pr_info("Enabled x2apic and interrupt-remapping\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001410 else
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001411 pr_info("Enabled Interrupt-remapping\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001412 } else
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001413 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001414#else
1415 if (!cpu_has_x2apic)
1416 return;
1417
1418 if (x2apic_preenabled)
1419 panic("x2apic enabled prior OS handover,"
1420 " enable CONFIG_INTR_REMAP");
1421
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001422 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1423 " and x2apic\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001424#endif
1425
1426 return;
1427}
Yinghai Lu49899ea2008-08-24 02:01:47 -07001428#endif /* HAVE_X2APIC */
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001429
Yinghai Lube7a6562008-08-24 02:01:51 -07001430#ifdef CONFIG_X86_64
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001431/*
1432 * Detect and enable local APICs on non-SMP boards.
1433 * Original code written by Keir Fraser.
1434 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1435 * not correctly set up (usually the APIC timer won't work etc.)
1436 */
1437static int __init detect_init_APIC(void)
1438{
1439 if (!cpu_has_apic) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001440 pr_info("No local APIC present\n");
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001441 return -1;
1442 }
1443
1444 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
Glauber de Oliveira Costac70dcb72008-03-19 14:25:58 -03001445 boot_cpu_physical_apicid = 0;
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001446 return 0;
1447}
Yinghai Lube7a6562008-08-24 02:01:51 -07001448#else
1449/*
1450 * Detect and initialize APIC
1451 */
1452static int __init detect_init_APIC(void)
1453{
1454 u32 h, l, features;
1455
1456 /* Disabled by kernel option? */
1457 if (disable_apic)
1458 return -1;
1459
1460 switch (boot_cpu_data.x86_vendor) {
1461 case X86_VENDOR_AMD:
1462 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1463 (boot_cpu_data.x86 == 15))
1464 break;
1465 goto no_apic;
1466 case X86_VENDOR_INTEL:
1467 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1468 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1469 break;
1470 goto no_apic;
1471 default:
1472 goto no_apic;
1473 }
1474
1475 if (!cpu_has_apic) {
1476 /*
1477 * Over-ride BIOS and try to enable the local APIC only if
1478 * "lapic" specified.
1479 */
1480 if (!force_enable_local_apic) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001481 pr_info("Local APIC disabled by BIOS -- "
1482 "you can enable it with \"lapic\"\n");
Yinghai Lube7a6562008-08-24 02:01:51 -07001483 return -1;
1484 }
1485 /*
1486 * Some BIOSes disable the local APIC in the APIC_BASE
1487 * MSR. This can only be done in software for Intel P6 or later
1488 * and AMD K7 (Model > 1) or later.
1489 */
1490 rdmsr(MSR_IA32_APICBASE, l, h);
1491 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001492 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
Yinghai Lube7a6562008-08-24 02:01:51 -07001493 l &= ~MSR_IA32_APICBASE_BASE;
1494 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1495 wrmsr(MSR_IA32_APICBASE, l, h);
1496 enabled_via_apicbase = 1;
1497 }
1498 }
1499 /*
1500 * The APIC feature bit should now be enabled
1501 * in `cpuid'
1502 */
1503 features = cpuid_edx(1);
1504 if (!(features & (1 << X86_FEATURE_APIC))) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001505 pr_warning("Could not enable APIC!\n");
Yinghai Lube7a6562008-08-24 02:01:51 -07001506 return -1;
1507 }
1508 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1509 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1510
1511 /* The BIOS may have set up the APIC at some other address */
1512 rdmsr(MSR_IA32_APICBASE, l, h);
1513 if (l & MSR_IA32_APICBASE_ENABLE)
1514 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1515
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001516 pr_info("Found and enabled local APIC!\n");
Yinghai Lube7a6562008-08-24 02:01:51 -07001517
1518 apic_pm_activate();
1519
1520 return 0;
1521
1522no_apic:
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001523 pr_info("No local APIC present or hardware disabled\n");
Yinghai Lube7a6562008-08-24 02:01:51 -07001524 return -1;
1525}
1526#endif
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001527
Yinghai Luf28c0ae2008-08-24 02:01:49 -07001528#ifdef CONFIG_X86_64
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001529void __init early_init_lapic_mapping(void)
1530{
Thomas Gleixner431ee792008-05-12 15:43:35 +02001531 unsigned long phys_addr;
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001532
1533 /*
1534 * If no local APIC can be found then go out
1535 * : it means there is no mpatable and MADT
1536 */
1537 if (!smp_found_config)
1538 return;
1539
Thomas Gleixner431ee792008-05-12 15:43:35 +02001540 phys_addr = mp_lapic_addr;
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001541
Thomas Gleixner431ee792008-05-12 15:43:35 +02001542 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001543 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
Thomas Gleixner431ee792008-05-12 15:43:35 +02001544 APIC_BASE, phys_addr);
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001545
1546 /*
1547 * Fetch the APIC ID of the BSP in case we have a
1548 * default configuration (or the MP table is broken).
1549 */
Yinghai Lu4c9961d2008-07-11 18:44:16 -07001550 boot_cpu_physical_apicid = read_apic_id();
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001551}
Yinghai Luf28c0ae2008-08-24 02:01:49 -07001552#endif
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001553
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001554/**
1555 * init_apic_mappings - initialize APIC mappings
1556 */
1557void __init init_apic_mappings(void)
1558{
Yinghai Lu49899ea2008-08-24 02:01:47 -07001559#ifdef HAVE_X2APIC
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001560 if (x2apic) {
Yinghai Lu4c9961d2008-07-11 18:44:16 -07001561 boot_cpu_physical_apicid = read_apic_id();
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001562 return;
1563 }
Yinghai Lu49899ea2008-08-24 02:01:47 -07001564#endif
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001565
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001566 /*
1567 * If no local APIC can be found then set up a fake all
1568 * zeroes page to simulate the local APIC and another
1569 * one for the IO-APIC.
1570 */
1571 if (!smp_found_config && detect_init_APIC()) {
1572 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1573 apic_phys = __pa(apic_phys);
1574 } else
1575 apic_phys = mp_lapic_addr;
1576
1577 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
Yinghai Lu79c09692008-09-07 17:58:57 -07001578 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001579 APIC_BASE, apic_phys);
1580
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001581 /*
1582 * Fetch the APIC ID of the BSP in case we have a
1583 * default configuration (or the MP table is broken).
1584 */
Yinghai Luf28c0ae2008-08-24 02:01:49 -07001585 if (boot_cpu_physical_apicid == -1U)
1586 boot_cpu_physical_apicid = read_apic_id();
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001587}
1588
1589/*
1590 * This initializes the IO-APIC and APIC hardware if this is
1591 * a UP kernel.
1592 */
Cyrill Gorcunov1b313f42008-08-18 20:45:57 +04001593int apic_version[MAX_APICS];
1594
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001595int __init APIC_init_uniprocessor(void)
1596{
1597 if (disable_apic) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001598 pr_info("Apic disabled\n");
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001599 return -1;
1600 }
Jan Beulichf1182632009-01-14 12:27:35 +00001601#ifdef CONFIG_X86_64
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001602 if (!cpu_has_apic) {
1603 disable_apic = 1;
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001604 pr_info("Apic disabled by BIOS\n");
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001605 return -1;
1606 }
Yinghai Lufa2bd352008-08-24 02:01:50 -07001607#else
1608 if (!smp_found_config && !cpu_has_apic)
1609 return -1;
1610
1611 /*
1612 * Complain if the BIOS pretends there is one.
1613 */
1614 if (!cpu_has_apic &&
1615 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001616 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1617 boot_cpu_physical_apicid);
Yinghai Lufa2bd352008-08-24 02:01:50 -07001618 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1619 return -1;
1620 }
1621#endif
1622
Yinghai Lu49899ea2008-08-24 02:01:47 -07001623#ifdef HAVE_X2APIC
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001624 enable_IR_x2apic();
Yinghai Lu49899ea2008-08-24 02:01:47 -07001625#endif
Yinghai Lufa2bd352008-08-24 02:01:50 -07001626#ifdef CONFIG_X86_64
Ingo Molnar72ce0162009-01-28 06:50:47 +01001627 default_setup_apic_routing();
Yinghai Lufa2bd352008-08-24 02:01:50 -07001628#endif
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001629
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001630 verify_local_APIC();
Glauber Costab5841762008-05-28 13:38:28 -03001631 connect_bsp_APIC();
1632
Yinghai Lufa2bd352008-08-24 02:01:50 -07001633#ifdef CONFIG_X86_64
Glauber de Oliveira Costac70dcb72008-03-19 14:25:58 -03001634 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
Yinghai Lufa2bd352008-08-24 02:01:50 -07001635#else
1636 /*
1637 * Hack: In case of kdump, after a crash, kernel might be booting
1638 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1639 * might be zero if read from MP tables. Get it from LAPIC.
1640 */
1641# ifdef CONFIG_CRASH_DUMP
1642 boot_cpu_physical_apicid = read_apic_id();
1643# endif
1644#endif
1645 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001646 setup_local_APIC();
1647
Yinghai Lufa2bd352008-08-24 02:01:50 -07001648#ifdef CONFIG_X86_64
Andi Kleen739f33b2008-01-30 13:30:40 +01001649 /*
1650 * Now enable IO-APICs, actually call clear_IO_APIC
1651 * We need clear_IO_APIC before enabling vector on BP
1652 */
1653 if (!skip_ioapic_setup && nr_ioapics)
1654 enable_IO_APIC();
Yinghai Lufa2bd352008-08-24 02:01:50 -07001655#endif
Andi Kleen739f33b2008-01-30 13:30:40 +01001656
Yinghai Lufa2bd352008-08-24 02:01:50 -07001657#ifdef CONFIG_X86_IO_APIC
Maciej W. Rozyckiacae7d92008-06-06 03:27:49 +01001658 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
Yinghai Lufa2bd352008-08-24 02:01:50 -07001659#endif
Maciej W. Rozyckiacae7d92008-06-06 03:27:49 +01001660 localise_nmi_watchdog();
Andi Kleen739f33b2008-01-30 13:30:40 +01001661 end_local_APIC_setup();
1662
Yinghai Lufa2bd352008-08-24 02:01:50 -07001663#ifdef CONFIG_X86_IO_APIC
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001664 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1665 setup_IO_APIC();
Yinghai Lufa2bd352008-08-24 02:01:50 -07001666# ifdef CONFIG_X86_64
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001667 else
1668 nr_ioapics = 0;
Yinghai Lufa2bd352008-08-24 02:01:50 -07001669# endif
1670#endif
1671
1672#ifdef CONFIG_X86_64
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001673 setup_boot_APIC_clock();
1674 check_nmi_watchdog();
Yinghai Lufa2bd352008-08-24 02:01:50 -07001675#else
1676 setup_boot_clock();
1677#endif
1678
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001679 return 0;
1680}
1681
1682/*
1683 * Local APIC interrupts
1684 */
1685
1686/*
1687 * This interrupt should _never_ happen with our APIC/SMP architecture
1688 */
Yinghai Ludc1528d2008-08-24 02:01:53 -07001689void smp_spurious_interrupt(struct pt_regs *regs)
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001690{
Yinghai Ludc1528d2008-08-24 02:01:53 -07001691 u32 v;
1692
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001693 exit_idle();
1694 irq_enter();
1695 /*
1696 * Check if this really is a spurious interrupt and ACK it
1697 * if it is a vectored one. Just in case...
1698 * Spurious interrupts should not be ACKed.
1699 */
1700 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1701 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1702 ack_APIC_irq();
1703
Hiroshi Shimamoto915b0d02008-12-08 19:19:26 -08001704 inc_irq_stat(irq_spurious_count);
1705
Yinghai Ludc1528d2008-08-24 02:01:53 -07001706 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001707 pr_info("spurious APIC interrupt on CPU#%d, "
1708 "should never happen.\n", smp_processor_id());
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001709 irq_exit();
1710}
1711
1712/*
1713 * This interrupt should never happen with our APIC/SMP architecture
1714 */
Yinghai Ludc1528d2008-08-24 02:01:53 -07001715void smp_error_interrupt(struct pt_regs *regs)
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001716{
Yinghai Ludc1528d2008-08-24 02:01:53 -07001717 u32 v, v1;
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001718
1719 exit_idle();
1720 irq_enter();
1721 /* First tickle the hardware, only then report what went on. -- REW */
1722 v = apic_read(APIC_ESR);
1723 apic_write(APIC_ESR, 0);
1724 v1 = apic_read(APIC_ESR);
1725 ack_APIC_irq();
1726 atomic_inc(&irq_err_count);
1727
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001728 /*
1729 * Here is what the APIC error bits mean:
1730 * 0: Send CS error
1731 * 1: Receive CS error
1732 * 2: Send accept error
1733 * 3: Receive accept error
1734 * 4: Reserved
1735 * 5: Send illegal vector
1736 * 6: Received illegal vector
1737 * 7: Illegal register address
1738 */
1739 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001740 smp_processor_id(), v , v1);
1741 irq_exit();
1742}
1743
Glauber Costab5841762008-05-28 13:38:28 -03001744/**
Cyrill Gorcunov36c9d672008-08-18 20:45:53 +04001745 * connect_bsp_APIC - attach the APIC to the interrupt system
1746 */
Glauber Costab5841762008-05-28 13:38:28 -03001747void __init connect_bsp_APIC(void)
1748{
Cyrill Gorcunov36c9d672008-08-18 20:45:53 +04001749#ifdef CONFIG_X86_32
1750 if (pic_mode) {
1751 /*
1752 * Do not trust the local APIC being empty at bootup.
1753 */
1754 clear_local_APIC();
1755 /*
1756 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1757 * local APIC to INT and NMI lines.
1758 */
1759 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1760 "enabling APIC mode.\n");
1761 outb(0x70, 0x22);
1762 outb(0x01, 0x23);
1763 }
1764#endif
Ingo Molnar49040332009-01-28 12:43:18 +01001765 if (apic->enable_apic_mode)
1766 apic->enable_apic_mode();
Glauber Costab5841762008-05-28 13:38:28 -03001767}
1768
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +04001769/**
1770 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1771 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1772 *
1773 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1774 * APIC is disabled.
1775 */
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001776void disconnect_bsp_APIC(int virt_wire_setup)
1777{
Cyrill Gorcunov1b4ee4e2008-08-18 23:12:33 +04001778 unsigned int value;
1779
Cyrill Gorcunovc177b0b2008-08-18 20:45:56 +04001780#ifdef CONFIG_X86_32
1781 if (pic_mode) {
1782 /*
1783 * Put the board back into PIC mode (has an effect only on
1784 * certain older boards). Note that APIC interrupts, including
1785 * IPIs, won't work beyond this point! The only exception are
1786 * INIT IPIs.
1787 */
1788 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1789 "entering PIC mode.\n");
1790 outb(0x70, 0x22);
1791 outb(0x00, 0x23);
1792 return;
1793 }
1794#endif
1795
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001796 /* Go back to Virtual Wire compatibility mode */
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001797
1798 /* For the spurious interrupt use vector F, and enable it */
1799 value = apic_read(APIC_SPIV);
1800 value &= ~APIC_VECTOR_MASK;
1801 value |= APIC_SPIV_APIC_ENABLED;
1802 value |= 0xf;
1803 apic_write(APIC_SPIV, value);
1804
1805 if (!virt_wire_setup) {
1806 /*
1807 * For LVT0 make it edge triggered, active high,
1808 * external and enabled
1809 */
1810 value = apic_read(APIC_LVT0);
1811 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1812 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1813 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1814 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1815 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1816 apic_write(APIC_LVT0, value);
1817 } else {
1818 /* Disable LVT0 */
1819 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1820 }
1821
Cyrill Gorcunovc177b0b2008-08-18 20:45:56 +04001822 /*
1823 * For LVT1 make it edge triggered, active high,
1824 * nmi and enabled
1825 */
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001826 value = apic_read(APIC_LVT1);
1827 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1828 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1829 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1830 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1831 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1832 apic_write(APIC_LVT1, value);
1833}
1834
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001835void __cpuinit generic_processor_info(int apicid, int version)
1836{
1837 int cpu;
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001838
Cyrill Gorcunov1b313f42008-08-18 20:45:57 +04001839 /*
1840 * Validate version
1841 */
1842 if (version == 0x0) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001843 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
Mike Travis3b11ce72008-12-17 15:21:39 -08001844 "fixing up to 0x10. (tell your hw vendor)\n",
1845 version);
Cyrill Gorcunov1b313f42008-08-18 20:45:57 +04001846 version = 0x10;
1847 }
1848 apic_version[apicid] = version;
1849
Mike Travis3b11ce72008-12-17 15:21:39 -08001850 if (num_processors >= nr_cpu_ids) {
1851 int max = nr_cpu_ids;
1852 int thiscpu = max + disabled_cpus;
1853
1854 pr_warning(
1855 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1856 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1857
1858 disabled_cpus++;
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001859 return;
1860 }
1861
1862 num_processors++;
Mike Travis3b11ce72008-12-17 15:21:39 -08001863 cpu = cpumask_next_zero(-1, cpu_present_mask);
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001864
Mike Traviscef30b32009-01-16 15:58:13 -08001865 if (version != apic_version[boot_cpu_physical_apicid])
1866 WARN_ONCE(1,
1867 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1868 apic_version[boot_cpu_physical_apicid], cpu, version);
1869
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001870 physid_set(apicid, phys_cpu_present_map);
1871 if (apicid == boot_cpu_physical_apicid) {
1872 /*
1873 * x86_bios_cpu_apicid is required to have processors listed
1874 * in same order as logical cpu numbers. Hence the first
1875 * entry is BSP, and so on.
1876 */
1877 cpu = 0;
1878 }
Yinghai Lue0da3362008-06-08 18:29:22 -07001879 if (apicid > max_physical_apicid)
1880 max_physical_apicid = apicid;
1881
Cyrill Gorcunov1b313f42008-08-18 20:45:57 +04001882#ifdef CONFIG_X86_32
1883 /*
1884 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1885 * but we need to work other dependencies like SMP_SUSPEND etc
1886 * before this can be done without some confusion.
1887 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1888 * - Ashok Raj <ashok.raj@intel.com>
1889 */
1890 if (max_physical_apicid >= 8) {
1891 switch (boot_cpu_data.x86_vendor) {
1892 case X86_VENDOR_INTEL:
1893 if (!APIC_XAPIC(version)) {
1894 def_to_bigsmp = 0;
1895 break;
1896 }
1897 /* If P4 and above fall through */
1898 case X86_VENDOR_AMD:
1899 def_to_bigsmp = 1;
1900 }
1901 }
1902#endif
1903
1904#if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
Tejun Heof10fcd42009-01-13 20:41:34 +09001905 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1906 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
Cyrill Gorcunov1b313f42008-08-18 20:45:57 +04001907#endif
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001908
Mike Travis1de88cd2008-12-16 17:34:02 -08001909 set_cpu_possible(cpu, true);
1910 set_cpu_present(cpu, true);
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001911}
1912
Yinghai Lu34919982008-08-24 02:01:48 -07001913#ifdef CONFIG_X86_64
Suresh Siddha0c81c742008-07-10 11:16:48 -07001914int hard_smp_processor_id(void)
1915{
1916 return read_apic_id();
1917}
Yinghai Lu34919982008-08-24 02:01:48 -07001918#endif
Suresh Siddha0c81c742008-07-10 11:16:48 -07001919
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001920/*
1921 * Power management
1922 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001923#ifdef CONFIG_PM
1924
1925static struct {
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +04001926 /*
1927 * 'active' is true if the local APIC was enabled by us and
1928 * not the BIOS; this signifies that we are also responsible
1929 * for disabling it before entering apm/acpi suspend
1930 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001931 int active;
1932 /* r/w apic fields */
1933 unsigned int apic_id;
1934 unsigned int apic_taskpri;
1935 unsigned int apic_ldr;
1936 unsigned int apic_dfr;
1937 unsigned int apic_spiv;
1938 unsigned int apic_lvtt;
1939 unsigned int apic_lvtpc;
1940 unsigned int apic_lvt0;
1941 unsigned int apic_lvt1;
1942 unsigned int apic_lvterr;
1943 unsigned int apic_tmict;
1944 unsigned int apic_tdcr;
1945 unsigned int apic_thmr;
1946} apic_pm_state;
1947
Pavel Machek0b9c33a2005-04-16 15:25:31 -07001948static int lapic_suspend(struct sys_device *dev, pm_message_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001949{
1950 unsigned long flags;
Karsten Wiesef990fff2006-12-07 02:14:11 +01001951 int maxlvt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001952
1953 if (!apic_pm_state.active)
1954 return 0;
1955
Thomas Gleixner37e650c2008-01-30 13:30:14 +01001956 maxlvt = lapic_get_maxlvt();
Karsten Wiesef990fff2006-12-07 02:14:11 +01001957
Suresh Siddha2d7a66d2008-07-11 14:24:19 -07001958 apic_pm_state.apic_id = apic_read(APIC_ID);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001959 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1960 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1961 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1962 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1963 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
Karsten Wiesef990fff2006-12-07 02:14:11 +01001964 if (maxlvt >= 4)
1965 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001966 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1967 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1968 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1969 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1970 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
Cyrill Gorcunov24968cf2008-08-16 23:21:52 +04001971#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
Karsten Wiesef990fff2006-12-07 02:14:11 +01001972 if (maxlvt >= 5)
1973 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1974#endif
Cyrill Gorcunov24968cf2008-08-16 23:21:52 +04001975
Fernando Luis Vázquez Cao2b94ab22006-09-26 10:52:33 +02001976 local_irq_save(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001977 disable_local_APIC();
1978 local_irq_restore(flags);
1979 return 0;
1980}
1981
1982static int lapic_resume(struct sys_device *dev)
1983{
1984 unsigned int l, h;
1985 unsigned long flags;
Karsten Wiesef990fff2006-12-07 02:14:11 +01001986 int maxlvt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001987
1988 if (!apic_pm_state.active)
1989 return 0;
1990
Thomas Gleixner37e650c2008-01-30 13:30:14 +01001991 maxlvt = lapic_get_maxlvt();
Karsten Wiesef990fff2006-12-07 02:14:11 +01001992
Linus Torvalds1da177e2005-04-16 15:20:36 -07001993 local_irq_save(flags);
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04001994
Yinghai Lu49899ea2008-08-24 02:01:47 -07001995#ifdef HAVE_X2APIC
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04001996 if (x2apic)
1997 enable_x2apic();
1998 else
1999#endif
Yinghai Lud5e629a2008-08-17 21:12:27 -07002000 {
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04002001 /*
2002 * Make sure the APICBASE points to the right address
2003 *
2004 * FIXME! This will be wrong if we ever support suspend on
2005 * SMP! We'll need to do this as part of the CPU restore!
2006 */
Suresh Siddha6e1cb382008-07-10 11:16:58 -07002007 rdmsr(MSR_IA32_APICBASE, l, h);
2008 l &= ~MSR_IA32_APICBASE_BASE;
2009 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2010 wrmsr(MSR_IA32_APICBASE, l, h);
Yinghai Lud5e629a2008-08-17 21:12:27 -07002011 }
Suresh Siddha6e1cb382008-07-10 11:16:58 -07002012
Linus Torvalds1da177e2005-04-16 15:20:36 -07002013 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2014 apic_write(APIC_ID, apic_pm_state.apic_id);
2015 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2016 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2017 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2018 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2019 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2020 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04002021#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
Karsten Wiesef990fff2006-12-07 02:14:11 +01002022 if (maxlvt >= 5)
2023 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2024#endif
2025 if (maxlvt >= 4)
2026 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002027 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2028 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2029 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2030 apic_write(APIC_ESR, 0);
2031 apic_read(APIC_ESR);
2032 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2033 apic_write(APIC_ESR, 0);
2034 apic_read(APIC_ESR);
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04002035
Linus Torvalds1da177e2005-04-16 15:20:36 -07002036 local_irq_restore(flags);
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04002037
Linus Torvalds1da177e2005-04-16 15:20:36 -07002038 return 0;
2039}
2040
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +04002041/*
2042 * This device has no shutdown method - fully functioning local APICs
2043 * are needed on every CPU up until machine_halt/restart/poweroff.
2044 */
2045
Linus Torvalds1da177e2005-04-16 15:20:36 -07002046static struct sysdev_class lapic_sysclass = {
Kay Sieversaf5ca3f2007-12-20 02:09:39 +01002047 .name = "lapic",
Linus Torvalds1da177e2005-04-16 15:20:36 -07002048 .resume = lapic_resume,
2049 .suspend = lapic_suspend,
2050};
2051
2052static struct sys_device device_lapic = {
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +01002053 .id = 0,
2054 .cls = &lapic_sysclass,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002055};
2056
Ashok Raje6982c62005-06-25 14:54:58 -07002057static void __cpuinit apic_pm_activate(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002058{
2059 apic_pm_state.active = 1;
2060}
2061
2062static int __init init_lapic_sysfs(void)
2063{
2064 int error;
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +01002065
Linus Torvalds1da177e2005-04-16 15:20:36 -07002066 if (!cpu_has_apic)
2067 return 0;
2068 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +01002069
Linus Torvalds1da177e2005-04-16 15:20:36 -07002070 error = sysdev_class_register(&lapic_sysclass);
2071 if (!error)
2072 error = sysdev_register(&device_lapic);
2073 return error;
2074}
2075device_initcall(init_lapic_sysfs);
2076
2077#else /* CONFIG_PM */
2078
2079static void apic_pm_activate(void) { }
2080
2081#endif /* CONFIG_PM */
2082
Yinghai Luf28c0ae2008-08-24 02:01:49 -07002083#ifdef CONFIG_X86_64
Linus Torvalds1da177e2005-04-16 15:20:36 -07002084/*
Vojtech Pavlikf8bf3c62006-06-26 13:58:23 +02002085 * apic_is_clustered_box() -- Check if we can expect good TSC
Linus Torvalds1da177e2005-04-16 15:20:36 -07002086 *
2087 * Thus far, the major user of this is IBM's Summit2 series:
2088 *
Linus Torvalds637029c2006-02-27 20:41:56 -08002089 * Clustered boxes may have unsynced TSC problems if they are
Linus Torvalds1da177e2005-04-16 15:20:36 -07002090 * multi-chassis. Use available data to take a good guess.
2091 * If in doubt, go HPET.
2092 */
Vojtech Pavlikf8bf3c62006-06-26 13:58:23 +02002093__cpuinit int apic_is_clustered_box(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002094{
2095 int i, clusters, zeros;
2096 unsigned id;
Yinghai Lu322850a2008-02-23 21:48:42 -08002097 u16 *bios_cpu_apicid;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002098 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2099
Yinghai Lu322850a2008-02-23 21:48:42 -08002100 /*
2101 * there is not this kind of box with AMD CPU yet.
2102 * Some AMD box with quadcore cpu and 8 sockets apicid
2103 * will be [4, 0x23] or [8, 0x27] could be thought to
Yinghai Luf8fffa42008-02-24 21:36:28 -08002104 * vsmp box still need checking...
Yinghai Lu322850a2008-02-23 21:48:42 -08002105 */
Ravikiran G Thirumalai1cb68482008-03-20 00:45:08 -07002106 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
Yinghai Lu322850a2008-02-23 21:48:42 -08002107 return 0;
2108
Mike Travis23ca4bb2008-05-12 21:21:12 +02002109 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
Suresh Siddha376ec332005-05-16 21:53:32 -07002110 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002111
Mike Travis168ef542008-12-16 17:34:01 -08002112 for (i = 0; i < nr_cpu_ids; i++) {
travis@sgi.come8c10ef2008-01-30 13:33:12 +01002113 /* are we being called early in kernel startup? */
Mike Travis693e3c52008-01-30 13:33:14 +01002114 if (bios_cpu_apicid) {
2115 id = bios_cpu_apicid[i];
Jaswinder Singh Rajpute423e332009-01-04 16:16:25 +05302116 } else if (i < nr_cpu_ids) {
travis@sgi.come8c10ef2008-01-30 13:33:12 +01002117 if (cpu_present(i))
2118 id = per_cpu(x86_bios_cpu_apicid, i);
2119 else
2120 continue;
Jaswinder Singh Rajpute423e332009-01-04 16:16:25 +05302121 } else
travis@sgi.come8c10ef2008-01-30 13:33:12 +01002122 break;
2123
Linus Torvalds1da177e2005-04-16 15:20:36 -07002124 if (id != BAD_APICID)
2125 __set_bit(APIC_CLUSTERID(id), clustermap);
2126 }
2127
2128 /* Problem: Partially populated chassis may not have CPUs in some of
2129 * the APIC clusters they have been allocated. Only present CPUs have
travis@sgi.com602a54a2008-01-30 13:33:21 +01002130 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2131 * Since clusters are allocated sequentially, count zeros only if
2132 * they are bounded by ones.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002133 */
2134 clusters = 0;
2135 zeros = 0;
2136 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2137 if (test_bit(i, clustermap)) {
2138 clusters += 1 + zeros;
2139 zeros = 0;
2140 } else
2141 ++zeros;
2142 }
2143
Ravikiran G Thirumalai1cb68482008-03-20 00:45:08 -07002144 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2145 * not guaranteed to be synced between boards
2146 */
2147 if (is_vsmp_box() && clusters > 1)
2148 return 1;
2149
Linus Torvalds1da177e2005-04-16 15:20:36 -07002150 /*
Vojtech Pavlikf8bf3c62006-06-26 13:58:23 +02002151 * If clusters > 2, then should be multi-chassis.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002152 * May have to revisit this when multi-core + hyperthreaded CPUs come
2153 * out, but AFAIK this will work even for them.
2154 */
2155 return (clusters > 2);
2156}
Yinghai Luf28c0ae2008-08-24 02:01:49 -07002157#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002158
2159/*
Thomas Gleixner0e078e22008-01-30 13:30:20 +01002160 * APIC command line parameters
Linus Torvalds1da177e2005-04-16 15:20:36 -07002161 */
Cyrill Gorcunov789fa732008-08-18 20:46:01 +04002162static int __init setup_disableapic(char *arg)
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002163{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002164 disable_apic = 1;
Yinghai Lu9175fc02008-07-21 01:38:14 -07002165 setup_clear_cpu_cap(X86_FEATURE_APIC);
Andi Kleen2c8c0e62006-09-26 10:52:32 +02002166 return 0;
2167}
2168early_param("disableapic", setup_disableapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002169
Andi Kleen2c8c0e62006-09-26 10:52:32 +02002170/* same as disableapic, for compatibility */
Cyrill Gorcunov789fa732008-08-18 20:46:01 +04002171static int __init setup_nolapic(char *arg)
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002172{
Cyrill Gorcunov789fa732008-08-18 20:46:01 +04002173 return setup_disableapic(arg);
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002174}
Andi Kleen2c8c0e62006-09-26 10:52:32 +02002175early_param("nolapic", setup_nolapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002176
Linus Torvalds2e7c2832007-03-23 11:32:31 -07002177static int __init parse_lapic_timer_c2_ok(char *arg)
2178{
2179 local_apic_timer_c2_ok = 1;
2180 return 0;
2181}
2182early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2183
Cyrill Gorcunov36fef092008-08-15 13:51:20 +02002184static int __init parse_disable_apic_timer(char *arg)
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002185{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002186 disable_apic_timer = 1;
Cyrill Gorcunov36fef092008-08-15 13:51:20 +02002187 return 0;
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002188}
Cyrill Gorcunov36fef092008-08-15 13:51:20 +02002189early_param("noapictimer", parse_disable_apic_timer);
2190
2191static int __init parse_nolapic_timer(char *arg)
2192{
2193 disable_apic_timer = 1;
2194 return 0;
2195}
2196early_param("nolapic_timer", parse_nolapic_timer);
Andi Kleen73dea472006-02-03 21:50:50 +01002197
Cyrill Gorcunov79af9be2008-08-18 20:46:00 +04002198static int __init apic_set_verbosity(char *arg)
2199{
2200 if (!arg) {
2201#ifdef CONFIG_X86_64
2202 skip_ioapic_setup = 0;
Cyrill Gorcunov79af9be2008-08-18 20:46:00 +04002203 return 0;
2204#endif
2205 return -EINVAL;
2206 }
2207
2208 if (strcmp("debug", arg) == 0)
2209 apic_verbosity = APIC_DEBUG;
2210 else if (strcmp("verbose", arg) == 0)
2211 apic_verbosity = APIC_VERBOSE;
2212 else {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01002213 pr_warning("APIC Verbosity level %s not recognised"
Cyrill Gorcunov79af9be2008-08-18 20:46:00 +04002214 " use apic=verbose or apic=debug\n", arg);
2215 return -EINVAL;
2216 }
2217
2218 return 0;
2219}
2220early_param("apic", apic_set_verbosity);
2221
Yinghai Lu1e934dd2008-02-22 13:37:26 -08002222static int __init lapic_insert_resource(void)
2223{
2224 if (!apic_phys)
2225 return -1;
2226
2227 /* Put local APIC into the resource map. */
2228 lapic_resource.start = apic_phys;
2229 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2230 insert_resource(&iomem_resource, &lapic_resource);
2231
2232 return 0;
2233}
2234
2235/*
2236 * need call insert after e820_reserve_resources()
2237 * that is using request_resource
2238 */
2239late_initcall(lapic_insert_resource);