NVIDIA Tegra124 DFLL FCPU clocksource

This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt

The DFLL IP block on Tegra is a root clocksource designed for clocking
the fast CPU cluster. It consists of a free-running voltage controlled
oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
control module that will automatically adjust the VDD_CPU voltage by
communicating with an off-chip PMIC either via an I2C bus or via PWM signals.

Required properties:
- compatible : should be one of following:
  - "nvidia,tegra124-dfll" for the Tegra124 SoC
  - "nvidia,tegra210-dfll" for the Tegra210 SoC
- reg : Defines the following set of registers, in the order listed:
        - registers for the DFLL control logic.
        - registers for the I2C output logic.
        - registers for the integrated I2C master controller.
        - look-up table RAM for voltage register values.
- interrupts: Should contain the DFLL block interrupt.
- clocks: Must contain an entry for each entry in clock-names.
  See clock-bindings.txt for details.
- clock-names: Must include the following entries:
  - soc: Clock source for the DFLL control logic.
  - ref: The closed loop reference clock
  - i2c: Clock source for the integrated I2C master.
- resets: Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
  - dvco: Reset control for the DFLL DVCO.
- #clock-cells: Must be 0.
- clock-output-names: Name of the clock output.
- vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL
  hardware will start controlling. The regulator will be queried for
  the I2C register, control values and supported voltages.

Optional properties:
- nvidia,pwm-to-pmic: Specify DFLL PMU interface as PWM. If the property
  is not defined, default PMU interface is I2C.

Reguired properties for build voltage table:
- nvidia,align-step-uv: Step uV of regulator for CPU voltage rail. This
  value will be applied when building frequency-voltage table to ensure
  all calculated voltages will be aligned to voltages regulator supplied.

Optional properties for build voltage table:
- nvidia,align-offset-uv: Offset uV for calculating DFLL output voltage.

Required properties for the control loop parameters:
- nvidia,sample-rate: Sample rate of the DFLL control loop.
- nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM.
- nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM.
- nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM.
- nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM.
- nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM.

Optional properties for the control loop parameters:
- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.

Required properties for I2C mode:
- nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.

Required properties for PWM mode:
- nvidia,init-uv: Initialized CPU voltage before DFLL is not ready yet.

Example:

clock@0,70110000 {
        compatible = "nvidia,tegra124-dfll";
        reg = <0 0x70110000 0 0x100>, /* DFLL control */
              <0 0x70110000 0 0x100>, /* I2C output control */
              <0 0x70110100 0 0x100>, /* Integrated I2C controller */
              <0 0x70110200 0 0x100>; /* Look-up table RAM */
        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
                 <&tegra_car TEGRA124_CLK_DFLL_REF>,
                 <&tegra_car TEGRA124_CLK_I2C5>;
        clock-names = "soc", "ref", "i2c";
        resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
        reset-names = "dvco";
        #clock-cells = <0>;
        clock-output-names = "dfllCPU_out";
        vdd-cpu-supply = <&vdd_cpu>;
        status = "okay";

        nvidia,align-step-uv = <10000>; /* 10mv */
        nvidia,sample-rate = <12500>;
        nvidia,droop-ctrl = <0x00000f00>;
        nvidia,force-mode = <1>;
        nvidia,cf = <10>;
        nvidia,ci = <0>;
        nvidia,cg = <2>;

        nvidia,i2c-fs-rate = <400000>;
};
