arm: tegra: enterprise: use proper backlight clk_div for A03/A04
The new TPS61160A part asks for the control PWM signal to be between
5kHZ and 100kHz. This change sets clk_div to 0x1D for a 5kHz signal.
This change also installs a linear table for
enterprise_bl_output_measured_a03.
Bug 956246
Reviewed-on: http://git-master/r/91606
(cherry picked from commit 32a67cf7b1c8223abe8de7d88b4bcd1906cda0a2)
Change-Id: Ic7907cfae6f918ef055add33615822ef8c5e0ec6
Signed-off-by: Tom Cherry <tcherry@nvidia.com>
Reviewed-on: http://git-master/r/93051
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
1 file changed