* Code cleanup (ARM mostly)
* Patch by Curt Brune, 17 May 2004:
- Add support for Samsung S3C4510B CPU (ARM7tdmi based SoC)
- Add support for ESPD-Inc. EVB4510 Board
diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c
index 0ad5481..58eab4e 100644
--- a/cpu/arm720t/cpu.c
+++ b/cpu/arm720t/cpu.c
@@ -33,7 +33,73 @@
#include <common.h>
#include <command.h>
#include <clps7111.h>
+#include <asm/hardware.h>
+int cpu_init (void)
+{
+ /*
+ * setup up stacks if necessary
+ */
+#ifdef CONFIG_USE_IRQ
+ DECLARE_GLOBAL_DATA_PTR;
+
+ IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+ FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
+#endif
+ return 0;
+}
+
+int cleanup_before_linux (void)
+{
+ /*
+ * this function is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we turn off caches etc ...
+ * and we set the CPU-speed to 73 MHz - see start.S for details
+ */
+
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
+ unsigned long i;
+
+ disable_interrupts ();
+
+ /* turn off I-cache */
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ i &= ~0x1000;
+ asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+
+ /* flush I-cache */
+ asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+#ifdef CONFIG_ARM7_REVD
+ /* go to high speed */
+ IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73;
+#endif
+#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B)
+ disable_interrupts ();
+ /* Nothing more needed */
+#else
+#error No cleanup_before_linux() defined for this CPU type
+#endif
+ return 0;
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ extern void reset_cpu (ulong addr);
+
+ disable_interrupts ();
+ reset_cpu (0);
+ /*NOTREACHED*/
+ return (0);
+}
+
+/*
+ * Instruction and Data cache enable and disable functions
+ *
+ */
+
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM)
/* read co-processor 15, register #1 (control register) */
static unsigned long read_p15_c1(void)
{
@@ -79,61 +145,6 @@
#define C1_ROM_PROT (1<<9) /* ROM protection */
#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
-int cpu_init (void)
-{
- /*
- * setup up stacks if necessary
- */
-#ifdef CONFIG_USE_IRQ
- DECLARE_GLOBAL_DATA_PTR;
-
- IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
- FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
- return 0;
-}
-
-int cleanup_before_linux (void)
-{
- /*
- * this function is called just before we call linux
- * it prepares the processor for linux
- *
- * we turn off caches etc ...
- * and we set the CPU-speed to 73 MHz - see start.S for details
- */
-
- unsigned long i;
-
- disable_interrupts ();
-#ifdef CONFIG_NETARM
- return 0;
-#endif
- /* turn off I-cache */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i &= ~0x1000;
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-
- /* flush I-cache */
- asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
-
-#ifdef CONFIG_ARM7_REVD
- /* go to high speed */
- IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73;
-#endif
- return 0;
-}
-
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- extern void reset_cpu (ulong addr);
-
- disable_interrupts ();
- reset_cpu (0);
- /*NOTREACHED*/
- return (0);
-}
-
void icache_enable (void)
{
ulong reg;
@@ -179,3 +190,65 @@
{
return (read_p15_c1 () & C1_IDC) != 0;
}
+
+#elif defined(CONFIG_S3C4510B)
+
+void icache_enable (void)
+{
+ s32 i;
+
+ /* disable all cache bits */
+ CLR_REG( REG_SYSCFG, 0x3F);
+
+ /* 8KB cache, write enable */
+ SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
+
+ /* clear TAG RAM bits */
+ for ( i = 0; i < 256; i++)
+ PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000);
+
+ /* clear SET0 RAM */
+ for(i=0; i < 1024; i++)
+ PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000);
+
+ /* clear SET1 RAM */
+ for(i=0; i < 1024; i++)
+ PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000);
+
+ /* enable cache */
+ SET_REG( REG_SYSCFG, CACHE_ENABLE);
+
+}
+
+void icache_disable (void)
+{
+ /* disable all cache bits */
+ CLR_REG( REG_SYSCFG, 0x3F);
+}
+
+int icache_status (void)
+{
+ return GET_REG( REG_SYSCFG) & CACHE_ENABLE;
+}
+
+void dcache_enable (void)
+{
+ /* we don't have seperate instruction/data caches */
+ icache_enable();
+}
+
+void dcache_disable (void)
+{
+ /* we don't have seperate instruction/data caches */
+ icache_disable();
+}
+
+int dcache_status (void)
+{
+ /* we don't have seperate instruction/data caches */
+ return icache_status();
+}
+
+#else
+#error No icache/dcache enable/disable functions defined for this CPU type
+#endif
diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c
index 67e581a..485443f 100644
--- a/cpu/arm720t/interrupts.c
+++ b/cpu/arm720t/interrupts.c
@@ -28,11 +28,8 @@
#include <common.h>
#include <clps7111.h>
-
#include <asm/proc-armv/ptrace.h>
-#ifdef CONFIG_NETARM
-#include <asm/arch/netarm_registers.h>
-#endif
+#include <asm/hardware.h>
extern void reset_cpu(ulong addr);
@@ -187,7 +184,8 @@
int interrupt_init (void)
{
-#ifdef CONFIG_NETARM
+
+#if defined(CONFIG_NETARM)
/* disable all interrupts */
IRQEN = 0;
@@ -198,7 +196,7 @@
/* set timer 2 counter */
lastdec = TIMER_LOAD_VAL;
-#else
+#elif defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
/* disable all interrupts */
IO_INTMR1 = 0;
@@ -210,6 +208,11 @@
/* set timer 1 counter */
lastdec = IO_TC1D = TIMER_LOAD_VAL;
+#elif defined(CONFIG_S3C4510B)
+ /* Nothing to do, interrupts not supported */
+ lastdec = 0;
+#else
+#error No interrupt_init() defined for this CPU type
#endif
timestamp = 0;
@@ -220,6 +223,9 @@
* timer without interrupts
*/
+
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM)
+
void reset_timer (void)
{
reset_timer_masked ();
@@ -285,3 +291,45 @@
while (get_timer_masked () < tmo)
/*NOP*/;
}
+
+#elif defined(CONFIG_S3C4510B)
+
+#define TMR_OFFSET (0x1000)
+
+void udelay (unsigned long usec)
+{
+ u32 rDATA;
+
+ rDATA = t_data_us(usec);
+
+ /* Stop timer 0 */
+ CLR_REG( REG_TMOD, TM0_RUN);
+
+ /* Configure for toggle mode */
+ SET_REG( REG_TMOD, TM0_TOGGLE);
+
+ /* Load Timer data register with count down value plus offset */
+ PUT_REG( REG_TDATA0, rDATA + TMR_OFFSET);
+
+ /* Clear timer counter register */
+ PUT_REG( REG_TCNT0, 0x0);
+
+ /* Start timer -- count down timer */
+ SET_REG( REG_TMOD, TM0_RUN);
+
+ /* spin during count down */
+ while ( GET_REG( REG_TCNT0) > TMR_OFFSET);
+
+ /* Stop timer */
+ CLR_REG( REG_TMOD, TM0_RUN);
+
+}
+
+ulong get_timer (ulong base)
+{
+ return (0xFFFFFFFF - GET_REG( REG_TCNT1)) - base;
+}
+
+#else
+#error Timer routines not defined for this CPU type
+#endif
diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c
index 5c6a0cc..a5da4b7 100644
--- a/cpu/arm720t/serial.c
+++ b/cpu/arm720t/serial.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2002
+ * (C) Copyright 2002-2004
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* (C) Copyright 2002
@@ -29,9 +29,10 @@
*/
#include <common.h>
-#include <clps7111.h>
-#ifndef CONFIG_NETARM
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
+
+#include <clps7111.h>
void serial_setbrg (void)
{
@@ -39,20 +40,15 @@
unsigned int reg = 0;
- if (gd->baudrate == 1200)
- reg = 191;
- else if (gd->baudrate == 9600)
- reg = 23;
- else if (gd->baudrate == 19200)
- reg = 11;
- else if (gd->baudrate == 38400)
- reg = 5;
- else if (gd->baudrate == 57600)
- reg = 3;
- else if (gd->baudrate == 115200)
- reg = 1;
- else
- hang ();
+ switch (gd->baudrate) {
+ case 1200: reg = 191; break;
+ case 9600: reg = 23; break;
+ case 19200: reg = 11; break;
+ case 38400: reg = 5; break;
+ case 57600: reg = 3; break;
+ case 115200: reg = 1; break;
+ default: hang (); break;
+ }
/* init serial serial 1,2 */
IO_SYSCON1 = SYSCON1_UART1EN;
@@ -127,4 +123,4 @@
}
}
-#endif /* CONFIG_NETARM */
+#endif /* defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) */
diff --git a/cpu/arm720t/serial_netarm.c b/cpu/arm720t/serial_netarm.c
index 8cfe049..56cdb0a 100644
--- a/cpu/arm720t/serial_netarm.c
+++ b/cpu/arm720t/serial_netarm.c
@@ -29,10 +29,11 @@
*/
#include <common.h>
-#include <asm/arch/netarm_registers.h>
#ifdef CONFIG_NETARM
+#include <asm/hardware.h>
+
#define PORTA (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA))
#define PORTB (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB))
diff --git a/cpu/arm720t/start.S b/cpu/arm720t/start.S
index f6ae9d6..15b9a05 100644
--- a/cpu/arm720t/start.S
+++ b/cpu/arm720t/start.S
@@ -26,9 +26,7 @@
#include <config.h>
#include <version.h>
-#ifdef CONFIG_NETARM
-#include <asm/arch/netarm_registers.h>
-#endif
+#include <asm/hardware.h>
/*
*************************************************************************
@@ -166,7 +164,6 @@
_start_armboot: .word start_armboot
-
/*
*************************************************************************
*
@@ -178,6 +175,7 @@
*************************************************************************
*/
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
/* Interupt-Controller base addresses */
INTMR1: .word 0x80000280 @ 32 bit size
@@ -195,8 +193,11 @@
#define CLKCTL_49 0x4 /* 49.152 MHz */
#define CLKCTL_73 0x6 /* 73.728 MHz */
+#endif
+
cpu_init_crit:
-#ifndef CONFIG_NETARM
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
+
/*
* mask all IRQs by clearing all bits in the INTMRs
*/
@@ -223,7 +224,7 @@
bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
mcr p15,0,r0,c1,c0
-#else /* CONFIG_NETARM */
+#elif defined(CONFIG_NETARM)
/*
* prior to software reset : need to set pin PORTC4 to be *HRESET
*/
@@ -270,7 +271,26 @@
mov r1, #0
ldr r0, =NETARM_GEN_MODULE_BASE
str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
-#endif /* CONFIG_NETARM */
+
+#elif defined(CONFIG_S3C4510B)
+
+ /*
+ * Mask off all IRQ sources
+ */
+ ldr r1, =REG_INTMASK
+ ldr r0, =0x3FFFFF
+ str r0, [r1]
+
+ /*
+ * Disable Cache
+ */
+ ldr r0, =REG_SYSCFG
+ ldr r1, =0x83ffffa0 /* cache-disabled */
+ str r1, [r0]
+
+#else
+#error No cpu_init_crit() defined for current CPU type
+#endif
#ifdef CONFIG_ARM7_REVD
/* set clock speed */
@@ -462,10 +482,10 @@
#endif
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
.align 5
.globl reset_cpu
reset_cpu:
-#ifndef CONFIG_NETARM
mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
@@ -474,7 +494,10 @@
bic ip, ip, #0x2100 @ ..v....s........
mcr p15, 0, ip, c1, c0, 0 @ ctrl register
mov pc, r0
-#else
+#elif defined(CONFIG_NETARM)
+ .align 5
+.globl reset_cpu
+reset_cpu:
ldr r1, =NETARM_MEM_MODULE_BASE
ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
ldr r1, =0xFFFFF000
@@ -491,4 +514,9 @@
ldr r1, =NETARM_GEN_SW_SVC_RESETB
str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
mov pc, r0
+#elif defined(CONFIG_S3C4510B)
+/* Nothing done here as reseting the CPU is board specific, depending
+ * on external peripherals such as watchdog timers, etc. */
+#else
+#error No reset_cpu() defined for current CPU type
#endif