Revert "pcie: host: tegra: add shutdown hook"
[linux-4.4.git] / drivers / tty / serial / serial-tegra.c
1 /*
2  * serial_tegra.c
3  *
4  * High-speed serial driver for NVIDIA Tegra SoCs
5  *
6  * Copyright (c) 2012-2017, NVIDIA CORPORATION.  All rights reserved.
7  *
8  * Author: Laxman Dewangan <ldewangan@nvidia.com>
9  *
10  * This program is free software; you can redistribute it and/or modify it
11  * under the terms and conditions of the GNU General Public License,
12  * version 2, as published by the Free Software Foundation.
13  *
14  * This program is distributed in the hope it will be useful, but WITHOUT
15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17  * more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21  */
22
23 #include <linux/clk.h>
24 #include <linux/debugfs.h>
25 #include <linux/delay.h>
26 #include <linux/dmaengine.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dmapool.h>
29 #include <linux/err.h>
30 #include <linux/io.h>
31 #include <linux/irq.h>
32 #include <linux/module.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/pagemap.h>
36 #include <linux/platform_device.h>
37 #include <linux/reset.h>
38 #include <linux/serial.h>
39 #include <linux/serial_8250.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial_reg.h>
42 #include <linux/slab.h>
43 #include <linux/string.h>
44 #include <linux/termios.h>
45 #include <linux/tty.h>
46 #include <linux/tty_flip.h>
47 #include <linux/timer.h>
48 #include <linux/kthread.h>
49
50 #define TEGRA_UART_TYPE                         "TEGRA_UART"
51 #define TX_EMPTY_STATUS                         (UART_LSR_TEMT | UART_LSR_THRE)
52 #define BYTES_TO_ALIGN(x)                       ((unsigned long)(x) & 0x3)
53
54 #define TEGRA_UART_RX_DMA_BUFFER_SIZE           4096
55 #define TEGRA_UART_LSR_TXFIFO_FULL              0x100
56 #define TEGRA_UART_IER_EORD                     0x20
57 #define TEGRA_UART_MCR_RTS_EN                   0x40
58 #define TEGRA_UART_MCR_CTS_EN                   0x20
59 #define TEGRA_UART_LSR_ANY                      (UART_LSR_OE | UART_LSR_BI | \
60                                                 UART_LSR_PE | UART_LSR_FE)
61 #define TEGRA_UART_IRDA_CSR                     0x08
62 #define TEGRA_UART_SIR_ENABLED                  0x80
63
64 #define TEGRA_UART_TX_PIO                       1
65 #define TEGRA_UART_TX_DMA                       2
66 #define TEGRA_UART_MIN_DMA                      16
67 #define TEGRA_UART_FIFO_SIZE                    32
68
69 /*
70  * Tx fifo trigger level setting in tegra uart is in
71  * reverse way then conventional uart.
72  */
73 #define TEGRA_UART_TX_TRIG_16B                  0x00
74 #define TEGRA_UART_TX_TRIG_8B                   0x10
75 #define TEGRA_UART_TX_TRIG_4B                   0x20
76 #define TEGRA_UART_TX_TRIG_1B                   0x30
77
78 #define TEGRA_UART_MAXIMUM                      5
79
80 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */
81 #define TEGRA_UART_DEFAULT_BAUD                 115200
82 #define TEGRA_UART_DEFAULT_LSR                  UART_LCR_WLEN8
83
84 /* Tx transfer mode */
85 #define TEGRA_TX_PIO                            1
86 #define TEGRA_TX_DMA                            2
87
88 #define TEGRA_UART_FCR_IIR_FIFO_EN              0x40
89 #define TEGRA_UART_MAX_RX_CHARS                 256
90 #define TEGRA_UART_MAX_REPEAT_ERRORS            100
91
92 /**
93  * tegra_uart_chip_data: SOC specific data.
94  *
95  * @tx_fifo_full_status: Status flag available for checking tx fifo full.
96  * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
97  *                      Tegra30 does not allow this.
98  * @support_clk_src_div: Clock source support the clock divider.
99  */
100 struct tegra_uart_chip_data {
101         bool    tx_fifo_full_status;
102         bool    allow_txfifo_reset_fifo_mode;
103         bool    support_clk_src_div;
104         bool    fifo_mode_enable_status;
105         bool    dma_8bytes_burst_only;
106         int     error_tolerance_low_range;
107         int     error_tolerance_high_range;
108 };
109
110 struct tegra_baud_tolerance {
111         u32 lower_range_baud;
112         u32 upper_range_baud;
113         s32 tolerance;
114 };
115
116 struct tegra_uart_port {
117         struct uart_port                        uport;
118         const struct tegra_uart_chip_data       *cdata;
119
120         struct clk                              *uart_clk;
121         struct reset_control                    *rst;
122         unsigned int                            current_baud;
123
124         /* Register shadow */
125         unsigned long                           fcr_shadow;
126         unsigned long                           mcr_shadow;
127         unsigned long                           lcr_shadow;
128         unsigned long                           ier_shadow;
129         bool                                    rts_active;
130
131         int                                     tx_in_progress;
132         unsigned int                            tx_bytes;
133
134         bool                                    enable_modem_interrupt;
135
136         bool                                    rx_timeout;
137         int                                     rx_in_progress;
138         int                                     symb_bit;
139
140         struct dma_chan                         *rx_dma_chan;
141         struct dma_chan                         *tx_dma_chan;
142         dma_addr_t                              rx_dma_buf_phys;
143         dma_addr_t                              tx_dma_buf_phys;
144         unsigned char                           *rx_dma_buf_virt;
145         unsigned char                           *tx_dma_buf_virt;
146         struct dma_async_tx_descriptor          *tx_dma_desc;
147         struct dma_async_tx_descriptor          *rx_dma_desc;
148         dma_cookie_t                            tx_cookie;
149         dma_cookie_t                            rx_cookie;
150         unsigned int                            tx_bytes_requested;
151         unsigned int                            rx_bytes_requested;
152         struct tegra_baud_tolerance             *baud_tolerance;
153         int                                     n_adjustable_baud_rates;
154         bool                                    use_rx_pio;
155         bool                                    use_tx_pio;
156         struct timer_list                       timer;
157         int                                     timer_timeout_jiffies;
158         bool                                    enable_rx_buffer_throttle;
159         bool                                    is_hw_flow_enabled;
160         struct timer_list                       error_timer;
161         int                                     error_timer_timeout_jiffies;
162         int                                     required_rate;
163         int                                     configured_rate;
164         struct dentry                           *debugfs;
165         bool                                    early_printk_console_instance;
166         bool                                    rt_flush;
167 };
168
169 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
170 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
171
172 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
173                 unsigned long reg)
174 {
175         return readl(tup->uport.membase + (reg << tup->uport.regshift));
176 }
177
178 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
179         unsigned long reg)
180 {
181         writel(val, tup->uport.membase + (reg << tup->uport.regshift));
182 }
183
184 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u)
185 {
186         return container_of(u, struct tegra_uart_port, uport);
187 }
188
189 static unsigned int tegra_uart_get_mctrl(struct uart_port *u)
190 {
191         struct tegra_uart_port *tup = to_tegra_uport(u);
192
193         /*
194          * RI - Ring detector is active
195          * CD/DCD/CAR - Carrier detect is always active. For some reason
196          *      linux has different names for carrier detect.
197          * DSR - Data Set ready is active as the hardware doesn't support it.
198          *      Don't know if the linux support this yet?
199          * CTS - Clear to send. Always set to active, as the hardware handles
200          *      CTS automatically.
201          */
202         if (tup->enable_modem_interrupt)
203                 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
204         return TIOCM_CTS;
205 }
206
207 static void set_rts(struct tegra_uart_port *tup, bool active)
208 {
209         unsigned long mcr;
210
211         mcr = tup->mcr_shadow;
212         if (active)
213                 mcr |= TEGRA_UART_MCR_RTS_EN;
214         else
215                 mcr &= ~TEGRA_UART_MCR_RTS_EN;
216         if (mcr != tup->mcr_shadow) {
217                 tegra_uart_write(tup, mcr, UART_MCR);
218                 tup->mcr_shadow = mcr;
219         }
220 }
221
222 static void set_dtr(struct tegra_uart_port *tup, bool active)
223 {
224         unsigned long mcr;
225
226         mcr = tup->mcr_shadow;
227         if (active)
228                 mcr |= UART_MCR_DTR;
229         else
230                 mcr &= ~UART_MCR_DTR;
231         if (mcr != tup->mcr_shadow) {
232                 tegra_uart_write(tup, mcr, UART_MCR);
233                 tup->mcr_shadow = mcr;
234         }
235 }
236
237 static void set_loopbk(struct tegra_uart_port *tup, bool active)
238 {
239         unsigned long mcr;
240
241         mcr = tup->mcr_shadow;
242         if (active)
243                 mcr |= UART_MCR_LOOP;
244         else
245                 mcr &= ~UART_MCR_LOOP;
246         if (mcr != tup->mcr_shadow) {
247                 tegra_uart_write(tup, mcr, UART_MCR);
248                 tup->mcr_shadow = mcr;
249         }
250 }
251
252 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
253 {
254         struct tegra_uart_port *tup = to_tegra_uport(u);
255         unsigned long mcr;
256         int dtr_enable;
257         int loopbk_enable;
258
259         mcr = tup->mcr_shadow;
260         tup->rts_active = !!(mctrl & TIOCM_RTS);
261         set_rts(tup, tup->rts_active);
262
263         dtr_enable = !!(mctrl & TIOCM_DTR);
264         set_dtr(tup, dtr_enable);
265
266         loopbk_enable = !!(mctrl & TIOCM_LOOP);
267         set_loopbk(tup, loopbk_enable);
268 }
269
270 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
271 {
272         struct tegra_uart_port *tup = to_tegra_uport(u);
273         unsigned long lcr;
274
275         lcr = tup->lcr_shadow;
276         if (break_ctl)
277                 lcr |= UART_LCR_SBC;
278         else
279                 lcr &= ~UART_LCR_SBC;
280         tegra_uart_write(tup, lcr, UART_LCR);
281         tup->lcr_shadow = lcr;
282 }
283
284 /**
285  * tegra_uart_wait_cycle_time: Wait for N UART clock periods
286  *
287  * @tup:        Tegra serial port data structure.
288  * @cycles:     Number of clock periods to wait.
289  *
290  * Tegra UARTs are clocked at 16X the baud/bit rate and hence the UART
291  * clock speed is 16X the current baud rate.
292  */
293 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup,
294                                        unsigned int cycles)
295 {
296         if (tup->current_baud)
297                 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16));
298 }
299
300 /* Wait for a symbol-time. */
301 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
302                 unsigned int syms)
303 {
304         if (tup->current_baud)
305                 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
306                         tup->current_baud));
307 }
308
309 static void tegra_uart_disable_rx_irqs(struct tegra_uart_port *tup)
310 {
311         unsigned long ier;
312
313         /* Disable Rx interrupts */
314         ier = tup->ier_shadow;
315         ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
316                         TEGRA_UART_IER_EORD);
317         tup->ier_shadow = ier;
318         tegra_uart_write(tup, ier, UART_IER);
319 }
320
321 static int tegra_uart_is_fifo_mode_enabled(struct tegra_uart_port *tup)
322 {
323         unsigned long iir;
324         unsigned int tmout = 100;
325         int ret = -EIO;
326
327         do {
328                 iir = tegra_uart_read(tup, UART_IIR);
329                 if (iir & TEGRA_UART_FCR_IIR_FIFO_EN) {
330                         ret = 0;
331                         break;
332                 }
333                 if (--tmout == 0)
334                         break;
335                 udelay(1);
336         } while (1);
337
338         return ret;
339 }
340
341 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
342 {
343         unsigned long fcr = tup->fcr_shadow;
344         int ret;
345
346         if (tup->cdata->allow_txfifo_reset_fifo_mode) {
347                 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
348                 tegra_uart_write(tup, fcr, UART_FCR);
349         } else {
350                 fcr &= ~UART_FCR_ENABLE_FIFO;
351                 tegra_uart_write(tup, fcr, UART_FCR);
352                 udelay(60);
353                 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
354                 tegra_uart_write(tup, fcr, UART_FCR);
355                 fcr |= UART_FCR_ENABLE_FIFO;
356                 tegra_uart_write(tup, fcr, UART_FCR);
357                 if (tup->cdata->fifo_mode_enable_status) {
358                         ret = tegra_uart_is_fifo_mode_enabled(tup);
359                         if (ret < 0)
360                                 dev_err(tup->uport.dev, "FIFO mode not enabled\n");
361                 }
362         }
363
364         /* Dummy read to ensure the write is posted */
365         tegra_uart_read(tup, UART_SCR);
366
367         /*
368          * For all tegra devices (up to t210), there is a hardware issue that
369          * requires software to wait for 32 UART clock periods for the flush
370          * to propagate, otherwise data could be lost.
371          */
372         tegra_uart_wait_cycle_time(tup, 32);
373 }
374
375 static long tegra_get_tolerance_rate(struct tegra_uart_port *tup,
376                 unsigned int baud, long rate)
377 {
378         int i;
379
380         for (i = 0; i < tup->n_adjustable_baud_rates; ++i) {
381                 if (baud >= tup->baud_tolerance[i].lower_range_baud &&
382                         baud <= tup->baud_tolerance[i].upper_range_baud)
383                         return (rate + (rate *
384                                 tup->baud_tolerance[i].tolerance) / 10000);
385         }
386
387         return rate;
388 }
389
390 static void tegra_check_rate_in_range(struct tegra_uart_port *tup)
391 {
392         int diff;
393         u32 error;
394
395         diff = ((tup->configured_rate - tup->required_rate) * 10000)
396                         / tup->required_rate;
397         error = diff < 0 ? -diff : diff;
398         if (diff < (tup->cdata->error_tolerance_low_range * 100) ||
399                         diff > (tup->cdata->error_tolerance_high_range * 100))
400                 dev_err(tup->uport.dev,
401                         "configured rate out of supported range by %c%d.%d %%",
402                         (diff < 0) ? '-':'+',
403                         (error/100), (error - (error/100) * 100));
404 }
405
406 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
407 {
408         unsigned long rate;
409         unsigned int divisor;
410         unsigned long lcr;
411         int ret;
412
413         if (tup->current_baud == baud)
414                 return 0;
415
416         if (tup->cdata->support_clk_src_div) {
417                 rate = baud * 16;
418                 tup->required_rate = rate;
419                 if (tup->n_adjustable_baud_rates)
420                         rate = tegra_get_tolerance_rate(tup, baud, rate);
421
422                 ret = clk_set_rate(tup->uart_clk, rate);
423                 if (ret < 0) {
424                         dev_err(tup->uport.dev,
425                                 "clk_set_rate() failed for rate %lu\n", rate);
426                         return ret;
427                 }
428                 tup->configured_rate = clk_get_rate(tup->uart_clk);
429                 tegra_check_rate_in_range(tup);
430                 divisor = 1;
431         } else {
432                 rate = clk_get_rate(tup->uart_clk);
433                 divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
434         }
435
436         lcr = tup->lcr_shadow;
437         lcr |= UART_LCR_DLAB;
438         tegra_uart_write(tup, lcr, UART_LCR);
439
440         tegra_uart_write(tup, divisor & 0xFF, UART_TX);
441         tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
442
443         lcr &= ~UART_LCR_DLAB;
444         tegra_uart_write(tup, lcr, UART_LCR);
445
446         /* Dummy read to ensure the write is posted */
447         tegra_uart_read(tup, UART_SCR);
448
449         tup->current_baud = baud;
450
451         /* wait two character intervals at new rate */
452         tegra_uart_wait_sym_time(tup, 2);
453         return 0;
454 }
455
456 static void tegra_uart_flush_fifo(struct tegra_uart_port *tup, u8 fcr_bits)
457 {
458         unsigned long fcr = tup->fcr_shadow;
459         unsigned int lsr, tmout = 10000;
460
461         fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
462         tegra_uart_write(tup, fcr, UART_FCR);
463
464         do {
465                 lsr = tegra_uart_read(tup, UART_LSR);
466                 if (!(lsr & UART_LSR_DR))
467                         break;
468                 if (--tmout == 0)
469                         break;
470                 udelay(1);
471         } while (1);
472 }
473
474 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
475                         unsigned long lsr)
476 {
477         char flag = TTY_NORMAL;
478
479         if (unlikely(lsr & TEGRA_UART_LSR_ANY)) {
480                 if (lsr & UART_LSR_BI) {
481                         tup->uport.icount.brk++;
482                         flag = TTY_BREAK;
483                         tegra_uart_flush_fifo(tup, UART_FCR_CLEAR_RCVR);
484
485                         if (tup->uport.ignore_status_mask & UART_LSR_BI)
486                                 goto exit;
487                         dev_dbg(tup->uport.dev, "Got Break\n");
488                 } else if (lsr & UART_LSR_PE) {
489                         /* Parity error */
490                         flag = TTY_PARITY;
491                         tup->uport.icount.parity++;
492                         dev_dbg(tup->uport.dev, "Got Parity errors\n");
493                 } else if (lsr & UART_LSR_FE) {
494                         flag = TTY_FRAME;
495                         tup->uport.icount.frame++;
496                         tegra_uart_flush_fifo(tup, UART_FCR_CLEAR_RCVR);
497                         dev_dbg(tup->uport.dev, "Got frame errors\n");
498                 } else if (lsr & UART_LSR_OE) {
499                         /* Overrrun error */
500                         flag |= TTY_OVERRUN;
501                         tup->uport.icount.overrun++;
502                         dev_dbg(tup->uport.dev, "Got overrun errors\n");
503                 }
504                 uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag);
505         }
506
507 exit:
508         return flag;
509 }
510
511 static int tegra_uart_request_port(struct uart_port *u)
512 {
513         return 0;
514 }
515
516 static void tegra_uart_release_port(struct uart_port *u)
517 {
518         /* Nothing to do here */
519 }
520
521 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
522 {
523         struct circ_buf *xmit = &tup->uport.state->xmit;
524         int i;
525
526         for (i = 0; i < max_bytes; i++) {
527                 BUG_ON(uart_circ_empty(xmit));
528                 if (tup->cdata->tx_fifo_full_status) {
529                         unsigned long lsr = tegra_uart_read(tup, UART_LSR);
530                         if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL))
531                                 break;
532                 }
533                 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX);
534                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
535                 tup->uport.icount.tx++;
536         }
537 }
538
539 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
540                 unsigned int bytes)
541 {
542         if (bytes > TEGRA_UART_MIN_DMA)
543                 bytes = TEGRA_UART_MIN_DMA;
544
545         tup->tx_in_progress = TEGRA_UART_TX_PIO;
546         tup->tx_bytes = bytes;
547         tup->ier_shadow |= UART_IER_THRI;
548         tegra_uart_write(tup, tup->ier_shadow, UART_IER);
549 }
550
551 static void tegra_uart_tx_dma_complete(void *args)
552 {
553         struct tegra_uart_port *tup = args;
554         struct circ_buf *xmit = &tup->uport.state->xmit;
555         struct dma_tx_state state;
556         unsigned long flags;
557         unsigned int count;
558
559         dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
560         count = tup->tx_bytes_requested - state.residue;
561         async_tx_ack(tup->tx_dma_desc);
562         spin_lock_irqsave(&tup->uport.lock, flags);
563         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
564         tup->tx_in_progress = 0;
565         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
566                 uart_write_wakeup(&tup->uport);
567         tegra_uart_start_next_tx(tup);
568         spin_unlock_irqrestore(&tup->uport.lock, flags);
569 }
570
571 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
572                 unsigned long count)
573 {
574         struct circ_buf *xmit = &tup->uport.state->xmit;
575         dma_addr_t tx_phys_addr;
576
577         dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys,
578                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
579
580         tup->tx_bytes = count & ~(0xF);
581         tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
582         tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
583                                 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
584                                 DMA_PREP_INTERRUPT);
585         if (!tup->tx_dma_desc) {
586                 dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
587                 return -EIO;
588         }
589
590         tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
591         tup->tx_dma_desc->callback_param = tup;
592         tup->tx_in_progress = TEGRA_UART_TX_DMA;
593         tup->tx_bytes_requested = tup->tx_bytes;
594         tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
595         dma_async_issue_pending(tup->tx_dma_chan);
596         return 0;
597 }
598
599 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
600 {
601         unsigned long tail;
602         unsigned long count;
603         struct circ_buf *xmit = &tup->uport.state->xmit;
604
605         tail = (unsigned long)&xmit->buf[xmit->tail];
606         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
607         if (!count)
608                 return;
609
610         if (tup->use_tx_pio) {
611                 tegra_uart_start_pio_tx(tup, count);
612         } else {
613                 if (count < TEGRA_UART_MIN_DMA)
614                         tegra_uart_start_pio_tx(tup, count);
615                 else if (BYTES_TO_ALIGN(tail) > 0)
616                         tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
617                 else
618                         tegra_uart_start_tx_dma(tup, count);
619         }
620 }
621
622 /* Called by serial core driver with u->lock taken. */
623 static void tegra_uart_start_tx(struct uart_port *u)
624 {
625         struct tegra_uart_port *tup = to_tegra_uport(u);
626         struct circ_buf *xmit = &u->state->xmit;
627
628         if (!uart_circ_empty(xmit) && !tup->tx_in_progress)
629                 tegra_uart_start_next_tx(tup);
630 }
631
632 static unsigned int tegra_uart_tx_empty(struct uart_port *u)
633 {
634         struct tegra_uart_port *tup = to_tegra_uport(u);
635         unsigned int ret = 0;
636         unsigned long flags;
637
638         spin_lock_irqsave(&u->lock, flags);
639         if (!tup->tx_in_progress) {
640                 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
641                 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
642                         ret = TIOCSER_TEMT;
643         }
644         spin_unlock_irqrestore(&u->lock, flags);
645         return ret;
646 }
647
648 static void tegra_uart_stop_tx(struct uart_port *u)
649 {
650         struct tegra_uart_port *tup = to_tegra_uport(u);
651         struct circ_buf *xmit = &tup->uport.state->xmit;
652         struct dma_tx_state state;
653         unsigned int count;
654
655         if (tup->tx_in_progress != TEGRA_UART_TX_DMA)
656                 return;
657
658         dmaengine_terminate_all(tup->tx_dma_chan);
659         dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
660         count = tup->tx_bytes_requested - state.residue;
661         async_tx_ack(tup->tx_dma_desc);
662         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
663         tup->tx_in_progress = 0;
664 }
665
666 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
667 {
668         struct circ_buf *xmit = &tup->uport.state->xmit;
669
670         tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
671         tup->tx_in_progress = 0;
672         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
673                 uart_write_wakeup(&tup->uport);
674         tegra_uart_start_next_tx(tup);
675 }
676
677 static int tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
678                 struct tty_port *tty)
679 {
680         int max_rx_count = TEGRA_UART_MAX_RX_CHARS;
681         int error_count = 0;
682
683         do {
684                 char flag = TTY_NORMAL;
685                 unsigned long lsr = 0;
686                 unsigned char ch;
687                 int copied;
688
689                 lsr = tegra_uart_read(tup, UART_LSR);
690                 if (!(lsr & UART_LSR_DR))
691                         break;
692
693                 flag = tegra_uart_decode_rx_error(tup, lsr);
694                 if (flag != TTY_NORMAL) {
695                         if (error_count++ > TEGRA_UART_MAX_REPEAT_ERRORS) {
696                                 tegra_uart_disable_rx_irqs(tup);
697                                 mod_timer(&tup->error_timer,
698                                         jiffies + tup->error_timer_timeout_jiffies);
699                                 return -EIO;
700                         }
701                         continue;
702                 }
703
704                 ch = (unsigned char) tegra_uart_read(tup, UART_RX);
705                 tup->uport.icount.rx++;
706
707                 if (tup->uport.ignore_status_mask & UART_LSR_DR)
708                         continue;
709
710                 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty) {
711                         copied  = tty_insert_flip_char(tty, ch, flag);
712                         if (copied != 1) {
713                                 dev_err(tup->uport.dev, "RxData PIO to tty layer failed\n");
714                                 tegra_uart_disable_rx_irqs(tup);
715                                 mod_timer(&tup->error_timer,
716                                         jiffies + tup->error_timer_timeout_jiffies);
717                                 return -ENOSPC;
718                         }
719                 }
720         } while (max_rx_count--);
721
722         return 0;
723 }
724
725 static void tegra_uart_rx_buffer_throttle_timer(unsigned long _data)
726 {
727         struct tegra_uart_port *tup = (struct tegra_uart_port *)_data;
728         struct uart_port *u = &tup->uport;
729         struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
730         struct tty_port *port = &tup->uport.state->port;
731         int rx_level;
732         unsigned long flags;
733
734         spin_lock_irqsave(&u->lock, flags);
735
736         rx_level = tty_buffer_get_level(port);
737         if (rx_level < 30) {
738                 if (tup->rts_active && tup->is_hw_flow_enabled)
739                         set_rts(tup, true);
740         } else {
741                 mod_timer(&tup->timer, jiffies + tup->timer_timeout_jiffies);
742         }
743
744         if (tty)
745                 tty_kref_put(tty);
746
747         spin_unlock_irqrestore(&u->lock, flags);
748 }
749
750 static void tegra_uart_rx_error_handle_timer(unsigned long _data)
751 {
752         struct tegra_uart_port *tup = (struct tegra_uart_port *)_data;
753         struct uart_port *u = &tup->uport;
754         unsigned long flags;
755         unsigned long ier;
756
757         spin_lock_irqsave(&u->lock, flags);
758         ier = tup->ier_shadow;
759         ier |= (UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD);
760         tup->ier_shadow = ier;
761         tegra_uart_write(tup, ier, UART_IER);
762         spin_unlock_irqrestore(&u->lock, flags);
763 }
764
765 static int tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
766                                       struct tty_port *tty,
767                                       unsigned int count)
768 {
769         int copied;
770         int ret = 0;
771
772         /* If count is zero, then there is no data to be copied */
773         if (!count)
774                 return 0;
775
776         tup->uport.icount.rx += count;
777         if (!tty) {
778                 dev_err(tup->uport.dev, "No tty port\n");
779                 return -EINVAL;
780         }
781
782         if (tup->uport.ignore_status_mask & UART_LSR_DR)
783                 return 0;
784
785         dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
786                                 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
787         copied = tty_insert_flip_string(tty,
788                         ((unsigned char *)(tup->rx_dma_buf_virt)), count);
789         if (copied != count) {
790                 dev_err(tup->uport.dev, "RxData DMA copy to tty layer failed\n");
791                 tegra_uart_disable_rx_irqs(tup);
792                 mod_timer(&tup->error_timer,
793                                 jiffies + tup->error_timer_timeout_jiffies);
794                 ret = -ENOSPC;
795         }
796         dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
797                                 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
798         return ret;
799 }
800
801 static int tegra_uart_rx_buffer_push(struct tegra_uart_port *tup,
802                                       unsigned int residue)
803 {
804         struct tty_port *port = &tup->uport.state->port;
805         struct tty_struct *tty = tty_port_tty_get(port);
806         unsigned int count;
807         int ret;
808
809         async_tx_ack(tup->rx_dma_desc);
810         count = tup->rx_bytes_requested - residue;
811
812         /* If we are here, DMA is stopped */
813         ret = tegra_uart_copy_rx_to_tty(tup, port, count);
814         if (ret)
815                 goto skip_pio;
816
817         ret = tegra_uart_handle_rx_pio(tup, port);
818 skip_pio:
819         if (tty) {
820                 tty_flip_buffer_push(port);
821                 tty_kref_put(tty);
822         }
823
824         return ret;
825 }
826
827 static void tegra_uart_rx_dma_complete(void *args)
828 {
829         struct tegra_uart_port *tup = args;
830         struct uart_port *u = &tup->uport;
831         struct tty_port *port = &u->state->port;
832         unsigned long flags;
833         struct dma_tx_state state;
834         enum dma_status status;
835         struct dma_async_tx_descriptor *prev_rx_dma_desc;
836         int rx_level = 0;
837
838         spin_lock_irqsave(&u->lock, flags);
839
840         status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
841
842         if (status == DMA_IN_PROGRESS) {
843                 dev_dbg(tup->uport.dev, "RX DMA is in progress\n");
844                 goto done;
845         }
846         prev_rx_dma_desc = tup->rx_dma_desc;
847
848         /* Deactivate flow control to stop sender */
849         if (tup->rts_active && tup->is_hw_flow_enabled)
850                 set_rts(tup, false);
851
852         tegra_uart_rx_buffer_push(tup, 0);
853
854         if (tup->enable_rx_buffer_throttle) {
855                 rx_level = tty_buffer_get_level(port);
856                 if (rx_level > 70)
857                         mod_timer(&tup->timer,
858                                   jiffies + tup->timer_timeout_jiffies);
859         }
860
861         tegra_uart_start_rx_dma(tup);
862         async_tx_ack(prev_rx_dma_desc);
863
864         /* Activate flow control to start transfer */
865         if (tup->enable_rx_buffer_throttle) {
866                 if ((rx_level <= 70) && tup->rts_active
867                                 && tup->is_hw_flow_enabled)
868                         set_rts(tup, true);
869         } else if (tup->rts_active && tup->is_hw_flow_enabled)
870                 set_rts(tup, true);
871
872 done:
873         spin_unlock_irqrestore(&u->lock, flags);
874 }
875
876 static int tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
877 {
878         struct tty_port *port = &tup->uport.state->port;
879         struct dma_tx_state state;
880         struct dma_async_tx_descriptor *prev_rx_dma_desc;
881         int rx_level = 0;
882         int ret;
883
884         /* Deactivate flow control to stop sender */
885         if (tup->rts_active && tup->is_hw_flow_enabled)
886                 set_rts(tup, false);
887
888         dmaengine_terminate_all(tup->rx_dma_chan);
889         dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
890         prev_rx_dma_desc = tup->rx_dma_desc;
891
892         ret = tegra_uart_rx_buffer_push(tup, state.residue);
893
894         if (tup->enable_rx_buffer_throttle) {
895                 rx_level = tty_buffer_get_level(port);
896                 if (rx_level > 70)
897                         mod_timer(&tup->timer,
898                                   jiffies + tup->timer_timeout_jiffies);
899         }
900
901         tegra_uart_start_rx_dma(tup);
902         async_tx_ack(prev_rx_dma_desc);
903
904         if (tup->enable_rx_buffer_throttle) {
905                 if ((rx_level <= 70) && tup->rts_active
906                                 && tup->is_hw_flow_enabled)
907                         set_rts(tup, true);
908         } else if (tup->rts_active && tup->is_hw_flow_enabled)
909                 set_rts(tup, true);
910
911         return ret;
912 }
913
914 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
915 {
916         unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
917
918         tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
919                                 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
920                                 DMA_PREP_INTERRUPT);
921         if (!tup->rx_dma_desc) {
922                 dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
923                 return -EIO;
924         }
925
926         tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
927         tup->rx_dma_desc->callback_param = tup;
928         dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
929                                 count, DMA_TO_DEVICE);
930         tup->rx_bytes_requested = count;
931         tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
932         dma_async_issue_pending(tup->rx_dma_chan);
933         return 0;
934 }
935
936 static void tegra_uart_handle_modem_signal_change(struct uart_port *u)
937 {
938         struct tegra_uart_port *tup = to_tegra_uport(u);
939         unsigned long msr;
940
941         msr = tegra_uart_read(tup, UART_MSR);
942         if (!(msr & UART_MSR_ANY_DELTA))
943                 return;
944
945         if (msr & UART_MSR_TERI)
946                 tup->uport.icount.rng++;
947         if (msr & UART_MSR_DDSR)
948                 tup->uport.icount.dsr++;
949         /* We may only get DDCD when HW init and reset */
950         if (msr & UART_MSR_DDCD)
951                 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
952         /* Will start/stop_tx accordingly */
953         if (msr & UART_MSR_DCTS)
954                 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
955 }
956
957 static void do_handle_rx_pio(struct tegra_uart_port *tup)
958 {
959         struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
960         struct tty_port *port = &tup->uport.state->port;
961         int rx_level = 0;
962
963         if (tup->rts_active && tup->is_hw_flow_enabled)
964                 set_rts(tup, false);
965
966         if (tup->enable_rx_buffer_throttle) {
967                 rx_level = tty_buffer_get_level(port);
968                 if (rx_level > 70) {
969                         mod_timer(&tup->timer,
970                                 jiffies + tup->timer_timeout_jiffies);
971                 }
972         }
973
974         tegra_uart_handle_rx_pio(tup, port);
975         if (tty) {
976                 tty_flip_buffer_push(port);
977                 tty_kref_put(tty);
978         }
979
980         if (tup->enable_rx_buffer_throttle) {
981                 if ((rx_level <= 70) && tup->rts_active
982                                 && tup->is_hw_flow_enabled)
983                         set_rts(tup, true);
984         } else if (tup->rts_active) {
985                 set_rts(tup, true);
986         }
987 }
988
989 static irqreturn_t tegra_uart_isr(int irq, void *data)
990 {
991         struct tegra_uart_port *tup = data;
992         struct uart_port *u = &tup->uport;
993         unsigned long iir;
994         unsigned long ier;
995         bool is_rx_int = false;
996         unsigned long flags;
997         int ret;
998
999         spin_lock_irqsave(&u->lock, flags);
1000         while (1) {
1001                 iir = tegra_uart_read(tup, UART_IIR);
1002                 if (iir & UART_IIR_NO_INT) {
1003                         if (!tup->use_rx_pio && is_rx_int) {
1004                                 ret = tegra_uart_handle_rx_dma(tup);
1005                                 if (ret) {
1006                                         spin_unlock_irqrestore(&u->lock, flags);
1007                                         return IRQ_HANDLED;
1008                                 }
1009                                 if (tup->rx_in_progress) {
1010                                         ier = tup->ier_shadow;
1011                                         ier |= (UART_IER_RLSI | UART_IER_RTOIE |
1012                                                 TEGRA_UART_IER_EORD);
1013                                         tup->ier_shadow = ier;
1014                                         tegra_uart_write(tup, ier, UART_IER);
1015                                 }
1016                         }
1017                         spin_unlock_irqrestore(&u->lock, flags);
1018                         return IRQ_HANDLED;
1019                 }
1020
1021                 switch ((iir >> 1) & 0x7) {
1022                 case 0: /* Modem signal change interrupt */
1023                         tegra_uart_handle_modem_signal_change(u);
1024                         break;
1025
1026                 case 1: /* Transmit interrupt only triggered when using PIO */
1027                         tup->ier_shadow &= ~UART_IER_THRI;
1028                         tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1029                         tegra_uart_handle_tx_pio(tup);
1030                         break;
1031
1032                 case 4: /* End of data */
1033                 case 6: /* Rx timeout */
1034                 case 2: /* Receive */
1035                         if (!tup->use_rx_pio && !is_rx_int) {
1036                                 is_rx_int = true;
1037                                 /* Disable Rx interrupts */
1038                                 ier = tup->ier_shadow;
1039                                 ier |= UART_IER_RDI;
1040                                 tegra_uart_write(tup, ier, UART_IER);
1041                                 ier &= ~(UART_IER_RDI | UART_IER_RLSI |
1042                                         UART_IER_RTOIE | TEGRA_UART_IER_EORD);
1043                                 tup->ier_shadow = ier;
1044                                 tegra_uart_write(tup, ier, UART_IER);
1045                         } else
1046                                 do_handle_rx_pio(tup);
1047                         break;
1048
1049                 case 3: /* Receive error */
1050                         tegra_uart_decode_rx_error(tup,
1051                                         tegra_uart_read(tup, UART_LSR));
1052                         break;
1053
1054                 case 5: /* break nothing to handle */
1055                 case 7: /* break nothing to handle */
1056                         break;
1057                 }
1058         }
1059 }
1060
1061 static void tegra_uart_stop_rx(struct uart_port *u)
1062 {
1063         struct tegra_uart_port *tup = to_tegra_uport(u);
1064         struct tty_port *port = &tup->uport.state->port;
1065         struct dma_tx_state state;
1066         unsigned long ier;
1067
1068         if (tup->rts_active && tup->is_hw_flow_enabled)
1069                 set_rts(tup, false);
1070
1071         if (!tup->rx_in_progress)
1072                 return;
1073
1074         tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */
1075
1076         ier = tup->ier_shadow;
1077         ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
1078                                         TEGRA_UART_IER_EORD);
1079         tup->ier_shadow = ier;
1080         tegra_uart_write(tup, ier, UART_IER);
1081         tup->rx_in_progress = 0;
1082         if (tup->rx_dma_chan && !tup->use_rx_pio) {
1083                 dmaengine_terminate_all(tup->rx_dma_chan);
1084                 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
1085                 tegra_uart_rx_buffer_push(tup, state.residue);
1086         } else {
1087                 tegra_uart_handle_rx_pio(tup, port);
1088         }
1089
1090         del_timer_sync(&tup->error_timer);
1091 }
1092
1093 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
1094 {
1095         unsigned long flags;
1096         unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
1097         unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
1098         unsigned long wait_time;
1099         unsigned long lsr;
1100         unsigned long msr;
1101         unsigned long mcr;
1102
1103         /* Disable interrupts */
1104         tegra_uart_write(tup, 0, UART_IER);
1105
1106         lsr = tegra_uart_read(tup, UART_LSR);
1107         if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
1108                 msr = tegra_uart_read(tup, UART_MSR);
1109                 mcr = tegra_uart_read(tup, UART_MCR);
1110                 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
1111                         dev_err(tup->uport.dev,
1112                                 "Tx Fifo not empty, CTS disabled, waiting\n");
1113
1114                 /* Wait for Tx fifo to be empty */
1115                 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
1116                         wait_time = min(fifo_empty_time, 100lu);
1117                         udelay(wait_time);
1118                         fifo_empty_time -= wait_time;
1119                         if (!fifo_empty_time) {
1120                                 msr = tegra_uart_read(tup, UART_MSR);
1121                                 mcr = tegra_uart_read(tup, UART_MCR);
1122                                 if ((mcr & TEGRA_UART_MCR_CTS_EN) &&
1123                                         (msr & UART_MSR_CTS))
1124                                         dev_err(tup->uport.dev,
1125                                                 "Slave not ready\n");
1126                                 break;
1127                         }
1128                         lsr = tegra_uart_read(tup, UART_LSR);
1129                 }
1130         }
1131
1132         spin_lock_irqsave(&tup->uport.lock, flags);
1133         /* Reset the Rx and Tx FIFOs */
1134         tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
1135         tup->current_baud = 0;
1136         spin_unlock_irqrestore(&tup->uport.lock, flags);
1137
1138         clk_disable_unprepare(tup->uart_clk);
1139 }
1140
1141 static int tegra_uart_hw_init(struct tegra_uart_port *tup)
1142 {
1143         int ret;
1144
1145         tup->fcr_shadow = 0;
1146         tup->mcr_shadow = 0;
1147         tup->lcr_shadow = 0;
1148         tup->ier_shadow = 0;
1149         tup->current_baud = 0;
1150
1151         clk_prepare_enable(tup->uart_clk);
1152
1153         /* Reset the UART controller to clear all previous status.*/
1154         reset_control_assert(tup->rst);
1155         udelay(10);
1156         reset_control_deassert(tup->rst);
1157
1158         tup->rx_in_progress = 0;
1159         tup->tx_in_progress = 0;
1160
1161         /*
1162          * Set the trigger level
1163          *
1164          * For PIO mode:
1165          *
1166          * For receive, this will interrupt the CPU after that many number of
1167          * bytes are received, for the remaining bytes the receive timeout
1168          * interrupt is received. Rx high watermark is set to 4.
1169          *
1170          * For transmit, if the trasnmit interrupt is enabled, this will
1171          * interrupt the CPU when the number of entries in the FIFO reaches the
1172          * low watermark. Tx low watermark is set to 16 bytes.
1173          *
1174          * For DMA mode:
1175          *
1176          * Set the Tx trigger to 16. This should match the DMA burst size that
1177          * programmed in the DMA registers.
1178          */
1179         tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
1180
1181         if (tup->use_rx_pio) {
1182                 tup->fcr_shadow |= UART_FCR_R_TRIG_11;
1183         } else {
1184                 if (tup->cdata->dma_8bytes_burst_only)
1185                         tup->fcr_shadow |= UART_FCR_R_TRIG_10;
1186                 else
1187                         tup->fcr_shadow |= UART_FCR_R_TRIG_01;
1188         }
1189
1190         tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
1191         tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1192
1193         /* Dummy read to ensure the write is posted */
1194         tegra_uart_read(tup, UART_SCR);
1195
1196
1197         if (tup->cdata->fifo_mode_enable_status) {
1198                 ret = tegra_uart_is_fifo_mode_enabled(tup);
1199                 if (ret < 0) {
1200                         dev_err(tup->uport.dev, "FIFO mode not enabled\n");
1201                         return ret;
1202                 }
1203         } else {
1204                 /*
1205                  * For all tegra devices (up to t210), there is a hardware issue that
1206                  * requires software to wait for 3 UART clock periods after enabling
1207                  * the TX fifo, otherwise data could be lost.
1208                  */
1209                 tegra_uart_wait_cycle_time(tup, 3);
1210         }
1211
1212         /*
1213          * Initialize the UART with default configuration
1214          * (115200, N, 8, 1) so that the receive DMA buffer may be
1215          * enqueued
1216          */
1217         if (!tup->use_rx_pio) {
1218                 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
1219                 tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
1220                 tup->fcr_shadow |= UART_FCR_DMA_SELECT;
1221                 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1222
1223                 ret = tegra_uart_start_rx_dma(tup);
1224                 if (ret < 0) {
1225                         dev_err(tup->uport.dev, "Not able to start Rx DMA\n");
1226                         return ret;
1227                 }
1228         } else {
1229                 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1230         }
1231         tup->rx_in_progress = 1;
1232
1233         /*
1234          * Enable IE_RXS for the receive status interrupts like line errros.
1235          * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
1236          *
1237          * If using DMA mode, enable EORD instead of receive interrupt which
1238          * will interrupt after the UART is done with the receive instead of
1239          * the interrupt when the FIFO "threshold" is reached.
1240          *
1241          * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
1242          * the DATA is sitting in the FIFO and couldn't be transferred to the
1243          * DMA as the DMA size alignment(4 bytes) is not met. EORD will be
1244          * triggered when there is a pause of the incomming data stream for 4
1245          * characters long.
1246          *
1247          * For pauses in the data which is not aligned to 4 bytes, we get
1248          * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
1249          * then the EORD.
1250          */
1251         if (!tup->use_rx_pio)
1252                 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE |
1253                         TEGRA_UART_IER_EORD;
1254         else
1255                 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI;
1256
1257         tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1258         return 0;
1259 }
1260
1261 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
1262                 bool dma_to_memory)
1263 {
1264         if (dma_to_memory) {
1265                 dmaengine_terminate_all(tup->rx_dma_chan);
1266                 dma_release_channel(tup->rx_dma_chan);
1267                 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
1268                                 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
1269                 tup->rx_dma_chan = NULL;
1270                 tup->rx_dma_buf_phys = 0;
1271                 tup->rx_dma_buf_virt = NULL;
1272         } else {
1273                 dmaengine_terminate_all(tup->tx_dma_chan);
1274                 dma_release_channel(tup->tx_dma_chan);
1275                 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
1276                         UART_XMIT_SIZE, DMA_TO_DEVICE);
1277                 tup->tx_dma_chan = NULL;
1278                 tup->tx_dma_buf_phys = 0;
1279                 tup->tx_dma_buf_virt = NULL;
1280         }
1281 }
1282
1283 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
1284                         bool dma_to_memory)
1285 {
1286         struct dma_chan *dma_chan;
1287         unsigned char *dma_buf;
1288         dma_addr_t dma_phys;
1289         int ret;
1290         struct dma_slave_config dma_sconfig;
1291
1292         dma_chan = dma_request_slave_channel_reason(tup->uport.dev,
1293                                                 dma_to_memory ? "rx" : "tx");
1294         if (IS_ERR(dma_chan)) {
1295                 ret = PTR_ERR(dma_chan);
1296                 dev_err(tup->uport.dev,
1297                         "DMA channel alloc failed: %d\n", ret);
1298                 return ret;
1299         }
1300
1301         if (dma_to_memory) {
1302                 dma_buf = dma_alloc_coherent(tup->uport.dev,
1303                                 TEGRA_UART_RX_DMA_BUFFER_SIZE,
1304                                  &dma_phys, GFP_KERNEL);
1305                 if (!dma_buf) {
1306                         dev_err(tup->uport.dev,
1307                                 "Not able to allocate the dma buffer\n");
1308                         dma_release_channel(dma_chan);
1309                         return -ENOMEM;
1310                 }
1311                 dma_sconfig.src_addr = tup->uport.mapbase;
1312                 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1313                 if (tup->cdata->dma_8bytes_burst_only)
1314                         dma_sconfig.src_maxburst = 8;
1315                 else
1316                         dma_sconfig.src_maxburst = 4;
1317                 tup->rx_dma_chan = dma_chan;
1318                 tup->rx_dma_buf_virt = dma_buf;
1319                 tup->rx_dma_buf_phys = dma_phys;
1320         } else {
1321                 dma_phys = dma_map_single(tup->uport.dev,
1322                         tup->uport.state->xmit.buf, UART_XMIT_SIZE,
1323                         DMA_TO_DEVICE);
1324                 if (dma_mapping_error(tup->uport.dev, dma_phys)) {
1325                         dev_err(tup->uport.dev, "dma_map_single tx failed\n");
1326                         dma_release_channel(dma_chan);
1327                         return -ENOMEM;
1328                 }
1329                 dma_buf = tup->uport.state->xmit.buf;
1330                 dma_sconfig.dst_addr = tup->uport.mapbase;
1331                 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1332                 dma_sconfig.dst_maxburst = 16;
1333                 tup->tx_dma_chan = dma_chan;
1334                 tup->tx_dma_buf_virt = dma_buf;
1335                 tup->tx_dma_buf_phys = dma_phys;
1336         }
1337
1338         ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
1339         if (ret < 0) {
1340                 dev_err(tup->uport.dev,
1341                         "Dma slave config failed, err = %d\n", ret);
1342                 tegra_uart_dma_channel_free(tup, dma_to_memory);
1343                 return ret;
1344         }
1345
1346         return 0;
1347 }
1348
1349 static int tegra_uart_startup(struct uart_port *u)
1350 {
1351         struct tegra_uart_port *tup = to_tegra_uport(u);
1352         int ret;
1353
1354         if (!tup->use_tx_pio) {
1355                 ret = tegra_uart_dma_channel_allocate(tup, false);
1356                 if (ret < 0) {
1357                         dev_err(u->dev, "Tx Dma allocation failed, err = %d\n",
1358                                         ret);
1359                         return ret;
1360                 }
1361         }
1362
1363         if (!tup->use_rx_pio) {
1364                 ret = tegra_uart_dma_channel_allocate(tup, true);
1365                 if (ret < 0) {
1366                         dev_err(u->dev, "Rx Dma allocation failed, err = %d\n",
1367                                         ret);
1368                         goto fail_rx_dma;
1369                 }
1370         }
1371
1372         ret = tegra_uart_hw_init(tup);
1373         if (ret < 0) {
1374                 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
1375                 goto fail_hw_init;
1376         }
1377
1378         ret = request_irq(u->irq, tegra_uart_isr, 0,
1379                                 dev_name(u->dev), tup);
1380         if (ret < 0) {
1381                 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
1382                 goto fail_hw_init;
1383         }
1384         return 0;
1385
1386 fail_hw_init:
1387         if (!tup->use_rx_pio)
1388                 tegra_uart_dma_channel_free(tup, true);
1389 fail_rx_dma:
1390         if (!tup->use_tx_pio)
1391                 tegra_uart_dma_channel_free(tup, false);
1392         return ret;
1393 }
1394
1395 /*
1396  * Flush any TX data submitted for DMA and PIO. Called when the
1397  * TX circular buffer is reset.
1398  */
1399 static void tegra_uart_flush_buffer(struct uart_port *u)
1400 {
1401         struct tegra_uart_port *tup = to_tegra_uport(u);
1402
1403         tup->tx_bytes = 0;
1404         if (tup->tx_dma_chan)
1405                 dmaengine_terminate_all(tup->tx_dma_chan);
1406 }
1407
1408 static void tegra_uart_shutdown(struct uart_port *u)
1409 {
1410         struct tegra_uart_port *tup = to_tegra_uport(u);
1411
1412         tegra_uart_hw_deinit(tup);
1413
1414         tup->rx_in_progress = 0;
1415         tup->tx_in_progress = 0;
1416
1417         if (!tup->use_rx_pio)
1418                 tegra_uart_dma_channel_free(tup, true);
1419         if (!tup->use_tx_pio)
1420                 tegra_uart_dma_channel_free(tup, false);
1421         free_irq(u->irq, tup);
1422 }
1423
1424 static void tegra_uart_enable_ms(struct uart_port *u)
1425 {
1426         struct tegra_uart_port *tup = to_tegra_uport(u);
1427
1428         if (tup->enable_modem_interrupt) {
1429                 tup->ier_shadow |= UART_IER_MSI;
1430                 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1431         }
1432 }
1433
1434 static void tegra_uart_set_termios(struct uart_port *u,
1435                 struct ktermios *termios, struct ktermios *oldtermios)
1436 {
1437         struct tegra_uart_port *tup = to_tegra_uport(u);
1438         unsigned int baud;
1439         unsigned long flags;
1440         unsigned int lcr;
1441         int symb_bit = 1;
1442         struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1443         unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1444         int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1445
1446         max_divider *= 16;
1447         spin_lock_irqsave(&u->lock, flags);
1448
1449         /* Changing configuration, it is safe to stop any rx now */
1450         if (tup->rts_active)
1451                 set_rts(tup, false);
1452
1453         /* Clear all interrupts as configuration is going to be change */
1454         tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1455         tegra_uart_read(tup, UART_IER);
1456         tegra_uart_write(tup, 0, UART_IER);
1457         tegra_uart_read(tup, UART_IER);
1458
1459         /* Parity */
1460         lcr = tup->lcr_shadow;
1461         lcr &= ~UART_LCR_PARITY;
1462
1463         /* CMSPAR isn't supported by this driver */
1464         termios->c_cflag &= ~CMSPAR;
1465
1466         if ((termios->c_cflag & PARENB) == PARENB) {
1467                 symb_bit++;
1468                 if (termios->c_cflag & PARODD) {
1469                         lcr |= UART_LCR_PARITY;
1470                         lcr &= ~UART_LCR_EPAR;
1471                         lcr &= ~UART_LCR_SPAR;
1472                 } else {
1473                         lcr |= UART_LCR_PARITY;
1474                         lcr |= UART_LCR_EPAR;
1475                         lcr &= ~UART_LCR_SPAR;
1476                 }
1477         }
1478
1479         lcr &= ~UART_LCR_WLEN8;
1480         switch (termios->c_cflag & CSIZE) {
1481         case CS5:
1482                 lcr |= UART_LCR_WLEN5;
1483                 symb_bit += 5;
1484                 break;
1485         case CS6:
1486                 lcr |= UART_LCR_WLEN6;
1487                 symb_bit += 6;
1488                 break;
1489         case CS7:
1490                 lcr |= UART_LCR_WLEN7;
1491                 symb_bit += 7;
1492                 break;
1493         default:
1494                 lcr |= UART_LCR_WLEN8;
1495                 symb_bit += 8;
1496                 break;
1497         }
1498
1499         /* Stop bits */
1500         if (termios->c_cflag & CSTOPB) {
1501                 lcr |= UART_LCR_STOP;
1502                 symb_bit += 2;
1503         } else {
1504                 lcr &= ~UART_LCR_STOP;
1505                 symb_bit++;
1506         }
1507
1508         tegra_uart_write(tup, lcr, UART_LCR);
1509         tup->lcr_shadow = lcr;
1510         tup->symb_bit = symb_bit;
1511
1512         /* Baud rate. */
1513         baud = uart_get_baud_rate(u, termios, oldtermios,
1514                         parent_clk_rate/max_divider,
1515                         parent_clk_rate/16);
1516         spin_unlock_irqrestore(&u->lock, flags);
1517         tegra_set_baudrate(tup, baud);
1518         if (tty_termios_baud_rate(termios))
1519                 tty_termios_encode_baud_rate(termios, baud, baud);
1520         spin_lock_irqsave(&u->lock, flags);
1521
1522         /* Flow control */
1523         if (termios->c_cflag & CRTSCTS) {
1524                 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1525                 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1526                 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1527                 tup->is_hw_flow_enabled = true;
1528                 /* if top layer has asked to set rts active then do so here */
1529                 if (tup->rts_active && tup->is_hw_flow_enabled)
1530                         set_rts(tup, true);
1531         } else {
1532                 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1533                 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1534                 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1535                 tup->is_hw_flow_enabled = false;
1536         }
1537
1538         /* update the port timeout based on new settings */
1539         uart_update_timeout(u, termios->c_cflag, baud);
1540
1541         /* Make sure all write has completed */
1542         tegra_uart_read(tup, UART_IER);
1543
1544         /* Reenable interrupt */
1545         tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1546         tegra_uart_read(tup, UART_IER);
1547
1548         tup->uport.ignore_status_mask = 0;
1549         /* Ignore all characters if CREAD is not set */
1550         if ((termios->c_cflag & CREAD) == 0)
1551                 tup->uport.ignore_status_mask |= UART_LSR_DR;
1552         if (termios->c_iflag & IGNBRK)
1553                 tup->uport.ignore_status_mask |= UART_LSR_BI;
1554
1555         spin_unlock_irqrestore(&u->lock, flags);
1556 }
1557
1558 static const char *tegra_uart_type(struct uart_port *u)
1559 {
1560         return TEGRA_UART_TYPE;
1561 }
1562
1563 static struct uart_ops tegra_uart_ops = {
1564         .tx_empty       = tegra_uart_tx_empty,
1565         .set_mctrl      = tegra_uart_set_mctrl,
1566         .get_mctrl      = tegra_uart_get_mctrl,
1567         .stop_tx        = tegra_uart_stop_tx,
1568         .start_tx       = tegra_uart_start_tx,
1569         .stop_rx        = tegra_uart_stop_rx,
1570         .flush_buffer   = tegra_uart_flush_buffer,
1571         .enable_ms      = tegra_uart_enable_ms,
1572         .break_ctl      = tegra_uart_break_ctl,
1573         .startup        = tegra_uart_startup,
1574         .shutdown       = tegra_uart_shutdown,
1575         .set_termios    = tegra_uart_set_termios,
1576         .type           = tegra_uart_type,
1577         .request_port   = tegra_uart_request_port,
1578         .release_port   = tegra_uart_release_port,
1579 };
1580
1581 static struct uart_driver tegra_uart_driver = {
1582         .owner          = THIS_MODULE,
1583         .driver_name    = "tegra_hsuart",
1584         .dev_name       = "ttyTHS",
1585         .cons           = NULL,
1586         .nr             = TEGRA_UART_MAXIMUM,
1587 };
1588
1589 static int tegra_uart_parse_dt(struct platform_device *pdev,
1590         struct tegra_uart_port *tup)
1591 {
1592         struct device_node *np = pdev->dev.of_node;
1593         int port;
1594         int ret;
1595         int index;
1596         u32 pval;
1597         int count;
1598         int n_entries;
1599
1600         port = of_alias_get_id(np, "serial");
1601         if (port < 0) {
1602                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
1603                 return port;
1604         }
1605         tup->uport.line = port;
1606
1607         tup->enable_modem_interrupt = of_property_read_bool(np,
1608                                         "nvidia,enable-modem-interrupt");
1609
1610         index = of_property_match_string(np, "dma-names", "rx");
1611         if (index < 0) {
1612                 tup->use_rx_pio = true;
1613                 dev_info(&pdev->dev, "RX in PIO mode\n");
1614         }
1615         index = of_property_match_string(np, "dma-names", "tx");
1616         if (index < 0) {
1617                 tup->use_tx_pio = true;
1618                 dev_info(&pdev->dev, "TX in PIO mode\n");
1619         }
1620
1621         tup->enable_rx_buffer_throttle = of_property_read_bool(np,
1622                         "nvidia,enable-rx-buffer-throttling");
1623         if (tup->enable_rx_buffer_throttle)
1624                 dev_info(&pdev->dev, "Rx buffer throttling enabled\n");
1625
1626         tup->early_printk_console_instance = of_property_read_bool(np,
1627                         "early-print-console-channel");
1628
1629         tup->rt_flush = of_property_read_bool(np, "rt-flush");
1630
1631         n_entries = of_property_count_u32_elems(np, "nvidia,adjust-baud-rates");
1632         if (n_entries > 0) {
1633                 tup->n_adjustable_baud_rates = n_entries/3;
1634                 tup->baud_tolerance = devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) *
1635                                 sizeof(*tup->baud_tolerance), GFP_KERNEL);
1636                 if (!tup->baud_tolerance)
1637                         return -ENOMEM;
1638                 for (count = 0, index = 0; count < n_entries; count += 3, index++) {
1639                         ret = of_property_read_u32_index(np, "nvidia,adjust-baud-rates",
1640                                         count, &pval);
1641                         if (!ret)
1642                                 tup->baud_tolerance[index].lower_range_baud = pval;
1643                         ret = of_property_read_u32_index(np, "nvidia,adjust-baud-rates",
1644                                         count + 1, &pval);
1645                         if (!ret)
1646                                 tup->baud_tolerance[index].upper_range_baud = pval;
1647                         ret = of_property_read_u32_index(np, "nvidia,adjust-baud-rates",
1648                                         count + 2, &pval);
1649                         if (!ret)
1650                                 tup->baud_tolerance[index].tolerance = (s32)pval;
1651                 }
1652         } else
1653                 tup->n_adjustable_baud_rates = 0;
1654
1655         return 0;
1656 }
1657
1658 #ifdef CONFIG_DEBUG_FS
1659 static void tegra_uart_debugfs_init(struct tegra_uart_port *tup)
1660 {
1661         tup->debugfs = debugfs_create_dir(dev_name(tup->uport.dev), NULL);
1662         if (IS_ERR_OR_NULL(tup->debugfs))
1663                 goto clean;
1664
1665         debugfs_create_u32("required_rate", 0644, tup->debugfs,
1666                         &tup->required_rate);
1667         debugfs_create_u32("config_rate", 0644, tup->debugfs,
1668                         &tup->configured_rate);
1669         return;
1670 clean:
1671         dev_warn(tup->uport.dev, "Failed to create debugfs!\n");
1672         debugfs_remove_recursive(tup->debugfs);
1673 }
1674
1675 static void tegra_uart_debugfs_deinit(struct tegra_uart_port *tup)
1676 {
1677         debugfs_remove_recursive(tup->debugfs);
1678 }
1679 #else
1680 static void tegra_uart_debugfs_init(struct tegra_uart_port *tup) {}
1681 static void tegra_uart_debugfs_deinit(struct tegra_uart_port *tup) {}
1682 #endif
1683
1684 static struct tegra_uart_chip_data tegra20_uart_chip_data = {
1685         .tx_fifo_full_status            = false,
1686         .allow_txfifo_reset_fifo_mode   = true,
1687         .support_clk_src_div            = false,
1688         .fifo_mode_enable_status        = false,
1689         .dma_8bytes_burst_only          = false,
1690         .error_tolerance_low_range      = 0,
1691         .error_tolerance_high_range     = 4,
1692 };
1693
1694 static struct tegra_uart_chip_data tegra30_uart_chip_data = {
1695         .tx_fifo_full_status            = true,
1696         .allow_txfifo_reset_fifo_mode   = false,
1697         .support_clk_src_div            = true,
1698         .fifo_mode_enable_status        = false,
1699         .dma_8bytes_burst_only          = false,
1700         .error_tolerance_low_range      = 0,
1701         .error_tolerance_high_range     = 4,
1702 };
1703
1704 static struct tegra_uart_chip_data tegra114_uart_chip_data = {
1705         .tx_fifo_full_status            = true,
1706         .allow_txfifo_reset_fifo_mode   = false,
1707         .support_clk_src_div            = true,
1708         .fifo_mode_enable_status        = false,
1709         .dma_8bytes_burst_only          = false,
1710         .error_tolerance_low_range      = 0,
1711         .error_tolerance_high_range     = 4,
1712 };
1713
1714 static struct tegra_uart_chip_data tegra186_uart_chip_data = {
1715         .tx_fifo_full_status            = true,
1716         .allow_txfifo_reset_fifo_mode   = false,
1717         .support_clk_src_div            = true,
1718         .fifo_mode_enable_status        = true,
1719         .dma_8bytes_burst_only          = true,
1720         .error_tolerance_low_range      = 0,
1721         .error_tolerance_high_range     = 4,
1722 };
1723
1724 static const struct of_device_id tegra_uart_of_match[] = {
1725         {
1726                 .compatible     = "nvidia,tegra30-hsuart",
1727                 .data           = &tegra30_uart_chip_data,
1728         }, {
1729                 .compatible     = "nvidia,tegra20-hsuart",
1730                 .data           = &tegra20_uart_chip_data,
1731         }, {
1732                 .compatible     = "nvidia,tegra114-hsuart",
1733                 .data           = &tegra114_uart_chip_data,
1734         }, {
1735                 .compatible     = "nvidia,tegra186-hsuart",
1736                 .data           = &tegra186_uart_chip_data,
1737         }, {
1738         },
1739 };
1740 MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
1741
1742 static int tegra_uart_probe(struct platform_device *pdev)
1743 {
1744         struct tegra_uart_port *tup;
1745         struct uart_port *u;
1746         struct resource *resource;
1747         struct clk *parent_clk;
1748         int ret;
1749         const struct tegra_uart_chip_data *cdata;
1750         const struct of_device_id *match;
1751
1752         match = of_match_device(tegra_uart_of_match, &pdev->dev);
1753         if (!match) {
1754                 dev_err(&pdev->dev, "Error: No device match found\n");
1755                 return -ENODEV;
1756         }
1757         cdata = match->data;
1758
1759         tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1760         if (!tup) {
1761                 dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1762                 return -ENOMEM;
1763         }
1764
1765         ret = tegra_uart_parse_dt(pdev, tup);
1766         if (ret < 0)
1767                 return ret;
1768
1769         u = &tup->uport;
1770         u->dev = &pdev->dev;
1771         u->ops = &tegra_uart_ops;
1772         u->type = PORT_TEGRA;
1773         u->fifosize = 32;
1774         tup->cdata = cdata;
1775
1776         platform_set_drvdata(pdev, tup);
1777         resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1778         if (!resource) {
1779                 dev_err(&pdev->dev, "No IO memory resource\n");
1780                 return -ENODEV;
1781         }
1782
1783         u->mapbase = resource->start;
1784         u->membase = devm_ioremap_resource(&pdev->dev, resource);
1785         if (IS_ERR(u->membase))
1786                 return PTR_ERR(u->membase);
1787
1788         tup->uart_clk = devm_clk_get(&pdev->dev, "serial");
1789         if (IS_ERR(tup->uart_clk)) {
1790                 dev_err(&pdev->dev, "Couldn't get the clock\n");
1791                 return PTR_ERR(tup->uart_clk);
1792         }
1793
1794         tup->rst = devm_reset_control_get(&pdev->dev, "serial");
1795         if (IS_ERR(tup->rst)) {
1796                 dev_err(&pdev->dev, "Couldn't get the reset\n");
1797                 return PTR_ERR(tup->rst);
1798         }
1799
1800         if (!tup->early_printk_console_instance) {
1801                 reset_control_assert(tup->rst);
1802                 udelay(10);
1803                 reset_control_deassert(tup->rst);
1804         }
1805
1806         parent_clk = devm_clk_get(&pdev->dev, "parent");
1807         if (IS_ERR(parent_clk))
1808                 dev_err(&pdev->dev, "Unable to get parent_clk err: %ld\n",
1809                                 PTR_ERR(parent_clk));
1810         else {
1811                 ret = clk_set_parent(tup->uart_clk, parent_clk);
1812                 if (ret < 0)
1813                         dev_warn(&pdev->dev,
1814                                 "Couldn't set the parent clock - %d\n", ret);
1815         }
1816
1817         u->iotype = UPIO_MEM32;
1818         u->irq = platform_get_irq(pdev, 0);
1819         u->regshift = 2;
1820         u->rt_flush = tup->rt_flush;
1821         ret = uart_add_one_port(&tegra_uart_driver, u);
1822         if (ret < 0) {
1823                 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
1824                 return ret;
1825         }
1826
1827         if (tup->enable_rx_buffer_throttle) {
1828                 setup_timer(&tup->timer, tegra_uart_rx_buffer_throttle_timer,
1829                                 (unsigned long)tup);
1830                 tup->timer_timeout_jiffies = msecs_to_jiffies(10);
1831         }
1832
1833         setup_timer(&tup->error_timer, tegra_uart_rx_error_handle_timer,
1834                         (unsigned long)tup);
1835         tup->error_timer_timeout_jiffies = msecs_to_jiffies(500);
1836         tegra_uart_debugfs_init(tup);
1837
1838         return ret;
1839 }
1840
1841 static int tegra_uart_remove(struct platform_device *pdev)
1842 {
1843         struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1844         struct uart_port *u = &tup->uport;
1845
1846         tegra_uart_debugfs_deinit(tup);
1847         if (tup->enable_rx_buffer_throttle)
1848                 del_timer_sync(&tup->timer);
1849         del_timer_sync(&tup->error_timer);
1850
1851         uart_remove_one_port(&tegra_uart_driver, u);
1852         return 0;
1853 }
1854
1855 #ifdef CONFIG_PM_SLEEP
1856 static int tegra_uart_suspend(struct device *dev)
1857 {
1858         struct tegra_uart_port *tup = dev_get_drvdata(dev);
1859         struct uart_port *u = &tup->uport;
1860
1861         return uart_suspend_port(&tegra_uart_driver, u);
1862 }
1863
1864 static int tegra_uart_resume(struct device *dev)
1865 {
1866         struct tegra_uart_port *tup = dev_get_drvdata(dev);
1867         struct uart_port *u = &tup->uport;
1868
1869         return uart_resume_port(&tegra_uart_driver, u);
1870 }
1871 #endif
1872
1873 static const struct dev_pm_ops tegra_uart_pm_ops = {
1874         SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume)
1875 };
1876
1877 static struct platform_driver tegra_uart_platform_driver = {
1878         .probe          = tegra_uart_probe,
1879         .remove         = tegra_uart_remove,
1880         .driver         = {
1881                 .name   = "serial-tegra",
1882                 .of_match_table = tegra_uart_of_match,
1883                 .pm     = &tegra_uart_pm_ops,
1884         },
1885 };
1886
1887 static int __init tegra_uart_init(void)
1888 {
1889         int ret;
1890
1891         ret = uart_register_driver(&tegra_uart_driver);
1892         if (ret < 0) {
1893                 pr_err("Could not register %s driver\n",
1894                         tegra_uart_driver.driver_name);
1895                 return ret;
1896         }
1897
1898         ret = platform_driver_register(&tegra_uart_platform_driver);
1899         if (ret < 0) {
1900                 pr_err("Uart platform driver register failed, e = %d\n", ret);
1901                 uart_unregister_driver(&tegra_uart_driver);
1902                 return ret;
1903         }
1904         return 0;
1905 }
1906
1907 static void __exit tegra_uart_exit(void)
1908 {
1909         pr_info("Unloading tegra uart driver\n");
1910         platform_driver_unregister(&tegra_uart_platform_driver);
1911         uart_unregister_driver(&tegra_uart_driver);
1912 }
1913
1914 module_init(tegra_uart_init);
1915 module_exit(tegra_uart_exit);
1916
1917 MODULE_ALIAS("platform:serial-tegra");
1918 MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
1919 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1920 MODULE_LICENSE("GPL v2");