X-Git-Url: https://nv-tegra.nvidia.com/r/gitweb?p=linux-3.10.git;a=blobdiff_plain;f=include%2Fasm-ppc%2Felf.h;h=c25cc35e6ab5818702dbca5241c92a93bbad2a97;hp=2c056966efd34650ee5dfeb6f0d79c0516659bc2;hb=36d57ac4a818cb4aa3edbdf63ad2ebc31106f925;hpb=32605a18152b246df483fadc1c23854addde8755

diff --git a/include/asm-ppc/elf.h b/include/asm-ppc/elf.h
index 2c056966efd..c25cc35e6ab 100644
--- a/include/asm-ppc/elf.h
+++ b/include/asm-ppc/elf.h
@@ -7,6 +7,7 @@
 #include <asm/types.h>
 #include <asm/ptrace.h>
 #include <asm/cputable.h>
+#include <asm/auxvec.h>
 
 /* PowerPC relocations defined by the ABIs */
 #define R_PPC_NONE		0
@@ -122,16 +123,6 @@ extern int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpu);
 
 #define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
 
-/*
- * We need to put in some extra aux table entries to tell glibc what
- * the cache block size is, so it can use the dcbz instruction safely.
- */
-#define AT_DCACHEBSIZE		19
-#define AT_ICACHEBSIZE		20
-#define AT_UCACHEBSIZE		21
-/* A special ignored type value for PPC, for glibc compatibility.  */
-#define AT_IGNOREPPC		22
-
 extern int dcache_bsize;
 extern int icache_bsize;
 extern int ucache_bsize;