* code to do general bookkeeping (e.g. update jiffies, run
* bottom halves, etc.)
*/
+#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#define SB1250_HPT_NUM 3
#define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */
-#define SB1250_HPT_SHIFT ((sizeof(unsigned int)*8)-V_SCD_TIMER_WIDTH)
extern int sb1250_steal_irq(int irq);
-static unsigned int sb1250_hpt_read(void);
-static void sb1250_hpt_init(unsigned int);
-
-static unsigned int hpt_offset;
-
-void __init sb1250_hpt_setup(void)
+/*
+ * The general purpose timer ticks at 1 Mhz independent if
+ * the rest of the system
+ */
+static void sibyte_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *evt)
{
- int cpu = smp_processor_id();
+ unsigned int cpu = smp_processor_id();
+ void __iomem *timer_cfg, *timer_init;
+
+ timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
+ timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
- if (!cpu) {
- /* Setup hpt using timer #3 but do not enable irq for it */
- __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
- __raw_writeq(SB1250_HPT_VALUE,
- IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_INIT)));
+ switch(mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ __raw_writeq(0, timer_cfg);
+ __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init);
__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
- IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
-
- /*
- * we need to fill 32 bits, so just use the upper 23 bits and pretend
- * the timer is going 512Mhz instead of 1Mhz
- */
- mips_hpt_frequency = V_SCD_TIMER_FREQ << SB1250_HPT_SHIFT;
- mips_hpt_init = sb1250_hpt_init;
- mips_hpt_read = sb1250_hpt_read;
+ timer_cfg);
+ break;
+
+ case CLOCK_EVT_MODE_ONESHOT:
+ /* Stop the timer until we actually program a shot */
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ __raw_writeq(0, timer_cfg);
+ break;
+
+ case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
+ case CLOCK_EVT_MODE_RESUME:
+ ;
}
}
+static int
+sibyte_next_event(unsigned long delta, struct clock_event_device *evt)
+{
+ unsigned int cpu = smp_processor_id();
+ void __iomem *timer_cfg, *timer_init;
+
+ timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
+ timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
+
+ __raw_writeq(0, timer_cfg);
+ __raw_writeq(delta, timer_init);
+ __raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg);
+
+ return 0;
+}
-void sb1250_time_init(void)
+static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
{
- int cpu = smp_processor_id();
- int irq = K_INT_TIMER_0+cpu;
+ unsigned int cpu = smp_processor_id();
+ struct clock_event_device *cd = dev_id;
+
+ /* ACK interrupt */
+ ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
+ IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
+
+ cd->event_handler(cd);
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction sibyte_irqaction = {
+ .handler = sibyte_counter_handler,
+ .flags = IRQF_DISABLED | IRQF_PERCPU,
+ .name = "timer",
+};
+
+static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
+static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
+static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
+
+void __cpuinit sb1250_clockevent_init(void)
+{
+ unsigned int cpu = smp_processor_id();
+ unsigned int irq = K_INT_TIMER_0 + cpu;
+ struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu);
+ struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
+ unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
/* Only have 4 general purpose timers, and we use last one as hpt */
- if (cpu > 2) {
- BUG();
- }
+ BUG_ON(cpu > 2);
+
+ sprintf(name, "bcm1480-counter %d", cpu);
+ cd->name = name;
+ cd->features = CLOCK_EVT_FEAT_PERIODIC |
+ CLOCK_EVT_MODE_ONESHOT;
+ clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
+ cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd);
+ cd->min_delta_ns = clockevent_delta2ns(1, cd);
+ cd->rating = 200;
+ cd->irq = irq;
+ cd->cpumask = cpumask_of_cpu(cpu);
+ cd->set_next_event = sibyte_next_event;
+ cd->set_mode = sibyte_set_mode;
+ clockevents_register_device(cd);
sb1250_mask_irq(cpu, irq);
__raw_writeq(IMR_IP4_VAL,
IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
(irq << 3)));
-
- /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */
- /* Disable the timer and set up the count */
- __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
-#ifdef CONFIG_SIMULATION
- __raw_writeq((50000 / HZ) - 1,
- IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
-#else
- __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1,
- IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
-#endif
-
- /* Set the timer running */
- __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
- IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
+ cd->cpumask = cpumask_of_cpu(0);
sb1250_unmask_irq(cpu, irq);
sb1250_steal_irq(irq);
- /*
- * This interrupt is "special" in that it doesn't use the request_irq
- * way to hook the irq line. The timer interrupt is initialized early
- * enough to make this a major pain, and it's also firing enough to
- * warrant a bit of special case code. sb1250_timer_interrupt is
- * called directly from irq_handler.S when IP[4] is set during an
- * interrupt
- */
-}
-void sb1250_timer_interrupt(void)
-{
- int cpu = smp_processor_id();
- int irq = K_INT_TIMER_0 + cpu;
-
- /* ACK interrupt */
- ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
- IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
-
- if (cpu == 0) {
- /*
- * CPU 0 handles the global timer interrupt job
- */
- ll_timer_interrupt(irq);
- }
- else {
- /*
- * other CPUs should just do profiling and process accounting
- */
- ll_local_timer_interrupt(irq);
- }
+ action->handler = sibyte_counter_handler;
+ action->flags = IRQF_DISABLED | IRQF_PERCPU;
+ action->name = name;
+ action->dev_id = cd;
+ setup_irq(irq, &sibyte_irqaction);
}
/*
* The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
- * again. There's no easy way to set to a specific value so store init value
- * in hpt_offset and subtract each time.
- *
- * Note: Timer isn't full 32bits so shift it into the upper part making
- * it appear to run at a higher frequency.
+ * again.
*/
-static unsigned int sb1250_hpt_read(void)
+static cycle_t sb1250_hpt_read(void)
{
unsigned int count;
count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT))));
- count = (SB1250_HPT_VALUE - count) << SB1250_HPT_SHIFT;
+ return SB1250_HPT_VALUE - count;
+}
+
+struct clocksource bcm1250_clocksource = {
+ .name = "MIPS",
+ .rating = 200,
+ .read = sb1250_hpt_read,
+ .mask = CLOCKSOURCE_MASK(23),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+void __init sb1250_clocksource_init(void)
+{
+ struct clocksource *cs = &bcm1250_clocksource;
+
+ /* Setup hpt using timer #3 but do not enable irq for it */
+ __raw_writeq(0,
+ IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
+ R_SCD_TIMER_CFG)));
+ __raw_writeq(SB1250_HPT_VALUE,
+ IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
+ R_SCD_TIMER_INIT)));
+ __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
+ IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
+ R_SCD_TIMER_CFG)));
- return count - hpt_offset;
+ clocksource_set_clock(cs, V_SCD_TIMER_FREQ);
+ clocksource_register(cs);
}
-static void sb1250_hpt_init(unsigned int count)
+void __init plat_time_init(void)
{
- hpt_offset = count;
- return;
+ sb1250_clocksource_init();
+ sb1250_clockevent_init();
}
Code Review / linux-3.10.git / blobdiff