KVM: consolidate ioapic/ipi interrupt delivery logic
[linux-3.10.git] / virt / kvm / ioapic.c
1 /*
2  *  Copyright (C) 2001  MandrakeSoft S.A.
3  *
4  *    MandrakeSoft S.A.
5  *    43, rue d'Aboukir
6  *    75002 Paris - France
7  *    http://www.linux-mandrake.com/
8  *    http://www.mandrakesoft.com/
9  *
10  *  This library is free software; you can redistribute it and/or
11  *  modify it under the terms of the GNU Lesser General Public
12  *  License as published by the Free Software Foundation; either
13  *  version 2 of the License, or (at your option) any later version.
14  *
15  *  This library is distributed in the hope that it will be useful,
16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18  *  Lesser General Public License for more details.
19  *
20  *  You should have received a copy of the GNU Lesser General Public
21  *  License along with this library; if not, write to the Free Software
22  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
23  *
24  *  Yunhong Jiang <yunhong.jiang@intel.com>
25  *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
26  *  Based on Xen 3.1 code.
27  */
28
29 #include <linux/kvm_host.h>
30 #include <linux/kvm.h>
31 #include <linux/mm.h>
32 #include <linux/highmem.h>
33 #include <linux/smp.h>
34 #include <linux/hrtimer.h>
35 #include <linux/io.h>
36 #include <asm/processor.h>
37 #include <asm/page.h>
38 #include <asm/current.h>
39
40 #include "ioapic.h"
41 #include "lapic.h"
42 #include "irq.h"
43
44 #if 0
45 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
46 #else
47 #define ioapic_debug(fmt, arg...)
48 #endif
49 static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
50
51 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
52                                           unsigned long addr,
53                                           unsigned long length)
54 {
55         unsigned long result = 0;
56
57         switch (ioapic->ioregsel) {
58         case IOAPIC_REG_VERSION:
59                 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
60                           | (IOAPIC_VERSION_ID & 0xff));
61                 break;
62
63         case IOAPIC_REG_APIC_ID:
64         case IOAPIC_REG_ARB_ID:
65                 result = ((ioapic->id & 0xf) << 24);
66                 break;
67
68         default:
69                 {
70                         u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
71                         u64 redir_content;
72
73                         ASSERT(redir_index < IOAPIC_NUM_PINS);
74
75                         redir_content = ioapic->redirtbl[redir_index].bits;
76                         result = (ioapic->ioregsel & 0x1) ?
77                             (redir_content >> 32) & 0xffffffff :
78                             redir_content & 0xffffffff;
79                         break;
80                 }
81         }
82
83         return result;
84 }
85
86 static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
87 {
88         union kvm_ioapic_redirect_entry *pent;
89         int injected = -1;
90
91         pent = &ioapic->redirtbl[idx];
92
93         if (!pent->fields.mask) {
94                 injected = ioapic_deliver(ioapic, idx);
95                 if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
96                         pent->fields.remote_irr = 1;
97         }
98         if (!pent->fields.trig_mode)
99                 ioapic->irr &= ~(1 << idx);
100
101         return injected;
102 }
103
104 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
105 {
106         unsigned index;
107         bool mask_before, mask_after;
108
109         switch (ioapic->ioregsel) {
110         case IOAPIC_REG_VERSION:
111                 /* Writes are ignored. */
112                 break;
113
114         case IOAPIC_REG_APIC_ID:
115                 ioapic->id = (val >> 24) & 0xf;
116                 break;
117
118         case IOAPIC_REG_ARB_ID:
119                 break;
120
121         default:
122                 index = (ioapic->ioregsel - 0x10) >> 1;
123
124                 ioapic_debug("change redir index %x val %x\n", index, val);
125                 if (index >= IOAPIC_NUM_PINS)
126                         return;
127                 mask_before = ioapic->redirtbl[index].fields.mask;
128                 if (ioapic->ioregsel & 1) {
129                         ioapic->redirtbl[index].bits &= 0xffffffff;
130                         ioapic->redirtbl[index].bits |= (u64) val << 32;
131                 } else {
132                         ioapic->redirtbl[index].bits &= ~0xffffffffULL;
133                         ioapic->redirtbl[index].bits |= (u32) val;
134                         ioapic->redirtbl[index].fields.remote_irr = 0;
135                 }
136                 mask_after = ioapic->redirtbl[index].fields.mask;
137                 if (mask_before != mask_after)
138                         kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
139                 if (ioapic->irr & (1 << index))
140                         ioapic_service(ioapic, index);
141                 break;
142         }
143 }
144
145 int ioapic_deliver_entry(struct kvm *kvm, union kvm_ioapic_redirect_entry *e)
146 {
147         DECLARE_BITMAP(deliver_bitmask, KVM_MAX_VCPUS);
148         int i, r = -1;
149
150         kvm_get_intr_delivery_bitmask(kvm, NULL, e->fields.dest_id,
151                         e->fields.dest_mode,
152                         e->fields.delivery_mode == IOAPIC_LOWEST_PRIORITY,
153                         0, deliver_bitmask);
154
155         if (find_first_bit(deliver_bitmask, KVM_MAX_VCPUS) >= KVM_MAX_VCPUS) {
156                 ioapic_debug("no target on destination\n");
157                 return r;
158         }
159
160         while ((i = find_first_bit(deliver_bitmask, KVM_MAX_VCPUS))
161                         < KVM_MAX_VCPUS) {
162                 struct kvm_vcpu *vcpu = kvm->vcpus[i];
163                 __clear_bit(i, deliver_bitmask);
164                 if (vcpu) {
165                         if (r < 0)
166                                 r = 0;
167                         r += kvm_apic_set_irq(vcpu, e->fields.vector,
168                                         e->fields.delivery_mode,
169                                         e->fields.trig_mode);
170                 } else
171                         ioapic_debug("null destination vcpu: "
172                                      "mask=%x vector=%x delivery_mode=%x\n",
173                                      e->fields.deliver_bitmask,
174                                      e->fields.vector, e->fields.delivery_mode);
175         }
176         return r;
177 }
178
179 static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
180 {
181         union kvm_ioapic_redirect_entry entry = ioapic->redirtbl[irq];
182
183         ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
184                      "vector=%x trig_mode=%x\n",
185                      entry.fields.dest, entry.fields.dest_mode,
186                      entry.fields.delivery_mode, entry.fields.vector,
187                      entry.fields.trig_mode);
188
189 #ifdef CONFIG_X86
190         /* Always delivery PIT interrupt to vcpu 0 */
191         if (irq == 0) {
192                 entry.fields.dest_mode = 0; /* Physical mode. */
193                 entry.fields.dest_id = ioapic->kvm->vcpus[0]->vcpu_id;
194         }
195 #endif
196         return ioapic_deliver_entry(ioapic->kvm, &entry);
197 }
198
199 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
200 {
201         u32 old_irr = ioapic->irr;
202         u32 mask = 1 << irq;
203         union kvm_ioapic_redirect_entry entry;
204         int ret = 1;
205
206         if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
207                 entry = ioapic->redirtbl[irq];
208                 level ^= entry.fields.polarity;
209                 if (!level)
210                         ioapic->irr &= ~mask;
211                 else {
212                         ioapic->irr |= mask;
213                         if ((!entry.fields.trig_mode && old_irr != ioapic->irr)
214                             || !entry.fields.remote_irr)
215                                 ret = ioapic_service(ioapic, irq);
216                 }
217         }
218         return ret;
219 }
220
221 static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
222                                     int trigger_mode)
223 {
224         union kvm_ioapic_redirect_entry *ent;
225
226         ent = &ioapic->redirtbl[pin];
227
228         kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
229
230         if (trigger_mode == IOAPIC_LEVEL_TRIG) {
231                 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
232                 ent->fields.remote_irr = 0;
233                 if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
234                         ioapic_service(ioapic, pin);
235         }
236 }
237
238 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
239 {
240         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
241         int i;
242
243         for (i = 0; i < IOAPIC_NUM_PINS; i++)
244                 if (ioapic->redirtbl[i].fields.vector == vector)
245                         __kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
246 }
247
248 static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr,
249                            int len, int is_write)
250 {
251         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
252
253         return ((addr >= ioapic->base_address &&
254                  (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
255 }
256
257 static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
258                              void *val)
259 {
260         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
261         u32 result;
262
263         ioapic_debug("addr %lx\n", (unsigned long)addr);
264         ASSERT(!(addr & 0xf));  /* check alignment */
265
266         addr &= 0xff;
267         switch (addr) {
268         case IOAPIC_REG_SELECT:
269                 result = ioapic->ioregsel;
270                 break;
271
272         case IOAPIC_REG_WINDOW:
273                 result = ioapic_read_indirect(ioapic, addr, len);
274                 break;
275
276         default:
277                 result = 0;
278                 break;
279         }
280         switch (len) {
281         case 8:
282                 *(u64 *) val = result;
283                 break;
284         case 1:
285         case 2:
286         case 4:
287                 memcpy(val, (char *)&result, len);
288                 break;
289         default:
290                 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
291         }
292 }
293
294 static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
295                               const void *val)
296 {
297         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
298         u32 data;
299
300         ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
301                      (void*)addr, len, val);
302         ASSERT(!(addr & 0xf));  /* check alignment */
303         if (len == 4 || len == 8)
304                 data = *(u32 *) val;
305         else {
306                 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
307                 return;
308         }
309
310         addr &= 0xff;
311         switch (addr) {
312         case IOAPIC_REG_SELECT:
313                 ioapic->ioregsel = data;
314                 break;
315
316         case IOAPIC_REG_WINDOW:
317                 ioapic_write_indirect(ioapic, data);
318                 break;
319 #ifdef  CONFIG_IA64
320         case IOAPIC_REG_EOI:
321                 kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
322                 break;
323 #endif
324
325         default:
326                 break;
327         }
328 }
329
330 void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
331 {
332         int i;
333
334         for (i = 0; i < IOAPIC_NUM_PINS; i++)
335                 ioapic->redirtbl[i].fields.mask = 1;
336         ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
337         ioapic->ioregsel = 0;
338         ioapic->irr = 0;
339         ioapic->id = 0;
340 }
341
342 int kvm_ioapic_init(struct kvm *kvm)
343 {
344         struct kvm_ioapic *ioapic;
345
346         ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
347         if (!ioapic)
348                 return -ENOMEM;
349         kvm->arch.vioapic = ioapic;
350         kvm_ioapic_reset(ioapic);
351         ioapic->dev.read = ioapic_mmio_read;
352         ioapic->dev.write = ioapic_mmio_write;
353         ioapic->dev.in_range = ioapic_in_range;
354         ioapic->dev.private = ioapic;
355         ioapic->kvm = kvm;
356         kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
357         return 0;
358 }
359