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1 /*
2  * include/asm-mips/vr41xx/vr41xx.h
3  *
4  * Include file for NEC VR4100 series.
5  *
6  * Copyright (C) 1999 Michael Klar
7  * Copyright (C) 2001, 2002 Paul Mundt
8  * Copyright (C) 2002 MontaVista Software, Inc.
9  * Copyright (C) 2002 TimeSys Corp.
10  * Copyright (C) 2003-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
11  *
12  * This program is free software; you can redistribute it and/or modify it
13  * under the terms of the GNU General Public License as published by the
14  * Free Software Foundation; either version 2 of the License, or (at your
15  * option) any later version.
16  */
17 #ifndef __NEC_VR41XX_H
18 #define __NEC_VR41XX_H
19
20 #include <linux/interrupt.h>
21
22 /*
23  * CPU Revision
24  */
25 /* VR4122 0x00000c70-0x00000c72 */
26 #define PRID_VR4122_REV1_0      0x00000c70
27 #define PRID_VR4122_REV2_0      0x00000c70
28 #define PRID_VR4122_REV2_1      0x00000c70
29 #define PRID_VR4122_REV3_0      0x00000c71
30 #define PRID_VR4122_REV3_1      0x00000c72
31
32 /* VR4181A 0x00000c73-0x00000c7f */
33 #define PRID_VR4181A_REV1_0     0x00000c73
34 #define PRID_VR4181A_REV1_1     0x00000c74
35
36 /* VR4131 0x00000c80-0x00000c83 */
37 #define PRID_VR4131_REV1_2      0x00000c80
38 #define PRID_VR4131_REV2_0      0x00000c81
39 #define PRID_VR4131_REV2_1      0x00000c82
40 #define PRID_VR4131_REV2_2      0x00000c83
41
42 /* VR4133 0x00000c84- */
43 #define PRID_VR4133             0x00000c84
44
45 /*
46  * Bus Control Uint
47  */
48 extern unsigned long vr41xx_calculate_clock_frequency(void);
49 extern unsigned long vr41xx_get_vtclock_frequency(void);
50 extern unsigned long vr41xx_get_tclock_frequency(void);
51
52 /*
53  * Clock Mask Unit
54  */
55 typedef enum {
56         PIU_CLOCK,
57         SIU_CLOCK,
58         AIU_CLOCK,
59         KIU_CLOCK,
60         FIR_CLOCK,
61         DSIU_CLOCK,
62         CSI_CLOCK,
63         PCIU_CLOCK,
64         HSP_CLOCK,
65         PCI_CLOCK,
66         CEU_CLOCK,
67         ETHER0_CLOCK,
68         ETHER1_CLOCK
69 } vr41xx_clock_t;
70
71 extern void vr41xx_supply_clock(vr41xx_clock_t clock);
72 extern void vr41xx_mask_clock(vr41xx_clock_t clock);
73
74 /*
75  * Interrupt Control Unit
76  */
77 /* CPU core Interrupt Numbers */
78 #define MIPS_CPU_IRQ_BASE       0
79 #define MIPS_CPU_IRQ(x)         (MIPS_CPU_IRQ_BASE + (x))
80 #define MIPS_SOFTINT0_IRQ       MIPS_CPU_IRQ(0)
81 #define MIPS_SOFTINT1_IRQ       MIPS_CPU_IRQ(1)
82 #define INT0_CASCADE_IRQ        MIPS_CPU_IRQ(2)
83 #define INT1_CASCADE_IRQ        MIPS_CPU_IRQ(3)
84 #define INT2_CASCADE_IRQ        MIPS_CPU_IRQ(4)
85 #define INT3_CASCADE_IRQ        MIPS_CPU_IRQ(5)
86 #define INT4_CASCADE_IRQ        MIPS_CPU_IRQ(6)
87 #define TIMER_IRQ               MIPS_CPU_IRQ(7)
88
89 /* SYINT1 Interrupt Numbers */
90 #define SYSINT1_IRQ_BASE        8
91 #define SYSINT1_IRQ(x)          (SYSINT1_IRQ_BASE + (x))
92 #define BATTRY_IRQ              SYSINT1_IRQ(0)
93 #define POWER_IRQ               SYSINT1_IRQ(1)
94 #define RTCLONG1_IRQ            SYSINT1_IRQ(2)
95 #define ELAPSEDTIME_IRQ         SYSINT1_IRQ(3)
96 /* RFU */
97 #define PIU_IRQ                 SYSINT1_IRQ(5)
98 #define AIU_IRQ                 SYSINT1_IRQ(6)
99 #define KIU_IRQ                 SYSINT1_IRQ(7)
100 #define GIUINT_CASCADE_IRQ      SYSINT1_IRQ(8)
101 #define SIU_IRQ                 SYSINT1_IRQ(9)
102 #define BUSERR_IRQ              SYSINT1_IRQ(10)
103 #define SOFTINT_IRQ             SYSINT1_IRQ(11)
104 #define CLKRUN_IRQ              SYSINT1_IRQ(12)
105 #define DOZEPIU_IRQ             SYSINT1_IRQ(13)
106 #define SYSINT1_IRQ_LAST        DOZEPIU_IRQ
107
108 /* SYSINT2 Interrupt Numbers */
109 #define SYSINT2_IRQ_BASE        24
110 #define SYSINT2_IRQ(x)          (SYSINT2_IRQ_BASE + (x))
111 #define RTCLONG2_IRQ            SYSINT2_IRQ(0)
112 #define LED_IRQ                 SYSINT2_IRQ(1)
113 #define HSP_IRQ                 SYSINT2_IRQ(2)
114 #define TCLOCK_IRQ              SYSINT2_IRQ(3)
115 #define FIR_IRQ                 SYSINT2_IRQ(4)
116 #define CEU_IRQ                 SYSINT2_IRQ(4)  /* same number as FIR_IRQ */
117 #define DSIU_IRQ                SYSINT2_IRQ(5)
118 #define PCI_IRQ                 SYSINT2_IRQ(6)
119 #define SCU_IRQ                 SYSINT2_IRQ(7)
120 #define CSI_IRQ                 SYSINT2_IRQ(8)
121 #define BCU_IRQ                 SYSINT2_IRQ(9)
122 #define ETHERNET_IRQ            SYSINT2_IRQ(10)
123 #define SYSINT2_IRQ_LAST        ETHERNET_IRQ
124
125 /* GIU Interrupt Numbers */
126 #define GIU_IRQ_BASE            40
127 #define GIU_IRQ(x)              (GIU_IRQ_BASE + (x))    /* IRQ 40-71 */
128 #define GIU_IRQ_LAST            GIU_IRQ(31)
129 #define GIU_IRQ_TO_PIN(x)       ((x) - GIU_IRQ_BASE)    /* Pin 0-31 */
130
131 extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
132 extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq));
133
134 #define PIUINT_COMMAND          0x0040
135 #define PIUINT_DATA             0x0020
136 #define PIUINT_PAGE1            0x0010
137 #define PIUINT_PAGE0            0x0008
138 #define PIUINT_DATALOST         0x0004
139 #define PIUINT_STATUSCHANGE     0x0001
140
141 extern void vr41xx_enable_piuint(uint16_t mask);
142 extern void vr41xx_disable_piuint(uint16_t mask);
143
144 #define AIUINT_INPUT_DMAEND     0x0800
145 #define AIUINT_INPUT_DMAHALT    0x0400
146 #define AIUINT_INPUT_DATALOST   0x0200
147 #define AIUINT_INPUT_DATA       0x0100
148 #define AIUINT_OUTPUT_DMAEND    0x0008
149 #define AIUINT_OUTPUT_DMAHALT   0x0004
150 #define AIUINT_OUTPUT_NODATA    0x0002
151
152 extern void vr41xx_enable_aiuint(uint16_t mask);
153 extern void vr41xx_disable_aiuint(uint16_t mask);
154
155 #define KIUINT_DATALOST         0x0004
156 #define KIUINT_DATAREADY        0x0002
157 #define KIUINT_SCAN             0x0001
158
159 extern void vr41xx_enable_kiuint(uint16_t mask);
160 extern void vr41xx_disable_kiuint(uint16_t mask);
161
162 #define DSIUINT_CTS             0x0800
163 #define DSIUINT_RXERR           0x0400
164 #define DSIUINT_RX              0x0200
165 #define DSIUINT_TX              0x0100
166 #define DSIUINT_ALL             0x0f00
167
168 extern void vr41xx_enable_dsiuint(uint16_t mask);
169 extern void vr41xx_disable_dsiuint(uint16_t mask);
170
171 #define FIRINT_UNIT             0x0010
172 #define FIRINT_RX_DMAEND        0x0008
173 #define FIRINT_RX_DMAHALT       0x0004
174 #define FIRINT_TX_DMAEND        0x0002
175 #define FIRINT_TX_DMAHALT       0x0001
176
177 extern void vr41xx_enable_firint(uint16_t mask);
178 extern void vr41xx_disable_firint(uint16_t mask);
179
180 extern void vr41xx_enable_pciint(void);
181 extern void vr41xx_disable_pciint(void);
182
183 extern void vr41xx_enable_scuint(void);
184 extern void vr41xx_disable_scuint(void);
185
186 #define CSIINT_TX_DMAEND        0x0040
187 #define CSIINT_TX_DMAHALT       0x0020
188 #define CSIINT_TX_DATA          0x0010
189 #define CSIINT_TX_FIFOEMPTY     0x0008
190 #define CSIINT_RX_DMAEND        0x0004
191 #define CSIINT_RX_DMAHALT       0x0002
192 #define CSIINT_RX_FIFOEMPTY     0x0001
193
194 extern void vr41xx_enable_csiint(uint16_t mask);
195 extern void vr41xx_disable_csiint(uint16_t mask);
196
197 extern void vr41xx_enable_bcuint(void);
198 extern void vr41xx_disable_bcuint(void);
199
200 /*
201  * Power Management Unit
202  */
203
204 /*
205  * RTC
206  */
207 extern void vr41xx_set_rtclong1_cycle(uint32_t cycles);
208 extern uint32_t vr41xx_read_rtclong1_counter(void);
209
210 extern void vr41xx_set_rtclong2_cycle(uint32_t cycles);
211 extern uint32_t vr41xx_read_rtclong2_counter(void);
212
213 extern void vr41xx_set_tclock_cycle(uint32_t cycles);
214 extern uint32_t vr41xx_read_tclock_counter(void);
215
216 /*
217  * General-Purpose I/O Unit
218  */
219 enum {
220         TRIGGER_LEVEL,
221         TRIGGER_EDGE,
222         TRIGGER_EDGE_FALLING,
223         TRIGGER_EDGE_RISING
224 };
225
226 enum {
227         SIGNAL_THROUGH,
228         SIGNAL_HOLD
229 };
230
231 extern void vr41xx_set_irq_trigger(int pin, int trigger, int hold);
232
233 enum {
234         LEVEL_LOW,
235         LEVEL_HIGH
236 };
237
238 extern void vr41xx_set_irq_level(int pin, int level);
239
240 enum {
241         PIO_INPUT,
242         PIO_OUTPUT
243 };
244
245 enum {
246         DATA_LOW,
247         DATA_HIGH
248 };
249
250 /*
251  * PCI Control Unit
252  */
253 #define PCI_MASTER_ADDRESS_MASK 0x7fffffffU
254
255 struct pci_master_address_conversion {
256         uint32_t bus_base_address;
257         uint32_t address_mask;
258         uint32_t pci_base_address;
259 };
260
261 struct pci_target_address_conversion {
262         uint32_t address_mask;
263         uint32_t bus_base_address;
264 };
265
266 typedef enum {
267         CANNOT_LOCK_FROM_DEVICE,
268         CAN_LOCK_FROM_DEVICE,
269 } pci_exclusive_access_t;
270
271 struct pci_mailbox_address {
272         uint32_t base_address;
273 };
274
275 struct pci_target_address_window {
276         uint32_t base_address;
277 };
278
279 typedef enum {
280         PCI_ARBITRATION_MODE_FAIR,
281         PCI_ARBITRATION_MODE_ALTERNATE_0,
282         PCI_ARBITRATION_MODE_ALTERNATE_B,
283 } pci_arbiter_priority_control_t;
284
285 typedef enum {
286         PCI_TAKE_AWAY_GNT_DISABLE,
287         PCI_TAKE_AWAY_GNT_ENABLE,
288 } pci_take_away_gnt_mode_t;
289
290 struct pci_controller_unit_setup {
291         struct pci_master_address_conversion *master_memory1;
292         struct pci_master_address_conversion *master_memory2;
293
294         struct pci_target_address_conversion *target_memory1;
295         struct pci_target_address_conversion *target_memory2;
296
297         struct pci_master_address_conversion *master_io;
298
299         pci_exclusive_access_t exclusive_access;
300
301         uint32_t pci_clock_max;
302         uint8_t wait_time_limit_from_irdy_to_trdy;      /* Only VR4122 is supported */
303
304         struct pci_mailbox_address *mailbox;
305         struct pci_target_address_window *target_window1;
306         struct pci_target_address_window *target_window2;
307
308         uint8_t master_latency_timer;
309         uint8_t retry_limit;
310
311         pci_arbiter_priority_control_t arbiter_priority_control;
312         pci_take_away_gnt_mode_t take_away_gnt_mode;
313
314         struct resource *mem_resource;
315         struct resource *io_resource;
316 };
317
318 extern void vr41xx_pciu_setup(struct pci_controller_unit_setup *setup);
319
320 #endif /* __NEC_VR41XX_H */