]> nv-tegra.nvidia Code Review - linux-3.10.git/blob - drivers/scsi/FlashPoint.c
[SCSI] drivers/scsi/FlashPoint.c: cleanups
[linux-3.10.git] / drivers / scsi / FlashPoint.c
1 /*
2
3   FlashPoint.c -- FlashPoint SCCB Manager for Linux
4
5   This file contains the FlashPoint SCCB Manager from BusLogic's FlashPoint
6   Driver Developer's Kit, with minor modifications by Leonard N. Zubkoff for
7   Linux compatibility.  It was provided by BusLogic in the form of 16 separate
8   source files, which would have unnecessarily cluttered the scsi directory, so
9   the individual files have been combined into this single file.
10
11   Copyright 1995-1996 by Mylex Corporation.  All Rights Reserved
12
13   This file is available under both the GNU General Public License
14   and a BSD-style copyright; see LICENSE.FlashPoint for details.
15
16 */
17
18
19 #include <linux/config.h>
20
21
22 #ifndef CONFIG_SCSI_OMIT_FLASHPOINT
23
24
25 #define MAX_CARDS       8
26 #undef BUSTYPE_PCI
27
28
29 #define OS_InPortByte(port)             inb(port)
30 #define OS_InPortWord(port)             inw(port)
31 #define OS_InPortLong(port)             inl(port)
32 #define OS_OutPortByte(port, value)     outb(value, port)
33 #define OS_OutPortWord(port, value)     outw(value, port)
34 #define OS_OutPortLong(port, value)     outl(value, port)
35
36
37 /*
38   Define name replacements for compatibility with the Linux BusLogic Driver.
39 */
40
41 #define SccbMgr_sense_adapter           FlashPoint_ProbeHostAdapter
42 #define SccbMgr_config_adapter          FlashPoint_HardwareResetHostAdapter
43 #define SccbMgr_unload_card             FlashPoint_ReleaseHostAdapter
44 #define SccbMgr_start_sccb              FlashPoint_StartCCB
45 #define SccbMgr_abort_sccb              FlashPoint_AbortCCB
46 #define SccbMgr_my_int                  FlashPoint_InterruptPending
47 #define SccbMgr_isr                     FlashPoint_HandleInterrupt
48
49
50 #define MAX_CDBLEN  12
51
52 #define SCAM_LEV_2      1
53
54 #define CRCMASK 0xA001
55
56 #define     BL_VENDOR_ID      0x104B
57 #define     FP_DEVICE_ID      0x8130
58 #define     MM_DEVICE_ID      0x1040
59
60
61 #define FAILURE         0xFFFFFFFFL
62
63
64 typedef unsigned char   UCHAR;
65 typedef unsigned short  USHORT;
66 typedef unsigned int    UINT;
67 typedef unsigned long   ULONG;
68 typedef unsigned char * PUCHAR;
69 typedef unsigned short* PUSHORT;
70 typedef unsigned long * PULONG;
71 typedef void *          PVOID;
72
73
74 typedef unsigned char           * uchar_ptr;
75 typedef unsigned short          * ushort_ptr;
76 typedef unsigned long           * ulong_ptr;
77
78
79 #define s08bits char
80 #define s16bits         short
81 #define s32bits long
82
83 #define u08bits unsigned s08bits
84 #define u16bits unsigned s16bits
85 #define u32bits unsigned s32bits
86
87 typedef u08bits         * pu08bits;
88 typedef u16bits         * pu16bits;
89 typedef u32bits         * pu32bits;
90
91
92 #define BIT(x)          ((UCHAR)(1<<(x)))    /* single-bit mask in bit position x */
93 #define BITW(x)          ((USHORT)(1<<(x)))  /* single-bit mask in bit position x */
94
95
96
97
98 typedef struct _SCCB *PSCCB;
99 typedef void (*CALL_BK_FN)(PSCCB);
100
101
102 typedef struct SCCBMgr_info {
103    ULONG    si_baseaddr;
104    UCHAR    si_present;
105    UCHAR    si_intvect;
106    UCHAR    si_id;
107    UCHAR    si_lun;
108    USHORT   si_fw_revision;
109    USHORT   si_per_targ_init_sync;
110    USHORT   si_per_targ_fast_nego;
111    USHORT   si_per_targ_ultra_nego;
112    USHORT   si_per_targ_no_disc;
113    USHORT   si_per_targ_wide_nego;
114    USHORT   si_flags;
115    UCHAR    si_card_family;
116    UCHAR    si_bustype;
117    UCHAR    si_card_model[3];
118    UCHAR    si_relative_cardnum;
119    UCHAR    si_reserved[4];
120    ULONG    si_OS_reserved;
121    UCHAR    si_XlatInfo[4];
122    ULONG    si_reserved2[5];
123    ULONG    si_secondary_range;
124 } SCCBMGR_INFO;
125
126 typedef SCCBMGR_INFO *      PSCCBMGR_INFO;
127
128
129 #define SCSI_PARITY_ENA           0x0001
130 #define LOW_BYTE_TERM             0x0010
131 #define HIGH_BYTE_TERM            0x0020
132 #define BUSTYPE_PCI       0x3
133
134 #define SUPPORT_16TAR_32LUN       0x0002
135 #define SOFT_RESET                0x0004
136 #define EXTENDED_TRANSLATION      0x0008
137 #define POST_ALL_UNDERRRUNS       0x0040
138 #define FLAG_SCAM_ENABLED         0x0080
139 #define FLAG_SCAM_LEVEL2          0x0100
140
141
142
143
144 #define HARPOON_FAMILY        0x02
145
146
147 #define ISA_BUS_CARD          0x01
148 #define EISA_BUS_CARD         0x02
149 #define PCI_BUS_CARD          0x03
150 #define VESA_BUS_CARD         0x04
151
152 /* SCCB struc used for both SCCB and UCB manager compiles! 
153  * The UCB Manager treats the SCCB as it's 'native hardware structure' 
154  */
155
156
157 #pragma pack(1)
158 typedef struct _SCCB {
159    UCHAR OperationCode;
160    UCHAR ControlByte;
161    UCHAR CdbLength;
162    UCHAR RequestSenseLength;
163    ULONG DataLength;
164    ULONG DataPointer;
165    UCHAR CcbRes[2];
166    UCHAR HostStatus;
167    UCHAR TargetStatus;
168    UCHAR TargID;
169    UCHAR Lun;
170    UCHAR Cdb[12];
171    UCHAR CcbRes1;
172    UCHAR Reserved1;
173    ULONG Reserved2;
174    ULONG SensePointer;
175
176
177    CALL_BK_FN SccbCallback;                  /* VOID (*SccbCallback)(); */
178    ULONG  SccbIOPort;                        /* Identifies board base port */
179    UCHAR  SccbStatus;
180    UCHAR  SCCBRes2;
181    USHORT SccbOSFlags;
182
183
184    ULONG   Sccb_XferCnt;            /* actual transfer count */
185    ULONG   Sccb_ATC;
186    ULONG   SccbVirtDataPtr;         /* virtual addr for OS/2 */
187    ULONG   Sccb_res1;
188    USHORT  Sccb_MGRFlags;
189    USHORT  Sccb_sgseg;
190    UCHAR   Sccb_scsimsg;            /* identify msg for selection */
191    UCHAR   Sccb_tag;
192    UCHAR   Sccb_scsistat;
193    UCHAR   Sccb_idmsg;              /* image of last msg in */
194    PSCCB   Sccb_forwardlink;
195    PSCCB   Sccb_backlink;
196    ULONG   Sccb_savedATC;
197    UCHAR   Save_Cdb[6];
198    UCHAR   Save_CdbLen;
199    UCHAR   Sccb_XferState;
200    ULONG   Sccb_SGoffset;
201    } SCCB;
202
203 #define SCCB_SIZE sizeof(SCCB)
204
205 #pragma pack()
206
207
208
209 #define SCSI_INITIATOR_COMMAND    0x00
210 #define TARGET_MODE_COMMAND       0x01
211 #define SCATTER_GATHER_COMMAND    0x02
212 #define RESIDUAL_COMMAND          0x03
213 #define RESIDUAL_SG_COMMAND       0x04
214 #define RESET_COMMAND             0x81
215
216
217 #define F_USE_CMD_Q              0x20     /*Inidcates TAGGED command. */
218 #define TAG_TYPE_MASK            0xC0     /*Type of tag msg to send. */
219 #define TAG_Q_MASK               0xE0
220 #define SCCB_DATA_XFER_OUT       0x10     /* Write */
221 #define SCCB_DATA_XFER_IN        0x08     /* Read */
222
223
224 #define FOURTEEN_BYTES           0x00     /* Request Sense Buffer size */
225 #define NO_AUTO_REQUEST_SENSE    0x01     /* No Request Sense Buffer */
226
227
228 #define BUS_FREE_ST     0       
229 #define SELECT_ST       1
230 #define SELECT_BDR_ST   2     /* Select w\ Bus Device Reset */
231 #define SELECT_SN_ST    3     /* Select w\ Sync Nego */
232 #define SELECT_WN_ST    4     /* Select w\ Wide Data Nego */
233 #define SELECT_Q_ST     5     /* Select w\ Tagged Q'ing */
234 #define COMMAND_ST      6
235 #define DATA_OUT_ST     7
236 #define DATA_IN_ST      8
237 #define DISCONNECT_ST   9
238 #define STATUS_ST       10
239 #define ABORT_ST        11
240 #define MESSAGE_ST      12
241
242
243 #define F_HOST_XFER_DIR                0x01
244 #define F_ALL_XFERRED                  0x02
245 #define F_SG_XFER                      0x04
246 #define F_AUTO_SENSE                   0x08
247 #define F_ODD_BALL_CNT                 0x10
248 #define F_NO_DATA_YET                  0x80
249
250
251 #define F_STATUSLOADED                 0x01
252 #define F_MSGLOADED                    0x02
253 #define F_DEV_SELECTED                 0x04
254
255
256 #define SCCB_COMPLETE               0x00  /* SCCB completed without error */
257 #define SCCB_DATA_UNDER_RUN         0x0C
258 #define SCCB_SELECTION_TIMEOUT      0x11  /* Set SCSI selection timed out */
259 #define SCCB_DATA_OVER_RUN          0x12
260 #define SCCB_UNEXPECTED_BUS_FREE    0x13  /* Target dropped SCSI BSY */
261 #define SCCB_PHASE_SEQUENCE_FAIL    0x14  /* Target bus phase sequence failure */
262
263 #define SCCB_INVALID_OP_CODE        0x16  /* SCCB invalid operation code */
264 #define SCCB_INVALID_SCCB           0x1A  /* Invalid SCCB - bad parameter */
265 #define SCCB_GROSS_FW_ERR           0x27  /* Major problem! */
266 #define SCCB_BM_ERR                 0x30  /* BusMaster error. */
267 #define SCCB_PARITY_ERR             0x34  /* SCSI parity error */
268
269
270
271 #define SCCB_INVALID_DIRECTION      0x18  /* Invalid target direction */
272 #define SCCB_DUPLICATE_SCCB         0x19  /* Duplicate SCCB */
273 #define SCCB_SCSI_RST               0x35  /* SCSI RESET detected. */
274
275
276 #define SCCB_IN_PROCESS            0x00
277 #define SCCB_SUCCESS               0x01
278 #define SCCB_ABORT                 0x02
279 #define SCCB_NOT_FOUND             0x03
280 #define SCCB_ERROR                 0x04
281 #define SCCB_INVALID               0x05
282
283 #define SCCB_SIZE sizeof(SCCB)
284
285
286 #define  ORION_FW_REV      3110
287
288 #define HARP_REVD    1
289
290
291 #define QUEUE_DEPTH     254+1            /*1 for Normal disconnect 32 for Q'ing. */
292
293 #define MAX_MB_CARDS    4                                       /* Max. no of cards suppoerted on Mother Board */
294
295 #define WIDE_SCSI       1
296
297 #define MAX_SCSI_TAR    16
298 #define MAX_LUN         32
299 #define LUN_MASK                        0x1f
300
301 #if defined(HARP_REVA)
302 #define SG_BUF_CNT      15             /*Number of prefetched elements. */
303 #else
304 #define SG_BUF_CNT      16             /*Number of prefetched elements. */
305 #endif
306
307 #define SG_ELEMENT_SIZE 8              /*Eight byte per element. */
308 #define SG_LOCAL_MASK   0x00000000L
309 #define SG_ELEMENT_MASK 0xFFFFFFFFL
310
311
312 #define RD_HARPOON(ioport)          OS_InPortByte((u32bits)ioport)
313 #define RDW_HARPOON(ioport)         OS_InPortWord((u32bits)ioport)
314 #define RD_HARP32(ioport,offset,data) (data = OS_InPortLong((u32bits)(ioport + offset)))
315 #define WR_HARPOON(ioport,val)      OS_OutPortByte((u32bits)ioport,(u08bits) val)
316 #define WRW_HARPOON(ioport,val)       OS_OutPortWord((u32bits)ioport,(u16bits)val)
317 #define WR_HARP32(ioport,offset,data)  OS_OutPortLong((u32bits)(ioport + offset), data)
318
319
320 #define  TAR_SYNC_MASK     (BIT(7)+BIT(6))
321 #define  SYNC_UNKNOWN      0x00
322 #define  SYNC_TRYING               BIT(6)
323 #define  SYNC_SUPPORTED    (BIT(7)+BIT(6))
324
325 #define  TAR_WIDE_MASK     (BIT(5)+BIT(4))
326 #define  WIDE_DISABLED     0x00
327 #define  WIDE_ENABLED              BIT(4)
328 #define  WIDE_NEGOCIATED   BIT(5)
329
330 #define  TAR_TAG_Q_MASK    (BIT(3)+BIT(2))
331 #define  TAG_Q_UNKNOWN     0x00
332 #define  TAG_Q_TRYING              BIT(2)
333 #define  TAG_Q_REJECT      BIT(3)
334 #define  TAG_Q_SUPPORTED   (BIT(3)+BIT(2))
335
336 #define  TAR_ALLOW_DISC    BIT(0)
337
338
339 #define  EE_SYNC_MASK      (BIT(0)+BIT(1))
340 #define  EE_SYNC_ASYNC     0x00
341 #define  EE_SYNC_5MB       BIT(0)
342 #define  EE_SYNC_10MB      BIT(1)
343 #define  EE_SYNC_20MB      (BIT(0)+BIT(1))
344
345 #define  EE_ALLOW_DISC     BIT(6)
346 #define  EE_WIDE_SCSI      BIT(7)
347
348
349 typedef struct SCCBMgr_tar_info *PSCCBMgr_tar_info;
350
351
352 typedef struct SCCBMgr_tar_info {
353
354    PSCCB    TarSelQ_Head;
355    PSCCB    TarSelQ_Tail;
356    UCHAR    TarLUN_CA;        /*Contingent Allgiance */
357    UCHAR    TarTagQ_Cnt;
358    UCHAR    TarSelQ_Cnt;
359    UCHAR    TarStatus;
360    UCHAR    TarEEValue;
361    UCHAR        TarSyncCtrl;
362    UCHAR        TarReserved[2];                 /* for alignment */ 
363    UCHAR        LunDiscQ_Idx[MAX_LUN];
364    UCHAR    TarLUNBusy[MAX_LUN];
365 } SCCBMGR_TAR_INFO;
366
367 typedef struct NVRAMInfo {
368         UCHAR           niModel;                                                                /* Model No. of card */
369         UCHAR           niCardNo;                                                       /* Card no. */
370         ULONG           niBaseAddr;                                                     /* Port Address of card */
371         UCHAR           niSysConf;                                                      /* Adapter Configuration byte - Byte 16 of eeprom map */
372         UCHAR           niScsiConf;                                                     /* SCSI Configuration byte - Byte 17 of eeprom map */
373         UCHAR           niScamConf;                                                     /* SCAM Configuration byte - Byte 20 of eeprom map */
374         UCHAR           niAdapId;                                                       /* Host Adapter ID - Byte 24 of eerpom map */
375         UCHAR           niSyncTbl[MAX_SCSI_TAR / 2];    /* Sync/Wide byte of targets */
376         UCHAR           niScamTbl[MAX_SCSI_TAR][4];     /* Compressed Scam name string of Targets */
377 }NVRAMINFO;
378
379 typedef NVRAMINFO *PNVRamInfo;
380
381 #define MODEL_LT                1
382 #define MODEL_DL                2
383 #define MODEL_LW                3
384 #define MODEL_DW                4
385
386
387 typedef struct SCCBcard {
388    PSCCB currentSCCB;
389    PSCCBMGR_INFO cardInfo;
390
391    ULONG ioPort;
392
393    USHORT cmdCounter;
394    UCHAR  discQCount;
395    UCHAR  tagQ_Lst; 
396    UCHAR cardIndex;
397    UCHAR scanIndex;
398    UCHAR globalFlags;
399    UCHAR ourId;
400    PNVRamInfo pNvRamInfo;
401    PSCCB discQ_Tbl[QUEUE_DEPTH]; 
402       
403 }SCCBCARD;
404
405 typedef struct SCCBcard *PSCCBcard;
406
407
408 #define F_TAG_STARTED           0x01
409 #define F_CONLUN_IO                     0x02
410 #define F_DO_RENEGO                     0x04
411 #define F_NO_FILTER                     0x08
412 #define F_GREEN_PC                      0x10
413 #define F_HOST_XFER_ACT         0x20
414 #define F_NEW_SCCB_CMD          0x40
415 #define F_UPDATE_EEPROM         0x80
416
417
418 #define  ID_STRING_LENGTH  32
419 #define  TYPE_CODE0        0x63           /*Level2 Mstr (bits 7-6),  */
420
421 #define  TYPE_CODE1        00             /*No ID yet */
422
423 #define  SLV_TYPE_CODE0    0xA3           /*Priority Bit set (bits 7-6),  */
424
425 #define  ASSIGN_ID   0x00
426 #define  SET_P_FLAG  0x01
427 #define  CFG_CMPLT   0x03
428 #define  DOM_MSTR    0x0F
429 #define  SYNC_PTRN   0x1F
430
431 #define  ID_0_7      0x18
432 #define  ID_8_F      0x11
433 #define  ID_10_17    0x12
434 #define  ID_18_1F    0x0B
435 #define  MISC_CODE   0x14
436 #define  CLR_P_FLAG  0x18
437 #define  LOCATE_ON   0x12
438 #define  LOCATE_OFF  0x0B
439
440 #define  LVL_1_MST   0x00
441 #define  LVL_2_MST   0x40
442 #define  DOM_LVL_2   0xC0
443
444
445 #define  INIT_SELTD  0x01
446 #define  LEVEL2_TAR  0x02
447
448
449 enum scam_id_st { ID0,ID1,ID2,ID3,ID4,ID5,ID6,ID7,ID8,ID9,ID10,ID11,ID12,
450                   ID13,ID14,ID15,ID_UNUSED,ID_UNASSIGNED,ID_ASSIGNED,LEGACY,
451                   CLR_PRIORITY,NO_ID_AVAIL };
452
453 typedef struct SCCBscam_info {
454
455    UCHAR    id_string[ID_STRING_LENGTH];
456    enum scam_id_st state;
457     
458 } SCCBSCAM_INFO, *PSCCBSCAM_INFO;
459
460
461 #define  SCSI_TEST_UNIT_READY    0x00
462 #define  SCSI_REZERO_UNIT        0x01
463 #define  SCSI_REQUEST_SENSE      0x03
464 #define  SCSI_FORMAT_UNIT        0x04
465 #define  SCSI_REASSIGN           0x07
466 #define  SCSI_READ               0x08
467 #define  SCSI_WRITE              0x0A
468 #define  SCSI_SEEK               0x0B
469 #define  SCSI_INQUIRY            0x12
470 #define  SCSI_MODE_SELECT        0x15
471 #define  SCSI_RESERVE_UNIT       0x16
472 #define  SCSI_RELEASE_UNIT       0x17
473 #define  SCSI_MODE_SENSE         0x1A
474 #define  SCSI_START_STOP_UNIT    0x1B
475 #define  SCSI_SEND_DIAGNOSTIC    0x1D
476 #define  SCSI_READ_CAPACITY      0x25
477 #define  SCSI_READ_EXTENDED      0x28
478 #define  SCSI_WRITE_EXTENDED     0x2A
479 #define  SCSI_SEEK_EXTENDED      0x2B
480 #define  SCSI_WRITE_AND_VERIFY   0x2E
481 #define  SCSI_VERIFY             0x2F
482 #define  SCSI_READ_DEFECT_DATA   0x37
483 #define  SCSI_WRITE_BUFFER       0x3B
484 #define  SCSI_READ_BUFFER        0x3C
485 #define  SCSI_RECV_DIAGNOSTIC    0x1C
486 #define  SCSI_READ_LONG          0x3E
487 #define  SCSI_WRITE_LONG         0x3F
488 #define  SCSI_LAST_SCSI_CMND     SCSI_WRITE_LONG
489 #define  SCSI_INVALID_CMND       0xFF
490
491
492
493 #define  SSGOOD                  0x00
494 #define  SSCHECK                 0x02
495 #define  SSCOND_MET              0x04
496 #define  SSBUSY                  0x08
497 #define  SSRESERVATION_CONFLICT  0x18
498 #define  SSCMD_TERM              0x22
499 #define  SSQ_FULL                0x28
500
501
502 #define  SKNO_SEN                0x00
503 #define  SKRECOV_ERR             0x01
504 #define  SKNOT_RDY               0x02
505 #define  SKMED_ERR               0x03
506 #define  SKHW_ERR                0x04
507 #define  SKILL_REQ               0x05
508 #define  SKUNIT_ATTN             0x06
509 #define  SKDATA_PROTECT          0x07
510 #define  SKBLNK_CHK              0x08
511 #define  SKCPY_ABORT             0x0A
512 #define  SKABORT_CMD             0x0B
513 #define  SKEQUAL                 0x0C
514 #define  SKVOL_OVF               0x0D
515 #define  SKMIS_CMP               0x0E
516
517
518 #define  SMCMD_COMP              0x00
519 #define  SMEXT                   0x01
520 #define  SMSAVE_DATA_PTR         0x02
521 #define  SMREST_DATA_PTR         0x03
522 #define  SMDISC                  0x04
523 #define  SMINIT_DETEC_ERR        0x05
524 #define  SMABORT                 0x06
525 #define  SMREJECT                0x07
526 #define  SMNO_OP                 0x08
527 #define  SMPARITY                0x09
528 #define  SMDEV_RESET             0x0C
529 #define SMABORT_TAG                                     0x0D
530 #define SMINIT_RECOVERY                 0x0F
531 #define SMREL_RECOVERY                          0x10
532
533 #define  SMIDENT                 0x80
534 #define  DISC_PRIV               0x40
535
536
537 #define  SMSYNC                  0x01
538 #define  SM10MBS                 0x19     /* 100ns           */
539 #define  SM5MBS                  0x32     /* 200ns           */
540 #define  SMOFFSET                0x0F     /* Maxoffset value */
541 #define  SMWDTR                  0x03
542 #define  SM8BIT                  0x00
543 #define  SM16BIT                 0x01
544 #define  SM32BIT                 0x02
545 #define  SMIGNORWR               0x23     /* Ignore Wide Residue */
546
547
548 #define  ARBITRATION_DELAY       0x01     /* 2.4us using a 40Mhz clock */
549 #define  BUS_SETTLE_DELAY        0x01     /* 400ns */
550 #define  BUS_CLEAR_DELAY         0x01     /* 800ns */
551
552
553
554 #define  SPHASE_TO               0x0A  /* 10 second timeout waiting for */
555 #define  SCMD_TO                 0x0F  /* Overall command timeout */
556
557
558
559 #define  SIX_BYTE_CMD            0x06
560 #define  TEN_BYTE_CMD            0x0A
561 #define  TWELVE_BYTE_CMD         0x0C
562
563 #define  ASYNC                   0x00
564 #define  PERI25NS                0x06  /* 25/4ns to next clock for xbow. */
565 #define  SYNC10MBS               0x19
566 #define  SYNC5MBS                0x32
567 #define  MAX_OFFSET              0x0F  /* Maxbyteoffset for Sync Xfers */
568
569
570 #define  EEPROM_WD_CNT     256
571
572 #define  EEPROM_CHECK_SUM  0
573 #define  FW_SIGNATURE      2
574 #define  MODEL_NUMB_0      4
575 #define  MODEL_NUMB_1      5
576 #define  MODEL_NUMB_2      6
577 #define  MODEL_NUMB_3      7
578 #define  MODEL_NUMB_4      8
579 #define  MODEL_NUMB_5      9
580 #define  IO_BASE_ADDR      10
581 #define  IRQ_NUMBER        12
582 #define  PCI_INT_PIN       13
583 #define  BUS_DELAY         14       /*On time in byte 14 off delay in 15 */
584 #define  SYSTEM_CONFIG     16
585 #define  SCSI_CONFIG       17
586 #define  BIOS_CONFIG       18
587 #define  SPIN_UP_DELAY     19
588 #define  SCAM_CONFIG       20
589 #define  ADAPTER_SCSI_ID   24
590
591
592 #define  IGNORE_B_SCAN     32
593 #define  SEND_START_ENA    34
594 #define  DEVICE_ENABLE     36
595
596 #define  SYNC_RATE_TBL     38
597 #define  SYNC_RATE_TBL01   38
598 #define  SYNC_RATE_TBL23   40
599 #define  SYNC_RATE_TBL45   42
600 #define  SYNC_RATE_TBL67   44
601 #define  SYNC_RATE_TBL89   46
602 #define  SYNC_RATE_TBLab   48
603 #define  SYNC_RATE_TBLcd   50
604 #define  SYNC_RATE_TBLef   52
605
606
607
608 #define  EE_SCAMBASE      256 
609
610
611
612    #define  DOM_MASTER     (BIT(0) + BIT(1))
613    #define  SCAM_ENABLED   BIT(2)
614    #define  SCAM_LEVEL2    BIT(3)
615
616
617         #define RENEGO_ENA              BITW(10)
618         #define CONNIO_ENA              BITW(11)
619    #define  GREEN_PC_ENA   BITW(12)
620
621
622    #define  AUTO_RATE_00   00
623    #define  AUTO_RATE_05   01
624    #define  AUTO_RATE_10   02
625    #define  AUTO_RATE_20   03
626
627    #define  WIDE_NEGO_BIT     BIT(7)
628    #define  DISC_ENABLE_BIT   BIT(6)
629
630
631
632    #define  hp_vendor_id_0       0x00           /* LSB */
633       #define  ORION_VEND_0   0x4B
634  
635    #define  hp_vendor_id_1       0x01           /* MSB */
636       #define  ORION_VEND_1   0x10
637
638    #define  hp_device_id_0       0x02           /* LSB */
639       #define  ORION_DEV_0    0x30 
640
641    #define  hp_device_id_1       0x03           /* MSB */
642       #define  ORION_DEV_1    0x81 
643
644         /* Sub Vendor ID and Sub Device ID only available in
645                 Harpoon Version 2 and higher */
646
647    #define  hp_sub_vendor_id_0   0x04           /* LSB */
648    #define  hp_sub_vendor_id_1   0x05           /* MSB */
649    #define  hp_sub_device_id_0   0x06           /* LSB */
650    #define  hp_sub_device_id_1   0x07           /* MSB */
651
652
653    #define  hp_dual_addr_lo      0x08
654    #define  hp_dual_addr_lmi     0x09
655    #define  hp_dual_addr_hmi     0x0A
656    #define  hp_dual_addr_hi      0x0B
657
658    #define  hp_semaphore         0x0C
659       #define SCCB_MGR_ACTIVE    BIT(0)
660       #define TICKLE_ME          BIT(1)
661       #define SCCB_MGR_PRESENT   BIT(3)
662       #define BIOS_IN_USE        BIT(4)
663
664    #define  hp_user_defined_D    0x0D
665
666    #define  hp_reserved_E        0x0E
667
668    #define  hp_sys_ctrl          0x0F
669
670       #define  STOP_CLK          BIT(0)      /*Turn off BusMaster Clock */
671       #define  DRVR_RST          BIT(1)      /*Firmware Reset to 80C15 chip */
672       #define  HALT_MACH         BIT(3)      /*Halt State Machine      */
673       #define  HARD_ABORT        BIT(4)      /*Hard Abort              */
674       #define  DIAG_MODE         BIT(5)      /*Diagnostic Mode         */
675
676       #define  BM_ABORT_TMOUT    0x50        /*Halt State machine time out */
677
678    #define  hp_sys_cfg           0x10
679
680       #define  DONT_RST_FIFO     BIT(7)      /*Don't reset FIFO      */
681
682
683    #define  hp_host_ctrl0        0x11
684
685       #define  DUAL_ADDR_MODE    BIT(0)   /*Enable 64-bit addresses */
686       #define  IO_MEM_SPACE      BIT(1)   /*I/O Memory Space    */
687       #define  RESOURCE_LOCK     BIT(2)   /*Enable Resource Lock */
688       #define  IGNOR_ACCESS_ERR  BIT(3)   /*Ignore Access Error */
689       #define  HOST_INT_EDGE     BIT(4)   /*Host interrupt level/edge mode sel */
690       #define  SIX_CLOCKS        BIT(5)   /*6 Clocks between Strobe   */
691       #define  DMA_EVEN_PARITY   BIT(6)   /*Enable DMA Enen Parity */
692
693 /*
694       #define  BURST_MODE        BIT(0)
695 */
696
697    #define  hp_reserved_12       0x12
698
699    #define  hp_host_blk_cnt      0x13
700
701       #define  XFER_BLK1         0x00     /*     0 0 0  1 byte per block*/
702       #define  XFER_BLK2         0x01     /*     0 0 1  2 byte per block*/
703       #define  XFER_BLK4         0x02     /*     0 1 0  4 byte per block*/
704       #define  XFER_BLK8         0x03     /*     0 1 1  8 byte per block*/
705       #define  XFER_BLK16        0x04     /*     1 0 0 16 byte per block*/
706       #define  XFER_BLK32        0x05     /*     1 0 1 32 byte per block*/
707       #define  XFER_BLK64        0x06     /*     1 1 0 64 byte per block*/
708    
709       #define  BM_THRESHOLD      0x40     /* PCI mode can only xfer 16 bytes*/
710
711
712    #define  hp_reserved_14       0x14
713    #define  hp_reserved_15       0x15
714    #define  hp_reserved_16       0x16
715
716    #define  hp_int_mask          0x17
717
718       #define  INT_CMD_COMPL     BIT(0)   /* DMA command complete   */
719       #define  INT_EXT_STATUS    BIT(1)   /* Extended Status Set    */
720       #define  INT_SCSI          BIT(2)   /* Scsi block interrupt   */
721       #define  INT_FIFO_RDY      BIT(4)   /* FIFO data ready        */
722
723
724    #define  hp_xfer_cnt_lo       0x18
725    #define  hp_xfer_cnt_mi       0x19
726    #define  hp_xfer_cnt_hi       0x1A
727    #define  hp_xfer_cmd          0x1B
728
729       #define  XFER_HOST_DMA     0x00     /*     0 0 0 Transfer Host -> DMA */
730       #define  XFER_DMA_HOST     0x01     /*     0 0 1 Transfer DMA  -> Host */
731       #define  XFER_HOST_MPU     0x02     /*     0 1 0 Transfer Host -> MPU  */
732       #define  XFER_MPU_HOST     0x03     /*     0 1 1 Transfer MPU  -> Host */
733       #define  XFER_DMA_MPU      0x04     /*     1 0 0 Transfer DMA  -> MPU  */
734       #define  XFER_MPU_DMA      0x05     /*     1 0 1 Transfer MPU  -> DMA  */
735       #define  SET_SEMAPHORE     0x06     /*     1 1 0 Set Semaphore         */
736       #define  XFER_NOP          0x07     /*     1 1 1 Transfer NOP          */
737       #define  XFER_MB_MPU       0x06     /*     1 1 0 Transfer MB -> MPU */
738       #define  XFER_MB_DMA       0x07     /*     1 1 1 Transfer MB -> DMA */
739
740
741       #define  XFER_HOST_AUTO    0x00     /*     0 0 Auto Transfer Size   */
742       #define  XFER_HOST_8BIT    0x08     /*     0 1 8 BIT Transfer Size  */
743       #define  XFER_HOST_16BIT   0x10     /*     1 0 16 BIT Transfer Size */
744       #define  XFER_HOST_32BIT   0x18     /*     1 1 32 BIT Transfer Size */
745
746       #define  XFER_DMA_8BIT     0x20     /*     0 1 8 BIT  Transfer Size */
747       #define  XFER_DMA_16BIT    0x40     /*     1 0 16 BIT Transfer Size */
748
749       #define  DISABLE_INT       BIT(7)   /*Do not interrupt at end of cmd. */
750
751       #define  HOST_WRT_CMD      ((DISABLE_INT + XFER_HOST_DMA + XFER_HOST_AUTO + XFER_DMA_8BIT))
752       #define  HOST_RD_CMD       ((DISABLE_INT + XFER_DMA_HOST + XFER_HOST_AUTO + XFER_DMA_8BIT))
753       #define  WIDE_HOST_WRT_CMD ((DISABLE_INT + XFER_HOST_DMA + XFER_HOST_AUTO + XFER_DMA_16BIT))
754       #define  WIDE_HOST_RD_CMD  ((DISABLE_INT + XFER_DMA_HOST + XFER_HOST_AUTO + XFER_DMA_16BIT))
755
756    #define  hp_host_addr_lo      0x1C
757    #define  hp_host_addr_lmi     0x1D
758    #define  hp_host_addr_hmi     0x1E
759    #define  hp_host_addr_hi      0x1F
760
761    #define  hp_pio_data          0x20
762    #define  hp_reserved_21       0x21
763    #define  hp_ee_ctrl           0x22
764
765       #define  EXT_ARB_ACK       BIT(7)
766       #define  SCSI_TERM_ENA_H   BIT(6)   /* SCSI high byte terminator */
767       #define  SEE_MS            BIT(5)
768       #define  SEE_CS            BIT(3)
769       #define  SEE_CLK           BIT(2)
770       #define  SEE_DO            BIT(1)
771       #define  SEE_DI            BIT(0)
772
773       #define  EE_READ           0x06
774       #define  EE_WRITE          0x05
775       #define  EWEN              0x04
776       #define  EWEN_ADDR         0x03C0
777       #define  EWDS              0x04
778       #define  EWDS_ADDR         0x0000
779
780    #define  hp_brdctl            0x23
781
782       #define  DAT_7             BIT(7)
783       #define  DAT_6             BIT(6)
784       #define  DAT_5             BIT(5)
785       #define  BRD_STB           BIT(4)
786       #define  BRD_CS            BIT(3)
787       #define  BRD_WR            BIT(2)
788
789    #define  hp_reserved_24       0x24
790    #define  hp_reserved_25       0x25
791
792
793
794
795    #define  hp_bm_ctrl           0x26
796
797       #define  SCSI_TERM_ENA_L   BIT(0)   /*Enable/Disable external terminators */
798       #define  FLUSH_XFER_CNTR   BIT(1)   /*Flush transfer counter */
799       #define  BM_XFER_MIN_8     BIT(2)   /*Enable bus master transfer of 9 */
800       #define  BIOS_ENA          BIT(3)   /*Enable BIOS/FLASH Enable */
801       #define  FORCE1_XFER       BIT(5)   /*Always xfer one byte in byte mode */
802       #define  FAST_SINGLE       BIT(6)   /*?? */
803
804       #define  BMCTRL_DEFAULT    (FORCE1_XFER|FAST_SINGLE|SCSI_TERM_ENA_L)
805
806    #define  hp_reserved_27       0x27
807
808    #define  hp_sg_addr           0x28
809    #define  hp_page_ctrl         0x29
810
811       #define  SCATTER_EN        BIT(0)   
812       #define  SGRAM_ARAM        BIT(1)   
813       #define  BIOS_SHADOW       BIT(2)   
814       #define  G_INT_DISABLE     BIT(3)   /* Enable/Disable all Interrupts */
815       #define  NARROW_SCSI_CARD  BIT(4)   /* NARROW/WIDE SCSI config pin */
816
817    #define  hp_reserved_2A       0x2A
818    #define  hp_pci_cmd_cfg       0x2B
819
820       #define  IO_SPACE_ENA      BIT(0)   /*enable I/O space */
821       #define  MEM_SPACE_ENA     BIT(1)   /*enable memory space */
822       #define  BUS_MSTR_ENA      BIT(2)   /*enable bus master operation */
823       #define  MEM_WI_ENA        BIT(4)   /*enable Write and Invalidate */
824       #define  PAR_ERR_RESP      BIT(6)   /*enable parity error responce. */
825
826    #define  hp_reserved_2C       0x2C
827
828    #define  hp_pci_stat_cfg      0x2D
829
830       #define  DATA_PARITY_ERR   BIT(0)   
831       #define  REC_TARGET_ABORT  BIT(4)   /*received Target abort */
832       #define  REC_MASTER_ABORT  BIT(5)   /*received Master abort */
833       #define  SIG_SYSTEM_ERR    BIT(6)   
834       #define  DETECTED_PAR_ERR  BIT(7)   
835
836    #define  hp_reserved_2E       0x2E
837
838    #define  hp_sys_status        0x2F
839
840       #define  SLV_DATA_RDY      BIT(0)   /*Slave data ready */
841       #define  XFER_CNT_ZERO     BIT(1)   /*Transfer counter = 0 */
842       #define  BM_FIFO_EMPTY     BIT(2)   /*FIFO empty */
843       #define  BM_FIFO_FULL      BIT(3)   /*FIFO full */
844       #define  HOST_OP_DONE      BIT(4)   /*host operation done */
845       #define  DMA_OP_DONE       BIT(5)   /*DMA operation done */
846       #define  SLV_OP_DONE       BIT(6)   /*Slave operation done */
847       #define  PWR_ON_FLAG       BIT(7)   /*Power on flag */
848
849    #define  hp_reserved_30       0x30
850
851    #define  hp_host_status0      0x31
852
853       #define  HOST_TERM         BIT(5)   /*Host Terminal Count */
854       #define  HOST_TRSHLD       BIT(6)   /*Host Threshold      */
855       #define  CONNECTED_2_HOST  BIT(7)   /*Connected to Host   */
856
857    #define  hp_reserved_32       0x32
858
859    #define  hp_rev_num           0x33
860
861       #define  REV_A_CONST       0x0E
862       #define  REV_B_CONST       0x0E
863
864    #define  hp_stack_data        0x34
865    #define  hp_stack_addr        0x35
866
867    #define  hp_ext_status        0x36
868
869       #define  BM_FORCE_OFF      BIT(0)   /*Bus Master is forced to get off */
870       #define  PCI_TGT_ABORT     BIT(0)   /*PCI bus master transaction aborted */
871       #define  PCI_DEV_TMOUT     BIT(1)   /*PCI Device Time out */
872       #define  FIFO_TC_NOT_ZERO  BIT(2)   /*FIFO or transfer counter not zero */
873       #define  CHIP_RST_OCCUR    BIT(3)   /*Chip reset occurs */
874       #define  CMD_ABORTED       BIT(4)   /*Command aborted */
875       #define  BM_PARITY_ERR     BIT(5)   /*parity error on data received   */
876       #define  PIO_OVERRUN       BIT(6)   /*Slave data overrun */
877       #define  BM_CMD_BUSY       BIT(7)   /*Bus master transfer command busy */
878       #define  BAD_EXT_STATUS    (BM_FORCE_OFF | PCI_DEV_TMOUT | CMD_ABORTED | \
879                                   BM_PARITY_ERR | PIO_OVERRUN)
880
881    #define  hp_int_status        0x37
882       
883       #define  BM_CMD_CMPL       BIT(0)   /*Bus Master command complete */
884       #define  EXT_STATUS_ON     BIT(1)   /*Extended status is valid */
885       #define  SCSI_INTERRUPT    BIT(2)   /*Global indication of a SCSI int. */
886       #define  BM_FIFO_RDY       BIT(4)   
887       #define  INT_ASSERTED      BIT(5)   /* */
888       #define  SRAM_BUSY         BIT(6)   /*Scatter/Gather RAM busy */
889       #define  CMD_REG_BUSY      BIT(7)                                       
890
891
892    #define  hp_fifo_cnt          0x38
893    #define  hp_curr_host_cnt     0x39
894    #define  hp_reserved_3A       0x3A
895    #define  hp_fifo_in_addr      0x3B
896
897    #define  hp_fifo_out_addr     0x3C
898    #define  hp_reserved_3D       0x3D
899    #define  hp_reserved_3E       0x3E
900    #define  hp_reserved_3F       0x3F
901
902
903
904    #define  hp_intena            0x40
905
906       #define  RESET             BITW(7)
907       #define  PROG_HLT          BITW(6)  
908       #define  PARITY            BITW(5)
909       #define  FIFO              BITW(4)
910       #define  SEL               BITW(3)
911       #define  SCAM_SEL          BITW(2) 
912       #define  RSEL              BITW(1)
913       #define  TIMEOUT           BITW(0)
914       #define  BUS_FREE          BITW(15)
915       #define  XFER_CNT_0        BITW(14)
916       #define  PHASE             BITW(13)
917       #define  IUNKWN            BITW(12)
918       #define  ICMD_COMP         BITW(11)
919       #define  ITICKLE           BITW(10)
920       #define  IDO_STRT          BITW(9)
921       #define  ITAR_DISC         BITW(8)
922       #define  AUTO_INT          (BITW(12)+BITW(11)+BITW(10)+BITW(9)+BITW(8))
923       #define  CLR_ALL_INT       0xFFFF
924       #define  CLR_ALL_INT_1     0xFF00
925
926    #define  hp_intstat           0x42
927
928    #define  hp_scsisig           0x44
929
930       #define  SCSI_SEL          BIT(7)
931       #define  SCSI_BSY          BIT(6)
932       #define  SCSI_REQ          BIT(5)
933       #define  SCSI_ACK          BIT(4)
934       #define  SCSI_ATN          BIT(3)
935       #define  SCSI_CD           BIT(2)
936       #define  SCSI_MSG          BIT(1)
937       #define  SCSI_IOBIT        BIT(0)
938
939       #define  S_SCSI_PHZ        (BIT(2)+BIT(1)+BIT(0))
940       #define  S_CMD_PH          (BIT(2)              )
941       #define  S_MSGO_PH         (BIT(2)+BIT(1)       )
942       #define  S_STAT_PH         (BIT(2)       +BIT(0))
943       #define  S_MSGI_PH         (BIT(2)+BIT(1)+BIT(0))
944       #define  S_DATAI_PH        (              BIT(0))
945       #define  S_DATAO_PH        0x00
946       #define  S_ILL_PH          (       BIT(1)       )
947
948    #define  hp_scsictrl_0        0x45
949
950       #define  NO_ARB            BIT(7)
951       #define  SEL_TAR           BIT(6)
952       #define  ENA_ATN           BIT(4)
953       #define  ENA_RESEL         BIT(2)
954       #define  SCSI_RST          BIT(1)
955       #define  ENA_SCAM_SEL      BIT(0)
956
957
958
959    #define  hp_portctrl_0        0x46
960
961       #define  SCSI_PORT         BIT(7)
962       #define  SCSI_INBIT        BIT(6)
963       #define  DMA_PORT          BIT(5)
964       #define  DMA_RD            BIT(4)
965       #define  HOST_PORT         BIT(3)
966       #define  HOST_WRT          BIT(2)
967       #define  SCSI_BUS_EN       BIT(1)
968       #define  START_TO          BIT(0)
969
970    #define  hp_scsireset         0x47
971
972       #define  SCSI_TAR          BIT(7)
973       #define  SCSI_INI          BIT(6)
974       #define  SCAM_EN           BIT(5)
975       #define  ACK_HOLD          BIT(4)
976       #define  DMA_RESET         BIT(3)
977       #define  HPSCSI_RESET      BIT(2)
978       #define  PROG_RESET        BIT(1)
979       #define  FIFO_CLR          BIT(0)
980
981    #define  hp_xfercnt_0         0x48
982    #define  hp_xfercnt_1         0x49
983    #define  hp_xfercnt_2         0x4A
984    #define  hp_xfercnt_3         0x4B
985
986    #define  hp_fifodata_0        0x4C
987    #define  hp_fifodata_1        0x4D
988    #define  hp_addstat           0x4E
989
990       #define  SCAM_TIMER        BIT(7)
991       #define  AUTO_RUNNING      BIT(6)
992       #define  FAST_SYNC         BIT(5)
993       #define  SCSI_MODE8        BIT(3)
994       #define  SCSI_PAR_ERR      BIT(0)
995
996    #define  hp_prgmcnt_0         0x4F
997
998       #define  AUTO_PC_MASK      0x3F
999
1000    #define  hp_selfid_0          0x50
1001    #define  hp_selfid_1          0x51
1002    #define  hp_arb_id            0x52
1003
1004       #define  ARB_ID            (BIT(3) + BIT(2) + BIT(1) + BIT(0))
1005
1006    #define  hp_select_id         0x53
1007
1008       #define  RESEL_ID          (BIT(7) + BIT(6) + BIT(5) + BIT(4))
1009       #define  SELECT_ID         (BIT(3) + BIT(2) + BIT(1) + BIT(0))
1010
1011    #define  hp_synctarg_base     0x54
1012    #define  hp_synctarg_12       0x54
1013    #define  hp_synctarg_13       0x55
1014    #define  hp_synctarg_14       0x56
1015    #define  hp_synctarg_15       0x57
1016
1017    #define  hp_synctarg_8        0x58
1018    #define  hp_synctarg_9        0x59
1019    #define  hp_synctarg_10       0x5A
1020    #define  hp_synctarg_11       0x5B
1021
1022    #define  hp_synctarg_4        0x5C
1023    #define  hp_synctarg_5        0x5D
1024    #define  hp_synctarg_6        0x5E
1025    #define  hp_synctarg_7        0x5F
1026
1027    #define  hp_synctarg_0        0x60
1028    #define  hp_synctarg_1        0x61
1029    #define  hp_synctarg_2        0x62
1030    #define  hp_synctarg_3        0x63
1031
1032       #define  RATE_20MB         0x00
1033       #define  RATE_10MB         (              BIT(5))
1034       #define  RATE_6_6MB        (       BIT(6)       )   
1035       #define  RATE_5MB          (       BIT(6)+BIT(5))
1036       #define  RATE_4MB          (BIT(7)              )
1037       #define  RATE_3_33MB       (BIT(7)       +BIT(5))
1038       #define  RATE_2_85MB       (BIT(7)+BIT(6)       )
1039       #define  RATE_2_5MB        (BIT(7)+BIT(5)+BIT(6))
1040       #define  NEXT_CLK          BIT(5)
1041       #define  SLOWEST_SYNC      (BIT(7)+BIT(6)+BIT(5))
1042       #define  NARROW_SCSI       BIT(4)
1043       #define  SYNC_OFFSET       (BIT(3) + BIT(2) + BIT(1) + BIT(0))
1044       #define  DEFAULT_ASYNC     0x00
1045       #define  DEFAULT_OFFSET    0x0F
1046
1047    #define  hp_autostart_0       0x64
1048    #define  hp_autostart_1       0x65
1049    #define  hp_autostart_2       0x66
1050    #define  hp_autostart_3       0x67
1051
1052
1053
1054       #define  DISABLE  0x00
1055       #define  AUTO_IMMED    BIT(5)
1056       #define  SELECT   BIT(6)
1057       #define  RESELECT (BIT(6)+BIT(5))
1058       #define  BUSFREE  BIT(7)
1059       #define  XFER_0   (BIT(7)+BIT(5))
1060       #define  END_DATA (BIT(7)+BIT(6))
1061       #define  MSG_PHZ  (BIT(7)+BIT(6)+BIT(5))
1062
1063    #define  hp_gp_reg_0          0x68
1064    #define  hp_gp_reg_1          0x69
1065    #define  hp_gp_reg_2          0x6A
1066    #define  hp_gp_reg_3          0x6B
1067
1068    #define  hp_seltimeout        0x6C
1069
1070
1071       #define  TO_2ms            0x54      /* 2.0503ms */
1072       #define  TO_4ms            0x67      /* 3.9959ms */
1073
1074       #define  TO_5ms            0x03      /* 4.9152ms */
1075       #define  TO_10ms           0x07      /* 11.xxxms */
1076       #define  TO_250ms          0x99      /* 250.68ms */
1077       #define  TO_290ms          0xB1      /* 289.99ms */
1078       #define  TO_350ms          0xD6      /* 350.62ms */
1079       #define  TO_417ms          0xFF      /* 417.79ms */
1080
1081    #define  hp_clkctrl_0         0x6D
1082
1083       #define  PWR_DWN           BIT(6)
1084       #define  ACTdeassert       BIT(4)
1085       #define  ATNonErr          BIT(3)
1086       #define  CLK_30MHZ         BIT(1)
1087       #define  CLK_40MHZ         (BIT(1) + BIT(0))
1088       #define  CLK_50MHZ         BIT(2)
1089
1090       #define  CLKCTRL_DEFAULT   (ACTdeassert | CLK_40MHZ)
1091
1092    #define  hp_fiforead          0x6E
1093    #define  hp_fifowrite         0x6F
1094
1095    #define  hp_offsetctr         0x70
1096    #define  hp_xferstat          0x71
1097
1098       #define  FIFO_FULL         BIT(7)
1099       #define  FIFO_EMPTY        BIT(6)
1100       #define  FIFO_MASK         0x3F   /* Mask for the FIFO count value. */
1101       #define  FIFO_LEN          0x20
1102
1103    #define  hp_portctrl_1        0x72
1104
1105       #define  EVEN_HOST_P       BIT(5)
1106       #define  INVT_SCSI         BIT(4)
1107       #define  CHK_SCSI_P        BIT(3)
1108       #define  HOST_MODE8        BIT(0)
1109       #define  HOST_MODE16       0x00
1110
1111    #define  hp_xfer_pad          0x73
1112
1113       #define  ID_UNLOCK         BIT(3)
1114       #define  XFER_PAD          BIT(2)
1115
1116    #define  hp_scsidata_0        0x74
1117    #define  hp_scsidata_1        0x75
1118    #define  hp_timer_0           0x76
1119    #define  hp_timer_1           0x77
1120
1121    #define  hp_reserved_78       0x78
1122    #define  hp_reserved_79       0x79
1123    #define  hp_reserved_7A       0x7A
1124    #define  hp_reserved_7B       0x7B
1125
1126    #define  hp_reserved_7C       0x7C
1127    #define  hp_reserved_7D       0x7D
1128    #define  hp_reserved_7E       0x7E
1129    #define  hp_reserved_7F       0x7F
1130
1131    #define  hp_aramBase          0x80
1132    #define  BIOS_DATA_OFFSET     0x60
1133    #define  BIOS_RELATIVE_CARD   0x64
1134
1135
1136
1137
1138       #define  AUTO_LEN 0x80
1139       #define  AR0      0x00
1140       #define  AR1      BITW(8)
1141       #define  AR2      BITW(9)
1142       #define  AR3      (BITW(9) + BITW(8))
1143       #define  SDATA    BITW(10)
1144
1145       #define  NOP_OP   0x00        /* Nop command */
1146
1147       #define  CRD_OP   BITW(11)     /* Cmp Reg. w/ Data */
1148
1149       #define  CRR_OP   BITW(12)     /* Cmp Reg. w. Reg. */
1150
1151       #define  CBE_OP   (BITW(14)+BITW(12)+BITW(11)) /* Cmp SCSI cmd class & Branch EQ */
1152       
1153       #define  CBN_OP   (BITW(14)+BITW(13))  /* Cmp SCSI cmd class & Branch NOT EQ */
1154       
1155       #define  CPE_OP   (BITW(14)+BITW(11))  /* Cmp SCSI phs & Branch EQ */
1156
1157       #define  CPN_OP   (BITW(14)+BITW(12))  /* Cmp SCSI phs & Branch NOT EQ */
1158
1159
1160       #define  ADATA_OUT   0x00     
1161       #define  ADATA_IN    BITW(8)
1162       #define  ACOMMAND    BITW(10)
1163       #define  ASTATUS     (BITW(10)+BITW(8))
1164       #define  AMSG_OUT    (BITW(10)+BITW(9))
1165       #define  AMSG_IN     (BITW(10)+BITW(9)+BITW(8))
1166       #define  AILLEGAL    (BITW(9)+BITW(8))
1167
1168
1169       #define  BRH_OP   BITW(13)   /* Branch */
1170
1171       
1172       #define  ALWAYS   0x00
1173       #define  EQUAL    BITW(8)
1174       #define  NOT_EQ   BITW(9)
1175
1176       #define  TCB_OP   (BITW(13)+BITW(11))    /* Test condition & branch */
1177
1178       
1179       #define  ATN_SET     BITW(8)
1180       #define  ATN_RESET   BITW(9)
1181       #define  XFER_CNT    (BITW(9)+BITW(8))
1182       #define  FIFO_0      BITW(10)
1183       #define  FIFO_NOT0   (BITW(10)+BITW(8))
1184       #define  T_USE_SYNC0 (BITW(10)+BITW(9))
1185
1186
1187       #define  MPM_OP   BITW(15)        /* Match phase and move data */
1188
1189       #define  MDR_OP   (BITW(12)+BITW(11)) /* Move data to Reg. */
1190
1191       #define  MRR_OP   BITW(14)        /* Move DReg. to Reg. */
1192
1193
1194       #define  S_IDREG  (BIT(2)+BIT(1)+BIT(0))
1195
1196
1197       #define  D_AR0    0x00
1198       #define  D_AR1    BIT(0)
1199       #define  D_AR2    BIT(1)
1200       #define  D_AR3    (BIT(1) + BIT(0))
1201       #define  D_SDATA  BIT(2)
1202       #define  D_BUCKET (BIT(2) + BIT(1) + BIT(0))
1203
1204
1205       #define  ADR_OP   (BITW(13)+BITW(12)) /* Logical AND Reg. w. Data */
1206
1207       #define  ADS_OP   (BITW(14)+BITW(13)+BITW(12)) 
1208
1209       #define  ODR_OP   (BITW(13)+BITW(12)+BITW(11))  
1210
1211       #define  ODS_OP   (BITW(14)+BITW(13)+BITW(12)+BITW(11))  
1212
1213       #define  STR_OP   (BITW(15)+BITW(14)) /* Store to A_Reg. */
1214
1215       #define  AINT_ENA1   0x00
1216       #define  AINT_STAT1  BITW(8)
1217       #define  ASCSI_SIG   BITW(9)
1218       #define  ASCSI_CNTL  (BITW(9)+BITW(8))
1219       #define  APORT_CNTL  BITW(10)
1220       #define  ARST_CNTL   (BITW(10)+BITW(8))
1221       #define  AXFERCNT0   (BITW(10)+BITW(9))
1222       #define  AXFERCNT1   (BITW(10)+BITW(9)+BITW(8))
1223       #define  AXFERCNT2   BITW(11)
1224       #define  AFIFO_DATA  (BITW(11)+BITW(8))
1225       #define  ASCSISELID  (BITW(11)+BITW(9))
1226       #define  ASCSISYNC0  (BITW(11)+BITW(9)+BITW(8))
1227
1228
1229       #define  RAT_OP      (BITW(14)+BITW(13)+BITW(11))
1230
1231       #define  SSI_OP      (BITW(15)+BITW(11))
1232
1233
1234       #define  SSI_ITAR_DISC    (ITAR_DISC >> 8)
1235       #define  SSI_IDO_STRT     (IDO_STRT >> 8)
1236       #define  SSI_IDI_STRT     (IDO_STRT >> 8)
1237
1238       #define  SSI_ICMD_COMP    (ICMD_COMP >> 8)
1239       #define  SSI_ITICKLE      (ITICKLE >> 8)
1240
1241       #define  SSI_IUNKWN       (IUNKWN >> 8)
1242       #define  SSI_INO_CC       (IUNKWN >> 8)
1243       #define  SSI_IRFAIL       (IUNKWN >> 8)
1244
1245
1246       #define  NP    0x10     /*Next Phase */
1247       #define  NTCMD 0x02     /*Non- Tagged Command start */
1248       #define  CMDPZ 0x04     /*Command phase */
1249       #define  DINT  0x12     /*Data Out/In interrupt */
1250       #define  DI    0x13     /*Data Out */
1251       #define  MI    0x14     /*Message In */
1252       #define  DC    0x19     /*Disconnect Message */
1253       #define  ST    0x1D     /*Status Phase */
1254       #define  UNKNWN 0x24    /*Unknown bus action */
1255       #define  CC    0x25     /*Command Completion failure */
1256       #define  TICK  0x26     /*New target reselected us. */
1257       #define  RFAIL 0x27     /*Reselection failed */
1258       #define  SELCHK 0x28     /*Select & Check SCSI ID latch reg */
1259
1260
1261       #define  ID_MSG_STRT    hp_aramBase + 0x00
1262       #define  NON_TAG_ID_MSG hp_aramBase + 0x06
1263       #define  CMD_STRT       hp_aramBase + 0x08
1264       #define  SYNC_MSGS      hp_aramBase + 0x08
1265
1266
1267
1268
1269
1270       #define  TAG_STRT          0x00
1271       #define  SELECTION_START   0x00
1272       #define  DISCONNECT_START  0x10/2
1273       #define  END_DATA_START    0x14/2
1274       #define  NONTAG_STRT       0x02/2
1275       #define  CMD_ONLY_STRT     CMDPZ/2
1276       #define  TICKLE_STRT     TICK/2
1277       #define  SELCHK_STRT     SELCHK/2
1278
1279
1280
1281
1282 #define mEEPROM_CLK_DELAY(port) (RD_HARPOON(port+hp_intstat_1))
1283
1284 #define mWAIT_10MS(port) (RD_HARPOON(port+hp_intstat_1))
1285
1286
1287 #define CLR_XFER_CNT(port) (WR_HARPOON(port+hp_xfercnt_0, 0x00))
1288
1289 #define SET_XFER_CNT(port, data) (WR_HARP32(port,hp_xfercnt_0,data))
1290
1291 #define GET_XFER_CNT(port, xfercnt) {RD_HARP32(port,hp_xfercnt_0,xfercnt); xfercnt &= 0xFFFFFF;}
1292 /* #define GET_XFER_CNT(port, xfercnt) (xfercnt = RD_HARPOON(port+hp_xfercnt_2), \
1293                                  xfercnt <<= 16,\
1294                                  xfercnt |= RDW_HARPOON((USHORT)(port+hp_xfercnt_0)))
1295  */
1296 #define HP_SETUP_ADDR_CNT(port,addr,count) (WRW_HARPOON((port+hp_host_addr_lo), (USHORT)(addr & 0x0000FFFFL)),\
1297          addr >>= 16,\
1298          WRW_HARPOON((port+hp_host_addr_hmi), (USHORT)(addr & 0x0000FFFFL)),\
1299          WR_HARP32(port,hp_xfercnt_0,count),\
1300          WRW_HARPOON((port+hp_xfer_cnt_lo), (USHORT)(count & 0x0000FFFFL)),\
1301          count >>= 16,\
1302          WR_HARPOON(port+hp_xfer_cnt_hi, (count & 0xFF)))
1303
1304 #define ACCEPT_MSG(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}\
1305                           WR_HARPOON(port+hp_scsisig, S_ILL_PH);}
1306
1307
1308 #define ACCEPT_MSG_ATN(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}\
1309                           WR_HARPOON(port+hp_scsisig, (S_ILL_PH|SCSI_ATN));}
1310
1311 #define ACCEPT_STAT(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}\
1312                           WR_HARPOON(port+hp_scsisig, S_ILL_PH);}
1313
1314 #define ACCEPT_STAT_ATN(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}\
1315                           WR_HARPOON(port+hp_scsisig, (S_ILL_PH|SCSI_ATN));}
1316
1317 #define DISABLE_AUTO(port) (WR_HARPOON(port+hp_scsireset, PROG_RESET),\
1318                         WR_HARPOON(port+hp_scsireset, 0x00))
1319
1320 #define ARAM_ACCESS(p_port) (WR_HARPOON(p_port+hp_page_ctrl, \
1321                              (RD_HARPOON(p_port+hp_page_ctrl) | SGRAM_ARAM)))
1322
1323 #define SGRAM_ACCESS(p_port) (WR_HARPOON(p_port+hp_page_ctrl, \
1324                              (RD_HARPOON(p_port+hp_page_ctrl) & ~SGRAM_ARAM)))
1325
1326 #define MDISABLE_INT(p_port) (WR_HARPOON(p_port+hp_page_ctrl, \
1327                              (RD_HARPOON(p_port+hp_page_ctrl) | G_INT_DISABLE)))
1328
1329 #define MENABLE_INT(p_port) (WR_HARPOON(p_port+hp_page_ctrl, \
1330                              (RD_HARPOON(p_port+hp_page_ctrl) & ~G_INT_DISABLE)))
1331
1332
1333
1334
1335 void  scsiStartAuto(ULONG port);
1336 static UCHAR FPT_sisyncn(ULONG port, UCHAR p_card, UCHAR syncFlag);
1337 static void  FPT_ssel(ULONG port, UCHAR p_card);
1338 static void  FPT_sres(ULONG port, UCHAR p_card, PSCCBcard pCurrCard);
1339 static void  FPT_shandem(ULONG port, UCHAR p_card,PSCCB pCurrSCCB);
1340 static void  FPT_stsyncn(ULONG port, UCHAR p_card);
1341 static void  FPT_sisyncr(ULONG port,UCHAR sync_pulse, UCHAR offset);
1342 static void  FPT_sssyncv(ULONG p_port, UCHAR p_id, UCHAR p_sync_value,
1343                          PSCCBMgr_tar_info currTar_Info);
1344 static void  FPT_sresb(ULONG port, UCHAR p_card);
1345 static void  FPT_sxfrp(ULONG p_port, UCHAR p_card);
1346 static void  FPT_schkdd(ULONG port, UCHAR p_card);
1347 static UCHAR FPT_RdStack(ULONG port, UCHAR index);
1348 static void  FPT_WrStack(ULONG portBase, UCHAR index, UCHAR data);
1349 static UCHAR FPT_ChkIfChipInitialized(ULONG ioPort);
1350
1351 static void FPT_SendMsg(ULONG port, UCHAR message);
1352 static void  FPT_queueFlushTargSccb(UCHAR p_card, UCHAR thisTarg,
1353                                     UCHAR error_code);
1354
1355 static void  FPT_sinits(PSCCB p_sccb, UCHAR p_card);
1356 static void  FPT_RNVRamData(PNVRamInfo pNvRamInfo);
1357
1358 static UCHAR FPT_siwidn(ULONG port, UCHAR p_card);
1359 static void  FPT_stwidn(ULONG port, UCHAR p_card);
1360 static void  FPT_siwidr(ULONG port, UCHAR width);
1361
1362
1363 static void  FPT_queueSelectFail(PSCCBcard pCurrCard, UCHAR p_card);
1364 static void  FPT_queueDisconnect(PSCCB p_SCCB, UCHAR p_card);
1365 static void  FPT_queueCmdComplete(PSCCBcard pCurrCard, PSCCB p_SCCB,
1366                                   UCHAR p_card);
1367 static void  FPT_queueSearchSelect(PSCCBcard pCurrCard, UCHAR p_card);
1368 static void  FPT_queueFlushSccb(UCHAR p_card, UCHAR error_code);
1369 static void  FPT_queueAddSccb(PSCCB p_SCCB, UCHAR card);
1370 static UCHAR FPT_queueFindSccb(PSCCB p_SCCB, UCHAR p_card);
1371 static void  FPT_utilUpdateResidual(PSCCB p_SCCB);
1372 static USHORT FPT_CalcCrc16(UCHAR buffer[]);
1373 static UCHAR  FPT_CalcLrc(UCHAR buffer[]);
1374
1375
1376 static void  FPT_Wait1Second(ULONG p_port);
1377 static void  FPT_Wait(ULONG p_port, UCHAR p_delay);
1378 static void  FPT_utilEEWriteOnOff(ULONG p_port,UCHAR p_mode);
1379 static void  FPT_utilEEWrite(ULONG p_port, USHORT ee_data, USHORT ee_addr);
1380 static USHORT FPT_utilEERead(ULONG p_port, USHORT ee_addr);
1381 static USHORT FPT_utilEEReadOrg(ULONG p_port, USHORT ee_addr);
1382 static void  FPT_utilEESendCmdAddr(ULONG p_port, UCHAR ee_cmd, USHORT ee_addr);
1383
1384
1385
1386 static void  FPT_phaseDataOut(ULONG port, UCHAR p_card);
1387 static void  FPT_phaseDataIn(ULONG port, UCHAR p_card);
1388 static void  FPT_phaseCommand(ULONG port, UCHAR p_card);
1389 static void  FPT_phaseStatus(ULONG port, UCHAR p_card);
1390 static void  FPT_phaseMsgOut(ULONG port, UCHAR p_card);
1391 static void  FPT_phaseMsgIn(ULONG port, UCHAR p_card);
1392 static void  FPT_phaseIllegal(ULONG port, UCHAR p_card);
1393
1394 static void  FPT_phaseDecode(ULONG port, UCHAR p_card);
1395 static void  FPT_phaseChkFifo(ULONG port, UCHAR p_card);
1396 static void  FPT_phaseBusFree(ULONG p_port, UCHAR p_card);
1397
1398
1399
1400
1401 static void  FPT_XbowInit(ULONG port, UCHAR scamFlg);
1402 static void  FPT_BusMasterInit(ULONG p_port);
1403 static void  FPT_DiagEEPROM(ULONG p_port);
1404
1405
1406
1407
1408 void  busMstrAbort(ULONG port);
1409 static void  FPT_dataXferProcessor(ULONG port, PSCCBcard pCurrCard);
1410 static void  FPT_busMstrSGDataXferStart(ULONG port, PSCCB pCurrSCCB);
1411 static void  FPT_busMstrDataXferStart(ULONG port, PSCCB pCurrSCCB);
1412 static void  FPT_hostDataXferAbort(ULONG port, UCHAR p_card, PSCCB pCurrSCCB);
1413 static void  FPT_hostDataXferRestart(PSCCB currSCCB);
1414
1415
1416 static UCHAR FPT_SccbMgr_bad_isr(ULONG p_port, UCHAR p_card,
1417                                  PSCCBcard pCurrCard, USHORT p_int);
1418
1419 static void  FPT_SccbMgrTableInitAll(void);
1420 static void  FPT_SccbMgrTableInitCard(PSCCBcard pCurrCard, UCHAR p_card);
1421 static void  FPT_SccbMgrTableInitTarget(UCHAR p_card, UCHAR target);
1422
1423
1424
1425 static void  FPT_scini(UCHAR p_card, UCHAR p_our_id, UCHAR p_power_up);
1426
1427 static int   FPT_scarb(ULONG p_port, UCHAR p_sel_type);
1428 static void  FPT_scbusf(ULONG p_port);
1429 static void  FPT_scsel(ULONG p_port);
1430 static void  FPT_scasid(UCHAR p_card, ULONG p_port);
1431 static UCHAR FPT_scxferc(ULONG p_port, UCHAR p_data);
1432 static UCHAR FPT_scsendi(ULONG p_port, UCHAR p_id_string[]);
1433 static UCHAR FPT_sciso(ULONG p_port, UCHAR p_id_string[]);
1434 static void  FPT_scwirod(ULONG p_port, UCHAR p_data_bit);
1435 static void  FPT_scwiros(ULONG p_port, UCHAR p_data_bit);
1436 static UCHAR FPT_scvalq(UCHAR p_quintet);
1437 static UCHAR FPT_scsell(ULONG p_port, UCHAR targ_id);
1438 static void  FPT_scwtsel(ULONG p_port);
1439 static void  FPT_inisci(UCHAR p_card, ULONG p_port, UCHAR p_our_id);
1440 static void  FPT_scsavdi(UCHAR p_card, ULONG p_port);
1441 static UCHAR FPT_scmachid(UCHAR p_card, UCHAR p_id_string[]);
1442
1443
1444 static void  FPT_autoCmdCmplt(ULONG p_port, UCHAR p_card);
1445 static void  FPT_autoLoadDefaultMap(ULONG p_port);
1446
1447
1448
1449 void  OS_start_timer(unsigned long ioport, unsigned long timeout);
1450 void  OS_stop_timer(unsigned long ioport, unsigned long timeout);
1451 void  OS_disable_int(unsigned char intvec);
1452 void  OS_enable_int(unsigned char intvec);
1453 void  OS_delay(unsigned long count);
1454 int   OS_VirtToPhys(u32bits CardHandle, u32bits *physaddr, u32bits *virtaddr);
1455
1456 static SCCBMGR_TAR_INFO FPT_sccbMgrTbl[MAX_CARDS][MAX_SCSI_TAR] = { { { 0 } } };
1457 static SCCBCARD FPT_BL_Card[MAX_CARDS] = { { 0 } };
1458 static SCCBSCAM_INFO FPT_scamInfo[MAX_SCSI_TAR] = { { { 0 } } };
1459 static NVRAMINFO FPT_nvRamInfo[MAX_MB_CARDS] = { { 0 } };
1460
1461
1462 static UCHAR FPT_mbCards = 0;
1463 static UCHAR FPT_scamHAString[] = {0x63, 0x07, 'B', 'U', 'S', 'L', 'O', 'G', 'I', 'C', \
1464                                    ' ', 'B', 'T', '-', '9', '3', '0', \
1465                                    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \
1466                                    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20};
1467
1468 static USHORT FPT_default_intena = 0;
1469
1470
1471 static void (*FPT_s_PhaseTbl[8]) (ULONG, UCHAR)= { 0 };
1472
1473
1474 /*---------------------------------------------------------------------
1475  *
1476  * Function: SccbMgr_sense_adapter
1477  *
1478  * Description: Setup and/or Search for cards and return info to caller.
1479  *
1480  *---------------------------------------------------------------------*/
1481
1482 static int SccbMgr_sense_adapter(PSCCBMGR_INFO pCardInfo)
1483 {
1484    static UCHAR first_time = 1;
1485
1486    UCHAR i,j,id,ScamFlg;
1487    USHORT temp,temp2,temp3,temp4,temp5,temp6;
1488    ULONG ioport;
1489         PNVRamInfo pCurrNvRam;
1490
1491    ioport = pCardInfo->si_baseaddr;
1492
1493
1494    if (RD_HARPOON(ioport+hp_vendor_id_0) != ORION_VEND_0)
1495       return((int)FAILURE);
1496
1497    if ((RD_HARPOON(ioport+hp_vendor_id_1) != ORION_VEND_1))
1498       return((int)FAILURE);
1499
1500    if ((RD_HARPOON(ioport+hp_device_id_0) != ORION_DEV_0))
1501       return((int)FAILURE);
1502
1503    if ((RD_HARPOON(ioport+hp_device_id_1) != ORION_DEV_1))
1504       return((int)FAILURE);
1505
1506
1507    if (RD_HARPOON(ioport+hp_rev_num) != 0x0f){
1508
1509 /* For new Harpoon then check for sub_device ID LSB
1510    the bits(0-3) must be all ZERO for compatible with
1511    current version of SCCBMgr, else skip this Harpoon
1512         device. */
1513
1514            if (RD_HARPOON(ioport+hp_sub_device_id_0) & 0x0f)
1515               return((int)FAILURE);
1516         }
1517
1518    if (first_time)
1519       {
1520       FPT_SccbMgrTableInitAll();
1521       first_time = 0;
1522                 FPT_mbCards = 0;
1523       }
1524
1525         if(FPT_RdStack(ioport, 0) != 0x00) {
1526                 if(FPT_ChkIfChipInitialized(ioport) == 0)
1527                 {
1528                         pCurrNvRam = NULL;
1529                    WR_HARPOON(ioport+hp_semaphore, 0x00);
1530                         FPT_XbowInit(ioport, 0);             /*Must Init the SCSI before attempting */
1531                         FPT_DiagEEPROM(ioport);
1532                 }
1533                 else
1534                 {
1535                         if(FPT_mbCards < MAX_MB_CARDS) {
1536                                 pCurrNvRam = &FPT_nvRamInfo[FPT_mbCards];
1537                                 FPT_mbCards++;
1538                                 pCurrNvRam->niBaseAddr = ioport;
1539                                 FPT_RNVRamData(pCurrNvRam);
1540                         }else
1541                                 return((int) FAILURE);
1542                 }
1543         }else
1544                 pCurrNvRam = NULL;
1545
1546    WR_HARPOON(ioport+hp_clkctrl_0, CLKCTRL_DEFAULT);
1547    WR_HARPOON(ioport+hp_sys_ctrl, 0x00);
1548
1549         if(pCurrNvRam)
1550                 pCardInfo->si_id = pCurrNvRam->niAdapId;
1551         else
1552            pCardInfo->si_id = (UCHAR)(FPT_utilEERead(ioport, (ADAPTER_SCSI_ID/2)) &
1553            (UCHAR)0x0FF);
1554
1555    pCardInfo->si_lun = 0x00;
1556    pCardInfo->si_fw_revision = ORION_FW_REV;
1557    temp2 = 0x0000;
1558    temp3 = 0x0000;
1559    temp4 = 0x0000;
1560    temp5 = 0x0000;
1561    temp6 = 0x0000;
1562
1563    for (id = 0; id < (16/2); id++) {
1564
1565                 if(pCurrNvRam){
1566                         temp = (USHORT) pCurrNvRam->niSyncTbl[id];
1567                         temp = ((temp & 0x03) + ((temp << 4) & 0xc0)) +
1568                                          (((temp << 4) & 0x0300) + ((temp << 8) & 0xc000));
1569                 }else
1570               temp = FPT_utilEERead(ioport, (USHORT)((SYNC_RATE_TBL/2)+id));
1571
1572       for (i = 0; i < 2; temp >>=8,i++) {
1573
1574          temp2 >>= 1;
1575          temp3 >>= 1;
1576          temp4 >>= 1;
1577          temp5 >>= 1;
1578          temp6 >>= 1;
1579          switch (temp & 0x3)
1580            {
1581            case AUTO_RATE_20:   /* Synchronous, 20 mega-transfers/second */
1582              temp6 |= 0x8000;   /* Fall through */
1583            case AUTO_RATE_10:   /* Synchronous, 10 mega-transfers/second */
1584              temp5 |= 0x8000;   /* Fall through */
1585            case AUTO_RATE_05:   /* Synchronous, 5 mega-transfers/second */
1586              temp2 |= 0x8000;   /* Fall through */
1587            case AUTO_RATE_00:   /* Asynchronous */
1588              break;
1589            }
1590
1591          if (temp & DISC_ENABLE_BIT)
1592            temp3 |= 0x8000;
1593
1594          if (temp & WIDE_NEGO_BIT)
1595            temp4 |= 0x8000;
1596
1597          }
1598       }
1599
1600    pCardInfo->si_per_targ_init_sync = temp2;
1601    pCardInfo->si_per_targ_no_disc = temp3;
1602    pCardInfo->si_per_targ_wide_nego = temp4;
1603    pCardInfo->si_per_targ_fast_nego = temp5;
1604    pCardInfo->si_per_targ_ultra_nego = temp6;
1605
1606         if(pCurrNvRam)
1607                 i = pCurrNvRam->niSysConf;
1608         else
1609            i = (UCHAR)(FPT_utilEERead(ioport, (SYSTEM_CONFIG/2)));
1610
1611         if(pCurrNvRam)
1612                 ScamFlg = pCurrNvRam->niScamConf;
1613         else
1614            ScamFlg = (UCHAR) FPT_utilEERead(ioport, SCAM_CONFIG/2);
1615
1616    pCardInfo->si_flags = 0x0000;
1617
1618    if (i & 0x01)
1619       pCardInfo->si_flags |= SCSI_PARITY_ENA;
1620
1621    if (!(i & 0x02))
1622       pCardInfo->si_flags |= SOFT_RESET;
1623
1624    if (i & 0x10)
1625       pCardInfo->si_flags |= EXTENDED_TRANSLATION;
1626
1627    if (ScamFlg & SCAM_ENABLED)
1628      pCardInfo->si_flags |= FLAG_SCAM_ENABLED;
1629
1630    if (ScamFlg & SCAM_LEVEL2)
1631      pCardInfo->si_flags |= FLAG_SCAM_LEVEL2;
1632
1633    j = (RD_HARPOON(ioport+hp_bm_ctrl) & ~SCSI_TERM_ENA_L);
1634    if (i & 0x04) {
1635       j |= SCSI_TERM_ENA_L;
1636       }
1637    WR_HARPOON(ioport+hp_bm_ctrl, j );
1638
1639    j = (RD_HARPOON(ioport+hp_ee_ctrl) & ~SCSI_TERM_ENA_H);
1640    if (i & 0x08) {
1641       j |= SCSI_TERM_ENA_H;
1642       }
1643    WR_HARPOON(ioport+hp_ee_ctrl, j );
1644
1645    if (!(RD_HARPOON(ioport+hp_page_ctrl) & NARROW_SCSI_CARD))
1646
1647       pCardInfo->si_flags |= SUPPORT_16TAR_32LUN;
1648
1649    pCardInfo->si_card_family = HARPOON_FAMILY;
1650    pCardInfo->si_bustype = BUSTYPE_PCI;
1651
1652         if(pCurrNvRam){
1653         pCardInfo->si_card_model[0] = '9';
1654                 switch(pCurrNvRam->niModel & 0x0f){
1655                         case MODEL_LT:
1656                         pCardInfo->si_card_model[1] = '3';
1657                         pCardInfo->si_card_model[2] = '0';
1658                                 break;
1659                         case MODEL_LW:
1660                         pCardInfo->si_card_model[1] = '5';
1661                         pCardInfo->si_card_model[2] = '0';
1662                                 break;
1663                         case MODEL_DL:
1664                         pCardInfo->si_card_model[1] = '3';
1665                         pCardInfo->si_card_model[2] = '2';
1666                                 break;
1667                         case MODEL_DW:
1668                         pCardInfo->si_card_model[1] = '5';
1669                         pCardInfo->si_card_model[2] = '2';
1670                                 break;
1671                 }
1672         }else{
1673            temp = FPT_utilEERead(ioport, (MODEL_NUMB_0/2));
1674         pCardInfo->si_card_model[0] = (UCHAR)(temp >> 8);
1675            temp = FPT_utilEERead(ioport, (MODEL_NUMB_2/2));
1676
1677         pCardInfo->si_card_model[1] = (UCHAR)(temp & 0x00FF);
1678            pCardInfo->si_card_model[2] = (UCHAR)(temp >> 8);
1679         }
1680
1681    if (pCardInfo->si_card_model[1] == '3')
1682      {
1683        if (RD_HARPOON(ioport+hp_ee_ctrl) & BIT(7))
1684          pCardInfo->si_flags |= LOW_BYTE_TERM;
1685      }
1686    else if (pCardInfo->si_card_model[2] == '0')
1687      {
1688        temp = RD_HARPOON(ioport+hp_xfer_pad);
1689        WR_HARPOON(ioport+hp_xfer_pad, (temp & ~BIT(4)));
1690        if (RD_HARPOON(ioport+hp_ee_ctrl) & BIT(7))
1691          pCardInfo->si_flags |= LOW_BYTE_TERM;
1692        WR_HARPOON(ioport+hp_xfer_pad, (temp | BIT(4)));
1693        if (RD_HARPOON(ioport+hp_ee_ctrl) & BIT(7))
1694          pCardInfo->si_flags |= HIGH_BYTE_TERM;
1695        WR_HARPOON(ioport+hp_xfer_pad, temp);
1696      }
1697    else
1698      {
1699        temp = RD_HARPOON(ioport+hp_ee_ctrl);
1700        temp2 = RD_HARPOON(ioport+hp_xfer_pad);
1701        WR_HARPOON(ioport+hp_ee_ctrl, (temp | SEE_CS));
1702        WR_HARPOON(ioport+hp_xfer_pad, (temp2 | BIT(4)));
1703        temp3 = 0;
1704        for (i = 0; i < 8; i++)
1705          {
1706            temp3 <<= 1;
1707            if (!(RD_HARPOON(ioport+hp_ee_ctrl) & BIT(7)))
1708              temp3 |= 1;
1709            WR_HARPOON(ioport+hp_xfer_pad, (temp2 & ~BIT(4)));
1710            WR_HARPOON(ioport+hp_xfer_pad, (temp2 | BIT(4)));
1711          }
1712        WR_HARPOON(ioport+hp_ee_ctrl, temp);
1713        WR_HARPOON(ioport+hp_xfer_pad, temp2);
1714        if (!(temp3 & BIT(7)))
1715          pCardInfo->si_flags |= LOW_BYTE_TERM;
1716        if (!(temp3 & BIT(6)))
1717          pCardInfo->si_flags |= HIGH_BYTE_TERM;
1718      }
1719
1720
1721    ARAM_ACCESS(ioport);
1722
1723    for ( i = 0; i < 4; i++ ) {
1724
1725       pCardInfo->si_XlatInfo[i] =
1726          RD_HARPOON(ioport+hp_aramBase+BIOS_DATA_OFFSET+i);
1727       }
1728
1729         /* return with -1 if no sort, else return with
1730            logical card number sorted by BIOS (zero-based) */
1731
1732         pCardInfo->si_relative_cardnum =
1733         (UCHAR)(RD_HARPOON(ioport+hp_aramBase+BIOS_RELATIVE_CARD)-1);
1734
1735    SGRAM_ACCESS(ioport);
1736
1737    FPT_s_PhaseTbl[0] = FPT_phaseDataOut;
1738    FPT_s_PhaseTbl[1] = FPT_phaseDataIn;
1739    FPT_s_PhaseTbl[2] = FPT_phaseIllegal;
1740    FPT_s_PhaseTbl[3] = FPT_phaseIllegal;
1741    FPT_s_PhaseTbl[4] = FPT_phaseCommand;
1742    FPT_s_PhaseTbl[5] = FPT_phaseStatus;
1743    FPT_s_PhaseTbl[6] = FPT_phaseMsgOut;
1744    FPT_s_PhaseTbl[7] = FPT_phaseMsgIn;
1745
1746    pCardInfo->si_present = 0x01;
1747
1748    return(0);
1749 }
1750
1751
1752 /*---------------------------------------------------------------------
1753  *
1754  * Function: SccbMgr_config_adapter
1755  *
1756  * Description: Setup adapter for normal operation (hard reset).
1757  *
1758  *---------------------------------------------------------------------*/
1759
1760 static ULONG SccbMgr_config_adapter(PSCCBMGR_INFO pCardInfo)
1761 {
1762    PSCCBcard CurrCard = NULL;
1763         PNVRamInfo pCurrNvRam;
1764    UCHAR i,j,thisCard, ScamFlg;
1765    USHORT temp,sync_bit_map,id;
1766    ULONG ioport;
1767
1768    ioport = pCardInfo->si_baseaddr;
1769
1770    for(thisCard =0; thisCard <= MAX_CARDS; thisCard++) {
1771
1772       if (thisCard == MAX_CARDS) {
1773
1774          return(FAILURE);
1775          }
1776
1777       if (FPT_BL_Card[thisCard].ioPort == ioport) {
1778
1779          CurrCard = &FPT_BL_Card[thisCard];
1780          FPT_SccbMgrTableInitCard(CurrCard,thisCard);
1781          break;
1782          }
1783
1784       else if (FPT_BL_Card[thisCard].ioPort == 0x00) {
1785
1786          FPT_BL_Card[thisCard].ioPort = ioport;
1787          CurrCard = &FPT_BL_Card[thisCard];
1788
1789                         if(FPT_mbCards)
1790                                 for(i = 0; i < FPT_mbCards; i++){
1791                                         if(CurrCard->ioPort == FPT_nvRamInfo[i].niBaseAddr)
1792                                                 CurrCard->pNvRamInfo = &FPT_nvRamInfo[i];
1793                                 }
1794          FPT_SccbMgrTableInitCard(CurrCard,thisCard);
1795          CurrCard->cardIndex = thisCard;
1796          CurrCard->cardInfo = pCardInfo;
1797
1798          break;
1799          }
1800       }
1801
1802         pCurrNvRam = CurrCard->pNvRamInfo;
1803
1804         if(pCurrNvRam){
1805                 ScamFlg = pCurrNvRam->niScamConf;
1806         }
1807         else{
1808            ScamFlg = (UCHAR) FPT_utilEERead(ioport, SCAM_CONFIG/2);
1809         }
1810
1811
1812    FPT_BusMasterInit(ioport);
1813    FPT_XbowInit(ioport, ScamFlg);
1814
1815    FPT_autoLoadDefaultMap(ioport);
1816
1817
1818    for (i = 0,id = 0x01; i != pCardInfo->si_id; i++,id <<= 1){}
1819
1820    WR_HARPOON(ioport+hp_selfid_0, id);
1821    WR_HARPOON(ioport+hp_selfid_1, 0x00);
1822    WR_HARPOON(ioport+hp_arb_id, pCardInfo->si_id);
1823    CurrCard->ourId = pCardInfo->si_id;
1824
1825    i = (UCHAR) pCardInfo->si_flags;
1826    if (i & SCSI_PARITY_ENA)
1827        WR_HARPOON(ioport+hp_portctrl_1,(HOST_MODE8 | CHK_SCSI_P));
1828
1829    j = (RD_HARPOON(ioport+hp_bm_ctrl) & ~SCSI_TERM_ENA_L);
1830    if (i & LOW_BYTE_TERM)
1831       j |= SCSI_TERM_ENA_L;
1832    WR_HARPOON(ioport+hp_bm_ctrl, j);
1833
1834    j = (RD_HARPOON(ioport+hp_ee_ctrl) & ~SCSI_TERM_ENA_H);
1835    if (i & HIGH_BYTE_TERM)
1836       j |= SCSI_TERM_ENA_H;
1837    WR_HARPOON(ioport+hp_ee_ctrl, j );
1838
1839
1840    if (!(pCardInfo->si_flags & SOFT_RESET)) {
1841
1842       FPT_sresb(ioport,thisCard);
1843
1844          FPT_scini(thisCard, pCardInfo->si_id, 0);
1845       }
1846
1847
1848
1849    if (pCardInfo->si_flags & POST_ALL_UNDERRRUNS)
1850       CurrCard->globalFlags |= F_NO_FILTER;
1851
1852         if(pCurrNvRam){
1853                 if(pCurrNvRam->niSysConf & 0x10)
1854                         CurrCard->globalFlags |= F_GREEN_PC;
1855         }
1856         else{
1857            if (FPT_utilEERead(ioport, (SYSTEM_CONFIG/2)) & GREEN_PC_ENA)
1858            CurrCard->globalFlags |= F_GREEN_PC;
1859         }
1860
1861         /* Set global flag to indicate Re-Negotiation to be done on all
1862                 ckeck condition */
1863         if(pCurrNvRam){
1864                 if(pCurrNvRam->niScsiConf & 0x04)
1865                         CurrCard->globalFlags |= F_DO_RENEGO;
1866         }
1867         else{
1868            if (FPT_utilEERead(ioport, (SCSI_CONFIG/2)) & RENEGO_ENA)
1869            CurrCard->globalFlags |= F_DO_RENEGO;
1870         }
1871
1872         if(pCurrNvRam){
1873                 if(pCurrNvRam->niScsiConf & 0x08)
1874                         CurrCard->globalFlags |= F_CONLUN_IO;
1875         }
1876         else{
1877            if (FPT_utilEERead(ioport, (SCSI_CONFIG/2)) & CONNIO_ENA)
1878            CurrCard->globalFlags |= F_CONLUN_IO;
1879         }
1880
1881
1882    temp = pCardInfo->si_per_targ_no_disc;
1883
1884    for (i = 0,id = 1; i < MAX_SCSI_TAR; i++, id <<= 1) {
1885
1886       if (temp & id)
1887          FPT_sccbMgrTbl[thisCard][i].TarStatus |= TAR_ALLOW_DISC;
1888       }
1889
1890    sync_bit_map = 0x0001;
1891
1892    for (id = 0; id < (MAX_SCSI_TAR/2); id++) {
1893
1894                 if(pCurrNvRam){
1895                         temp = (USHORT) pCurrNvRam->niSyncTbl[id];
1896                         temp = ((temp & 0x03) + ((temp << 4) & 0xc0)) +
1897                                          (((temp << 4) & 0x0300) + ((temp << 8) & 0xc000));
1898                 }else
1899               temp = FPT_utilEERead(ioport, (USHORT)((SYNC_RATE_TBL/2)+id));
1900
1901       for (i = 0; i < 2; temp >>=8,i++) {
1902
1903          if (pCardInfo->si_per_targ_init_sync & sync_bit_map) {
1904
1905             FPT_sccbMgrTbl[thisCard][id*2+i].TarEEValue = (UCHAR)temp;
1906             }
1907
1908          else {
1909             FPT_sccbMgrTbl[thisCard][id*2+i].TarStatus |= SYNC_SUPPORTED;
1910             FPT_sccbMgrTbl[thisCard][id*2+i].TarEEValue =
1911                (UCHAR)(temp & ~EE_SYNC_MASK);
1912             }
1913
1914 /*         if ((pCardInfo->si_per_targ_wide_nego & sync_bit_map) ||
1915             (id*2+i >= 8)){
1916 */
1917          if (pCardInfo->si_per_targ_wide_nego & sync_bit_map){
1918
1919             FPT_sccbMgrTbl[thisCard][id*2+i].TarEEValue |= EE_WIDE_SCSI;
1920
1921             }
1922
1923          else { /* NARROW SCSI */
1924             FPT_sccbMgrTbl[thisCard][id*2+i].TarStatus |= WIDE_NEGOCIATED;
1925             }
1926
1927
1928          sync_bit_map <<= 1;
1929
1930
1931
1932          }
1933       }
1934
1935    WR_HARPOON((ioport+hp_semaphore),
1936       (UCHAR)(RD_HARPOON((ioport+hp_semaphore)) | SCCB_MGR_PRESENT));
1937
1938    return((ULONG)CurrCard);
1939 }
1940
1941 static void SccbMgr_unload_card(ULONG pCurrCard)
1942 {
1943         UCHAR i;
1944         ULONG portBase;
1945         ULONG regOffset;
1946         ULONG scamData;
1947         ULONG *pScamTbl;
1948         PNVRamInfo pCurrNvRam;
1949
1950         pCurrNvRam = ((PSCCBcard)pCurrCard)->pNvRamInfo;
1951
1952         if(pCurrNvRam){
1953                 FPT_WrStack(pCurrNvRam->niBaseAddr, 0, pCurrNvRam->niModel);
1954                 FPT_WrStack(pCurrNvRam->niBaseAddr, 1, pCurrNvRam->niSysConf);
1955                 FPT_WrStack(pCurrNvRam->niBaseAddr, 2, pCurrNvRam->niScsiConf);
1956                 FPT_WrStack(pCurrNvRam->niBaseAddr, 3, pCurrNvRam->niScamConf);
1957                 FPT_WrStack(pCurrNvRam->niBaseAddr, 4, pCurrNvRam->niAdapId);
1958
1959                 for(i = 0; i < MAX_SCSI_TAR / 2; i++)
1960                         FPT_WrStack(pCurrNvRam->niBaseAddr, (UCHAR)(i+5), pCurrNvRam->niSyncTbl[i]);
1961
1962                 portBase = pCurrNvRam->niBaseAddr;
1963
1964                 for(i = 0; i < MAX_SCSI_TAR; i++){
1965                         regOffset = hp_aramBase + 64 + i*4;
1966                         pScamTbl = (ULONG *) &pCurrNvRam->niScamTbl[i];
1967                         scamData = *pScamTbl;
1968                         WR_HARP32(portBase, regOffset, scamData);
1969                 }
1970
1971         }else{
1972                 FPT_WrStack(((PSCCBcard)pCurrCard)->ioPort, 0, 0);
1973         }
1974 }
1975
1976
1977 static void FPT_RNVRamData(PNVRamInfo pNvRamInfo)
1978 {
1979         UCHAR i;
1980         ULONG portBase;
1981         ULONG regOffset;
1982         ULONG scamData;
1983         ULONG *pScamTbl;
1984
1985         pNvRamInfo->niModel    = FPT_RdStack(pNvRamInfo->niBaseAddr, 0);
1986         pNvRamInfo->niSysConf  = FPT_RdStack(pNvRamInfo->niBaseAddr, 1);
1987         pNvRamInfo->niScsiConf = FPT_RdStack(pNvRamInfo->niBaseAddr, 2);
1988         pNvRamInfo->niScamConf = FPT_RdStack(pNvRamInfo->niBaseAddr, 3);
1989         pNvRamInfo->niAdapId   = FPT_RdStack(pNvRamInfo->niBaseAddr, 4);
1990
1991         for(i = 0; i < MAX_SCSI_TAR / 2; i++)
1992                 pNvRamInfo->niSyncTbl[i] = FPT_RdStack(pNvRamInfo->niBaseAddr, (UCHAR)(i+5));
1993
1994         portBase = pNvRamInfo->niBaseAddr;
1995
1996         for(i = 0; i < MAX_SCSI_TAR; i++){
1997                 regOffset = hp_aramBase + 64 + i*4;
1998                 RD_HARP32(portBase, regOffset, scamData);
1999                 pScamTbl = (ULONG *) &pNvRamInfo->niScamTbl[i];
2000                 *pScamTbl = scamData;
2001         }
2002
2003 }
2004
2005 static UCHAR FPT_RdStack(ULONG portBase, UCHAR index)
2006 {
2007         WR_HARPOON(portBase + hp_stack_addr, index);
2008         return(RD_HARPOON(portBase + hp_stack_data));
2009 }
2010
2011 static void FPT_WrStack(ULONG portBase, UCHAR index, UCHAR data)
2012 {
2013         WR_HARPOON(portBase + hp_stack_addr, index);
2014         WR_HARPOON(portBase + hp_stack_data, data);
2015 }
2016
2017
2018 static UCHAR FPT_ChkIfChipInitialized(ULONG ioPort)
2019 {
2020         if((RD_HARPOON(ioPort + hp_arb_id) & 0x0f) != FPT_RdStack(ioPort, 4))
2021                 return(0);
2022         if((RD_HARPOON(ioPort + hp_clkctrl_0) & CLKCTRL_DEFAULT)
2023                                                                 != CLKCTRL_DEFAULT)
2024                 return(0);
2025         if((RD_HARPOON(ioPort + hp_seltimeout) == TO_250ms) ||
2026                 (RD_HARPOON(ioPort + hp_seltimeout) == TO_290ms))
2027                 return(1);
2028         return(0);
2029
2030 }
2031 /*---------------------------------------------------------------------
2032  *
2033  * Function: SccbMgr_start_sccb
2034  *
2035  * Description: Start a command pointed to by p_Sccb. When the
2036  *              command is completed it will be returned via the
2037  *              callback function.
2038  *
2039  *---------------------------------------------------------------------*/
2040 static void SccbMgr_start_sccb(ULONG pCurrCard, PSCCB p_Sccb)
2041 {
2042    ULONG ioport;
2043    UCHAR thisCard, lun;
2044         PSCCB pSaveSccb;
2045    CALL_BK_FN callback;
2046
2047    thisCard = ((PSCCBcard) pCurrCard)->cardIndex;
2048    ioport = ((PSCCBcard) pCurrCard)->ioPort;
2049
2050         if((p_Sccb->TargID > MAX_SCSI_TAR) || (p_Sccb->Lun > MAX_LUN))
2051         {
2052
2053                 p_Sccb->HostStatus = SCCB_COMPLETE;
2054                 p_Sccb->SccbStatus = SCCB_ERROR;
2055                 callback = (CALL_BK_FN)p_Sccb->SccbCallback;
2056                 if (callback)
2057                         callback(p_Sccb);
2058
2059                 return;
2060         }
2061
2062    FPT_sinits(p_Sccb,thisCard);
2063
2064
2065    if (!((PSCCBcard) pCurrCard)->cmdCounter)
2066       {
2067       WR_HARPOON(ioport+hp_semaphore, (RD_HARPOON(ioport+hp_semaphore)
2068          | SCCB_MGR_ACTIVE));
2069
2070       if (((PSCCBcard) pCurrCard)->globalFlags & F_GREEN_PC)
2071          {
2072                  WR_HARPOON(ioport+hp_clkctrl_0, CLKCTRL_DEFAULT);
2073                  WR_HARPOON(ioport+hp_sys_ctrl, 0x00);
2074          }
2075       }
2076
2077    ((PSCCBcard)pCurrCard)->cmdCounter++;
2078
2079    if (RD_HARPOON(ioport+hp_semaphore) & BIOS_IN_USE) {
2080
2081       WR_HARPOON(ioport+hp_semaphore, (RD_HARPOON(ioport+hp_semaphore)
2082          | TICKLE_ME));
2083                 if(p_Sccb->OperationCode == RESET_COMMAND)
2084                         {
2085                                 pSaveSccb = ((PSCCBcard) pCurrCard)->currentSCCB;
2086                                 ((PSCCBcard) pCurrCard)->currentSCCB = p_Sccb;
2087                                 FPT_queueSelectFail(&FPT_BL_Card[thisCard], thisCard);
2088                                 ((PSCCBcard) pCurrCard)->currentSCCB = pSaveSccb;
2089                         }
2090                 else
2091                         {
2092               FPT_queueAddSccb(p_Sccb,thisCard);
2093                         }
2094       }
2095
2096    else if ((RD_HARPOON(ioport+hp_page_ctrl) & G_INT_DISABLE)) {
2097
2098                         if(p_Sccb->OperationCode == RESET_COMMAND)
2099                                 {
2100                                         pSaveSccb = ((PSCCBcard) pCurrCard)->currentSCCB;
2101                                         ((PSCCBcard) pCurrCard)->currentSCCB = p_Sccb;
2102                                         FPT_queueSelectFail(&FPT_BL_Card[thisCard], thisCard);
2103                                         ((PSCCBcard) pCurrCard)->currentSCCB = pSaveSccb;
2104                                 }
2105                         else
2106                                 {
2107                       FPT_queueAddSccb(p_Sccb,thisCard);
2108                                 }
2109       }
2110
2111    else {
2112
2113       MDISABLE_INT(ioport);
2114
2115                 if((((PSCCBcard) pCurrCard)->globalFlags & F_CONLUN_IO) && 
2116                         ((FPT_sccbMgrTbl[thisCard][p_Sccb->TargID].TarStatus & TAR_TAG_Q_MASK) != TAG_Q_TRYING))
2117                         lun = p_Sccb->Lun;
2118                 else
2119                         lun = 0;
2120       if ((((PSCCBcard) pCurrCard)->currentSCCB == NULL) &&
2121          (FPT_sccbMgrTbl[thisCard][p_Sccb->TargID].TarSelQ_Cnt == 0) &&
2122          (FPT_sccbMgrTbl[thisCard][p_Sccb->TargID].TarLUNBusy[lun]
2123          == 0)) {
2124
2125             ((PSCCBcard) pCurrCard)->currentSCCB = p_Sccb;
2126             FPT_ssel(p_Sccb->SccbIOPort,thisCard);
2127          }
2128
2129       else {
2130
2131                         if(p_Sccb->OperationCode == RESET_COMMAND)
2132                                 {
2133                                         pSaveSccb = ((PSCCBcard) pCurrCard)->currentSCCB;
2134                                         ((PSCCBcard) pCurrCard)->currentSCCB = p_Sccb;
2135                                         FPT_queueSelectFail(&FPT_BL_Card[thisCard], thisCard);
2136                                         ((PSCCBcard) pCurrCard)->currentSCCB = pSaveSccb;
2137                                 }
2138                         else
2139                                 {
2140                         FPT_queueAddSccb(p_Sccb,thisCard);
2141                                 }
2142          }
2143
2144
2145       MENABLE_INT(ioport);
2146       }
2147
2148 }
2149
2150
2151 /*---------------------------------------------------------------------
2152  *
2153  * Function: SccbMgr_abort_sccb
2154  *
2155  * Description: Abort the command pointed to by p_Sccb.  When the
2156  *              command is completed it will be returned via the
2157  *              callback function.
2158  *
2159  *---------------------------------------------------------------------*/
2160 static int SccbMgr_abort_sccb(ULONG pCurrCard, PSCCB p_Sccb)
2161 {
2162         ULONG ioport;
2163
2164         UCHAR thisCard;
2165         CALL_BK_FN callback;
2166         UCHAR TID;
2167         PSCCB pSaveSCCB;
2168         PSCCBMgr_tar_info currTar_Info;
2169
2170
2171         ioport = ((PSCCBcard) pCurrCard)->ioPort;
2172
2173         thisCard = ((PSCCBcard)pCurrCard)->cardIndex;
2174
2175         if (!(RD_HARPOON(ioport+hp_page_ctrl) & G_INT_DISABLE))
2176         {
2177
2178                 if (FPT_queueFindSccb(p_Sccb,thisCard))
2179                 {
2180
2181                         ((PSCCBcard)pCurrCard)->cmdCounter--;
2182
2183                         if (!((PSCCBcard)pCurrCard)->cmdCounter)
2184                                 WR_HARPOON(ioport+hp_semaphore,(RD_HARPOON(ioport+hp_semaphore)
2185                                         & (UCHAR)(~(SCCB_MGR_ACTIVE | TICKLE_ME)) ));
2186
2187                         p_Sccb->SccbStatus = SCCB_ABORT;
2188                         callback = p_Sccb->SccbCallback;
2189                         callback(p_Sccb);
2190
2191                         return(0);
2192                 }
2193
2194                 else
2195                 {
2196                         if (((PSCCBcard)pCurrCard)->currentSCCB == p_Sccb)
2197                         {
2198                                 p_Sccb->SccbStatus = SCCB_ABORT;
2199                                 return(0);
2200
2201                         }
2202
2203                         else
2204                         {
2205
2206                                 TID = p_Sccb->TargID;
2207
2208
2209                                 if(p_Sccb->Sccb_tag)
2210                                 {
2211                                         MDISABLE_INT(ioport);
2212                                         if (((PSCCBcard) pCurrCard)->discQ_Tbl[p_Sccb->Sccb_tag]==p_Sccb)
2213                                         {
2214                                                 p_Sccb->SccbStatus = SCCB_ABORT;
2215                                                 p_Sccb->Sccb_scsistat = ABORT_ST;
2216                                                 p_Sccb->Sccb_scsimsg = SMABORT_TAG;
2217
2218                                                 if(((PSCCBcard) pCurrCard)->currentSCCB == NULL)
2219                                                 {
2220                                                         ((PSCCBcard) pCurrCard)->currentSCCB = p_Sccb;
2221                                                         FPT_ssel(ioport, thisCard);
2222                                                 }
2223                                                 else
2224                                                 {
2225                                                         pSaveSCCB = ((PSCCBcard) pCurrCard)->currentSCCB;
2226                                                         ((PSCCBcard) pCurrCard)->currentSCCB = p_Sccb;
2227                                                         FPT_queueSelectFail((PSCCBcard) pCurrCard, thisCard);
2228                                                         ((PSCCBcard) pCurrCard)->currentSCCB = pSaveSCCB;
2229                                                 }
2230                                         }
2231                                         MENABLE_INT(ioport);
2232                                         return(0);
2233                                 }
2234                                 else
2235                                 {
2236                                         currTar_Info = &FPT_sccbMgrTbl[thisCard][p_Sccb->TargID];
2237
2238                                         if(FPT_BL_Card[thisCard].discQ_Tbl[currTar_Info->LunDiscQ_Idx[p_Sccb->Lun]] 
2239                                                         == p_Sccb)
2240                                         {
2241                                                 p_Sccb->SccbStatus = SCCB_ABORT;
2242                                                 return(0);
2243                                         }
2244                                 }
2245                         }
2246                 }
2247         }
2248         return(-1);
2249 }
2250
2251
2252 /*---------------------------------------------------------------------
2253  *
2254  * Function: SccbMgr_my_int
2255  *
2256  * Description: Do a quick check to determine if there is a pending
2257  *              interrupt for this card and disable the IRQ Pin if so.
2258  *
2259  *---------------------------------------------------------------------*/
2260 static UCHAR SccbMgr_my_int(ULONG pCurrCard)
2261 {
2262    ULONG ioport;
2263
2264    ioport = ((PSCCBcard)pCurrCard)->ioPort;
2265
2266    if (RD_HARPOON(ioport+hp_int_status) & INT_ASSERTED)
2267    {
2268       return(1);
2269    }
2270
2271    else
2272
2273       return(0);
2274 }
2275
2276
2277
2278 /*---------------------------------------------------------------------
2279  *
2280  * Function: SccbMgr_isr
2281  *
2282  * Description: This is our entry point when an interrupt is generated
2283  *              by the card and the upper level driver passes it on to
2284  *              us.
2285  *
2286  *---------------------------------------------------------------------*/
2287 static int SccbMgr_isr(ULONG pCurrCard)
2288 {
2289    PSCCB currSCCB;
2290    UCHAR thisCard,result,bm_status, bm_int_st;
2291    USHORT hp_int;
2292    UCHAR i, target;
2293    ULONG ioport;
2294
2295    thisCard = ((PSCCBcard)pCurrCard)->cardIndex;
2296    ioport = ((PSCCBcard)pCurrCard)->ioPort;
2297
2298    MDISABLE_INT(ioport);
2299
2300    if ((bm_int_st=RD_HARPOON(ioport+hp_int_status)) & EXT_STATUS_ON)
2301                 bm_status = RD_HARPOON(ioport+hp_ext_status) & (UCHAR)BAD_EXT_STATUS;
2302    else
2303       bm_status = 0;
2304
2305    WR_HARPOON(ioport+hp_int_mask, (INT_CMD_COMPL | SCSI_INTERRUPT));
2306
2307    while ((hp_int = RDW_HARPOON((ioport+hp_intstat)) & FPT_default_intena) |
2308           bm_status)
2309      {
2310
2311        currSCCB = ((PSCCBcard)pCurrCard)->currentSCCB;
2312
2313       if (hp_int & (FIFO | TIMEOUT | RESET | SCAM_SEL) || bm_status) {
2314          result = FPT_SccbMgr_bad_isr(ioport,thisCard,((PSCCBcard)pCurrCard),hp_int);
2315          WRW_HARPOON((ioport+hp_intstat), (FIFO | TIMEOUT | RESET | SCAM_SEL));
2316          bm_status = 0;
2317
2318          if (result) {
2319
2320             MENABLE_INT(ioport);
2321             return(result);
2322             }
2323          }
2324
2325
2326       else if (hp_int & ICMD_COMP) {
2327
2328          if ( !(hp_int & BUS_FREE) ) {
2329             /* Wait for the BusFree before starting a new command.  We
2330                must also check for being reselected since the BusFree
2331                may not show up if another device reselects us in 1.5us or
2332                less.  SRR Wednesday, 3/8/1995.
2333                  */
2334            while (!(RDW_HARPOON((ioport+hp_intstat)) & (BUS_FREE | RSEL))) ;
2335          }
2336
2337          if (((PSCCBcard)pCurrCard)->globalFlags & F_HOST_XFER_ACT)
2338
2339             FPT_phaseChkFifo(ioport, thisCard);
2340
2341 /*         WRW_HARPOON((ioport+hp_intstat),
2342             (BUS_FREE | ICMD_COMP | ITAR_DISC | XFER_CNT_0));
2343          */
2344
2345                  WRW_HARPOON((ioport+hp_intstat), CLR_ALL_INT_1);
2346
2347          FPT_autoCmdCmplt(ioport,thisCard);
2348
2349          }
2350
2351
2352       else if (hp_int & ITAR_DISC)
2353          {
2354
2355          if (((PSCCBcard)pCurrCard)->globalFlags & F_HOST_XFER_ACT) {
2356
2357             FPT_phaseChkFifo(ioport, thisCard);
2358
2359             }
2360
2361          if (RD_HARPOON(ioport+hp_gp_reg_1) == SMSAVE_DATA_PTR) {
2362
2363             WR_HARPOON(ioport+hp_gp_reg_1, 0x00);
2364             currSCCB->Sccb_XferState |= F_NO_DATA_YET;
2365
2366             currSCCB->Sccb_savedATC = currSCCB->Sccb_ATC;
2367             }
2368
2369          currSCCB->Sccb_scsistat = DISCONNECT_ST;
2370          FPT_queueDisconnect(currSCCB,thisCard);
2371
2372             /* Wait for the BusFree before starting a new command.  We
2373                must also check for being reselected since the BusFree
2374                may not show up if another device reselects us in 1.5us or
2375                less.  SRR Wednesday, 3/8/1995.
2376              */
2377            while (!(RDW_HARPOON((ioport+hp_intstat)) & (BUS_FREE | RSEL)) &&
2378                   !((RDW_HARPOON((ioport+hp_intstat)) & PHASE) &&
2379                     RD_HARPOON((ioport+hp_scsisig)) ==
2380                     (SCSI_BSY | SCSI_REQ | SCSI_CD | SCSI_MSG | SCSI_IOBIT))) ;
2381
2382            /*
2383              The additional loop exit condition above detects a timing problem
2384              with the revision D/E harpoon chips.  The caller should reset the
2385              host adapter to recover when 0xFE is returned.
2386            */
2387            if (!(RDW_HARPOON((ioport+hp_intstat)) & (BUS_FREE | RSEL)))
2388              {
2389                MENABLE_INT(ioport);
2390                return 0xFE;
2391              }
2392
2393          WRW_HARPOON((ioport+hp_intstat), (BUS_FREE | ITAR_DISC));
2394
2395
2396          ((PSCCBcard)pCurrCard)->globalFlags |= F_NEW_SCCB_CMD;
2397
2398         }
2399
2400
2401       else if (hp_int & RSEL) {
2402
2403          WRW_HARPOON((ioport+hp_intstat), (PROG_HLT | RSEL | PHASE | BUS_FREE));
2404
2405          if (RDW_HARPOON((ioport+hp_intstat)) & ITAR_DISC)
2406                       {
2407             if (((PSCCBcard)pCurrCard)->globalFlags & F_HOST_XFER_ACT)
2408                               {
2409                FPT_phaseChkFifo(ioport, thisCard);
2410                }
2411
2412             if (RD_HARPOON(ioport+hp_gp_reg_1) == SMSAVE_DATA_PTR)
2413                               {
2414                WR_HARPOON(ioport+hp_gp_reg_1, 0x00);
2415                currSCCB->Sccb_XferState |= F_NO_DATA_YET;
2416                currSCCB->Sccb_savedATC = currSCCB->Sccb_ATC;
2417                }
2418
2419             WRW_HARPOON((ioport+hp_intstat), (BUS_FREE | ITAR_DISC));
2420             currSCCB->Sccb_scsistat = DISCONNECT_ST;
2421             FPT_queueDisconnect(currSCCB,thisCard);
2422             }
2423
2424          FPT_sres(ioport,thisCard,((PSCCBcard)pCurrCard));
2425          FPT_phaseDecode(ioport,thisCard);
2426
2427          }
2428
2429
2430       else if ((hp_int & IDO_STRT) && (!(hp_int & BUS_FREE)))
2431          {
2432
2433             WRW_HARPOON((ioport+hp_intstat), (IDO_STRT | XFER_CNT_0));
2434             FPT_phaseDecode(ioport,thisCard);
2435
2436          }
2437
2438
2439       else if ( (hp_int & IUNKWN) || (hp_int & PROG_HLT) )
2440                    {
2441                    WRW_HARPOON((ioport+hp_intstat), (PHASE | IUNKWN | PROG_HLT));
2442                    if ((RD_HARPOON(ioport+hp_prgmcnt_0) & (UCHAR)0x3f)< (UCHAR)SELCHK)
2443                         {
2444                         FPT_phaseDecode(ioport,thisCard);
2445                         }
2446                    else
2447                         {
2448    /* Harpoon problem some SCSI target device respond to selection
2449    with short BUSY pulse (<400ns) this will make the Harpoon is not able
2450    to latch the correct Target ID into reg. x53.
2451    The work around require to correct this reg. But when write to this
2452    reg. (0x53) also increment the FIFO write addr reg (0x6f), thus we
2453    need to read this reg first then restore it later. After update to 0x53 */
2454
2455                         i = (UCHAR)(RD_HARPOON(ioport+hp_fifowrite));
2456                         target = (UCHAR)(RD_HARPOON(ioport+hp_gp_reg_3));
2457                         WR_HARPOON(ioport+hp_xfer_pad, (UCHAR) ID_UNLOCK);
2458                         WR_HARPOON(ioport+hp_select_id, (UCHAR)(target | target<<4));
2459                         WR_HARPOON(ioport+hp_xfer_pad, (UCHAR) 0x00);
2460                         WR_HARPOON(ioport+hp_fifowrite, i);
2461                         WR_HARPOON(ioport+hp_autostart_3, (AUTO_IMMED+TAG_STRT));
2462                         }
2463                    }
2464
2465       else if (hp_int & XFER_CNT_0) {
2466
2467          WRW_HARPOON((ioport+hp_intstat), XFER_CNT_0);
2468
2469          FPT_schkdd(ioport,thisCard);
2470
2471          }
2472
2473
2474       else if (hp_int & BUS_FREE) {
2475
2476          WRW_HARPOON((ioport+hp_intstat), BUS_FREE);
2477
2478                 if (((PSCCBcard)pCurrCard)->globalFlags & F_HOST_XFER_ACT) {
2479
2480                 FPT_hostDataXferAbort(ioport,thisCard,currSCCB);
2481                                 }
2482
2483          FPT_phaseBusFree(ioport,thisCard);
2484                         }
2485
2486
2487       else if (hp_int & ITICKLE) {
2488
2489          WRW_HARPOON((ioport+hp_intstat), ITICKLE);
2490          ((PSCCBcard)pCurrCard)->globalFlags |= F_NEW_SCCB_CMD;
2491          }
2492
2493
2494
2495       if (((PSCCBcard)pCurrCard)->globalFlags & F_NEW_SCCB_CMD) {
2496
2497
2498          ((PSCCBcard)pCurrCard)->globalFlags &= ~F_NEW_SCCB_CMD;
2499
2500
2501          if (((PSCCBcard)pCurrCard)->currentSCCB == NULL) {
2502
2503             FPT_queueSearchSelect(((PSCCBcard)pCurrCard),thisCard);
2504             }
2505
2506          if (((PSCCBcard)pCurrCard)->currentSCCB != NULL) {
2507             ((PSCCBcard)pCurrCard)->globalFlags &= ~F_NEW_SCCB_CMD;
2508             FPT_ssel(ioport,thisCard);
2509             }
2510
2511          break;
2512
2513          }
2514
2515       }  /*end while */
2516
2517    MENABLE_INT(ioport);
2518
2519    return(0);
2520 }
2521
2522 /*---------------------------------------------------------------------
2523  *
2524  * Function: Sccb_bad_isr
2525  *
2526  * Description: Some type of interrupt has occurred which is slightly
2527  *              out of the ordinary.  We will now decode it fully, in
2528  *              this routine.  This is broken up in an attempt to save
2529  *              processing time.
2530  *
2531  *---------------------------------------------------------------------*/
2532 static UCHAR FPT_SccbMgr_bad_isr(ULONG p_port, UCHAR p_card,
2533                                  PSCCBcard pCurrCard, USHORT p_int)
2534 {
2535    UCHAR temp, ScamFlg;
2536    PSCCBMgr_tar_info currTar_Info;
2537    PNVRamInfo pCurrNvRam;
2538
2539
2540    if (RD_HARPOON(p_port+hp_ext_status) &
2541          (BM_FORCE_OFF | PCI_DEV_TMOUT | BM_PARITY_ERR | PIO_OVERRUN) )
2542       {
2543
2544       if (pCurrCard->globalFlags & F_HOST_XFER_ACT)
2545          {
2546
2547          FPT_hostDataXferAbort(p_port,p_card, pCurrCard->currentSCCB);
2548          }
2549
2550       if (RD_HARPOON(p_port+hp_pci_stat_cfg) & REC_MASTER_ABORT)
2551
2552          {
2553          WR_HARPOON(p_port+hp_pci_stat_cfg,
2554             (RD_HARPOON(p_port+hp_pci_stat_cfg) & ~REC_MASTER_ABORT));
2555
2556          WR_HARPOON(p_port+hp_host_blk_cnt, 0x00);
2557
2558          }
2559
2560       if (pCurrCard->currentSCCB != NULL)
2561          {
2562
2563          if (!pCurrCard->currentSCCB->HostStatus)
2564             pCurrCard->currentSCCB->HostStatus = SCCB_BM_ERR;
2565
2566          FPT_sxfrp(p_port,p_card);
2567
2568              temp = (UCHAR)(RD_HARPOON(p_port+hp_ee_ctrl) &
2569                                                         (EXT_ARB_ACK | SCSI_TERM_ENA_H));
2570         WR_HARPOON(p_port+hp_ee_ctrl, ((UCHAR)temp | SEE_MS | SEE_CS));
2571          WR_HARPOON(p_port+hp_ee_ctrl, temp);
2572
2573          if (!(RDW_HARPOON((p_port+hp_intstat)) & (BUS_FREE | RESET)))
2574             {
2575             FPT_phaseDecode(p_port,p_card);
2576             }
2577          }
2578       }
2579
2580
2581    else if (p_int & RESET)
2582          {
2583
2584                                 WR_HARPOON(p_port+hp_clkctrl_0, CLKCTRL_DEFAULT);
2585                                 WR_HARPOON(p_port+hp_sys_ctrl, 0x00);
2586            if (pCurrCard->currentSCCB != NULL) {
2587
2588                if (pCurrCard->globalFlags & F_HOST_XFER_ACT)
2589
2590                FPT_hostDataXferAbort(p_port,p_card, pCurrCard->currentSCCB);
2591                }
2592
2593
2594            DISABLE_AUTO(p_port);
2595
2596            FPT_sresb(p_port,p_card);
2597
2598            while(RD_HARPOON(p_port+hp_scsictrl_0) & SCSI_RST) {}
2599
2600                                 pCurrNvRam = pCurrCard->pNvRamInfo;
2601                                 if(pCurrNvRam){
2602                                         ScamFlg = pCurrNvRam->niScamConf;
2603                                 }
2604                                 else{
2605                                    ScamFlg = (UCHAR) FPT_utilEERead(p_port, SCAM_CONFIG/2);
2606                                 }
2607
2608            FPT_XbowInit(p_port, ScamFlg);
2609
2610                FPT_scini(p_card, pCurrCard->ourId, 0);
2611
2612            return(0xFF);
2613          }
2614
2615
2616    else if (p_int & FIFO) {
2617
2618       WRW_HARPOON((p_port+hp_intstat), FIFO);
2619
2620       if (pCurrCard->currentSCCB != NULL)
2621          FPT_sxfrp(p_port,p_card);
2622       }
2623
2624    else if (p_int & TIMEOUT)
2625       {
2626
2627       DISABLE_AUTO(p_port);
2628
2629       WRW_HARPOON((p_port+hp_intstat),
2630                   (PROG_HLT | TIMEOUT | SEL |BUS_FREE | PHASE | IUNKWN));
2631
2632       pCurrCard->currentSCCB->HostStatus = SCCB_SELECTION_TIMEOUT;
2633
2634
2635                 currTar_Info = &FPT_sccbMgrTbl[p_card][pCurrCard->currentSCCB->TargID];
2636                 if((pCurrCard->globalFlags & F_CONLUN_IO) &&
2637                         ((currTar_Info->TarStatus & TAR_TAG_Q_MASK) != TAG_Q_TRYING))
2638               currTar_Info->TarLUNBusy[pCurrCard->currentSCCB->Lun] = 0;
2639                 else
2640               currTar_Info->TarLUNBusy[0] = 0;
2641
2642
2643       if (currTar_Info->TarEEValue & EE_SYNC_MASK)
2644          {
2645                currTar_Info->TarSyncCtrl = 0;
2646          currTar_Info->TarStatus &= ~TAR_SYNC_MASK;
2647          }
2648
2649       if (currTar_Info->TarEEValue & EE_WIDE_SCSI)
2650          {
2651          currTar_Info->TarStatus &= ~TAR_WIDE_MASK;
2652          }
2653
2654       FPT_sssyncv(p_port, pCurrCard->currentSCCB->TargID, NARROW_SCSI,currTar_Info);
2655
2656       FPT_queueCmdComplete(pCurrCard, pCurrCard->currentSCCB, p_card);
2657
2658       }
2659
2660    else if (p_int & SCAM_SEL)
2661       {
2662
2663       FPT_scarb(p_port,LEVEL2_TAR);
2664       FPT_scsel(p_port);
2665       FPT_scasid(p_card, p_port);
2666
2667       FPT_scbusf(p_port);
2668
2669       WRW_HARPOON((p_port+hp_intstat), SCAM_SEL);
2670       }
2671
2672    return(0x00);
2673 }
2674
2675
2676 /*---------------------------------------------------------------------
2677  *
2678  * Function: SccbMgrTableInit
2679  *
2680  * Description: Initialize all Sccb manager data structures.
2681  *
2682  *---------------------------------------------------------------------*/
2683
2684 static void FPT_SccbMgrTableInitAll()
2685 {
2686    UCHAR thisCard;
2687
2688    for (thisCard = 0; thisCard < MAX_CARDS; thisCard++)
2689       {
2690       FPT_SccbMgrTableInitCard(&FPT_BL_Card[thisCard],thisCard);
2691
2692       FPT_BL_Card[thisCard].ioPort      = 0x00;
2693       FPT_BL_Card[thisCard].cardInfo    = NULL;
2694       FPT_BL_Card[thisCard].cardIndex   = 0xFF;
2695       FPT_BL_Card[thisCard].ourId       = 0x00;
2696                 FPT_BL_Card[thisCard].pNvRamInfo        = NULL;
2697       }
2698 }
2699
2700
2701 /*---------------------------------------------------------------------
2702  *
2703  * Function: SccbMgrTableInit
2704  *
2705  * Description: Initialize all Sccb manager data structures.
2706  *
2707  *---------------------------------------------------------------------*/
2708
2709 static void FPT_SccbMgrTableInitCard(PSCCBcard pCurrCard, UCHAR p_card)
2710 {
2711    UCHAR scsiID, qtag;
2712
2713         for (qtag = 0; qtag < QUEUE_DEPTH; qtag++)
2714         {
2715                 FPT_BL_Card[p_card].discQ_Tbl[qtag] = NULL;
2716         }
2717
2718    for (scsiID = 0; scsiID < MAX_SCSI_TAR; scsiID++)
2719       {
2720       FPT_sccbMgrTbl[p_card][scsiID].TarStatus = 0;
2721       FPT_sccbMgrTbl[p_card][scsiID].TarEEValue = 0;
2722       FPT_SccbMgrTableInitTarget(p_card, scsiID);
2723       }
2724
2725    pCurrCard->scanIndex = 0x00;
2726    pCurrCard->currentSCCB = NULL;
2727    pCurrCard->globalFlags = 0x00;
2728    pCurrCard->cmdCounter  = 0x00;
2729         pCurrCard->tagQ_Lst = 0x01;
2730         pCurrCard->discQCount = 0; 
2731
2732
2733 }
2734
2735
2736 /*---------------------------------------------------------------------
2737  *
2738  * Function: SccbMgrTableInit
2739  *
2740  * Description: Initialize all Sccb manager data structures.
2741  *
2742  *---------------------------------------------------------------------*/
2743
2744 static void FPT_SccbMgrTableInitTarget(UCHAR p_card, UCHAR target)
2745 {
2746
2747         UCHAR lun, qtag;
2748         PSCCBMgr_tar_info currTar_Info;
2749
2750         currTar_Info = &FPT_sccbMgrTbl[p_card][target];
2751
2752         currTar_Info->TarSelQ_Cnt = 0;
2753         currTar_Info->TarSyncCtrl = 0;
2754
2755         currTar_Info->TarSelQ_Head = NULL;
2756         currTar_Info->TarSelQ_Tail = NULL;
2757         currTar_Info->TarTagQ_Cnt = 0;
2758         currTar_Info->TarLUN_CA = 0;
2759
2760
2761         for (lun = 0; lun < MAX_LUN; lun++)
2762         {
2763                 currTar_Info->TarLUNBusy[lun] = 0;
2764                 currTar_Info->LunDiscQ_Idx[lun] = 0;
2765         }
2766
2767         for (qtag = 0; qtag < QUEUE_DEPTH; qtag++)
2768         {
2769                 if(FPT_BL_Card[p_card].discQ_Tbl[qtag] != NULL)
2770                 {
2771                         if(FPT_BL_Card[p_card].discQ_Tbl[qtag]->TargID == target)
2772                         {
2773                                 FPT_BL_Card[p_card].discQ_Tbl[qtag] = NULL;
2774                                 FPT_BL_Card[p_card].discQCount--;
2775                         }
2776                 }
2777         }
2778 }
2779
2780
2781 /*---------------------------------------------------------------------
2782  *
2783  * Function: sfetm
2784  *
2785  * Description: Read in a message byte from the SCSI bus, and check
2786  *              for a parity error.
2787  *
2788  *---------------------------------------------------------------------*/
2789
2790 static UCHAR FPT_sfm(ULONG port, PSCCB pCurrSCCB)
2791 {
2792         UCHAR message;
2793         USHORT TimeOutLoop;
2794
2795         TimeOutLoop = 0;
2796         while( (!(RD_HARPOON(port+hp_scsisig) & SCSI_REQ)) &&
2797                         (TimeOutLoop++ < 20000) ){}
2798
2799
2800         WR_HARPOON(port+hp_portctrl_0, SCSI_PORT);
2801
2802         message = RD_HARPOON(port+hp_scsidata_0);
2803
2804         WR_HARPOON(port+hp_scsisig, SCSI_ACK + S_MSGI_PH);
2805
2806
2807         if (TimeOutLoop > 20000)
2808                 message = 0x00;   /* force message byte = 0 if Time Out on Req */
2809
2810         if ((RDW_HARPOON((port+hp_intstat)) & PARITY) &&
2811                 (RD_HARPOON(port+hp_addstat) & SCSI_PAR_ERR))
2812         {
2813                 WR_HARPOON(port+hp_scsisig, (SCSI_ACK + S_ILL_PH));
2814                 WR_HARPOON(port+hp_xferstat, 0);
2815                 WR_HARPOON(port+hp_fiforead, 0);
2816                 WR_HARPOON(port+hp_fifowrite, 0);
2817                 if (pCurrSCCB != NULL)
2818                 {
2819                         pCurrSCCB->Sccb_scsimsg = SMPARITY;
2820                 }
2821                 message = 0x00;
2822                 do
2823                 {
2824                         ACCEPT_MSG_ATN(port);
2825                         TimeOutLoop = 0;
2826                         while( (!(RD_HARPOON(port+hp_scsisig) & SCSI_REQ)) &&
2827                                 (TimeOutLoop++ < 20000) ){}
2828                         if (TimeOutLoop > 20000)
2829                         {
2830                                 WRW_HARPOON((port+hp_intstat), PARITY);
2831                                 return(message);
2832                         }
2833                         if ((RD_HARPOON(port+hp_scsisig) & S_SCSI_PHZ) != S_MSGI_PH)
2834                         {
2835                                 WRW_HARPOON((port+hp_intstat), PARITY);
2836                                 return(message);
2837                         }
2838                         WR_HARPOON(port+hp_portctrl_0, SCSI_PORT);
2839
2840                         RD_HARPOON(port+hp_scsidata_0);
2841
2842                         WR_HARPOON(port+hp_scsisig, (SCSI_ACK + S_ILL_PH));
2843
2844                 }while(1);
2845
2846         }
2847         WR_HARPOON(port+hp_scsisig, (SCSI_ACK + S_ILL_PH));
2848         WR_HARPOON(port+hp_xferstat, 0);
2849         WR_HARPOON(port+hp_fiforead, 0);
2850         WR_HARPOON(port+hp_fifowrite, 0);
2851         return(message);
2852 }
2853
2854
2855 /*---------------------------------------------------------------------
2856  *
2857  * Function: FPT_ssel
2858  *
2859  * Description: Load up automation and select target device.
2860  *
2861  *---------------------------------------------------------------------*/
2862
2863 static void FPT_ssel(ULONG port, UCHAR p_card)
2864 {
2865
2866    UCHAR auto_loaded, i, target, *theCCB;
2867
2868    ULONG cdb_reg;
2869    PSCCBcard CurrCard;
2870    PSCCB currSCCB;
2871    PSCCBMgr_tar_info currTar_Info;
2872    UCHAR lastTag, lun;
2873
2874    CurrCard = &FPT_BL_Card[p_card];
2875    currSCCB = CurrCard->currentSCCB;
2876    target = currSCCB->TargID;
2877    currTar_Info = &FPT_sccbMgrTbl[p_card][target];
2878    lastTag = CurrCard->tagQ_Lst;
2879
2880    ARAM_ACCESS(port);
2881
2882
2883         if ((currTar_Info->TarStatus & TAR_TAG_Q_MASK) == TAG_Q_REJECT)
2884                 currSCCB->ControlByte &= ~F_USE_CMD_Q;
2885
2886         if(((CurrCard->globalFlags & F_CONLUN_IO) && 
2887                 ((currTar_Info->TarStatus & TAR_TAG_Q_MASK) != TAG_Q_TRYING)))
2888
2889            lun = currSCCB->Lun;
2890         else
2891                 lun = 0;
2892
2893
2894    if (CurrCard->globalFlags & F_TAG_STARTED)
2895       {
2896       if (!(currSCCB->ControlByte & F_USE_CMD_Q))
2897          {
2898         if ((currTar_Info->TarLUN_CA == 0)
2899             && ((currTar_Info->TarStatus & TAR_TAG_Q_MASK)
2900             == TAG_Q_TRYING))
2901             {
2902
2903                  if (currTar_Info->TarTagQ_Cnt !=0)
2904                   {
2905                            currTar_Info->TarLUNBusy[lun] = 1;
2906                         FPT_queueSelectFail(CurrCard,p_card);
2907                                            SGRAM_ACCESS(port);
2908                            return;
2909                            }
2910
2911             else {
2912                           currTar_Info->TarLUNBusy[lun] = 1;
2913                           }
2914
2915               }  /*End non-tagged */
2916
2917               else {
2918                  currTar_Info->TarLUNBusy[lun] = 1;
2919                  }
2920
2921               }  /*!Use cmd Q Tagged */
2922
2923            else {
2924              if (currTar_Info->TarLUN_CA == 1)
2925                {
2926               FPT_queueSelectFail(CurrCard,p_card);
2927                                    SGRAM_ACCESS(port);
2928               return;
2929                     }
2930
2931                 currTar_Info->TarLUNBusy[lun] = 1;
2932
2933              }  /*else use cmd Q tagged */
2934
2935       }  /*if glob tagged started */
2936
2937    else {
2938         currTar_Info->TarLUNBusy[lun] = 1;
2939         }
2940
2941
2942
2943         if((((CurrCard->globalFlags & F_CONLUN_IO) && 
2944                 ((currTar_Info->TarStatus & TAR_TAG_Q_MASK) != TAG_Q_TRYING)) 
2945                 || (!(currSCCB->ControlByte & F_USE_CMD_Q))))
2946         {
2947                 if(CurrCard->discQCount >= QUEUE_DEPTH)
2948                 {
2949                         currTar_Info->TarLUNBusy[lun] = 1;
2950                         FPT_queueSelectFail(CurrCard,p_card);
2951                         SGRAM_ACCESS(port);
2952                         return;
2953                 }
2954                 for (i = 1; i < QUEUE_DEPTH; i++)
2955                 {
2956                         if (++lastTag >= QUEUE_DEPTH) lastTag = 1;
2957                         if (CurrCard->discQ_Tbl[lastTag] == NULL)
2958                         {
2959                                 CurrCard->tagQ_Lst = lastTag;
2960                                 currTar_Info->LunDiscQ_Idx[lun] = lastTag;
2961                                 CurrCard->discQ_Tbl[lastTag] = currSCCB;
2962                                 CurrCard->discQCount++;
2963                                 break;
2964                         }
2965                 }
2966                 if(i == QUEUE_DEPTH)
2967                 {
2968                         currTar_Info->TarLUNBusy[lun] = 1;
2969                         FPT_queueSelectFail(CurrCard,p_card);
2970                         SGRAM_ACCESS(port);
2971                         return;
2972                 }
2973         }
2974
2975
2976
2977    auto_loaded = 0;
2978
2979    WR_HARPOON(port+hp_select_id, target);
2980    WR_HARPOON(port+hp_gp_reg_3, target);  /* Use by new automation logic */
2981
2982    if (currSCCB->OperationCode == RESET_COMMAND) {
2983       WRW_HARPOON((port+ID_MSG_STRT), (MPM_OP+AMSG_OUT+
2984                  (currSCCB->Sccb_idmsg & ~DISC_PRIV)));
2985
2986       WRW_HARPOON((port+ID_MSG_STRT+2),BRH_OP+ALWAYS+NP);
2987
2988       currSCCB->Sccb_scsimsg = SMDEV_RESET;
2989
2990       WR_HARPOON(port+hp_autostart_3, (SELECT+SELCHK_STRT));
2991       auto_loaded = 1;
2992       currSCCB->Sccb_scsistat = SELECT_BDR_ST;
2993
2994       if (currTar_Info->TarEEValue & EE_SYNC_MASK)
2995          {
2996                currTar_Info->TarSyncCtrl = 0;
2997               currTar_Info->TarStatus &= ~TAR_SYNC_MASK;
2998               }
2999
3000       if (currTar_Info->TarEEValue & EE_WIDE_SCSI)
3001          {
3002         currTar_Info->TarStatus &= ~TAR_WIDE_MASK;
3003         }
3004
3005       FPT_sssyncv(port, target, NARROW_SCSI,currTar_Info);
3006       FPT_SccbMgrTableInitTarget(p_card, target);
3007
3008       }
3009
3010                 else if(currSCCB->Sccb_scsistat == ABORT_ST)
3011                 {
3012                         WRW_HARPOON((port+ID_MSG_STRT), (MPM_OP+AMSG_OUT+
3013                                                                 (currSCCB->Sccb_idmsg & ~DISC_PRIV)));
3014
3015       WRW_HARPOON((port+ID_MSG_STRT+2),BRH_OP+ALWAYS+CMDPZ);
3016
3017                         WRW_HARPOON((port+SYNC_MSGS+0), (MPM_OP+AMSG_OUT+
3018                                                                 (((UCHAR)(currSCCB->ControlByte & TAG_TYPE_MASK)
3019                                                                 >> 6) | (UCHAR)0x20)));
3020                         WRW_HARPOON((port+SYNC_MSGS+2),
3021                                                         (MPM_OP+AMSG_OUT+currSCCB->Sccb_tag));
3022                         WRW_HARPOON((port+SYNC_MSGS+4), (BRH_OP+ALWAYS+NP ));
3023
3024                         WR_HARPOON(port+hp_autostart_3, (SELECT+SELCHK_STRT));
3025                         auto_loaded = 1;
3026                 
3027                 }
3028
3029    else if (!(currTar_Info->TarStatus & WIDE_NEGOCIATED))  {
3030       auto_loaded = FPT_siwidn(port,p_card);
3031       currSCCB->Sccb_scsistat = SELECT_WN_ST;
3032       }
3033
3034    else if (!((currTar_Info->TarStatus & TAR_SYNC_MASK)
3035       == SYNC_SUPPORTED))  {
3036       auto_loaded = FPT_sisyncn(port,p_card, 0);
3037       currSCCB->Sccb_scsistat = SELECT_SN_ST;
3038       }
3039
3040
3041    if (!auto_loaded)
3042       {
3043
3044       if (currSCCB->ControlByte & F_USE_CMD_Q)
3045          {
3046
3047          CurrCard->globalFlags |= F_TAG_STARTED;
3048
3049          if ((currTar_Info->TarStatus & TAR_TAG_Q_MASK)
3050             == TAG_Q_REJECT)
3051             {
3052             currSCCB->ControlByte &= ~F_USE_CMD_Q;
3053
3054             /* Fix up the start instruction with a jump to
3055                Non-Tag-CMD handling */
3056             WRW_HARPOON((port+ID_MSG_STRT),BRH_OP+ALWAYS+NTCMD);
3057
3058             WRW_HARPOON((port+NON_TAG_ID_MSG),
3059                              (MPM_OP+AMSG_OUT+currSCCB->Sccb_idmsg));
3060
3061                  WR_HARPOON(port+hp_autostart_3, (SELECT+SELCHK_STRT));
3062
3063                  /* Setup our STATE so we know what happend when
3064                the wheels fall off. */
3065             currSCCB->Sccb_scsistat = SELECT_ST;
3066
3067                  currTar_Info->TarLUNBusy[lun] = 1;
3068             }
3069
3070          else
3071             {
3072             WRW_HARPOON((port+ID_MSG_STRT), (MPM_OP+AMSG_OUT+currSCCB->Sccb_idmsg));
3073
3074             WRW_HARPOON((port+ID_MSG_STRT+2), (MPM_OP+AMSG_OUT+
3075                         (((UCHAR)(currSCCB->ControlByte & TAG_TYPE_MASK)
3076                         >> 6) | (UCHAR)0x20)));
3077
3078                                 for (i = 1; i < QUEUE_DEPTH; i++)
3079                                 {
3080                                         if (++lastTag >= QUEUE_DEPTH) lastTag = 1;
3081                                         if (CurrCard->discQ_Tbl[lastTag] == NULL)
3082                                         {
3083                                                 WRW_HARPOON((port+ID_MSG_STRT+6),
3084                                                         (MPM_OP+AMSG_OUT+lastTag));
3085                                                 CurrCard->tagQ_Lst = lastTag;
3086                                                 currSCCB->Sccb_tag = lastTag;
3087                                                 CurrCard->discQ_Tbl[lastTag] = currSCCB;
3088                                                 CurrCard->discQCount++;
3089                                                 break;
3090                                         }
3091                                 }
3092
3093
3094             if ( i == QUEUE_DEPTH )
3095                {
3096                  currTar_Info->TarLUNBusy[lun] = 1;
3097                FPT_queueSelectFail(CurrCard,p_card);
3098                                    SGRAM_ACCESS(port);
3099                  return;
3100                  }
3101
3102             currSCCB->Sccb_scsistat = SELECT_Q_ST;
3103
3104               WR_HARPOON(port+hp_autostart_3, (SELECT+SELCHK_STRT));
3105             }
3106          }
3107
3108       else
3109          {
3110
3111          WRW_HARPOON((port+ID_MSG_STRT),BRH_OP+ALWAYS+NTCMD);
3112
3113         WRW_HARPOON((port+NON_TAG_ID_MSG),
3114             (MPM_OP+AMSG_OUT+currSCCB->Sccb_idmsg));
3115
3116          currSCCB->Sccb_scsistat = SELECT_ST;
3117
3118          WR_HARPOON(port+hp_autostart_3, (SELECT+SELCHK_STRT));
3119          }
3120
3121
3122       theCCB = (UCHAR *)&currSCCB->Cdb[0];
3123
3124       cdb_reg = port + CMD_STRT;
3125
3126       for (i=0; i < currSCCB->CdbLength; i++)
3127          {
3128          WRW_HARPOON(cdb_reg, (MPM_OP + ACOMMAND + *theCCB));
3129          cdb_reg +=2;
3130          theCCB++;
3131          }
3132
3133       if (currSCCB->CdbLength != TWELVE_BYTE_CMD)
3134          WRW_HARPOON(cdb_reg, (BRH_OP+ALWAYS+    NP));
3135
3136       }  /* auto_loaded */
3137
3138    WRW_HARPOON((port+hp_fiforead), (USHORT) 0x00);
3139    WR_HARPOON(port+hp_xferstat, 0x00);
3140
3141    WRW_HARPOON((port+hp_intstat), (PROG_HLT | TIMEOUT | SEL | BUS_FREE));
3142
3143    WR_HARPOON(port+hp_portctrl_0,(SCSI_PORT));
3144
3145
3146    if (!(currSCCB->Sccb_MGRFlags & F_DEV_SELECTED))
3147       {
3148       WR_HARPOON(port+hp_scsictrl_0, (SEL_TAR | ENA_ATN | ENA_RESEL | ENA_SCAM_SEL));
3149       }
3150    else
3151       {
3152
3153 /*      auto_loaded =  (RD_HARPOON(port+hp_autostart_3) & (UCHAR)0x1F);
3154       auto_loaded |= AUTO_IMMED; */
3155       auto_loaded = AUTO_IMMED;
3156
3157       DISABLE_AUTO(port);
3158
3159       WR_HARPOON(port+hp_autostart_3, auto_loaded);
3160       }
3161
3162    SGRAM_ACCESS(port);
3163 }
3164
3165
3166 /*---------------------------------------------------------------------
3167  *
3168  * Function: FPT_sres
3169  *
3170  * Description: Hookup the correct CCB and handle the incoming messages.
3171  *
3172  *---------------------------------------------------------------------*/
3173
3174 static void FPT_sres(ULONG port, UCHAR p_card, PSCCBcard pCurrCard)
3175 {
3176
3177    UCHAR our_target, message, lun = 0, tag, msgRetryCount;
3178
3179
3180    PSCCBMgr_tar_info currTar_Info;
3181         PSCCB currSCCB;
3182
3183
3184
3185
3186         if(pCurrCard->currentSCCB != NULL)
3187         {
3188                 currTar_Info = &FPT_sccbMgrTbl[p_card][pCurrCard->currentSCCB->TargID];
3189                 DISABLE_AUTO(port);
3190
3191
3192                 WR_HARPOON((port+hp_scsictrl_0),(ENA_RESEL | ENA_SCAM_SEL));
3193
3194
3195                 currSCCB = pCurrCard->currentSCCB;
3196                 if(currSCCB->Sccb_scsistat == SELECT_WN_ST)
3197                 {
3198                         currTar_Info->TarStatus &= ~TAR_WIDE_MASK;
3199                         currSCCB->Sccb_scsistat = BUS_FREE_ST;
3200                 }
3201                 if(currSCCB->Sccb_scsistat == SELECT_SN_ST)
3202                 {
3203                         currTar_Info->TarStatus &= ~TAR_SYNC_MASK;
3204                         currSCCB->Sccb_scsistat = BUS_FREE_ST;
3205                 }
3206                 if(((pCurrCard->globalFlags & F_CONLUN_IO) &&
3207                         ((currTar_Info->TarStatus & TAR_TAG_Q_MASK) != TAG_Q_TRYING)))
3208                 {
3209         currTar_Info->TarLUNBusy[currSCCB->Lun] = 0;
3210                         if(currSCCB->Sccb_scsistat != ABORT_ST)
3211                         {
3212                                 pCurrCard->discQCount--;
3213                                 pCurrCard->discQ_Tbl[currTar_Info->LunDiscQ_Idx[currSCCB->Lun]] 
3214                                                                                                         = NULL;
3215                         }
3216                 }
3217                 else
3218                 {
3219               currTar_Info->TarLUNBusy[0] = 0;
3220                         if(currSCCB->Sccb_tag)
3221                         {
3222                                 if(currSCCB->Sccb_scsistat != ABORT_ST)
3223                                 {
3224                                         pCurrCard->discQCount--;
3225                                         pCurrCard->discQ_Tbl[currSCCB->Sccb_tag] = NULL;
3226                                 }
3227                         }else
3228                         {
3229                                 if(currSCCB->Sccb_scsistat != ABORT_ST)
3230                                 {
3231                                         pCurrCard->discQCount--;
3232                                         pCurrCard->discQ_Tbl[currTar_Info->LunDiscQ_Idx[0]] = NULL;
3233                                 }
3234                         }
3235                 }
3236
3237       FPT_queueSelectFail(&FPT_BL_Card[p_card],p_card);
3238         }
3239
3240         WRW_HARPOON((port+hp_fiforead), (USHORT) 0x00);
3241
3242
3243         our_target = (UCHAR)(RD_HARPOON(port+hp_select_id) >> 4);
3244         currTar_Info = &FPT_sccbMgrTbl[p_card][our_target];
3245
3246
3247         msgRetryCount = 0;
3248         do
3249         {
3250
3251                 currTar_Info = &FPT_sccbMgrTbl[p_card][our_target];
3252                 tag = 0;
3253
3254
3255                 while(!(RD_HARPOON(port+hp_scsisig) & SCSI_REQ))
3256                 {
3257                         if (! (RD_HARPOON(port+hp_scsisig) & SCSI_BSY))
3258                         {
3259
3260                                 WRW_HARPOON((port+hp_intstat), PHASE);
3261                                 return;
3262                         }
3263                 }
3264
3265                 WRW_HARPOON((port+hp_intstat), PHASE);
3266                 if ((RD_HARPOON(port+hp_scsisig) & S_SCSI_PHZ) == S_MSGI_PH)
3267                 {
3268
3269                         message = FPT_sfm(port,pCurrCard->currentSCCB);
3270                         if (message)
3271                         {
3272
3273                                 if (message <= (0x80 | LUN_MASK))
3274                                 {
3275                                         lun = message & (UCHAR)LUN_MASK;
3276
3277                                         if ((currTar_Info->TarStatus & TAR_TAG_Q_MASK) == TAG_Q_TRYING)
3278                                         {
3279                                                 if (currTar_Info->TarTagQ_Cnt != 0)
3280                                                 {
3281
3282                                                         if (!(currTar_Info->TarLUN_CA))
3283                                                         {
3284                                                                 ACCEPT_MSG(port);    /*Release the ACK for ID msg. */
3285
3286
3287                                                                 message = FPT_sfm(port,pCurrCard->currentSCCB);
3288                                                                 if (message)
3289                                                                 {
3290                                                                         ACCEPT_MSG(port);
3291                                                                 }
3292
3293                                                                 else
3294                                                                 message = 0;
3295
3296                                                                 if(message != 0)
3297                                                                 {
3298                                                                         tag = FPT_sfm(port,pCurrCard->currentSCCB);
3299
3300                                                                         if (!(tag)) 
3301                                                                                 message = 0;
3302                                                                 }
3303
3304                                                         } /*C.A. exists! */
3305
3306                                                 } /*End Q cnt != 0 */
3307
3308                                         } /*End Tag cmds supported! */
3309
3310                                 } /*End valid ID message.  */
3311
3312                                 else
3313                                 {
3314
3315                                         ACCEPT_MSG_ATN(port);
3316                                 }
3317
3318                         } /* End good id message. */
3319
3320                         else
3321                         {
3322
3323                                 message = 0;
3324                         }
3325                 }
3326                 else
3327                 {
3328                         ACCEPT_MSG_ATN(port);
3329
3330                    while (!(RDW_HARPOON((port+hp_intstat)) & (PHASE | RESET)) &&
3331                           !(RD_HARPOON(port+hp_scsisig) & SCSI_REQ) &&
3332                           (RD_HARPOON(port+hp_scsisig) & SCSI_BSY)) ;
3333
3334                         return;
3335                 }
3336
3337                 if(message == 0)
3338                 {
3339                         msgRetryCount++;
3340                         if(msgRetryCount == 1)
3341                         {
3342                                 FPT_SendMsg(port, SMPARITY);
3343                         }
3344                         else
3345                         {
3346                                 FPT_SendMsg(port, SMDEV_RESET);
3347
3348                                 FPT_sssyncv(port, our_target, NARROW_SCSI,currTar_Info);
3349
3350                                 if (FPT_sccbMgrTbl[p_card][our_target].TarEEValue & EE_SYNC_MASK) 
3351                                 {
3352                         
3353                                         FPT_sccbMgrTbl[p_card][our_target].TarStatus &= ~TAR_SYNC_MASK;