bb9c484d7e195303414eba2df621cd55e503977a
[linux-3.10.git] / drivers / net / wireless / bcm43xx / bcm43xx_radio.c
1 /*
2
3   Broadcom BCM43xx wireless driver
4
5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6                      Stefano Brivio <st3@riseup.net>
7                      Michael Buesch <mbuesch@freenet.de>
8                      Danny van Dyk <kugelfang@gentoo.org>
9                      Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11   Some parts of the code in this file are derived from the ipw2200
12   driver  Copyright(c) 2003 - 2004 Intel Corporation.
13
14   This program is free software; you can redistribute it and/or modify
15   it under the terms of the GNU General Public License as published by
16   the Free Software Foundation; either version 2 of the License, or
17   (at your option) any later version.
18
19   This program is distributed in the hope that it will be useful,
20   but WITHOUT ANY WARRANTY; without even the implied warranty of
21   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22   GNU General Public License for more details.
23
24   You should have received a copy of the GNU General Public License
25   along with this program; see the file COPYING.  If not, write to
26   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27   Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32
33 #include "bcm43xx.h"
34 #include "bcm43xx_main.h"
35 #include "bcm43xx_phy.h"
36 #include "bcm43xx_radio.h"
37 #include "bcm43xx_ilt.h"
38
39
40 /* Table for bcm43xx_radio_calibrationvalue() */
41 static const u16 rcc_table[16] = {
42         0x0002, 0x0003, 0x0001, 0x000F,
43         0x0006, 0x0007, 0x0005, 0x000F,
44         0x000A, 0x000B, 0x0009, 0x000F,
45         0x000E, 0x000F, 0x000D, 0x000F,
46 };
47
48 /* Reverse the bits of a 4bit value.
49  * Example:  1101 is flipped 1011
50  */
51 static u16 flip_4bit(u16 value)
52 {
53         u16 flipped = 0x0000;
54
55         assert((value & ~0x000F) == 0x0000);
56
57         flipped |= (value & 0x0001) << 3;
58         flipped |= (value & 0x0002) << 1;
59         flipped |= (value & 0x0004) >> 1;
60         flipped |= (value & 0x0008) >> 3;
61
62         return flipped;
63 }
64
65 /* Get the freq, as it has to be written to the device. */
66 static inline
67 u16 channel2freq_bg(u8 channel)
68 {
69         /* Frequencies are given as frequencies_bg[index] + 2.4GHz
70          * Starting with channel 1
71          */
72         static const u16 frequencies_bg[14] = {
73                 12, 17, 22, 27,
74                 32, 37, 42, 47,
75                 52, 57, 62, 67,
76                 72, 84,
77         };
78
79         assert(channel >= 1 && channel <= 14);
80
81         return frequencies_bg[channel - 1];
82 }
83
84 /* Get the freq, as it has to be written to the device. */
85 static inline
86 u16 channel2freq_a(u8 channel)
87 {
88         assert(channel <= 200);
89
90         return (5000 + 5 * channel);
91 }
92
93 void bcm43xx_radio_lock(struct bcm43xx_private *bcm)
94 {
95         u32 status;
96
97         status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
98         status |= BCM43xx_SBF_RADIOREG_LOCK;
99         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
100         mmiowb();
101         udelay(10);
102 }
103
104 void bcm43xx_radio_unlock(struct bcm43xx_private *bcm)
105 {
106         u32 status;
107
108         bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_VER); /* dummy read */
109         status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
110         status &= ~BCM43xx_SBF_RADIOREG_LOCK;
111         bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
112         mmiowb();
113 }
114
115 u16 bcm43xx_radio_read16(struct bcm43xx_private *bcm, u16 offset)
116 {
117         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
118         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
119
120         switch (phy->type) {
121         case BCM43xx_PHYTYPE_A:
122                 offset |= 0x0040;
123                 break;
124         case BCM43xx_PHYTYPE_B:
125                 if (radio->version == 0x2053) {
126                         if (offset < 0x70)
127                                 offset += 0x80;
128                         else if (offset < 0x80)
129                                 offset += 0x70;
130                 } else if (radio->version == 0x2050) {
131                         offset |= 0x80;
132                 } else
133                         assert(0);
134                 break;
135         case BCM43xx_PHYTYPE_G:
136                 offset |= 0x80;
137                 break;
138         }
139
140         bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, offset);
141         return bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_LOW);
142 }
143
144 void bcm43xx_radio_write16(struct bcm43xx_private *bcm, u16 offset, u16 val)
145 {
146         bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, offset);
147         mmiowb();
148         bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_DATA_LOW, val);
149 }
150
151 static void bcm43xx_set_all_gains(struct bcm43xx_private *bcm,
152                                   s16 first, s16 second, s16 third)
153 {
154         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
155         u16 i;
156         u16 start = 0x08, end = 0x18;
157         u16 offset = 0x0400;
158         u16 tmp;
159
160         if (phy->rev <= 1) {
161                 offset = 0x5000;
162                 start = 0x10;
163                 end = 0x20;
164         }
165
166         for (i = 0; i < 4; i++)
167                 bcm43xx_ilt_write(bcm, offset + i, first);
168
169         for (i = start; i < end; i++)
170                 bcm43xx_ilt_write(bcm, offset + i, second);
171
172         if (third != -1) {
173                 tmp = ((u16)third << 14) | ((u16)third << 6);
174                 bcm43xx_phy_write(bcm, 0x04A0,
175                                   (bcm43xx_phy_read(bcm, 0x04A0) & 0xBFBF) | tmp);
176                 bcm43xx_phy_write(bcm, 0x04A1,
177                                   (bcm43xx_phy_read(bcm, 0x04A1) & 0xBFBF) | tmp);
178                 bcm43xx_phy_write(bcm, 0x04A2,
179                                   (bcm43xx_phy_read(bcm, 0x04A2) & 0xBFBF) | tmp);
180         }
181         bcm43xx_dummy_transmission(bcm);
182 }
183
184 static void bcm43xx_set_original_gains(struct bcm43xx_private *bcm)
185 {
186         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
187         u16 i, tmp;
188         u16 offset = 0x0400;
189         u16 start = 0x0008, end = 0x0018;
190
191         if (phy->rev <= 1) {
192                 offset = 0x5000;
193                 start = 0x0010;
194                 end = 0x0020;
195         }
196
197         for (i = 0; i < 4; i++) {
198                 tmp = (i & 0xFFFC);
199                 tmp |= (i & 0x0001) << 1;
200                 tmp |= (i & 0x0002) >> 1;
201
202                 bcm43xx_ilt_write(bcm, offset + i, tmp);
203         }
204
205         for (i = start; i < end; i++)
206                 bcm43xx_ilt_write(bcm, offset + i, i - start);
207
208         bcm43xx_phy_write(bcm, 0x04A0,
209                           (bcm43xx_phy_read(bcm, 0x04A0) & 0xBFBF) | 0x4040);
210         bcm43xx_phy_write(bcm, 0x04A1,
211                           (bcm43xx_phy_read(bcm, 0x04A1) & 0xBFBF) | 0x4040);
212         bcm43xx_phy_write(bcm, 0x04A2,
213                           (bcm43xx_phy_read(bcm, 0x04A2) & 0xBFBF) | 0x4000);
214         bcm43xx_dummy_transmission(bcm);
215 }
216
217 /* Synthetic PU workaround */
218 static void bcm43xx_synth_pu_workaround(struct bcm43xx_private *bcm, u8 channel)
219 {
220         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
221         
222         if (radio->version != 0x2050 || radio->revision >= 6) {
223                 /* We do not need the workaround. */
224                 return;
225         }
226
227         if (channel <= 10) {
228                 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL,
229                                 channel2freq_bg(channel + 4));
230         } else {
231                 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL,
232                                 channel2freq_bg(1));
233         }
234         udelay(100);
235         bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL,
236                         channel2freq_bg(channel));
237 }
238
239 u8 bcm43xx_radio_aci_detect(struct bcm43xx_private *bcm, u8 channel)
240 {
241         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
242         u8 ret = 0;
243         u16 saved, rssi, temp;
244         int i, j = 0;
245
246         saved = bcm43xx_phy_read(bcm, 0x0403);
247         bcm43xx_radio_selectchannel(bcm, channel, 0);
248         bcm43xx_phy_write(bcm, 0x0403, (saved & 0xFFF8) | 5);
249         if (radio->aci_hw_rssi)
250                 rssi = bcm43xx_phy_read(bcm, 0x048A) & 0x3F;
251         else
252                 rssi = saved & 0x3F;
253         /* clamp temp to signed 5bit */
254         if (rssi > 32)
255                 rssi -= 64;
256         for (i = 0;i < 100; i++) {
257                 temp = (bcm43xx_phy_read(bcm, 0x047F) >> 8) & 0x3F;
258                 if (temp > 32)
259                         temp -= 64;
260                 if (temp < rssi)
261                         j++;
262                 if (j >= 20)
263                         ret = 1;
264         }
265         bcm43xx_phy_write(bcm, 0x0403, saved);
266
267         return ret;
268 }
269
270 u8 bcm43xx_radio_aci_scan(struct bcm43xx_private *bcm)
271 {
272         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
273         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
274         u8 ret[13];
275         unsigned int channel = radio->channel;
276         unsigned int i, j, start, end;
277         unsigned long phylock_flags;
278
279         if (!((phy->type == BCM43xx_PHYTYPE_G) && (phy->rev > 0)))
280                 return 0;
281
282         bcm43xx_phy_lock(bcm, phylock_flags);
283         bcm43xx_radio_lock(bcm);
284         bcm43xx_phy_write(bcm, 0x0802,
285                           bcm43xx_phy_read(bcm, 0x0802) & 0xFFFC);
286         bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
287                           bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS) & 0x7FFF);
288         bcm43xx_set_all_gains(bcm, 3, 8, 1);
289
290         start = (channel - 5 > 0) ? channel - 5 : 1;
291         end = (channel + 5 < 14) ? channel + 5 : 13;
292
293         for (i = start; i <= end; i++) {
294                 if (abs(channel - i) > 2)
295                         ret[i-1] = bcm43xx_radio_aci_detect(bcm, i);
296         }
297         bcm43xx_radio_selectchannel(bcm, channel, 0);
298         bcm43xx_phy_write(bcm, 0x0802,
299                           (bcm43xx_phy_read(bcm, 0x0802) & 0xFFFC) | 0x0003);
300         bcm43xx_phy_write(bcm, 0x0403,
301                           bcm43xx_phy_read(bcm, 0x0403) & 0xFFF8);
302         bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
303                           bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS) | 0x8000);
304         bcm43xx_set_original_gains(bcm);
305         for (i = 0; i < 13; i++) {
306                 if (!ret[i])
307                         continue;
308                 end = (i + 5 < 13) ? i + 5 : 13;
309                 for (j = i; j < end; j++)
310                         ret[j] = 1;
311         }
312         bcm43xx_radio_unlock(bcm);
313         bcm43xx_phy_unlock(bcm, phylock_flags);
314
315         return ret[channel - 1];
316 }
317
318 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
319 void bcm43xx_nrssi_hw_write(struct bcm43xx_private *bcm, u16 offset, s16 val)
320 {
321         bcm43xx_phy_write(bcm, BCM43xx_PHY_NRSSILT_CTRL, offset);
322         mmiowb();
323         bcm43xx_phy_write(bcm, BCM43xx_PHY_NRSSILT_DATA, (u16)val);
324 }
325
326 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
327 s16 bcm43xx_nrssi_hw_read(struct bcm43xx_private *bcm, u16 offset)
328 {
329         u16 val;
330
331         bcm43xx_phy_write(bcm, BCM43xx_PHY_NRSSILT_CTRL, offset);
332         val = bcm43xx_phy_read(bcm, BCM43xx_PHY_NRSSILT_DATA);
333
334         return (s16)val;
335 }
336
337 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
338 void bcm43xx_nrssi_hw_update(struct bcm43xx_private *bcm, u16 val)
339 {
340         u16 i;
341         s16 tmp;
342
343         for (i = 0; i < 64; i++) {
344                 tmp = bcm43xx_nrssi_hw_read(bcm, i);
345                 tmp -= val;
346                 tmp = limit_value(tmp, -32, 31);
347                 bcm43xx_nrssi_hw_write(bcm, i, tmp);
348         }
349 }
350
351 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
352 void bcm43xx_nrssi_mem_update(struct bcm43xx_private *bcm)
353 {
354         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
355         s16 i, delta;
356         s32 tmp;
357
358         delta = 0x1F - radio->nrssi[0];
359         for (i = 0; i < 64; i++) {
360                 tmp = (i - delta) * radio->nrssislope;
361                 tmp /= 0x10000;
362                 tmp += 0x3A;
363                 tmp = limit_value(tmp, 0, 0x3F);
364                 radio->nrssi_lt[i] = tmp;
365         }
366 }
367
368 static void bcm43xx_calc_nrssi_offset(struct bcm43xx_private *bcm)
369 {
370         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
371         u16 backup[20] = { 0 };
372         s16 v47F;
373         u16 i;
374         u16 saved = 0xFFFF;
375
376         backup[0] = bcm43xx_phy_read(bcm, 0x0001);
377         backup[1] = bcm43xx_phy_read(bcm, 0x0811);
378         backup[2] = bcm43xx_phy_read(bcm, 0x0812);
379         backup[3] = bcm43xx_phy_read(bcm, 0x0814);
380         backup[4] = bcm43xx_phy_read(bcm, 0x0815);
381         backup[5] = bcm43xx_phy_read(bcm, 0x005A);
382         backup[6] = bcm43xx_phy_read(bcm, 0x0059);
383         backup[7] = bcm43xx_phy_read(bcm, 0x0058);
384         backup[8] = bcm43xx_phy_read(bcm, 0x000A);
385         backup[9] = bcm43xx_phy_read(bcm, 0x0003);
386         backup[10] = bcm43xx_radio_read16(bcm, 0x007A);
387         backup[11] = bcm43xx_radio_read16(bcm, 0x0043);
388
389         bcm43xx_phy_write(bcm, 0x0429,
390                           bcm43xx_phy_read(bcm, 0x0429) & 0x7FFF);
391         bcm43xx_phy_write(bcm, 0x0001,
392                           (bcm43xx_phy_read(bcm, 0x0001) & 0x3FFF) | 0x4000);
393         bcm43xx_phy_write(bcm, 0x0811,
394                           bcm43xx_phy_read(bcm, 0x0811) | 0x000C);
395         bcm43xx_phy_write(bcm, 0x0812,
396                           (bcm43xx_phy_read(bcm, 0x0812) & 0xFFF3) | 0x0004);
397         bcm43xx_phy_write(bcm, 0x0802,
398                           bcm43xx_phy_read(bcm, 0x0802) & ~(0x1 | 0x2));
399         if (phy->rev >= 6) {
400                 backup[12] = bcm43xx_phy_read(bcm, 0x002E);
401                 backup[13] = bcm43xx_phy_read(bcm, 0x002F);
402                 backup[14] = bcm43xx_phy_read(bcm, 0x080F);
403                 backup[15] = bcm43xx_phy_read(bcm, 0x0810);
404                 backup[16] = bcm43xx_phy_read(bcm, 0x0801);
405                 backup[17] = bcm43xx_phy_read(bcm, 0x0060);
406                 backup[18] = bcm43xx_phy_read(bcm, 0x0014);
407                 backup[19] = bcm43xx_phy_read(bcm, 0x0478);
408
409                 bcm43xx_phy_write(bcm, 0x002E, 0);
410                 bcm43xx_phy_write(bcm, 0x002F, 0);
411                 bcm43xx_phy_write(bcm, 0x080F, 0);
412                 bcm43xx_phy_write(bcm, 0x0810, 0);
413                 bcm43xx_phy_write(bcm, 0x0478,
414                                   bcm43xx_phy_read(bcm, 0x0478) | 0x0100);
415                 bcm43xx_phy_write(bcm, 0x0801,
416                                   bcm43xx_phy_read(bcm, 0x0801) | 0x0040);
417                 bcm43xx_phy_write(bcm, 0x0060,
418                                   bcm43xx_phy_read(bcm, 0x0060) | 0x0040);
419                 bcm43xx_phy_write(bcm, 0x0014,
420                                   bcm43xx_phy_read(bcm, 0x0014) | 0x0200);
421         }
422         bcm43xx_radio_write16(bcm, 0x007A,
423                               bcm43xx_radio_read16(bcm, 0x007A) | 0x0070);
424         bcm43xx_radio_write16(bcm, 0x007A,
425                               bcm43xx_radio_read16(bcm, 0x007A) | 0x0080);
426         udelay(30);
427
428         v47F = (s16)((bcm43xx_phy_read(bcm, 0x047F) >> 8) & 0x003F);
429         if (v47F >= 0x20)
430                 v47F -= 0x40;
431         if (v47F == 31) {
432                 for (i = 7; i >= 4; i--) {
433                         bcm43xx_radio_write16(bcm, 0x007B, i);
434                         udelay(20);
435                         v47F = (s16)((bcm43xx_phy_read(bcm, 0x047F) >> 8) & 0x003F);
436                         if (v47F >= 0x20)
437                                 v47F -= 0x40;
438                         if (v47F < 31 && saved == 0xFFFF)
439                                 saved = i;
440                 }
441                 if (saved == 0xFFFF)
442                         saved = 4;
443         } else {
444                 bcm43xx_radio_write16(bcm, 0x007A,
445                                       bcm43xx_radio_read16(bcm, 0x007A) & 0x007F);
446                 bcm43xx_phy_write(bcm, 0x0814,
447                                   bcm43xx_phy_read(bcm, 0x0814) | 0x0001);
448                 bcm43xx_phy_write(bcm, 0x0815,
449                                   bcm43xx_phy_read(bcm, 0x0815) & 0xFFFE);
450                 bcm43xx_phy_write(bcm, 0x0811,
451                                   bcm43xx_phy_read(bcm, 0x0811) | 0x000C);
452                 bcm43xx_phy_write(bcm, 0x0812,
453                                   bcm43xx_phy_read(bcm, 0x0812) | 0x000C);
454                 bcm43xx_phy_write(bcm, 0x0811,
455                                   bcm43xx_phy_read(bcm, 0x0811) | 0x0030);
456                 bcm43xx_phy_write(bcm, 0x0812,
457                                   bcm43xx_phy_read(bcm, 0x0812) | 0x0030);
458                 bcm43xx_phy_write(bcm, 0x005A, 0x0480);
459                 bcm43xx_phy_write(bcm, 0x0059, 0x0810);
460                 bcm43xx_phy_write(bcm, 0x0058, 0x000D);
461                 if (phy->rev == 0) {
462                         bcm43xx_phy_write(bcm, 0x0003, 0x0122);
463                 } else {
464                         bcm43xx_phy_write(bcm, 0x000A,
465                                           bcm43xx_phy_read(bcm, 0x000A)
466                                           | 0x2000);
467                 }
468                 bcm43xx_phy_write(bcm, 0x0814,
469                                   bcm43xx_phy_read(bcm, 0x0814) | 0x0004);
470                 bcm43xx_phy_write(bcm, 0x0815,
471                                   bcm43xx_phy_read(bcm, 0x0815) & 0xFFFB);
472                 bcm43xx_phy_write(bcm, 0x0003,
473                                   (bcm43xx_phy_read(bcm, 0x0003) & 0xFF9F)
474                                   | 0x0040);
475                 bcm43xx_radio_write16(bcm, 0x007A,
476                                       bcm43xx_radio_read16(bcm, 0x007A) | 0x000F);
477                 bcm43xx_set_all_gains(bcm, 3, 0, 1);
478                 bcm43xx_radio_write16(bcm, 0x0043,
479                                       (bcm43xx_radio_read16(bcm, 0x0043)
480                                        & 0x00F0) | 0x000F);
481                 udelay(30);
482                 v47F = (s16)((bcm43xx_phy_read(bcm, 0x047F) >> 8) & 0x003F);
483                 if (v47F >= 0x20)
484                         v47F -= 0x40;
485                 if (v47F == -32) {
486                         for (i = 0; i < 4; i++) {
487                                 bcm43xx_radio_write16(bcm, 0x007B, i);
488                                 udelay(20);
489                                 v47F = (s16)((bcm43xx_phy_read(bcm, 0x047F) >> 8) & 0x003F);
490                                 if (v47F >= 0x20)
491                                         v47F -= 0x40;
492                                 if (v47F > -31 && saved == 0xFFFF)
493                                         saved = i;
494                         }
495                         if (saved == 0xFFFF)
496                                 saved = 3;
497                 } else
498                         saved = 0;
499         }
500         bcm43xx_radio_write16(bcm, 0x007B, saved);
501
502         if (phy->rev >= 6) {
503                 bcm43xx_phy_write(bcm, 0x002E, backup[12]);
504                 bcm43xx_phy_write(bcm, 0x002F, backup[13]);
505                 bcm43xx_phy_write(bcm, 0x080F, backup[14]);
506                 bcm43xx_phy_write(bcm, 0x0810, backup[15]);
507         }
508         bcm43xx_phy_write(bcm, 0x0814, backup[3]);
509         bcm43xx_phy_write(bcm, 0x0815, backup[4]);
510         bcm43xx_phy_write(bcm, 0x005A, backup[5]);
511         bcm43xx_phy_write(bcm, 0x0059, backup[6]);
512         bcm43xx_phy_write(bcm, 0x0058, backup[7]);
513         bcm43xx_phy_write(bcm, 0x000A, backup[8]);
514         bcm43xx_phy_write(bcm, 0x0003, backup[9]);
515         bcm43xx_radio_write16(bcm, 0x0043, backup[11]);
516         bcm43xx_radio_write16(bcm, 0x007A, backup[10]);
517         bcm43xx_phy_write(bcm, 0x0802,
518                           bcm43xx_phy_read(bcm, 0x0802) | 0x1 | 0x2);
519         bcm43xx_phy_write(bcm, 0x0429,
520                           bcm43xx_phy_read(bcm, 0x0429) | 0x8000);
521         bcm43xx_set_original_gains(bcm);
522         if (phy->rev >= 6) {
523                 bcm43xx_phy_write(bcm, 0x0801, backup[16]);
524                 bcm43xx_phy_write(bcm, 0x0060, backup[17]);
525                 bcm43xx_phy_write(bcm, 0x0014, backup[18]);
526                 bcm43xx_phy_write(bcm, 0x0478, backup[19]);
527         }
528         bcm43xx_phy_write(bcm, 0x0001, backup[0]);
529         bcm43xx_phy_write(bcm, 0x0812, backup[2]);
530         bcm43xx_phy_write(bcm, 0x0811, backup[1]);
531 }
532
533 void bcm43xx_calc_nrssi_slope(struct bcm43xx_private *bcm)
534 {
535         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
536         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
537         u16 backup[18] = { 0 };
538         u16 tmp;
539         s16 nrssi0, nrssi1;
540
541         switch (phy->type) {
542         case BCM43xx_PHYTYPE_B:
543                 backup[0] = bcm43xx_radio_read16(bcm, 0x007A);
544                 backup[1] = bcm43xx_radio_read16(bcm, 0x0052);
545                 backup[2] = bcm43xx_radio_read16(bcm, 0x0043);
546                 backup[3] = bcm43xx_phy_read(bcm, 0x0030);
547                 backup[4] = bcm43xx_phy_read(bcm, 0x0026);
548                 backup[5] = bcm43xx_phy_read(bcm, 0x0015);
549                 backup[6] = bcm43xx_phy_read(bcm, 0x002A);
550                 backup[7] = bcm43xx_phy_read(bcm, 0x0020);
551                 backup[8] = bcm43xx_phy_read(bcm, 0x005A);
552                 backup[9] = bcm43xx_phy_read(bcm, 0x0059);
553                 backup[10] = bcm43xx_phy_read(bcm, 0x0058);
554                 backup[11] = bcm43xx_read16(bcm, 0x03E2);
555                 backup[12] = bcm43xx_read16(bcm, 0x03E6);
556                 backup[13] = bcm43xx_read16(bcm, BCM43xx_MMIO_CHANNEL_EXT);
557
558                 tmp  = bcm43xx_radio_read16(bcm, 0x007A);
559                 tmp &= (phy->rev >= 5) ? 0x007F : 0x000F;
560                 bcm43xx_radio_write16(bcm, 0x007A, tmp);
561                 bcm43xx_phy_write(bcm, 0x0030, 0x00FF);
562                 bcm43xx_write16(bcm, 0x03EC, 0x7F7F);
563                 bcm43xx_phy_write(bcm, 0x0026, 0x0000);
564                 bcm43xx_phy_write(bcm, 0x0015,
565                                   bcm43xx_phy_read(bcm, 0x0015) | 0x0020);
566                 bcm43xx_phy_write(bcm, 0x002A, 0x08A3);
567                 bcm43xx_radio_write16(bcm, 0x007A,
568                                       bcm43xx_radio_read16(bcm, 0x007A) | 0x0080);
569
570                 nrssi0 = (s16)bcm43xx_phy_read(bcm, 0x0027);
571                 bcm43xx_radio_write16(bcm, 0x007A,
572                                       bcm43xx_radio_read16(bcm, 0x007A) & 0x007F);
573                 if (phy->rev >= 2) {
574                         bcm43xx_write16(bcm, 0x03E6, 0x0040);
575                 } else if (phy->rev == 0) {
576                         bcm43xx_write16(bcm, 0x03E6, 0x0122);
577                 } else {
578                         bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT,
579                                         bcm43xx_read16(bcm, BCM43xx_MMIO_CHANNEL_EXT) & 0x2000);
580                 }
581                 bcm43xx_phy_write(bcm, 0x0020, 0x3F3F);
582                 bcm43xx_phy_write(bcm, 0x0015, 0xF330);
583                 bcm43xx_radio_write16(bcm, 0x005A, 0x0060);
584                 bcm43xx_radio_write16(bcm, 0x0043,
585                                       bcm43xx_radio_read16(bcm, 0x0043) & 0x00F0);
586                 bcm43xx_phy_write(bcm, 0x005A, 0x0480);
587                 bcm43xx_phy_write(bcm, 0x0059, 0x0810);
588                 bcm43xx_phy_write(bcm, 0x0058, 0x000D);
589                 udelay(20);
590
591                 nrssi1 = (s16)bcm43xx_phy_read(bcm, 0x0027);
592                 bcm43xx_phy_write(bcm, 0x0030, backup[3]);
593                 bcm43xx_radio_write16(bcm, 0x007A, backup[0]);
594                 bcm43xx_write16(bcm, 0x03E2, backup[11]);
595                 bcm43xx_phy_write(bcm, 0x0026, backup[4]);
596                 bcm43xx_phy_write(bcm, 0x0015, backup[5]);
597                 bcm43xx_phy_write(bcm, 0x002A, backup[6]);
598                 bcm43xx_synth_pu_workaround(bcm, radio->channel);
599                 if (phy->rev != 0)
600                         bcm43xx_write16(bcm, 0x03F4, backup[13]);
601
602                 bcm43xx_phy_write(bcm, 0x0020, backup[7]);
603                 bcm43xx_phy_write(bcm, 0x005A, backup[8]);
604                 bcm43xx_phy_write(bcm, 0x0059, backup[9]);
605                 bcm43xx_phy_write(bcm, 0x0058, backup[10]);
606                 bcm43xx_radio_write16(bcm, 0x0052, backup[1]);
607                 bcm43xx_radio_write16(bcm, 0x0043, backup[2]);
608
609                 if (nrssi0 == nrssi1)
610                         radio->nrssislope = 0x00010000;
611                 else 
612                         radio->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
613
614                 if (nrssi0 <= -4) {
615                         radio->nrssi[0] = nrssi0;
616                         radio->nrssi[1] = nrssi1;
617                 }
618                 break;
619         case BCM43xx_PHYTYPE_G:
620                 if (radio->revision >= 9)
621                         return;
622                 if (radio->revision == 8)
623                         bcm43xx_calc_nrssi_offset(bcm);
624
625                 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
626                                   bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS) & 0x7FFF);
627                 bcm43xx_phy_write(bcm, 0x0802,
628                                   bcm43xx_phy_read(bcm, 0x0802) & 0xFFFC);
629                 backup[7] = bcm43xx_read16(bcm, 0x03E2);
630                 bcm43xx_write16(bcm, 0x03E2,
631                                 bcm43xx_read16(bcm, 0x03E2) | 0x8000);
632                 backup[0] = bcm43xx_radio_read16(bcm, 0x007A);
633                 backup[1] = bcm43xx_radio_read16(bcm, 0x0052);
634                 backup[2] = bcm43xx_radio_read16(bcm, 0x0043);
635                 backup[3] = bcm43xx_phy_read(bcm, 0x0015);
636                 backup[4] = bcm43xx_phy_read(bcm, 0x005A);
637                 backup[5] = bcm43xx_phy_read(bcm, 0x0059);
638                 backup[6] = bcm43xx_phy_read(bcm, 0x0058);
639                 backup[8] = bcm43xx_read16(bcm, 0x03E6);
640                 backup[9] = bcm43xx_read16(bcm, BCM43xx_MMIO_CHANNEL_EXT);
641                 if (phy->rev >= 3) {
642                         backup[10] = bcm43xx_phy_read(bcm, 0x002E);
643                         backup[11] = bcm43xx_phy_read(bcm, 0x002F);
644                         backup[12] = bcm43xx_phy_read(bcm, 0x080F);
645                         backup[13] = bcm43xx_phy_read(bcm, BCM43xx_PHY_G_LO_CONTROL);
646                         backup[14] = bcm43xx_phy_read(bcm, 0x0801);
647                         backup[15] = bcm43xx_phy_read(bcm, 0x0060);
648                         backup[16] = bcm43xx_phy_read(bcm, 0x0014);
649                         backup[17] = bcm43xx_phy_read(bcm, 0x0478);
650                         bcm43xx_phy_write(bcm, 0x002E, 0);
651                         bcm43xx_phy_write(bcm, BCM43xx_PHY_G_LO_CONTROL, 0);
652                         switch (phy->rev) {
653                         case 4: case 6: case 7:
654                                 bcm43xx_phy_write(bcm, 0x0478,
655                                                   bcm43xx_phy_read(bcm, 0x0478)
656                                                   | 0x0100);
657                                 bcm43xx_phy_write(bcm, 0x0801,
658                                                   bcm43xx_phy_read(bcm, 0x0801)
659                                                   | 0x0040);
660                                 break;
661                         case 3: case 5:
662                                 bcm43xx_phy_write(bcm, 0x0801,
663                                                   bcm43xx_phy_read(bcm, 0x0801)
664                                                   & 0xFFBF);
665                                 break;
666                         }
667                         bcm43xx_phy_write(bcm, 0x0060,
668                                           bcm43xx_phy_read(bcm, 0x0060)
669                                           | 0x0040);
670                         bcm43xx_phy_write(bcm, 0x0014,
671                                           bcm43xx_phy_read(bcm, 0x0014)
672                                           | 0x0200);
673                 }
674                 bcm43xx_radio_write16(bcm, 0x007A,
675                                       bcm43xx_radio_read16(bcm, 0x007A) | 0x0070);
676                 bcm43xx_set_all_gains(bcm, 0, 8, 0);
677                 bcm43xx_radio_write16(bcm, 0x007A,
678                                       bcm43xx_radio_read16(bcm, 0x007A) & 0x00F7);
679                 if (phy->rev >= 2) {
680                         bcm43xx_phy_write(bcm, 0x0811,
681                                           (bcm43xx_phy_read(bcm, 0x0811) & 0xFFCF) | 0x0030);
682                         bcm43xx_phy_write(bcm, 0x0812,
683                                           (bcm43xx_phy_read(bcm, 0x0812) & 0xFFCF) | 0x0010);
684                 }
685                 bcm43xx_radio_write16(bcm, 0x007A,
686                                       bcm43xx_radio_read16(bcm, 0x007A) | 0x0080);
687                 udelay(20);
688
689                 nrssi0 = (s16)((bcm43xx_phy_read(bcm, 0x047F) >> 8) & 0x003F);
690                 if (nrssi0 >= 0x0020)
691                         nrssi0 -= 0x0040;
692
693                 bcm43xx_radio_write16(bcm, 0x007A,
694                                       bcm43xx_radio_read16(bcm, 0x007A) & 0x007F);
695                 if (phy->rev >= 2) {
696                         bcm43xx_phy_write(bcm, 0x0003,
697                                           (bcm43xx_phy_read(bcm, 0x0003)
698                                            & 0xFF9F) | 0x0040);
699                 }
700
701                 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT,
702                                 bcm43xx_read16(bcm, BCM43xx_MMIO_CHANNEL_EXT)
703                                 | 0x2000);
704                 bcm43xx_radio_write16(bcm, 0x007A,
705                                       bcm43xx_radio_read16(bcm, 0x007A) | 0x000F);
706                 bcm43xx_phy_write(bcm, 0x0015, 0xF330);
707                 if (phy->rev >= 2) {
708                         bcm43xx_phy_write(bcm, 0x0812,
709                                           (bcm43xx_phy_read(bcm, 0x0812) & 0xFFCF) | 0x0020);
710                         bcm43xx_phy_write(bcm, 0x0811,
711                                           (bcm43xx_phy_read(bcm, 0x0811) & 0xFFCF) | 0x0020);
712                 }
713
714                 bcm43xx_set_all_gains(bcm, 3, 0, 1);
715                 if (radio->revision == 8) {
716                         bcm43xx_radio_write16(bcm, 0x0043, 0x001F);
717                 } else {
718                         tmp = bcm43xx_radio_read16(bcm, 0x0052) & 0xFF0F;
719                         bcm43xx_radio_write16(bcm, 0x0052, tmp | 0x0060);
720                         tmp = bcm43xx_radio_read16(bcm, 0x0043) & 0xFFF0;
721                         bcm43xx_radio_write16(bcm, 0x0043, tmp | 0x0009);
722                 }
723                 bcm43xx_phy_write(bcm, 0x005A, 0x0480);
724                 bcm43xx_phy_write(bcm, 0x0059, 0x0810);
725                 bcm43xx_phy_write(bcm, 0x0058, 0x000D);
726                 udelay(20);
727                 nrssi1 = (s16)((bcm43xx_phy_read(bcm, 0x047F) >> 8) & 0x003F);
728                 if (nrssi1 >= 0x0020)
729                         nrssi1 -= 0x0040;
730                 if (nrssi0 == nrssi1)
731                         radio->nrssislope = 0x00010000;
732                 else
733                         radio->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
734                 if (nrssi0 >= -4) {
735                         radio->nrssi[0] = nrssi1;
736                         radio->nrssi[1] = nrssi0;
737                 }
738                 if (phy->rev >= 3) {
739                         bcm43xx_phy_write(bcm, 0x002E, backup[10]);
740                         bcm43xx_phy_write(bcm, 0x002F, backup[11]);
741                         bcm43xx_phy_write(bcm, 0x080F, backup[12]);
742                         bcm43xx_phy_write(bcm, BCM43xx_PHY_G_LO_CONTROL, backup[13]);
743                 }
744                 if (phy->rev >= 2) {
745                         bcm43xx_phy_write(bcm, 0x0812,
746                                           bcm43xx_phy_read(bcm, 0x0812) & 0xFFCF);
747                         bcm43xx_phy_write(bcm, 0x0811,
748                                           bcm43xx_phy_read(bcm, 0x0811) & 0xFFCF);
749                 }
750
751                 bcm43xx_radio_write16(bcm, 0x007A, backup[0]);
752                 bcm43xx_radio_write16(bcm, 0x0052, backup[1]);
753                 bcm43xx_radio_write16(bcm, 0x0043, backup[2]);
754                 bcm43xx_write16(bcm, 0x03E2, backup[7]);
755                 bcm43xx_write16(bcm, 0x03E6, backup[8]);
756                 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT, backup[9]);
757                 bcm43xx_phy_write(bcm, 0x0015, backup[3]);
758                 bcm43xx_phy_write(bcm, 0x005A, backup[4]);
759                 bcm43xx_phy_write(bcm, 0x0059, backup[5]);
760                 bcm43xx_phy_write(bcm, 0x0058, backup[6]);
761                 bcm43xx_synth_pu_workaround(bcm, radio->channel);
762                 bcm43xx_phy_write(bcm, 0x0802,
763                                   bcm43xx_phy_read(bcm, 0x0802) | (0x0001 | 0x0002));
764                 bcm43xx_set_original_gains(bcm);
765                 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
766                                   bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS) | 0x8000);
767                 if (phy->rev >= 3) {
768                         bcm43xx_phy_write(bcm, 0x0801, backup[14]);
769                         bcm43xx_phy_write(bcm, 0x0060, backup[15]);
770                         bcm43xx_phy_write(bcm, 0x0014, backup[16]);
771                         bcm43xx_phy_write(bcm, 0x0478, backup[17]);
772                 }
773                 bcm43xx_nrssi_mem_update(bcm);
774                 bcm43xx_calc_nrssi_threshold(bcm);
775                 break;
776         default:
777                 assert(0);
778         }
779 }
780
781 void bcm43xx_calc_nrssi_threshold(struct bcm43xx_private *bcm)
782 {
783         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
784         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
785         s32 threshold;
786         s32 a, b;
787         s16 tmp16;
788         u16 tmp_u16;
789
790         switch (phy->type) {
791         case BCM43xx_PHYTYPE_B: {
792                 if (radio->version != 0x2050)
793                         return;
794                 if (!(bcm->sprom.boardflags & BCM43xx_BFL_RSSI))
795                         return;
796
797                 if (radio->revision >= 6) {
798                         threshold = (radio->nrssi[1] - radio->nrssi[0]) * 32;
799                         threshold += 20 * (radio->nrssi[0] + 1);
800                         threshold /= 40;
801                 } else
802                         threshold = radio->nrssi[1] - 5;
803
804                 threshold = limit_value(threshold, 0, 0x3E);
805                 bcm43xx_phy_read(bcm, 0x0020); /* dummy read */
806                 bcm43xx_phy_write(bcm, 0x0020, (((u16)threshold) << 8) | 0x001C);
807
808                 if (radio->revision >= 6) {
809                         bcm43xx_phy_write(bcm, 0x0087, 0x0E0D);
810                         bcm43xx_phy_write(bcm, 0x0086, 0x0C0B);
811                         bcm43xx_phy_write(bcm, 0x0085, 0x0A09);
812                         bcm43xx_phy_write(bcm, 0x0084, 0x0808);
813                         bcm43xx_phy_write(bcm, 0x0083, 0x0808);
814                         bcm43xx_phy_write(bcm, 0x0082, 0x0604);
815                         bcm43xx_phy_write(bcm, 0x0081, 0x0302);
816                         bcm43xx_phy_write(bcm, 0x0080, 0x0100);
817                 }
818                 break;
819         }
820         case BCM43xx_PHYTYPE_G:
821                 if (!phy->connected ||
822                     !(bcm->sprom.boardflags & BCM43xx_BFL_RSSI)) {
823                         tmp16 = bcm43xx_nrssi_hw_read(bcm, 0x20);
824                         if (tmp16 >= 0x20)
825                                 tmp16 -= 0x40;
826                         if (tmp16 < 3) {
827                                 bcm43xx_phy_write(bcm, 0x048A,
828                                                   (bcm43xx_phy_read(bcm, 0x048A)
829                                                    & 0xF000) | 0x09EB);
830                         } else {
831                                 bcm43xx_phy_write(bcm, 0x048A,
832                                                   (bcm43xx_phy_read(bcm, 0x048A)
833                                                    & 0xF000) | 0x0AED);
834                         }
835                 } else {
836                         if (radio->interfmode == BCM43xx_RADIO_INTERFMODE_NONWLAN) {
837                                 a = 0xE;
838                                 b = 0xA;
839                         } else if (!radio->aci_wlan_automatic && radio->aci_enable) {
840                                 a = 0x13;
841                                 b = 0x12;
842                         } else {
843                                 a = 0xE;
844                                 b = 0x11;
845                         }
846
847                         a = a * (radio->nrssi[1] - radio->nrssi[0]);
848                         a += (radio->nrssi[0] << 6);
849                         if (a < 32)
850                                 a += 31;
851                         else
852                                 a += 32;
853                         a = a >> 6;
854                         a = limit_value(a, -31, 31);
855
856                         b = b * (radio->nrssi[1] - radio->nrssi[0]);
857                         b += (radio->nrssi[0] << 6);
858                         if (b < 32)
859                                 b += 31;
860                         else
861                                 b += 32;
862                         b = b >> 6;
863                         b = limit_value(b, -31, 31);
864
865                         tmp_u16 = bcm43xx_phy_read(bcm, 0x048A) & 0xF000;
866                         tmp_u16 |= ((u32)b & 0x0000003F);
867                         tmp_u16 |= (((u32)a & 0x0000003F) << 6);
868                         bcm43xx_phy_write(bcm, 0x048A, tmp_u16);
869                 }
870                 break;
871         default:
872                 assert(0);
873         }
874 }
875
876 /* Stack implementation to save/restore values from the
877  * interference mitigation code.
878  * It is save to restore values in random order.
879  */
880 static void _stack_save(u32 *_stackptr, size_t *stackidx,
881                         u8 id, u16 offset, u16 value)
882 {
883         u32 *stackptr = &(_stackptr[*stackidx]);
884
885         assert((offset & 0xF000) == 0x0000);
886         assert((id & 0xF0) == 0x00);
887         *stackptr = offset;
888         *stackptr |= ((u32)id) << 12;
889         *stackptr |= ((u32)value) << 16;
890         (*stackidx)++;
891         assert(*stackidx < BCM43xx_INTERFSTACK_SIZE);
892 }
893
894 static u16 _stack_restore(u32 *stackptr,
895                           u8 id, u16 offset)
896 {
897         size_t i;
898
899         assert((offset & 0xF000) == 0x0000);
900         assert((id & 0xF0) == 0x00);
901         for (i = 0; i < BCM43xx_INTERFSTACK_SIZE; i++, stackptr++) {
902                 if ((*stackptr & 0x00000FFF) != offset)
903                         continue;
904                 if (((*stackptr & 0x0000F000) >> 12) != id)
905                         continue;
906                 return ((*stackptr & 0xFFFF0000) >> 16);
907         }
908         assert(0);
909
910         return 0;
911 }
912
913 #define phy_stacksave(offset)                                   \
914         do {                                                    \
915                 _stack_save(stack, &stackidx, 0x1, (offset),    \
916                             bcm43xx_phy_read(bcm, (offset)));   \
917         } while (0)
918 #define phy_stackrestore(offset)                                \
919         do {                                                    \
920                 bcm43xx_phy_write(bcm, (offset),                \
921                                   _stack_restore(stack, 0x1,    \
922                                                  (offset)));    \
923         } while (0)
924 #define radio_stacksave(offset)                                         \
925         do {                                                            \
926                 _stack_save(stack, &stackidx, 0x2, (offset),            \
927                             bcm43xx_radio_read16(bcm, (offset)));       \
928         } while (0)
929 #define radio_stackrestore(offset)                                      \
930         do {                                                            \
931                 bcm43xx_radio_write16(bcm, (offset),                    \
932                                       _stack_restore(stack, 0x2,        \
933                                                      (offset)));        \
934         } while (0)
935 #define ilt_stacksave(offset)                                   \
936         do {                                                    \
937                 _stack_save(stack, &stackidx, 0x3, (offset),    \
938                             bcm43xx_ilt_read(bcm, (offset)));   \
939         } while (0)
940 #define ilt_stackrestore(offset)                                \
941         do {                                                    \
942                 bcm43xx_ilt_write(bcm, (offset),                \
943                                   _stack_restore(stack, 0x3,    \
944                                                  (offset)));    \
945         } while (0)
946
947 static void
948 bcm43xx_radio_interference_mitigation_enable(struct bcm43xx_private *bcm,
949                                              int mode)
950 {
951         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
952         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
953         u16 tmp, flipped;
954         u32 tmp32;
955         size_t stackidx = 0;
956         u32 *stack = radio->interfstack;
957
958         switch (mode) {
959         case BCM43xx_RADIO_INTERFMODE_NONWLAN:
960                 if (phy->rev != 1) {
961                         bcm43xx_phy_write(bcm, 0x042B,
962                                           bcm43xx_phy_read(bcm, 0x042B) | 0x0800);
963                         bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
964                                           bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS) & ~0x4000);
965                         break;
966                 }
967                 radio_stacksave(0x0078);
968                 tmp = (bcm43xx_radio_read16(bcm, 0x0078) & 0x001E);
969                 flipped = flip_4bit(tmp);
970                 if (flipped < 10 && flipped >= 8)
971                         flipped = 7;
972                 else if (flipped >= 10)
973                         flipped -= 3;
974                 flipped = flip_4bit(flipped);
975                 flipped = (flipped << 1) | 0x0020;
976                 bcm43xx_radio_write16(bcm, 0x0078, flipped);
977
978                 bcm43xx_calc_nrssi_threshold(bcm);
979
980                 phy_stacksave(0x0406);
981                 bcm43xx_phy_write(bcm, 0x0406, 0x7E28);
982
983                 bcm43xx_phy_write(bcm, 0x042B,
984                                   bcm43xx_phy_read(bcm, 0x042B) | 0x0800);
985                 bcm43xx_phy_write(bcm, BCM43xx_PHY_RADIO_BITFIELD,
986                                   bcm43xx_phy_read(bcm, BCM43xx_PHY_RADIO_BITFIELD) | 0x1000);
987
988                 phy_stacksave(0x04A0);
989                 bcm43xx_phy_write(bcm, 0x04A0,
990                                   (bcm43xx_phy_read(bcm, 0x04A0) & 0xC0C0) | 0x0008);
991                 phy_stacksave(0x04A1);
992                 bcm43xx_phy_write(bcm, 0x04A1,
993                                   (bcm43xx_phy_read(bcm, 0x04A1) & 0xC0C0) | 0x0605);
994                 phy_stacksave(0x04A2);
995                 bcm43xx_phy_write(bcm, 0x04A2,
996                                   (bcm43xx_phy_read(bcm, 0x04A2) & 0xC0C0) | 0x0204);
997                 phy_stacksave(0x04A8);
998                 bcm43xx_phy_write(bcm, 0x04A8,
999                                   (bcm43xx_phy_read(bcm, 0x04A8) & 0xC0C0) | 0x0803);
1000                 phy_stacksave(0x04AB);
1001                 bcm43xx_phy_write(bcm, 0x04AB,
1002                                   (bcm43xx_phy_read(bcm, 0x04AB) & 0xC0C0) | 0x0605);
1003
1004                 phy_stacksave(0x04A7);
1005                 bcm43xx_phy_write(bcm, 0x04A7, 0x0002);
1006                 phy_stacksave(0x04A3);
1007                 bcm43xx_phy_write(bcm, 0x04A3, 0x287A);
1008                 phy_stacksave(0x04A9);
1009                 bcm43xx_phy_write(bcm, 0x04A9, 0x2027);
1010                 phy_stacksave(0x0493);
1011                 bcm43xx_phy_write(bcm, 0x0493, 0x32F5);
1012                 phy_stacksave(0x04AA);
1013                 bcm43xx_phy_write(bcm, 0x04AA, 0x2027);
1014                 phy_stacksave(0x04AC);
1015                 bcm43xx_phy_write(bcm, 0x04AC, 0x32F5);
1016                 break;
1017         case BCM43xx_RADIO_INTERFMODE_MANUALWLAN:
1018                 if (bcm43xx_phy_read(bcm, 0x0033) & 0x0800)
1019                         break;
1020
1021                 radio->aci_enable = 1;
1022
1023                 phy_stacksave(BCM43xx_PHY_RADIO_BITFIELD);
1024                 phy_stacksave(BCM43xx_PHY_G_CRS);
1025                 if (phy->rev < 2) {
1026                         phy_stacksave(0x0406);
1027                 } else {
1028                         phy_stacksave(0x04C0);
1029                         phy_stacksave(0x04C1);
1030                 }
1031                 phy_stacksave(0x0033);
1032                 phy_stacksave(0x04A7);
1033                 phy_stacksave(0x04A3);
1034                 phy_stacksave(0x04A9);
1035                 phy_stacksave(0x04AA);
1036                 phy_stacksave(0x04AC);
1037                 phy_stacksave(0x0493);
1038                 phy_stacksave(0x04A1);
1039                 phy_stacksave(0x04A0);
1040                 phy_stacksave(0x04A2);
1041                 phy_stacksave(0x048A);
1042                 phy_stacksave(0x04A8);
1043                 phy_stacksave(0x04AB);
1044                 if (phy->rev == 2) {
1045                         phy_stacksave(0x04AD);
1046                         phy_stacksave(0x04AE);
1047                 } else if (phy->rev >= 3) {
1048                         phy_stacksave(0x04AD);
1049                         phy_stacksave(0x0415);
1050                         phy_stacksave(0x0416);
1051                         phy_stacksave(0x0417);
1052                         ilt_stacksave(0x1A00 + 0x2);
1053                         ilt_stacksave(0x1A00 + 0x3);
1054                 }
1055                 phy_stacksave(0x042B);
1056                 phy_stacksave(0x048C);
1057
1058                 bcm43xx_phy_write(bcm, BCM43xx_PHY_RADIO_BITFIELD,
1059                                   bcm43xx_phy_read(bcm, BCM43xx_PHY_RADIO_BITFIELD)
1060                                   & ~0x1000);
1061                 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
1062                                   (bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS)
1063                                    & 0xFFFC) | 0x0002);
1064
1065                 bcm43xx_phy_write(bcm, 0x0033, 0x0800);
1066                 bcm43xx_phy_write(bcm, 0x04A3, 0x2027);
1067                 bcm43xx_phy_write(bcm, 0x04A9, 0x1CA8);
1068                 bcm43xx_phy_write(bcm, 0x0493, 0x287A);
1069                 bcm43xx_phy_write(bcm, 0x04AA, 0x1CA8);
1070                 bcm43xx_phy_write(bcm, 0x04AC, 0x287A);
1071
1072                 bcm43xx_phy_write(bcm, 0x04A0,
1073                                   (bcm43xx_phy_read(bcm, 0x04A0)
1074                                    & 0xFFC0) | 0x001A);
1075                 bcm43xx_phy_write(bcm, 0x04A7, 0x000D);
1076
1077                 if (phy->rev < 2) {
1078                         bcm43xx_phy_write(bcm, 0x0406, 0xFF0D);
1079                 } else if (phy->rev == 2) {
1080                         bcm43xx_phy_write(bcm, 0x04C0, 0xFFFF);
1081                         bcm43xx_phy_write(bcm, 0x04C1, 0x00A9);
1082                 } else {
1083                         bcm43xx_phy_write(bcm, 0x04C0, 0x00C1);
1084                         bcm43xx_phy_write(bcm, 0x04C1, 0x0059);
1085                 }
1086
1087                 bcm43xx_phy_write(bcm, 0x04A1,
1088                                   (bcm43xx_phy_read(bcm, 0x04A1)
1089                                    & 0xC0FF) | 0x1800);
1090                 bcm43xx_phy_write(bcm, 0x04A1,
1091                                   (bcm43xx_phy_read(bcm, 0x04A1)
1092                                    & 0xFFC0) | 0x0015);
1093                 bcm43xx_phy_write(bcm, 0x04A8,
1094                                   (bcm43xx_phy_read(bcm, 0x04A8)
1095                                    & 0xCFFF) | 0x1000);
1096                 bcm43xx_phy_write(bcm, 0x04A8,
1097                                   (bcm43xx_phy_read(bcm, 0x04A8)
1098                                    & 0xF0FF) | 0x0A00);
1099                 bcm43xx_phy_write(bcm, 0x04AB,
1100                                   (bcm43xx_phy_read(bcm, 0x04AB)
1101                                    & 0xCFFF) | 0x1000);
1102                 bcm43xx_phy_write(bcm, 0x04AB,
1103                                   (bcm43xx_phy_read(bcm, 0x04AB)
1104                                    & 0xF0FF) | 0x0800);
1105                 bcm43xx_phy_write(bcm, 0x04AB,
1106                                   (bcm43xx_phy_read(bcm, 0x04AB)
1107                                    & 0xFFCF) | 0x0010);
1108                 bcm43xx_phy_write(bcm, 0x04AB,
1109                                   (bcm43xx_phy_read(bcm, 0x04AB)
1110                                    & 0xFFF0) | 0x0005);
1111                 bcm43xx_phy_write(bcm, 0x04A8,
1112                                   (bcm43xx_phy_read(bcm, 0x04A8)
1113                                    & 0xFFCF) | 0x0010);
1114                 bcm43xx_phy_write(bcm, 0x04A8,
1115                                   (bcm43xx_phy_read(bcm, 0x04A8)
1116                                    & 0xFFF0) | 0x0006);
1117                 bcm43xx_phy_write(bcm, 0x04A2,
1118                                   (bcm43xx_phy_read(bcm, 0x04A2)
1119                                    & 0xF0FF) | 0x0800);
1120                 bcm43xx_phy_write(bcm, 0x04A0,
1121                                   (bcm43xx_phy_read(bcm, 0x04A0)
1122                                    & 0xF0FF) | 0x0500);
1123                 bcm43xx_phy_write(bcm, 0x04A2,
1124                                   (bcm43xx_phy_read(bcm, 0x04A2)
1125                                    & 0xFFF0) | 0x000B);
1126
1127                 if (phy->rev >= 3) {
1128                         bcm43xx_phy_write(bcm, 0x048A,
1129                                           bcm43xx_phy_read(bcm, 0x048A)
1130                                           & ~0x8000);
1131                         bcm43xx_phy_write(bcm, 0x0415,
1132                                           (bcm43xx_phy_read(bcm, 0x0415)
1133                                            & 0x8000) | 0x36D8);
1134                         bcm43xx_phy_write(bcm, 0x0416,
1135                                           (bcm43xx_phy_read(bcm, 0x0416)
1136                                            & 0x8000) | 0x36D8);
1137                         bcm43xx_phy_write(bcm, 0x0417,
1138                                           (bcm43xx_phy_read(bcm, 0x0417)
1139                                            & 0xFE00) | 0x016D);
1140                 } else {
1141                         bcm43xx_phy_write(bcm, 0x048A,
1142                                           bcm43xx_phy_read(bcm, 0x048A)
1143                                           | 0x1000);
1144                         bcm43xx_phy_write(bcm, 0x048A,
1145                                           (bcm43xx_phy_read(bcm, 0x048A)
1146                                            & 0x9FFF) | 0x2000);
1147                         tmp32 = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
1148                                                    BCM43xx_UCODEFLAGS_OFFSET);
1149                         if (!(tmp32 & 0x800)) {
1150                                 tmp32 |= 0x800;
1151                                 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
1152                                                     BCM43xx_UCODEFLAGS_OFFSET,
1153                                                     tmp32);
1154                         }
1155                 }
1156                 if (phy->rev >= 2) {
1157                         bcm43xx_phy_write(bcm, 0x042B,
1158                                           bcm43xx_phy_read(bcm, 0x042B)
1159                                           | 0x0800);
1160                 }
1161                 bcm43xx_phy_write(bcm, 0x048C,
1162                                   (bcm43xx_phy_read(bcm, 0x048C)
1163                                    & 0xF0FF) | 0x0200);
1164                 if (phy->rev == 2) {
1165                         bcm43xx_phy_write(bcm, 0x04AE,
1166                                           (bcm43xx_phy_read(bcm, 0x04AE)
1167                                            & 0xFF00) | 0x007F);
1168                         bcm43xx_phy_write(bcm, 0x04AD,
1169                                           (bcm43xx_phy_read(bcm, 0x04AD)
1170                                            & 0x00FF) | 0x1300);
1171                 } else if (phy->rev >= 6) {
1172                         bcm43xx_ilt_write(bcm, 0x1A00 + 0x3, 0x007F);
1173                         bcm43xx_ilt_write(bcm, 0x1A00 + 0x2, 0x007F);
1174                         bcm43xx_phy_write(bcm, 0x04AD,
1175                                           bcm43xx_phy_read(bcm, 0x04AD)
1176                                           & 0x00FF);
1177                 }
1178                 bcm43xx_calc_nrssi_slope(bcm);
1179                 break;
1180         default:
1181                 assert(0);
1182         }
1183 }
1184
1185 static void
1186 bcm43xx_radio_interference_mitigation_disable(struct bcm43xx_private *bcm,
1187                                               int mode)
1188 {
1189         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1190         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1191         u32 tmp32;
1192         u32 *stack = radio->interfstack;
1193
1194         switch (mode) {
1195         case BCM43xx_RADIO_INTERFMODE_NONWLAN:
1196                 if (phy->rev != 1) {
1197                         bcm43xx_phy_write(bcm, 0x042B,
1198                                           bcm43xx_phy_read(bcm, 0x042B) & ~0x0800);
1199                         bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
1200                                           bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS) | 0x4000);
1201                         break;
1202                 }
1203                 phy_stackrestore(0x0078);
1204                 bcm43xx_calc_nrssi_threshold(bcm);
1205                 phy_stackrestore(0x0406);
1206                 bcm43xx_phy_write(bcm, 0x042B,
1207                                   bcm43xx_phy_read(bcm, 0x042B) & ~0x0800);
1208                 if (!bcm->bad_frames_preempt) {
1209                         bcm43xx_phy_write(bcm, BCM43xx_PHY_RADIO_BITFIELD,
1210                                           bcm43xx_phy_read(bcm, BCM43xx_PHY_RADIO_BITFIELD)
1211                                           & ~(1 << 11));
1212                 }
1213                 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
1214                                   bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS) | 0x4000);
1215                 phy_stackrestore(0x04A0);
1216                 phy_stackrestore(0x04A1);
1217                 phy_stackrestore(0x04A2);
1218                 phy_stackrestore(0x04A8);
1219                 phy_stackrestore(0x04AB);
1220                 phy_stackrestore(0x04A7);
1221                 phy_stackrestore(0x04A3);
1222                 phy_stackrestore(0x04A9);
1223                 phy_stackrestore(0x0493);
1224                 phy_stackrestore(0x04AA);
1225                 phy_stackrestore(0x04AC);
1226                 break;
1227         case BCM43xx_RADIO_INTERFMODE_MANUALWLAN:
1228                 if (!(bcm43xx_phy_read(bcm, 0x0033) & 0x0800))
1229                         break;
1230
1231                 radio->aci_enable = 0;
1232
1233                 phy_stackrestore(BCM43xx_PHY_RADIO_BITFIELD);
1234                 phy_stackrestore(BCM43xx_PHY_G_CRS);
1235                 phy_stackrestore(0x0033);
1236                 phy_stackrestore(0x04A3);
1237                 phy_stackrestore(0x04A9);
1238                 phy_stackrestore(0x0493);
1239                 phy_stackrestore(0x04AA);
1240                 phy_stackrestore(0x04AC);
1241                 phy_stackrestore(0x04A0);
1242                 phy_stackrestore(0x04A7);
1243                 if (phy->rev >= 2) {
1244                         phy_stackrestore(0x04C0);
1245                         phy_stackrestore(0x04C1);
1246                 } else
1247                         phy_stackrestore(0x0406);
1248                 phy_stackrestore(0x04A1);
1249                 phy_stackrestore(0x04AB);
1250                 phy_stackrestore(0x04A8);
1251                 if (phy->rev == 2) {
1252                         phy_stackrestore(0x04AD);
1253                         phy_stackrestore(0x04AE);
1254                 } else if (phy->rev >= 3) {
1255                         phy_stackrestore(0x04AD);
1256                         phy_stackrestore(0x0415);
1257                         phy_stackrestore(0x0416);
1258                         phy_stackrestore(0x0417);
1259                         ilt_stackrestore(0x1A00 + 0x2);
1260                         ilt_stackrestore(0x1A00 + 0x3);
1261                 }
1262                 phy_stackrestore(0x04A2);
1263                 phy_stackrestore(0x04A8);
1264                 phy_stackrestore(0x042B);
1265                 phy_stackrestore(0x048C);
1266                 tmp32 = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
1267                                            BCM43xx_UCODEFLAGS_OFFSET);
1268                 if (tmp32 & 0x800) {
1269                         tmp32 &= ~0x800;
1270                         bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
1271                                             BCM43xx_UCODEFLAGS_OFFSET,
1272                                             tmp32);
1273                 }
1274                 bcm43xx_calc_nrssi_slope(bcm);
1275                 break;
1276         default:
1277                 assert(0);
1278         }
1279 }
1280
1281 #undef phy_stacksave
1282 #undef phy_stackrestore
1283 #undef radio_stacksave
1284 #undef radio_stackrestore
1285 #undef ilt_stacksave
1286 #undef ilt_stackrestore
1287
1288 int bcm43xx_radio_set_interference_mitigation(struct bcm43xx_private *bcm,
1289                                               int mode)
1290 {
1291         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1292         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1293         int currentmode;
1294
1295         if ((phy->type != BCM43xx_PHYTYPE_G) ||
1296             (phy->rev == 0) ||
1297             (!phy->connected))
1298                 return -ENODEV;
1299
1300         radio->aci_wlan_automatic = 0;
1301         switch (mode) {
1302         case BCM43xx_RADIO_INTERFMODE_AUTOWLAN:
1303                 radio->aci_wlan_automatic = 1;
1304                 if (radio->aci_enable)
1305                         mode = BCM43xx_RADIO_INTERFMODE_MANUALWLAN;
1306                 else
1307                         mode = BCM43xx_RADIO_INTERFMODE_NONE;
1308                 break;
1309         case BCM43xx_RADIO_INTERFMODE_NONE:
1310         case BCM43xx_RADIO_INTERFMODE_NONWLAN:
1311         case BCM43xx_RADIO_INTERFMODE_MANUALWLAN:
1312                 break;
1313         default:
1314                 return -EINVAL;
1315         }
1316
1317         currentmode = radio->interfmode;
1318         if (currentmode == mode)
1319                 return 0;
1320         if (currentmode != BCM43xx_RADIO_INTERFMODE_NONE)
1321                 bcm43xx_radio_interference_mitigation_disable(bcm, currentmode);
1322
1323         if (mode == BCM43xx_RADIO_INTERFMODE_NONE) {
1324                 radio->aci_enable = 0;
1325                 radio->aci_hw_rssi = 0;
1326         } else
1327                 bcm43xx_radio_interference_mitigation_enable(bcm, mode);
1328         radio->interfmode = mode;
1329
1330         return 0;
1331 }
1332
1333 u16 bcm43xx_radio_calibrationvalue(struct bcm43xx_private *bcm)
1334 {
1335         u16 reg, index, ret;
1336
1337         reg = bcm43xx_radio_read16(bcm, 0x0060);
1338         index = (reg & 0x001E) >> 1;
1339         ret = rcc_table[index] << 1;
1340         ret |= (reg & 0x0001);
1341         ret |= 0x0020;
1342
1343         return ret;
1344 }
1345
1346 u16 bcm43xx_radio_init2050(struct bcm43xx_private *bcm)
1347 {
1348         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1349         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1350         u16 backup[19] = { 0 };
1351         u16 ret;
1352         u16 i, j;
1353         u32 tmp1 = 0, tmp2 = 0;
1354
1355         backup[0] = bcm43xx_radio_read16(bcm, 0x0043);
1356         backup[14] = bcm43xx_radio_read16(bcm, 0x0051);
1357         backup[15] = bcm43xx_radio_read16(bcm, 0x0052);
1358         backup[1] = bcm43xx_phy_read(bcm, 0x0015);
1359         backup[16] = bcm43xx_phy_read(bcm, 0x005A);
1360         backup[17] = bcm43xx_phy_read(bcm, 0x0059);
1361         backup[18] = bcm43xx_phy_read(bcm, 0x0058);
1362         if (phy->type == BCM43xx_PHYTYPE_B) {
1363                 backup[2] = bcm43xx_phy_read(bcm, 0x0030);
1364                 backup[3] = bcm43xx_read16(bcm, 0x03EC);
1365                 bcm43xx_phy_write(bcm, 0x0030, 0x00FF);
1366                 bcm43xx_write16(bcm, 0x03EC, 0x3F3F);
1367         } else {
1368                 if (phy->connected) {
1369                         backup[4] = bcm43xx_phy_read(bcm, 0x0811);
1370                         backup[5] = bcm43xx_phy_read(bcm, 0x0812);
1371                         backup[6] = bcm43xx_phy_read(bcm, 0x0814);
1372                         backup[7] = bcm43xx_phy_read(bcm, 0x0815);
1373                         backup[8] = bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS);
1374                         backup[9] = bcm43xx_phy_read(bcm, 0x0802);
1375                         bcm43xx_phy_write(bcm, 0x0814,
1376                                           (bcm43xx_phy_read(bcm, 0x0814) | 0x0003));
1377                         bcm43xx_phy_write(bcm, 0x0815,
1378                                           (bcm43xx_phy_read(bcm, 0x0815) & 0xFFFC));    
1379                         bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
1380                                           (bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS) & 0x7FFF));
1381                         bcm43xx_phy_write(bcm, 0x0802,
1382                                           (bcm43xx_phy_read(bcm, 0x0802) & 0xFFFC));
1383                         bcm43xx_phy_write(bcm, 0x0811, 0x01B3);
1384                         bcm43xx_phy_write(bcm, 0x0812, 0x0FB2);
1385                 }
1386                 bcm43xx_write16(bcm, BCM43xx_MMIO_PHY_RADIO,
1387                                 (bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_RADIO) | 0x8000));
1388         }
1389         backup[10] = bcm43xx_phy_read(bcm, 0x0035);
1390         bcm43xx_phy_write(bcm, 0x0035,
1391                           (bcm43xx_phy_read(bcm, 0x0035) & 0xFF7F));
1392         backup[11] = bcm43xx_read16(bcm, 0x03E6);
1393         backup[12] = bcm43xx_read16(bcm, BCM43xx_MMIO_CHANNEL_EXT);
1394
1395         // Initialization
1396         if (phy->version == 0) {
1397                 bcm43xx_write16(bcm, 0x03E6, 0x0122);
1398         } else {
1399                 if (phy->version >= 2)
1400                         bcm43xx_write16(bcm, 0x03E6, 0x0040);
1401                 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT,
1402                                 (bcm43xx_read16(bcm, BCM43xx_MMIO_CHANNEL_EXT) | 0x2000));
1403         }
1404
1405         ret = bcm43xx_radio_calibrationvalue(bcm);
1406
1407         if (phy->type == BCM43xx_PHYTYPE_B)
1408                 bcm43xx_radio_write16(bcm, 0x0078, 0x0003);
1409
1410         bcm43xx_phy_write(bcm, 0x0015, 0xBFAF);
1411         bcm43xx_phy_write(bcm, 0x002B, 0x1403);
1412         if (phy->connected)
1413                 bcm43xx_phy_write(bcm, 0x0812, 0x00B2);
1414         bcm43xx_phy_write(bcm, 0x0015, 0xBFA0);
1415         bcm43xx_radio_write16(bcm, 0x0051,
1416                               (bcm43xx_radio_read16(bcm, 0x0051) | 0x0004));
1417         bcm43xx_radio_write16(bcm, 0x0052, 0x0000);
1418         bcm43xx_radio_write16(bcm, 0x0043,
1419                               bcm43xx_radio_read16(bcm, 0x0043) | 0x0009);
1420         bcm43xx_phy_write(bcm, 0x0058, 0x0000);
1421
1422         for (i = 0; i < 16; i++) {
1423                 bcm43xx_phy_write(bcm, 0x005A, 0x0480);
1424                 bcm43xx_phy_write(bcm, 0x0059, 0xC810);
1425                 bcm43xx_phy_write(bcm, 0x0058, 0x000D);
1426                 if (phy->connected)
1427                         bcm43xx_phy_write(bcm, 0x0812, 0x30B2);
1428                 bcm43xx_phy_write(bcm, 0x0015, 0xAFB0);
1429                 udelay(10);
1430                 if (phy->connected)
1431                         bcm43xx_phy_write(bcm, 0x0812, 0x30B2);
1432                 bcm43xx_phy_write(bcm, 0x0015, 0xEFB0);
1433                 udelay(10);
1434                 if (phy->connected)
1435                         bcm43xx_phy_write(bcm, 0x0812, 0x30B2);
1436                 bcm43xx_phy_write(bcm, 0x0015, 0xFFF0);
1437                 udelay(10);
1438                 tmp1 += bcm43xx_phy_read(bcm, 0x002D);
1439                 bcm43xx_phy_write(bcm, 0x0058, 0x0000);
1440                 if (phy->connected)
1441                         bcm43xx_phy_write(bcm, 0x0812, 0x30B2);
1442                 bcm43xx_phy_write(bcm, 0x0015, 0xAFB0);
1443         }
1444
1445         tmp1++;
1446         tmp1 >>= 9;
1447         udelay(10);
1448         bcm43xx_phy_write(bcm, 0x0058, 0x0000);
1449
1450         for (i = 0; i < 16; i++) {
1451                 bcm43xx_radio_write16(bcm, 0x0078, (flip_4bit(i) << 1) | 0x0020);
1452                 backup[13] = bcm43xx_radio_read16(bcm, 0x0078);
1453                 udelay(10);
1454                 for (j = 0; j < 16; j++) {
1455                         bcm43xx_phy_write(bcm, 0x005A, 0x0D80);
1456                         bcm43xx_phy_write(bcm, 0x0059, 0xC810);
1457                         bcm43xx_phy_write(bcm, 0x0058, 0x000D);
1458                         if (phy->connected)
1459                                 bcm43xx_phy_write(bcm, 0x0812, 0x30B2);
1460                         bcm43xx_phy_write(bcm, 0x0015, 0xAFB0);
1461                         udelay(10);
1462                         if (phy->connected)
1463                                 bcm43xx_phy_write(bcm, 0x0812, 0x30B2);
1464                         bcm43xx_phy_write(bcm, 0x0015, 0xEFB0);
1465                         udelay(10);
1466                         if (phy->connected)
1467                                 bcm43xx_phy_write(bcm, 0x0812, 0x30B3); /* 0x30B3 is not a typo */
1468                         bcm43xx_phy_write(bcm, 0x0015, 0xFFF0);
1469                         udelay(10);
1470                         tmp2 += bcm43xx_phy_read(bcm, 0x002D);
1471                         bcm43xx_phy_write(bcm, 0x0058, 0x0000);
1472                         if (phy->connected)
1473                                 bcm43xx_phy_write(bcm, 0x0812, 0x30B2);
1474                         bcm43xx_phy_write(bcm, 0x0015, 0xAFB0);
1475                 }
1476                 tmp2++;
1477                 tmp2 >>= 8;
1478                 if (tmp1 < tmp2)
1479                         break;
1480         }
1481
1482         /* Restore the registers */
1483         bcm43xx_phy_write(bcm, 0x0015, backup[1]);
1484         bcm43xx_radio_write16(bcm, 0x0051, backup[14]);
1485         bcm43xx_radio_write16(bcm, 0x0052, backup[15]);
1486         bcm43xx_radio_write16(bcm, 0x0043, backup[0]);
1487         bcm43xx_phy_write(bcm, 0x005A, backup[16]);
1488         bcm43xx_phy_write(bcm, 0x0059, backup[17]);
1489         bcm43xx_phy_write(bcm, 0x0058, backup[18]);
1490         bcm43xx_write16(bcm, 0x03E6, backup[11]);
1491         if (phy->version != 0)
1492                 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT, backup[12]);
1493         bcm43xx_phy_write(bcm, 0x0035, backup[10]);
1494         bcm43xx_radio_selectchannel(bcm, radio->channel, 1);
1495         if (phy->type == BCM43xx_PHYTYPE_B) {
1496                 bcm43xx_phy_write(bcm, 0x0030, backup[2]);
1497                 bcm43xx_write16(bcm, 0x03EC, backup[3]);
1498         } else {
1499                 bcm43xx_write16(bcm, BCM43xx_MMIO_PHY_RADIO,
1500                                 (bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_RADIO) & 0x7FFF));
1501                 if (phy->connected) {
1502                         bcm43xx_phy_write(bcm, 0x0811, backup[4]);
1503                         bcm43xx_phy_write(bcm, 0x0812, backup[5]);
1504                         bcm43xx_phy_write(bcm, 0x0814, backup[6]);
1505                         bcm43xx_phy_write(bcm, 0x0815, backup[7]);
1506                         bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS, backup[8]);
1507                         bcm43xx_phy_write(bcm, 0x0802, backup[9]);
1508                 }
1509         }
1510         if (i >= 15)
1511                 ret = backup[13];
1512
1513         return ret;
1514 }
1515
1516 void bcm43xx_radio_init2060(struct bcm43xx_private *bcm)
1517 {
1518         int err;
1519
1520         bcm43xx_radio_write16(bcm, 0x0004, 0x00C0);
1521         bcm43xx_radio_write16(bcm, 0x0005, 0x0008);
1522         bcm43xx_radio_write16(bcm, 0x0009, 0x0040);
1523         bcm43xx_radio_write16(bcm, 0x0005, 0x00AA);
1524         bcm43xx_radio_write16(bcm, 0x0032, 0x008F);
1525         bcm43xx_radio_write16(bcm, 0x0006, 0x008F);
1526         bcm43xx_radio_write16(bcm, 0x0034, 0x008F);
1527         bcm43xx_radio_write16(bcm, 0x002C, 0x0007);
1528         bcm43xx_radio_write16(bcm, 0x0082, 0x0080);
1529         bcm43xx_radio_write16(bcm, 0x0080, 0x0000);
1530         bcm43xx_radio_write16(bcm, 0x003F, 0x00DA);
1531         bcm43xx_radio_write16(bcm, 0x0005, bcm43xx_radio_read16(bcm, 0x0005) & ~0x0008);
1532         bcm43xx_radio_write16(bcm, 0x0081, bcm43xx_radio_read16(bcm, 0x0081) & ~0x0010);
1533         bcm43xx_radio_write16(bcm, 0x0081, bcm43xx_radio_read16(bcm, 0x0081) & ~0x0020);
1534         bcm43xx_radio_write16(bcm, 0x0081, bcm43xx_radio_read16(bcm, 0x0081) & ~0x0020);
1535         udelay(400);
1536
1537         bcm43xx_radio_write16(bcm, 0x0081, (bcm43xx_radio_read16(bcm, 0x0081) & ~0x0020) | 0x0010);
1538         udelay(400);
1539
1540         bcm43xx_radio_write16(bcm, 0x0005, (bcm43xx_radio_read16(bcm, 0x0005) & ~0x0008) | 0x0008);
1541         bcm43xx_radio_write16(bcm, 0x0085, bcm43xx_radio_read16(bcm, 0x0085) & ~0x0010);
1542         bcm43xx_radio_write16(bcm, 0x0005, bcm43xx_radio_read16(bcm, 0x0005) & ~0x0008);
1543         bcm43xx_radio_write16(bcm, 0x0081, bcm43xx_radio_read16(bcm, 0x0081) & ~0x0040);
1544         bcm43xx_radio_write16(bcm, 0x0081, (bcm43xx_radio_read16(bcm, 0x0081) & ~0x0040) | 0x0040);
1545         bcm43xx_radio_write16(bcm, 0x0005, (bcm43xx_radio_read16(bcm, 0x0081) & ~0x0008) | 0x0008);
1546         bcm43xx_phy_write(bcm, 0x0063, 0xDDC6);
1547         bcm43xx_phy_write(bcm, 0x0069, 0x07BE);
1548         bcm43xx_phy_write(bcm, 0x006A, 0x0000);
1549
1550         err = bcm43xx_radio_selectchannel(bcm, BCM43xx_RADIO_DEFAULT_CHANNEL_A, 0);
1551         assert(err == 0);
1552         udelay(1000);
1553 }
1554
1555 static inline
1556 u16 freq_r3A_value(u16 frequency)
1557 {
1558         u16 value;
1559
1560         if (frequency < 5091)
1561                 value = 0x0040;
1562         else if (frequency < 5321)
1563                 value = 0x0000;
1564         else if (frequency < 5806)
1565                 value = 0x0080;
1566         else
1567                 value = 0x0040;
1568
1569         return value;
1570 }
1571
1572 void bcm43xx_radio_set_tx_iq(struct bcm43xx_private *bcm)
1573 {
1574         static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
1575         static const u8 data_low[5]  = { 0x00, 0x01, 0x05, 0x06, 0x0A };
1576         u16 tmp = bcm43xx_radio_read16(bcm, 0x001E);
1577         int i, j;
1578         
1579         for (i = 0; i < 5; i++) {
1580                 for (j = 0; j < 5; j++) {
1581                         if (tmp == (data_high[i] << 4 | data_low[j])) {
1582                                 bcm43xx_phy_write(bcm, 0x0069, (i - j) << 8 | 0x00C0);
1583                                 return;
1584                         }
1585                 }
1586         }
1587 }
1588
1589 int bcm43xx_radio_selectchannel(struct bcm43xx_private *bcm,
1590                                 u8 channel,
1591                                 int synthetic_pu_workaround)
1592 {
1593         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1594         u16 r8, tmp;
1595         u16 freq;
1596
1597         if (!ieee80211_is_valid_channel(bcm->ieee, channel))
1598                 return -EINVAL;
1599         if ((radio->manufact == 0x17F) &&
1600             (radio->version == 0x2060) &&
1601             (radio->revision == 1)) {
1602                 freq = channel2freq_a(channel);
1603
1604                 r8 = bcm43xx_radio_read16(bcm, 0x0008);
1605                 bcm43xx_write16(bcm, 0x03F0, freq);
1606                 bcm43xx_radio_write16(bcm, 0x0008, r8);
1607
1608                 TODO();//TODO: write max channel TX power? to Radio 0x2D
1609                 tmp = bcm43xx_radio_read16(bcm, 0x002E);
1610                 tmp &= 0x0080;
1611                 TODO();//TODO: OR tmp with the Power out estimation for this channel?
1612                 bcm43xx_radio_write16(bcm, 0x002E, tmp);
1613
1614                 if (freq >= 4920 && freq <= 5500) {
1615                         /* 
1616                          * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
1617                          *    = (freq * 0.025862069
1618                          */
1619                         r8 = 3 * freq / 116; /* is equal to r8 = freq * 0.025862 */
1620                 }
1621                 bcm43xx_radio_write16(bcm, 0x0007, (r8 << 4) | r8);
1622                 bcm43xx_radio_write16(bcm, 0x0020, (r8 << 4) | r8);
1623                 bcm43xx_radio_write16(bcm, 0x0021, (r8 << 4) | r8);
1624                 bcm43xx_radio_write16(bcm, 0x0022,
1625                                       (bcm43xx_radio_read16(bcm, 0x0022)
1626                                        & 0x000F) | (r8 << 4));
1627                 bcm43xx_radio_write16(bcm, 0x002A, (r8 << 4));
1628                 bcm43xx_radio_write16(bcm, 0x002B, (r8 << 4));
1629                 bcm43xx_radio_write16(bcm, 0x0008,
1630                                       (bcm43xx_radio_read16(bcm, 0x0008)
1631                                        & 0x00F0) | (r8 << 4));
1632                 bcm43xx_radio_write16(bcm, 0x0029,
1633                                       (bcm43xx_radio_read16(bcm, 0x0029)
1634                                        & 0xFF0F) | 0x00B0);
1635                 bcm43xx_radio_write16(bcm, 0x0035, 0x00AA);
1636                 bcm43xx_radio_write16(bcm, 0x0036, 0x0085);
1637                 bcm43xx_radio_write16(bcm, 0x003A,
1638                                       (bcm43xx_radio_read16(bcm, 0x003A)
1639                                        & 0xFF20) | freq_r3A_value(freq));
1640                 bcm43xx_radio_write16(bcm, 0x003D,
1641                                       bcm43xx_radio_read16(bcm, 0x003D) & 0x00FF);
1642                 bcm43xx_radio_write16(bcm, 0x0081,
1643                                       (bcm43xx_radio_read16(bcm, 0x0081)
1644                                        & 0xFF7F) | 0x0080);
1645                 bcm43xx_radio_write16(bcm, 0x0035,
1646                                       bcm43xx_radio_read16(bcm, 0x0035) & 0xFFEF);
1647                 bcm43xx_radio_write16(bcm, 0x0035,
1648                                       (bcm43xx_radio_read16(bcm, 0x0035)
1649                                        & 0xFFEF) | 0x0010);
1650                 bcm43xx_radio_set_tx_iq(bcm);
1651                 TODO(); //TODO: TSSI2dbm workaround
1652                 bcm43xx_phy_xmitpower(bcm);//FIXME correct?
1653         } else {
1654                 if (synthetic_pu_workaround)
1655                         bcm43xx_synth_pu_workaround(bcm, channel);
1656
1657                 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL,
1658                                 channel2freq_bg(channel));
1659
1660                 if (channel == 14) {
1661                         if (bcm->sprom.locale == BCM43xx_LOCALE_JAPAN) {
1662                                 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
1663                                                     BCM43xx_UCODEFLAGS_OFFSET,
1664                                                     bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
1665                                                                        BCM43xx_UCODEFLAGS_OFFSET)
1666                                                     & ~(1 << 7));
1667                         } else {
1668                                 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
1669                                                     BCM43xx_UCODEFLAGS_OFFSET,
1670                                                     bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
1671                                                                        BCM43xx_UCODEFLAGS_OFFSET)
1672                                                     | (1 << 7));
1673                         }
1674                         bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT,
1675                                         bcm43xx_read16(bcm, BCM43xx_MMIO_CHANNEL_EXT)
1676                                         | (1 << 11));
1677                 } else {
1678                         bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT,
1679                                         bcm43xx_read16(bcm, BCM43xx_MMIO_CHANNEL_EXT)
1680                                         & 0xF7BF);
1681                 }
1682         }
1683
1684         radio->channel = channel;
1685         //XXX: Using the longer of 2 timeouts (8000 vs 2000 usecs). Specs states
1686         //     that 2000 usecs might suffice.
1687         udelay(8000);
1688
1689         return 0;
1690 }
1691
1692 void bcm43xx_radio_set_txantenna(struct bcm43xx_private *bcm, u32 val)
1693 {
1694         u16 tmp;
1695
1696         val <<= 8;
1697         tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x0022) & 0xFCFF;
1698         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0022, tmp | val);
1699         tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x03A8) & 0xFCFF;
1700         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x03A8, tmp | val);
1701         tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x0054) & 0xFCFF;
1702         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0054, tmp | val);
1703 }
1704
1705 /* http://bcm-specs.sipsolutions.net/TX_Gain_Base_Band */
1706 static u16 bcm43xx_get_txgain_base_band(u16 txpower)
1707 {
1708         u16 ret;
1709
1710         assert(txpower <= 63);
1711
1712         if (txpower >= 54)
1713                 ret = 2;
1714         else if (txpower >= 49)
1715                 ret = 4;
1716         else if (txpower >= 44)
1717                 ret = 5;
1718         else
1719                 ret = 6;
1720
1721         return ret;
1722 }
1723
1724 /* http://bcm-specs.sipsolutions.net/TX_Gain_Radio_Frequency_Power_Amplifier */
1725 static u16 bcm43xx_get_txgain_freq_power_amp(u16 txpower)
1726 {
1727         u16 ret;
1728
1729         assert(txpower <= 63);
1730
1731         if (txpower >= 32)
1732                 ret = 0;
1733         else if (txpower >= 25)
1734                 ret = 1;
1735         else if (txpower >= 20)
1736                 ret = 2;
1737         else if (txpower >= 12)
1738                 ret = 3;
1739         else
1740                 ret = 4;
1741
1742         return ret;
1743 }
1744
1745 /* http://bcm-specs.sipsolutions.net/TX_Gain_Digital_Analog_Converter */
1746 static u16 bcm43xx_get_txgain_dac(u16 txpower)
1747 {
1748         u16 ret;
1749
1750         assert(txpower <= 63);
1751
1752         if (txpower >= 54)
1753                 ret = txpower - 53;
1754         else if (txpower >= 49)
1755                 ret = txpower - 42;
1756         else if (txpower >= 44)
1757                 ret = txpower - 37;
1758         else if (txpower >= 32)
1759                 ret = txpower - 32;
1760         else if (txpower >= 25)
1761                 ret = txpower - 20;
1762         else if (txpower >= 20)
1763                 ret = txpower - 13;
1764         else if (txpower >= 12)
1765                 ret = txpower - 8;
1766         else
1767                 ret = txpower;
1768
1769         return ret;
1770 }
1771
1772 void bcm43xx_radio_set_txpower_a(struct bcm43xx_private *bcm, u16 txpower)
1773 {
1774         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1775         u16 pamp, base, dac, ilt;
1776
1777         txpower = limit_value(txpower, 0, 63);
1778
1779         pamp = bcm43xx_get_txgain_freq_power_amp(txpower);
1780         pamp <<= 5;
1781         pamp &= 0x00E0;
1782         bcm43xx_phy_write(bcm, 0x0019, pamp);
1783
1784         base = bcm43xx_get_txgain_base_band(txpower);
1785         base &= 0x000F;
1786         bcm43xx_phy_write(bcm, 0x0017, base | 0x0020);
1787
1788         ilt = bcm43xx_ilt_read(bcm, 0x3001);
1789         ilt &= 0x0007;
1790
1791         dac = bcm43xx_get_txgain_dac(txpower);
1792         dac <<= 3;
1793         dac |= ilt;
1794
1795         bcm43xx_ilt_write(bcm, 0x3001, dac);
1796
1797         radio->txpwr_offset = txpower;
1798
1799         TODO();
1800         //TODO: FuncPlaceholder (Adjust BB loft cancel)
1801 }
1802
1803 void bcm43xx_radio_set_txpower_bg(struct bcm43xx_private *bcm,
1804                                  u16 baseband_attenuation, u16 radio_attenuation,
1805                                  u16 txpower)
1806 {
1807         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1808         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1809
1810         if (baseband_attenuation == 0xFFFF)
1811                 baseband_attenuation = radio->baseband_atten;
1812         if (radio_attenuation == 0xFFFF)
1813                 radio_attenuation = radio->radio_atten;
1814         if (txpower == 0xFFFF)
1815                 txpower = radio->txctl1;
1816         radio->baseband_atten = baseband_attenuation;
1817         radio->radio_atten = radio_attenuation;
1818         radio->txctl1 = txpower;
1819
1820         assert(/*baseband_attenuation >= 0 &&*/ baseband_attenuation <= 11);
1821         if (radio->revision < 6)
1822                 assert(/*radio_attenuation >= 0 &&*/ radio_attenuation <= 9);
1823         else
1824                 assert(/* radio_attenuation >= 0 &&*/ radio_attenuation <= 31);
1825         assert(/*txpower >= 0 &&*/ txpower <= 7);
1826
1827         bcm43xx_phy_set_baseband_attenuation(bcm, baseband_attenuation);
1828         bcm43xx_radio_write16(bcm, 0x0043, radio_attenuation);
1829         bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0064, radio_attenuation);
1830         if (radio->version == 0x2050) {
1831                 bcm43xx_radio_write16(bcm, 0x0052,
1832                                       (bcm43xx_radio_read16(bcm, 0x0052) & ~0x0070)
1833                                        | ((txpower << 4) & 0x0070));
1834         }
1835         //FIXME: The spec is very weird and unclear here.
1836         if (phy->type == BCM43xx_PHYTYPE_G)
1837                 bcm43xx_phy_lo_adjust(bcm, 0);
1838 }
1839
1840 u16 bcm43xx_default_baseband_attenuation(struct bcm43xx_private *bcm)
1841 {
1842         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1843
1844         if (radio->version == 0x2050 && radio->revision < 6)
1845                 return 0;
1846         return 2;
1847 }
1848
1849 u16 bcm43xx_default_radio_attenuation(struct bcm43xx_private *bcm)
1850 {
1851         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1852         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1853         u16 att = 0xFFFF;
1854
1855         if (phy->type == BCM43xx_PHYTYPE_A)
1856                 return 0x60;
1857
1858         switch (radio->version) {
1859         case 0x2053:
1860                 switch (radio->revision) {
1861                 case 1:
1862                         att = 6;
1863                         break;
1864                 }
1865                 break;
1866         case 0x2050:
1867                 switch (radio->revision) {
1868                 case 0:
1869                         att = 5;
1870                         break;
1871                 case 1:
1872                         if (phy->type == BCM43xx_PHYTYPE_G) {
1873                                 if (bcm->board_vendor == PCI_VENDOR_ID_BROADCOM &&
1874                                     bcm->board_type == 0x421 &&
1875                                     bcm->board_revision >= 30)
1876                                         att = 3;
1877                                 else if (bcm->board_vendor == PCI_VENDOR_ID_BROADCOM &&
1878                                          bcm->board_type == 0x416)
1879                                         att = 3;
1880                                 else
1881                                         att = 1;
1882                         } else {
1883                                 if (bcm->board_vendor == PCI_VENDOR_ID_BROADCOM &&
1884                                     bcm->board_type == 0x421 &&
1885                                     bcm->board_revision >= 30)
1886                                         att = 7;
1887                                 else
1888                                         att = 6;
1889                         }
1890                         break;
1891                 case 2:
1892                         if (phy->type == BCM43xx_PHYTYPE_G) {
1893                                 if (bcm->board_vendor == PCI_VENDOR_ID_BROADCOM &&
1894                                     bcm->board_type == 0x421 &&
1895                                     bcm->board_revision >= 30)
1896                                         att = 3;
1897                                 else if (bcm->board_vendor == PCI_VENDOR_ID_BROADCOM &&
1898                                          bcm->board_type == 0x416)
1899                                         att = 5;
1900                                 else if (bcm->chip_id == 0x4320)
1901                                         att = 4;
1902                                 else
1903                                         att = 3;
1904                         } else
1905                                 att = 6;
1906                         break;
1907                 case 3:
1908                         att = 5;
1909                         break;
1910                 case 4:
1911                 case 5:
1912                         att = 1;
1913                         break;
1914                 case 6:
1915                 case 7:
1916                         att = 5;
1917                         break;
1918                 case 8:
1919                         att = 0x1A;
1920                         break;
1921                 case 9:
1922                 default:
1923                         att = 5;
1924                 }
1925         }
1926         if (bcm->board_vendor == PCI_VENDOR_ID_BROADCOM &&
1927             bcm->board_type == 0x421) {
1928                 if (bcm->board_revision < 0x43)
1929                         att = 2;
1930                 else if (bcm->board_revision < 0x51)
1931                         att = 3;
1932         }
1933         if (att == 0xFFFF)
1934                 att = 5;
1935
1936         return att;
1937 }
1938
1939 u16 bcm43xx_default_txctl1(struct bcm43xx_private *bcm)
1940 {
1941         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1942
1943         if (radio->version != 0x2050)
1944                 return 0;
1945         if (radio->revision == 1)
1946                 return 3;
1947         if (radio->revision < 6)
1948                 return 2;
1949         if (radio->revision == 8)
1950                 return 1;
1951         return 0;
1952 }
1953
1954 void bcm43xx_radio_turn_on(struct bcm43xx_private *bcm)
1955 {
1956         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1957         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1958         int err;
1959
1960         if (radio->enabled)
1961                 return;
1962
1963         switch (phy->type) {
1964         case BCM43xx_PHYTYPE_A:
1965                 bcm43xx_radio_write16(bcm, 0x0004, 0x00C0);
1966                 bcm43xx_radio_write16(bcm, 0x0005, 0x0008);
1967                 bcm43xx_phy_write(bcm, 0x0010, bcm43xx_phy_read(bcm, 0x0010) & 0xFFF7);
1968                 bcm43xx_phy_write(bcm, 0x0011, bcm43xx_phy_read(bcm, 0x0011) & 0xFFF7);
1969                 bcm43xx_radio_init2060(bcm);    
1970                 break;
1971         case BCM43xx_PHYTYPE_B:
1972         case BCM43xx_PHYTYPE_G:
1973                 bcm43xx_phy_write(bcm, 0x0015, 0x8000);
1974                 bcm43xx_phy_write(bcm, 0x0015, 0xCC00);
1975                 bcm43xx_phy_write(bcm, 0x0015, (phy->connected ? 0x00C0 : 0x0000));
1976                 err = bcm43xx_radio_selectchannel(bcm, BCM43xx_RADIO_DEFAULT_CHANNEL_BG, 1);
1977                 assert(err == 0);
1978                 break;
1979         default:
1980                 assert(0);
1981         }
1982         radio->enabled = 1;
1983         dprintk(KERN_INFO PFX "Radio turned on\n");
1984 }
1985         
1986 void bcm43xx_radio_turn_off(struct bcm43xx_private *bcm)
1987 {
1988         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1989         struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1990
1991         if (phy->type == BCM43xx_PHYTYPE_A) {
1992                 bcm43xx_radio_write16(bcm, 0x0004, 0x00FF);
1993                 bcm43xx_radio_write16(bcm, 0x0005, 0x00FB);
1994                 bcm43xx_phy_write(bcm, 0x0010, bcm43xx_phy_read(bcm, 0x0010) | 0x0008);
1995                 bcm43xx_phy_write(bcm, 0x0011, bcm43xx_phy_read(bcm, 0x0011) | 0x0008);
1996         }
1997         if (phy->type == BCM43xx_PHYTYPE_G && bcm->current_core->rev >= 5) {
1998                 bcm43xx_phy_write(bcm, 0x0811, bcm43xx_phy_read(bcm, 0x0811) | 0x008C);
1999                 bcm43xx_phy_write(bcm, 0x0812, bcm43xx_phy_read(bcm, 0x0812) & 0xFF73);
2000         } else
2001                 bcm43xx_phy_write(bcm, 0x0015, 0xAA00);
2002         radio->enabled = 0;
2003         dprintk(KERN_INFO PFX "Radio turned off\n");
2004 }
2005
2006 void bcm43xx_radio_clear_tssi(struct bcm43xx_private *bcm)
2007 {
2008         struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2009
2010         switch (phy->type) {
2011         case BCM43xx_PHYTYPE_A:
2012                 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0068, 0x7F7F);
2013                 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x006a, 0x7F7F);
2014                 break;
2015         case BCM43xx_PHYTYPE_B:
2016         case BCM43xx_PHYTYPE_G:
2017                 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0058, 0x7F7F);
2018                 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x005a, 0x7F7F);
2019                 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0070, 0x7F7F);
2020                 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0072, 0x7F7F);
2021                 break;
2022         }
2023 }