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[linux-3.10.git] / drivers / net / tg3.h
1 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2  * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  */
8
9 #ifndef _T3_H
10 #define _T3_H
11
12 #define TG3_64BIT_REG_HIGH              0x00UL
13 #define TG3_64BIT_REG_LOW               0x04UL
14
15 /* Descriptor block info. */
16 #define TG3_BDINFO_HOST_ADDR            0x0UL /* 64-bit */
17 #define TG3_BDINFO_MAXLEN_FLAGS         0x8UL /* 32-bit */
18 #define  BDINFO_FLAGS_USE_EXT_RECV       0x00000001 /* ext rx_buffer_desc */
19 #define  BDINFO_FLAGS_DISABLED           0x00000002
20 #define  BDINFO_FLAGS_MAXLEN_MASK        0xffff0000
21 #define  BDINFO_FLAGS_MAXLEN_SHIFT       16
22 #define TG3_BDINFO_NIC_ADDR             0xcUL /* 32-bit */
23 #define TG3_BDINFO_SIZE                 0x10UL
24
25 #define RX_COPY_THRESHOLD               256
26
27 #define RX_STD_MAX_SIZE                 1536
28 #define RX_STD_MAX_SIZE_5705            512
29 #define RX_JUMBO_MAX_SIZE               0xdeadbeef /* XXX */
30
31 /* First 256 bytes are a mirror of PCI config space. */
32 #define TG3PCI_VENDOR                   0x00000000
33 #define  TG3PCI_VENDOR_BROADCOM          0x14e4
34 #define TG3PCI_DEVICE                   0x00000002
35 #define  TG3PCI_DEVICE_TIGON3_1          0x1644 /* BCM5700 */
36 #define  TG3PCI_DEVICE_TIGON3_2          0x1645 /* BCM5701 */
37 #define  TG3PCI_DEVICE_TIGON3_3          0x1646 /* BCM5702 */
38 #define  TG3PCI_DEVICE_TIGON3_4          0x1647 /* BCM5703 */
39 #define TG3PCI_COMMAND                  0x00000004
40 #define TG3PCI_STATUS                   0x00000006
41 #define TG3PCI_CCREVID                  0x00000008
42 #define TG3PCI_CACHELINESZ              0x0000000c
43 #define TG3PCI_LATTIMER                 0x0000000d
44 #define TG3PCI_HEADERTYPE               0x0000000e
45 #define TG3PCI_BIST                     0x0000000f
46 #define TG3PCI_BASE0_LOW                0x00000010
47 #define TG3PCI_BASE0_HIGH               0x00000014
48 /* 0x18 --> 0x2c unused */
49 #define TG3PCI_SUBSYSVENID              0x0000002c
50 #define TG3PCI_SUBSYSID                 0x0000002e
51 #define TG3PCI_ROMADDR                  0x00000030
52 #define TG3PCI_CAPLIST                  0x00000034
53 /* 0x35 --> 0x3c unused */
54 #define TG3PCI_IRQ_LINE                 0x0000003c
55 #define TG3PCI_IRQ_PIN                  0x0000003d
56 #define TG3PCI_MIN_GNT                  0x0000003e
57 #define TG3PCI_MAX_LAT                  0x0000003f
58 #define TG3PCI_X_CAPS                   0x00000040
59 #define  PCIX_CAPS_RELAXED_ORDERING      0x00020000
60 #define  PCIX_CAPS_SPLIT_MASK            0x00700000
61 #define  PCIX_CAPS_SPLIT_SHIFT           20
62 #define  PCIX_CAPS_BURST_MASK            0x000c0000
63 #define  PCIX_CAPS_BURST_SHIFT           18
64 #define  PCIX_CAPS_MAX_BURST_CPIOB       2
65 #define TG3PCI_PM_CAP_PTR               0x00000041
66 #define TG3PCI_X_COMMAND                0x00000042
67 #define TG3PCI_X_STATUS                 0x00000044
68 #define TG3PCI_PM_CAP_ID                0x00000048
69 #define TG3PCI_VPD_CAP_PTR              0x00000049
70 #define TG3PCI_PM_CAPS                  0x0000004a
71 #define TG3PCI_PM_CTRL_STAT             0x0000004c
72 #define TG3PCI_BR_SUPP_EXT              0x0000004e
73 #define TG3PCI_PM_DATA                  0x0000004f
74 #define TG3PCI_VPD_CAP_ID               0x00000050
75 #define TG3PCI_MSI_CAP_PTR              0x00000051
76 #define TG3PCI_VPD_ADDR_FLAG            0x00000052
77 #define  VPD_ADDR_FLAG_WRITE            0x00008000
78 #define TG3PCI_VPD_DATA                 0x00000054
79 #define TG3PCI_MSI_CAP_ID               0x00000058
80 #define TG3PCI_NXT_CAP_PTR              0x00000059
81 #define TG3PCI_MSI_CTRL                 0x0000005a
82 #define TG3PCI_MSI_ADDR_LOW             0x0000005c
83 #define TG3PCI_MSI_ADDR_HIGH            0x00000060
84 #define TG3PCI_MSI_DATA                 0x00000064
85 /* 0x66 --> 0x68 unused */
86 #define TG3PCI_MISC_HOST_CTRL           0x00000068
87 #define  MISC_HOST_CTRL_CLEAR_INT        0x00000001
88 #define  MISC_HOST_CTRL_MASK_PCI_INT     0x00000002
89 #define  MISC_HOST_CTRL_BYTE_SWAP        0x00000004
90 #define  MISC_HOST_CTRL_WORD_SWAP        0x00000008
91 #define  MISC_HOST_CTRL_PCISTATE_RW      0x00000010
92 #define  MISC_HOST_CTRL_CLKREG_RW        0x00000020
93 #define  MISC_HOST_CTRL_REGWORD_SWAP     0x00000040
94 #define  MISC_HOST_CTRL_INDIR_ACCESS     0x00000080
95 #define  MISC_HOST_CTRL_IRQ_MASK_MODE    0x00000100
96 #define  MISC_HOST_CTRL_TAGGED_STATUS    0x00000200
97 #define  MISC_HOST_CTRL_CHIPREV          0xffff0000
98 #define  MISC_HOST_CTRL_CHIPREV_SHIFT    16
99 #define  GET_CHIP_REV_ID(MISC_HOST_CTRL) \
100          (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
101           MISC_HOST_CTRL_CHIPREV_SHIFT)
102 #define  CHIPREV_ID_5700_A0              0x7000
103 #define  CHIPREV_ID_5700_A1              0x7001
104 #define  CHIPREV_ID_5700_B0              0x7100
105 #define  CHIPREV_ID_5700_B1              0x7101
106 #define  CHIPREV_ID_5700_B3              0x7102
107 #define  CHIPREV_ID_5700_ALTIMA          0x7104
108 #define  CHIPREV_ID_5700_C0              0x7200
109 #define  CHIPREV_ID_5701_A0              0x0000
110 #define  CHIPREV_ID_5701_B0              0x0100
111 #define  CHIPREV_ID_5701_B2              0x0102
112 #define  CHIPREV_ID_5701_B5              0x0105
113 #define  CHIPREV_ID_5703_A0              0x1000
114 #define  CHIPREV_ID_5703_A1              0x1001
115 #define  CHIPREV_ID_5703_A2              0x1002
116 #define  CHIPREV_ID_5703_A3              0x1003
117 #define  CHIPREV_ID_5704_A0              0x2000
118 #define  CHIPREV_ID_5704_A1              0x2001
119 #define  CHIPREV_ID_5704_A2              0x2002
120 #define  CHIPREV_ID_5704_A3              0x2003
121 #define  CHIPREV_ID_5705_A0              0x3000
122 #define  CHIPREV_ID_5705_A1              0x3001
123 #define  CHIPREV_ID_5705_A2              0x3002
124 #define  CHIPREV_ID_5705_A3              0x3003
125 #define  CHIPREV_ID_5750_A0              0x4000
126 #define  CHIPREV_ID_5750_A1              0x4001
127 #define  CHIPREV_ID_5750_A3              0x4003
128 #define  CHIPREV_ID_5752_A0_HW           0x5000
129 #define  CHIPREV_ID_5752_A0              0x6000
130 #define  CHIPREV_ID_5752_A1              0x6001
131 #define  GET_ASIC_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 12)
132 #define   ASIC_REV_5700                  0x07
133 #define   ASIC_REV_5701                  0x00
134 #define   ASIC_REV_5703                  0x01
135 #define   ASIC_REV_5704                  0x02
136 #define   ASIC_REV_5705                  0x03
137 #define   ASIC_REV_5750                  0x04
138 #define   ASIC_REV_5752                  0x06
139 #define  GET_CHIP_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 8)
140 #define   CHIPREV_5700_AX                0x70
141 #define   CHIPREV_5700_BX                0x71
142 #define   CHIPREV_5700_CX                0x72
143 #define   CHIPREV_5701_AX                0x00
144 #define   CHIPREV_5703_AX                0x10
145 #define   CHIPREV_5704_AX                0x20
146 #define   CHIPREV_5704_BX                0x21
147 #define   CHIPREV_5750_AX                0x40
148 #define   CHIPREV_5750_BX                0x41
149 #define  GET_METAL_REV(CHIP_REV_ID)     ((CHIP_REV_ID) & 0xff)
150 #define   METAL_REV_A0                   0x00
151 #define   METAL_REV_A1                   0x01
152 #define   METAL_REV_B0                   0x00
153 #define   METAL_REV_B1                   0x01
154 #define   METAL_REV_B2                   0x02
155 #define TG3PCI_DMA_RW_CTRL              0x0000006c
156 #define  DMA_RWCTRL_MIN_DMA              0x000000ff
157 #define  DMA_RWCTRL_MIN_DMA_SHIFT        0
158 #define  DMA_RWCTRL_READ_BNDRY_MASK      0x00000700
159 #define  DMA_RWCTRL_READ_BNDRY_DISAB     0x00000000
160 #define  DMA_RWCTRL_READ_BNDRY_16        0x00000100
161 #define  DMA_RWCTRL_READ_BNDRY_128_PCIX  0x00000100
162 #define  DMA_RWCTRL_READ_BNDRY_32        0x00000200
163 #define  DMA_RWCTRL_READ_BNDRY_256_PCIX  0x00000200
164 #define  DMA_RWCTRL_READ_BNDRY_64        0x00000300
165 #define  DMA_RWCTRL_READ_BNDRY_384_PCIX  0x00000300
166 #define  DMA_RWCTRL_READ_BNDRY_128       0x00000400
167 #define  DMA_RWCTRL_READ_BNDRY_256       0x00000500
168 #define  DMA_RWCTRL_READ_BNDRY_512       0x00000600
169 #define  DMA_RWCTRL_READ_BNDRY_1024      0x00000700
170 #define  DMA_RWCTRL_WRITE_BNDRY_MASK     0x00003800
171 #define  DMA_RWCTRL_WRITE_BNDRY_DISAB    0x00000000
172 #define  DMA_RWCTRL_WRITE_BNDRY_16       0x00000800
173 #define  DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
174 #define  DMA_RWCTRL_WRITE_BNDRY_32       0x00001000
175 #define  DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
176 #define  DMA_RWCTRL_WRITE_BNDRY_64       0x00001800
177 #define  DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
178 #define  DMA_RWCTRL_WRITE_BNDRY_128      0x00002000
179 #define  DMA_RWCTRL_WRITE_BNDRY_256      0x00002800
180 #define  DMA_RWCTRL_WRITE_BNDRY_512      0x00003000
181 #define  DMA_RWCTRL_WRITE_BNDRY_1024     0x00003800
182 #define  DMA_RWCTRL_ONE_DMA              0x00004000
183 #define  DMA_RWCTRL_READ_WATER           0x00070000
184 #define  DMA_RWCTRL_READ_WATER_SHIFT     16
185 #define  DMA_RWCTRL_WRITE_WATER          0x00380000
186 #define  DMA_RWCTRL_WRITE_WATER_SHIFT    19
187 #define  DMA_RWCTRL_USE_MEM_READ_MULT    0x00400000
188 #define  DMA_RWCTRL_ASSERT_ALL_BE        0x00800000
189 #define  DMA_RWCTRL_PCI_READ_CMD         0x0f000000
190 #define  DMA_RWCTRL_PCI_READ_CMD_SHIFT   24
191 #define  DMA_RWCTRL_PCI_WRITE_CMD        0xf0000000
192 #define  DMA_RWCTRL_PCI_WRITE_CMD_SHIFT  28
193 #define  DMA_RWCTRL_WRITE_BNDRY_64_PCIE  0x10000000
194 #define  DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
195 #define  DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
196 #define TG3PCI_PCISTATE                 0x00000070
197 #define  PCISTATE_FORCE_RESET            0x00000001
198 #define  PCISTATE_INT_NOT_ACTIVE         0x00000002
199 #define  PCISTATE_CONV_PCI_MODE          0x00000004
200 #define  PCISTATE_BUS_SPEED_HIGH         0x00000008
201 #define  PCISTATE_BUS_32BIT              0x00000010
202 #define  PCISTATE_ROM_ENABLE             0x00000020
203 #define  PCISTATE_ROM_RETRY_ENABLE       0x00000040
204 #define  PCISTATE_FLAT_VIEW              0x00000100
205 #define  PCISTATE_RETRY_SAME_DMA         0x00002000
206 #define TG3PCI_CLOCK_CTRL               0x00000074
207 #define  CLOCK_CTRL_CORECLK_DISABLE      0x00000200
208 #define  CLOCK_CTRL_RXCLK_DISABLE        0x00000400
209 #define  CLOCK_CTRL_TXCLK_DISABLE        0x00000800
210 #define  CLOCK_CTRL_ALTCLK               0x00001000
211 #define  CLOCK_CTRL_PWRDOWN_PLL133       0x00008000
212 #define  CLOCK_CTRL_44MHZ_CORE           0x00040000
213 #define  CLOCK_CTRL_625_CORE             0x00100000
214 #define  CLOCK_CTRL_FORCE_CLKRUN         0x00200000
215 #define  CLOCK_CTRL_CLKRUN_OENABLE       0x00400000
216 #define  CLOCK_CTRL_DELAY_PCI_GRANT      0x80000000
217 #define TG3PCI_REG_BASE_ADDR            0x00000078
218 #define TG3PCI_MEM_WIN_BASE_ADDR        0x0000007c
219 #define TG3PCI_REG_DATA                 0x00000080
220 #define TG3PCI_MEM_WIN_DATA             0x00000084
221 #define TG3PCI_MODE_CTRL                0x00000088
222 #define TG3PCI_MISC_CFG                 0x0000008c
223 #define TG3PCI_MISC_LOCAL_CTRL          0x00000090
224 /* 0x94 --> 0x98 unused */
225 #define TG3PCI_STD_RING_PROD_IDX        0x00000098 /* 64-bit */
226 #define TG3PCI_RCV_RET_RING_CON_IDX     0x000000a0 /* 64-bit */
227 #define TG3PCI_SND_PROD_IDX             0x000000a8 /* 64-bit */
228 /* 0xb0 --> 0xb8 unused */
229 #define TG3PCI_DUAL_MAC_CTRL            0x000000b8
230 #define  DUAL_MAC_CTRL_CH_MASK           0x00000003
231 #define  DUAL_MAC_CTRL_ID                0x00000004
232 /* 0xbc --> 0x100 unused */
233
234 /* 0x100 --> 0x200 unused */
235
236 /* Mailbox registers */
237 #define MAILBOX_INTERRUPT_0             0x00000200 /* 64-bit */
238 #define MAILBOX_INTERRUPT_1             0x00000208 /* 64-bit */
239 #define MAILBOX_INTERRUPT_2             0x00000210 /* 64-bit */
240 #define MAILBOX_INTERRUPT_3             0x00000218 /* 64-bit */
241 #define MAILBOX_GENERAL_0               0x00000220 /* 64-bit */
242 #define MAILBOX_GENERAL_1               0x00000228 /* 64-bit */
243 #define MAILBOX_GENERAL_2               0x00000230 /* 64-bit */
244 #define MAILBOX_GENERAL_3               0x00000238 /* 64-bit */
245 #define MAILBOX_GENERAL_4               0x00000240 /* 64-bit */
246 #define MAILBOX_GENERAL_5               0x00000248 /* 64-bit */
247 #define MAILBOX_GENERAL_6               0x00000250 /* 64-bit */
248 #define MAILBOX_GENERAL_7               0x00000258 /* 64-bit */
249 #define MAILBOX_RELOAD_STAT             0x00000260 /* 64-bit */
250 #define MAILBOX_RCV_STD_PROD_IDX        0x00000268 /* 64-bit */
251 #define MAILBOX_RCV_JUMBO_PROD_IDX      0x00000270 /* 64-bit */
252 #define MAILBOX_RCV_MINI_PROD_IDX       0x00000278 /* 64-bit */
253 #define MAILBOX_RCVRET_CON_IDX_0        0x00000280 /* 64-bit */
254 #define MAILBOX_RCVRET_CON_IDX_1        0x00000288 /* 64-bit */
255 #define MAILBOX_RCVRET_CON_IDX_2        0x00000290 /* 64-bit */
256 #define MAILBOX_RCVRET_CON_IDX_3        0x00000298 /* 64-bit */
257 #define MAILBOX_RCVRET_CON_IDX_4        0x000002a0 /* 64-bit */
258 #define MAILBOX_RCVRET_CON_IDX_5        0x000002a8 /* 64-bit */
259 #define MAILBOX_RCVRET_CON_IDX_6        0x000002b0 /* 64-bit */
260 #define MAILBOX_RCVRET_CON_IDX_7        0x000002b8 /* 64-bit */
261 #define MAILBOX_RCVRET_CON_IDX_8        0x000002c0 /* 64-bit */
262 #define MAILBOX_RCVRET_CON_IDX_9        0x000002c8 /* 64-bit */
263 #define MAILBOX_RCVRET_CON_IDX_10       0x000002d0 /* 64-bit */
264 #define MAILBOX_RCVRET_CON_IDX_11       0x000002d8 /* 64-bit */
265 #define MAILBOX_RCVRET_CON_IDX_12       0x000002e0 /* 64-bit */
266 #define MAILBOX_RCVRET_CON_IDX_13       0x000002e8 /* 64-bit */
267 #define MAILBOX_RCVRET_CON_IDX_14       0x000002f0 /* 64-bit */
268 #define MAILBOX_RCVRET_CON_IDX_15       0x000002f8 /* 64-bit */
269 #define MAILBOX_SNDHOST_PROD_IDX_0      0x00000300 /* 64-bit */
270 #define MAILBOX_SNDHOST_PROD_IDX_1      0x00000308 /* 64-bit */
271 #define MAILBOX_SNDHOST_PROD_IDX_2      0x00000310 /* 64-bit */
272 #define MAILBOX_SNDHOST_PROD_IDX_3      0x00000318 /* 64-bit */
273 #define MAILBOX_SNDHOST_PROD_IDX_4      0x00000320 /* 64-bit */
274 #define MAILBOX_SNDHOST_PROD_IDX_5      0x00000328 /* 64-bit */
275 #define MAILBOX_SNDHOST_PROD_IDX_6      0x00000330 /* 64-bit */
276 #define MAILBOX_SNDHOST_PROD_IDX_7      0x00000338 /* 64-bit */
277 #define MAILBOX_SNDHOST_PROD_IDX_8      0x00000340 /* 64-bit */
278 #define MAILBOX_SNDHOST_PROD_IDX_9      0x00000348 /* 64-bit */
279 #define MAILBOX_SNDHOST_PROD_IDX_10     0x00000350 /* 64-bit */
280 #define MAILBOX_SNDHOST_PROD_IDX_11     0x00000358 /* 64-bit */
281 #define MAILBOX_SNDHOST_PROD_IDX_12     0x00000360 /* 64-bit */
282 #define MAILBOX_SNDHOST_PROD_IDX_13     0x00000368 /* 64-bit */
283 #define MAILBOX_SNDHOST_PROD_IDX_14     0x00000370 /* 64-bit */
284 #define MAILBOX_SNDHOST_PROD_IDX_15     0x00000378 /* 64-bit */
285 #define MAILBOX_SNDNIC_PROD_IDX_0       0x00000380 /* 64-bit */
286 #define MAILBOX_SNDNIC_PROD_IDX_1       0x00000388 /* 64-bit */
287 #define MAILBOX_SNDNIC_PROD_IDX_2       0x00000390 /* 64-bit */
288 #define MAILBOX_SNDNIC_PROD_IDX_3       0x00000398 /* 64-bit */
289 #define MAILBOX_SNDNIC_PROD_IDX_4       0x000003a0 /* 64-bit */
290 #define MAILBOX_SNDNIC_PROD_IDX_5       0x000003a8 /* 64-bit */
291 #define MAILBOX_SNDNIC_PROD_IDX_6       0x000003b0 /* 64-bit */
292 #define MAILBOX_SNDNIC_PROD_IDX_7       0x000003b8 /* 64-bit */
293 #define MAILBOX_SNDNIC_PROD_IDX_8       0x000003c0 /* 64-bit */
294 #define MAILBOX_SNDNIC_PROD_IDX_9       0x000003c8 /* 64-bit */
295 #define MAILBOX_SNDNIC_PROD_IDX_10      0x000003d0 /* 64-bit */
296 #define MAILBOX_SNDNIC_PROD_IDX_11      0x000003d8 /* 64-bit */
297 #define MAILBOX_SNDNIC_PROD_IDX_12      0x000003e0 /* 64-bit */
298 #define MAILBOX_SNDNIC_PROD_IDX_13      0x000003e8 /* 64-bit */
299 #define MAILBOX_SNDNIC_PROD_IDX_14      0x000003f0 /* 64-bit */
300 #define MAILBOX_SNDNIC_PROD_IDX_15      0x000003f8 /* 64-bit */
301
302 /* MAC control registers */
303 #define MAC_MODE                        0x00000400
304 #define  MAC_MODE_RESET                  0x00000001
305 #define  MAC_MODE_HALF_DUPLEX            0x00000002
306 #define  MAC_MODE_PORT_MODE_MASK         0x0000000c
307 #define  MAC_MODE_PORT_MODE_TBI          0x0000000c
308 #define  MAC_MODE_PORT_MODE_GMII         0x00000008
309 #define  MAC_MODE_PORT_MODE_MII          0x00000004
310 #define  MAC_MODE_PORT_MODE_NONE         0x00000000
311 #define  MAC_MODE_PORT_INT_LPBACK        0x00000010
312 #define  MAC_MODE_TAGGED_MAC_CTRL        0x00000080
313 #define  MAC_MODE_TX_BURSTING            0x00000100
314 #define  MAC_MODE_MAX_DEFER              0x00000200
315 #define  MAC_MODE_LINK_POLARITY          0x00000400
316 #define  MAC_MODE_RXSTAT_ENABLE          0x00000800
317 #define  MAC_MODE_RXSTAT_CLEAR           0x00001000
318 #define  MAC_MODE_RXSTAT_FLUSH           0x00002000
319 #define  MAC_MODE_TXSTAT_ENABLE          0x00004000
320 #define  MAC_MODE_TXSTAT_CLEAR           0x00008000
321 #define  MAC_MODE_TXSTAT_FLUSH           0x00010000
322 #define  MAC_MODE_SEND_CONFIGS           0x00020000
323 #define  MAC_MODE_MAGIC_PKT_ENABLE       0x00040000
324 #define  MAC_MODE_ACPI_ENABLE            0x00080000
325 #define  MAC_MODE_MIP_ENABLE             0x00100000
326 #define  MAC_MODE_TDE_ENABLE             0x00200000
327 #define  MAC_MODE_RDE_ENABLE             0x00400000
328 #define  MAC_MODE_FHDE_ENABLE            0x00800000
329 #define MAC_STATUS                      0x00000404
330 #define  MAC_STATUS_PCS_SYNCED           0x00000001
331 #define  MAC_STATUS_SIGNAL_DET           0x00000002
332 #define  MAC_STATUS_RCVD_CFG             0x00000004
333 #define  MAC_STATUS_CFG_CHANGED          0x00000008
334 #define  MAC_STATUS_SYNC_CHANGED         0x00000010
335 #define  MAC_STATUS_PORT_DEC_ERR         0x00000400
336 #define  MAC_STATUS_LNKSTATE_CHANGED     0x00001000
337 #define  MAC_STATUS_MI_COMPLETION        0x00400000
338 #define  MAC_STATUS_MI_INTERRUPT         0x00800000
339 #define  MAC_STATUS_AP_ERROR             0x01000000
340 #define  MAC_STATUS_ODI_ERROR            0x02000000
341 #define  MAC_STATUS_RXSTAT_OVERRUN       0x04000000
342 #define  MAC_STATUS_TXSTAT_OVERRUN       0x08000000
343 #define MAC_EVENT                       0x00000408
344 #define  MAC_EVENT_PORT_DECODE_ERR       0x00000400
345 #define  MAC_EVENT_LNKSTATE_CHANGED      0x00001000
346 #define  MAC_EVENT_MI_COMPLETION         0x00400000
347 #define  MAC_EVENT_MI_INTERRUPT          0x00800000
348 #define  MAC_EVENT_AP_ERROR              0x01000000
349 #define  MAC_EVENT_ODI_ERROR             0x02000000
350 #define  MAC_EVENT_RXSTAT_OVERRUN        0x04000000
351 #define  MAC_EVENT_TXSTAT_OVERRUN        0x08000000
352 #define MAC_LED_CTRL                    0x0000040c
353 #define  LED_CTRL_LNKLED_OVERRIDE        0x00000001
354 #define  LED_CTRL_1000MBPS_ON            0x00000002
355 #define  LED_CTRL_100MBPS_ON             0x00000004
356 #define  LED_CTRL_10MBPS_ON              0x00000008
357 #define  LED_CTRL_TRAFFIC_OVERRIDE       0x00000010
358 #define  LED_CTRL_TRAFFIC_BLINK          0x00000020
359 #define  LED_CTRL_TRAFFIC_LED            0x00000040
360 #define  LED_CTRL_1000MBPS_STATUS        0x00000080
361 #define  LED_CTRL_100MBPS_STATUS         0x00000100
362 #define  LED_CTRL_10MBPS_STATUS          0x00000200
363 #define  LED_CTRL_TRAFFIC_STATUS         0x00000400
364 #define  LED_CTRL_MODE_MAC               0x00000000
365 #define  LED_CTRL_MODE_PHY_1             0x00000800
366 #define  LED_CTRL_MODE_PHY_2             0x00001000
367 #define  LED_CTRL_MODE_SHASTA_MAC        0x00002000
368 #define  LED_CTRL_MODE_SHARED            0x00004000
369 #define  LED_CTRL_MODE_COMBO             0x00008000
370 #define  LED_CTRL_BLINK_RATE_MASK        0x7ff80000
371 #define  LED_CTRL_BLINK_RATE_SHIFT       19
372 #define  LED_CTRL_BLINK_PER_OVERRIDE     0x00080000
373 #define  LED_CTRL_BLINK_RATE_OVERRIDE    0x80000000
374 #define MAC_ADDR_0_HIGH                 0x00000410 /* upper 2 bytes */
375 #define MAC_ADDR_0_LOW                  0x00000414 /* lower 4 bytes */
376 #define MAC_ADDR_1_HIGH                 0x00000418 /* upper 2 bytes */
377 #define MAC_ADDR_1_LOW                  0x0000041c /* lower 4 bytes */
378 #define MAC_ADDR_2_HIGH                 0x00000420 /* upper 2 bytes */
379 #define MAC_ADDR_2_LOW                  0x00000424 /* lower 4 bytes */
380 #define MAC_ADDR_3_HIGH                 0x00000428 /* upper 2 bytes */
381 #define MAC_ADDR_3_LOW                  0x0000042c /* lower 4 bytes */
382 #define MAC_ACPI_MBUF_PTR               0x00000430
383 #define MAC_ACPI_LEN_OFFSET             0x00000434
384 #define  ACPI_LENOFF_LEN_MASK            0x0000ffff
385 #define  ACPI_LENOFF_LEN_SHIFT           0
386 #define  ACPI_LENOFF_OFF_MASK            0x0fff0000
387 #define  ACPI_LENOFF_OFF_SHIFT           16
388 #define MAC_TX_BACKOFF_SEED             0x00000438
389 #define  TX_BACKOFF_SEED_MASK            0x000003ff
390 #define MAC_RX_MTU_SIZE                 0x0000043c
391 #define  RX_MTU_SIZE_MASK                0x0000ffff
392 #define MAC_PCS_TEST                    0x00000440
393 #define  PCS_TEST_PATTERN_MASK           0x000fffff
394 #define  PCS_TEST_PATTERN_SHIFT          0
395 #define  PCS_TEST_ENABLE                 0x00100000
396 #define MAC_TX_AUTO_NEG                 0x00000444
397 #define  TX_AUTO_NEG_MASK                0x0000ffff
398 #define  TX_AUTO_NEG_SHIFT               0
399 #define MAC_RX_AUTO_NEG                 0x00000448
400 #define  RX_AUTO_NEG_MASK                0x0000ffff
401 #define  RX_AUTO_NEG_SHIFT               0
402 #define MAC_MI_COM                      0x0000044c
403 #define  MI_COM_CMD_MASK                 0x0c000000
404 #define  MI_COM_CMD_WRITE                0x04000000
405 #define  MI_COM_CMD_READ                 0x08000000
406 #define  MI_COM_READ_FAILED              0x10000000
407 #define  MI_COM_START                    0x20000000
408 #define  MI_COM_BUSY                     0x20000000
409 #define  MI_COM_PHY_ADDR_MASK            0x03e00000
410 #define  MI_COM_PHY_ADDR_SHIFT           21
411 #define  MI_COM_REG_ADDR_MASK            0x001f0000
412 #define  MI_COM_REG_ADDR_SHIFT           16
413 #define  MI_COM_DATA_MASK                0x0000ffff
414 #define MAC_MI_STAT                     0x00000450
415 #define  MAC_MI_STAT_LNKSTAT_ATTN_ENAB   0x00000001
416 #define MAC_MI_MODE                     0x00000454
417 #define  MAC_MI_MODE_CLK_10MHZ           0x00000001
418 #define  MAC_MI_MODE_SHORT_PREAMBLE      0x00000002
419 #define  MAC_MI_MODE_AUTO_POLL           0x00000010
420 #define  MAC_MI_MODE_CORE_CLK_62MHZ      0x00008000
421 #define  MAC_MI_MODE_BASE                0x000c0000 /* XXX magic values XXX */
422 #define MAC_AUTO_POLL_STATUS            0x00000458
423 #define  MAC_AUTO_POLL_ERROR             0x00000001
424 #define MAC_TX_MODE                     0x0000045c
425 #define  TX_MODE_RESET                   0x00000001
426 #define  TX_MODE_ENABLE                  0x00000002
427 #define  TX_MODE_FLOW_CTRL_ENABLE        0x00000010
428 #define  TX_MODE_BIG_BCKOFF_ENABLE       0x00000020
429 #define  TX_MODE_LONG_PAUSE_ENABLE       0x00000040
430 #define MAC_TX_STATUS                   0x00000460
431 #define  TX_STATUS_XOFFED                0x00000001
432 #define  TX_STATUS_SENT_XOFF             0x00000002
433 #define  TX_STATUS_SENT_XON              0x00000004
434 #define  TX_STATUS_LINK_UP               0x00000008
435 #define  TX_STATUS_ODI_UNDERRUN          0x00000010
436 #define  TX_STATUS_ODI_OVERRUN           0x00000020
437 #define MAC_TX_LENGTHS                  0x00000464
438 #define  TX_LENGTHS_SLOT_TIME_MASK       0x000000ff
439 #define  TX_LENGTHS_SLOT_TIME_SHIFT      0
440 #define  TX_LENGTHS_IPG_MASK             0x00000f00
441 #define  TX_LENGTHS_IPG_SHIFT            8
442 #define  TX_LENGTHS_IPG_CRS_MASK         0x00003000
443 #define  TX_LENGTHS_IPG_CRS_SHIFT        12
444 #define MAC_RX_MODE                     0x00000468
445 #define  RX_MODE_RESET                   0x00000001
446 #define  RX_MODE_ENABLE                  0x00000002
447 #define  RX_MODE_FLOW_CTRL_ENABLE        0x00000004
448 #define  RX_MODE_KEEP_MAC_CTRL           0x00000008
449 #define  RX_MODE_KEEP_PAUSE              0x00000010
450 #define  RX_MODE_ACCEPT_OVERSIZED        0x00000020
451 #define  RX_MODE_ACCEPT_RUNTS            0x00000040
452 #define  RX_MODE_LEN_CHECK               0x00000080
453 #define  RX_MODE_PROMISC                 0x00000100
454 #define  RX_MODE_NO_CRC_CHECK            0x00000200
455 #define  RX_MODE_KEEP_VLAN_TAG           0x00000400
456 #define MAC_RX_STATUS                   0x0000046c
457 #define  RX_STATUS_REMOTE_TX_XOFFED      0x00000001
458 #define  RX_STATUS_XOFF_RCVD             0x00000002
459 #define  RX_STATUS_XON_RCVD              0x00000004
460 #define MAC_HASH_REG_0                  0x00000470
461 #define MAC_HASH_REG_1                  0x00000474
462 #define MAC_HASH_REG_2                  0x00000478
463 #define MAC_HASH_REG_3                  0x0000047c
464 #define MAC_RCV_RULE_0                  0x00000480
465 #define MAC_RCV_VALUE_0                 0x00000484
466 #define MAC_RCV_RULE_1                  0x00000488
467 #define MAC_RCV_VALUE_1                 0x0000048c
468 #define MAC_RCV_RULE_2                  0x00000490
469 #define MAC_RCV_VALUE_2                 0x00000494
470 #define MAC_RCV_RULE_3                  0x00000498
471 #define MAC_RCV_VALUE_3                 0x0000049c
472 #define MAC_RCV_RULE_4                  0x000004a0
473 #define MAC_RCV_VALUE_4                 0x000004a4
474 #define MAC_RCV_RULE_5                  0x000004a8
475 #define MAC_RCV_VALUE_5                 0x000004ac
476 #define MAC_RCV_RULE_6                  0x000004b0
477 #define MAC_RCV_VALUE_6                 0x000004b4
478 #define MAC_RCV_RULE_7                  0x000004b8
479 #define MAC_RCV_VALUE_7                 0x000004bc
480 #define MAC_RCV_RULE_8                  0x000004c0
481 #define MAC_RCV_VALUE_8                 0x000004c4
482 #define MAC_RCV_RULE_9                  0x000004c8
483 #define MAC_RCV_VALUE_9                 0x000004cc
484 #define MAC_RCV_RULE_10                 0x000004d0
485 #define MAC_RCV_VALUE_10                0x000004d4
486 #define MAC_RCV_RULE_11                 0x000004d8
487 #define MAC_RCV_VALUE_11                0x000004dc
488 #define MAC_RCV_RULE_12                 0x000004e0
489 #define MAC_RCV_VALUE_12                0x000004e4
490 #define MAC_RCV_RULE_13                 0x000004e8
491 #define MAC_RCV_VALUE_13                0x000004ec
492 #define MAC_RCV_RULE_14                 0x000004f0
493 #define MAC_RCV_VALUE_14                0x000004f4
494 #define MAC_RCV_RULE_15                 0x000004f8
495 #define MAC_RCV_VALUE_15                0x000004fc
496 #define  RCV_RULE_DISABLE_MASK           0x7fffffff
497 #define MAC_RCV_RULE_CFG                0x00000500
498 #define  RCV_RULE_CFG_DEFAULT_CLASS     0x00000008
499 #define MAC_LOW_WMARK_MAX_RX_FRAME      0x00000504
500 /* 0x508 --> 0x520 unused */
501 #define MAC_HASHREGU_0                  0x00000520
502 #define MAC_HASHREGU_1                  0x00000524
503 #define MAC_HASHREGU_2                  0x00000528
504 #define MAC_HASHREGU_3                  0x0000052c
505 #define MAC_EXTADDR_0_HIGH              0x00000530
506 #define MAC_EXTADDR_0_LOW               0x00000534
507 #define MAC_EXTADDR_1_HIGH              0x00000538
508 #define MAC_EXTADDR_1_LOW               0x0000053c
509 #define MAC_EXTADDR_2_HIGH              0x00000540
510 #define MAC_EXTADDR_2_LOW               0x00000544
511 #define MAC_EXTADDR_3_HIGH              0x00000548
512 #define MAC_EXTADDR_3_LOW               0x0000054c
513 #define MAC_EXTADDR_4_HIGH              0x00000550
514 #define MAC_EXTADDR_4_LOW               0x00000554
515 #define MAC_EXTADDR_5_HIGH              0x00000558
516 #define MAC_EXTADDR_5_LOW               0x0000055c
517 #define MAC_EXTADDR_6_HIGH              0x00000560
518 #define MAC_EXTADDR_6_LOW               0x00000564
519 #define MAC_EXTADDR_7_HIGH              0x00000568
520 #define MAC_EXTADDR_7_LOW               0x0000056c
521 #define MAC_EXTADDR_8_HIGH              0x00000570
522 #define MAC_EXTADDR_8_LOW               0x00000574
523 #define MAC_EXTADDR_9_HIGH              0x00000578
524 #define MAC_EXTADDR_9_LOW               0x0000057c
525 #define MAC_EXTADDR_10_HIGH             0x00000580
526 #define MAC_EXTADDR_10_LOW              0x00000584
527 #define MAC_EXTADDR_11_HIGH             0x00000588
528 #define MAC_EXTADDR_11_LOW              0x0000058c
529 #define MAC_SERDES_CFG                  0x00000590
530 #define  MAC_SERDES_CFG_EDGE_SELECT      0x00001000
531 #define MAC_SERDES_STAT                 0x00000594
532 /* 0x598 --> 0x5b0 unused */
533 #define SG_DIG_CTRL                     0x000005b0
534 #define  SG_DIG_USING_HW_AUTONEG         0x80000000
535 #define  SG_DIG_SOFT_RESET               0x40000000
536 #define  SG_DIG_DISABLE_LINKRDY          0x20000000
537 #define  SG_DIG_CRC16_CLEAR_N            0x01000000
538 #define  SG_DIG_EN10B                    0x00800000
539 #define  SG_DIG_CLEAR_STATUS             0x00400000
540 #define  SG_DIG_LOCAL_DUPLEX_STATUS      0x00200000
541 #define  SG_DIG_LOCAL_LINK_STATUS        0x00100000
542 #define  SG_DIG_SPEED_STATUS_MASK        0x000c0000
543 #define  SG_DIG_SPEED_STATUS_SHIFT       18
544 #define  SG_DIG_JUMBO_PACKET_DISABLE     0x00020000
545 #define  SG_DIG_RESTART_AUTONEG          0x00010000
546 #define  SG_DIG_FIBER_MODE               0x00008000
547 #define  SG_DIG_REMOTE_FAULT_MASK        0x00006000
548 #define  SG_DIG_PAUSE_MASK               0x00001800
549 #define  SG_DIG_GBIC_ENABLE              0x00000400
550 #define  SG_DIG_CHECK_END_ENABLE         0x00000200
551 #define  SG_DIG_SGMII_AUTONEG_TIMER      0x00000100
552 #define  SG_DIG_CLOCK_PHASE_SELECT       0x00000080
553 #define  SG_DIG_GMII_INPUT_SELECT        0x00000040
554 #define  SG_DIG_MRADV_CRC16_SELECT       0x00000020
555 #define  SG_DIG_COMMA_DETECT_ENABLE      0x00000010
556 #define  SG_DIG_AUTONEG_TIMER_REDUCE     0x00000008
557 #define  SG_DIG_AUTONEG_LOW_ENABLE       0x00000004
558 #define  SG_DIG_REMOTE_LOOPBACK          0x00000002
559 #define  SG_DIG_LOOPBACK                 0x00000001
560 #define SG_DIG_STATUS                   0x000005b4
561 #define  SG_DIG_CRC16_BUS_MASK           0xffff0000
562 #define  SG_DIG_PARTNER_FAULT_MASK       0x00600000 /* If !MRADV_CRC16_SELECT */
563 #define  SG_DIG_PARTNER_ASYM_PAUSE       0x00100000 /* If !MRADV_CRC16_SELECT */
564 #define  SG_DIG_PARTNER_PAUSE_CAPABLE    0x00080000 /* If !MRADV_CRC16_SELECT */
565 #define  SG_DIG_PARTNER_HALF_DUPLEX      0x00040000 /* If !MRADV_CRC16_SELECT */
566 #define  SG_DIG_PARTNER_FULL_DUPLEX      0x00020000 /* If !MRADV_CRC16_SELECT */
567 #define  SG_DIG_PARTNER_NEXT_PAGE        0x00010000 /* If !MRADV_CRC16_SELECT */
568 #define  SG_DIG_AUTONEG_STATE_MASK       0x00000ff0
569 #define  SG_DIG_COMMA_DETECTOR           0x00000008
570 #define  SG_DIG_MAC_ACK_STATUS           0x00000004
571 #define  SG_DIG_AUTONEG_COMPLETE         0x00000002
572 #define  SG_DIG_AUTONEG_ERROR            0x00000001
573 /* 0x5b8 --> 0x600 unused */
574 #define MAC_TX_MAC_STATE_BASE           0x00000600 /* 16 bytes */
575 #define MAC_RX_MAC_STATE_BASE           0x00000610 /* 20 bytes */
576 /* 0x624 --> 0x800 unused */
577 #define MAC_TX_STATS_OCTETS             0x00000800
578 #define MAC_TX_STATS_RESV1              0x00000804
579 #define MAC_TX_STATS_COLLISIONS         0x00000808
580 #define MAC_TX_STATS_XON_SENT           0x0000080c
581 #define MAC_TX_STATS_XOFF_SENT          0x00000810
582 #define MAC_TX_STATS_RESV2              0x00000814
583 #define MAC_TX_STATS_MAC_ERRORS         0x00000818
584 #define MAC_TX_STATS_SINGLE_COLLISIONS  0x0000081c
585 #define MAC_TX_STATS_MULT_COLLISIONS    0x00000820
586 #define MAC_TX_STATS_DEFERRED           0x00000824
587 #define MAC_TX_STATS_RESV3              0x00000828
588 #define MAC_TX_STATS_EXCESSIVE_COL      0x0000082c
589 #define MAC_TX_STATS_LATE_COL           0x00000830
590 #define MAC_TX_STATS_RESV4_1            0x00000834
591 #define MAC_TX_STATS_RESV4_2            0x00000838
592 #define MAC_TX_STATS_RESV4_3            0x0000083c
593 #define MAC_TX_STATS_RESV4_4            0x00000840
594 #define MAC_TX_STATS_RESV4_5            0x00000844
595 #define MAC_TX_STATS_RESV4_6            0x00000848
596 #define MAC_TX_STATS_RESV4_7            0x0000084c
597 #define MAC_TX_STATS_RESV4_8            0x00000850
598 #define MAC_TX_STATS_RESV4_9            0x00000854
599 #define MAC_TX_STATS_RESV4_10           0x00000858
600 #define MAC_TX_STATS_RESV4_11           0x0000085c
601 #define MAC_TX_STATS_RESV4_12           0x00000860
602 #define MAC_TX_STATS_RESV4_13           0x00000864
603 #define MAC_TX_STATS_RESV4_14           0x00000868
604 #define MAC_TX_STATS_UCAST              0x0000086c
605 #define MAC_TX_STATS_MCAST              0x00000870
606 #define MAC_TX_STATS_BCAST              0x00000874
607 #define MAC_TX_STATS_RESV5_1            0x00000878
608 #define MAC_TX_STATS_RESV5_2            0x0000087c
609 #define MAC_RX_STATS_OCTETS             0x00000880
610 #define MAC_RX_STATS_RESV1              0x00000884
611 #define MAC_RX_STATS_FRAGMENTS          0x00000888
612 #define MAC_RX_STATS_UCAST              0x0000088c
613 #define MAC_RX_STATS_MCAST              0x00000890
614 #define MAC_RX_STATS_BCAST              0x00000894
615 #define MAC_RX_STATS_FCS_ERRORS         0x00000898
616 #define MAC_RX_STATS_ALIGN_ERRORS       0x0000089c
617 #define MAC_RX_STATS_XON_PAUSE_RECVD    0x000008a0
618 #define MAC_RX_STATS_XOFF_PAUSE_RECVD   0x000008a4
619 #define MAC_RX_STATS_MAC_CTRL_RECVD     0x000008a8
620 #define MAC_RX_STATS_XOFF_ENTERED       0x000008ac
621 #define MAC_RX_STATS_FRAME_TOO_LONG     0x000008b0
622 #define MAC_RX_STATS_JABBERS            0x000008b4
623 #define MAC_RX_STATS_UNDERSIZE          0x000008b8
624 /* 0x8bc --> 0xc00 unused */
625
626 /* Send data initiator control registers */
627 #define SNDDATAI_MODE                   0x00000c00
628 #define  SNDDATAI_MODE_RESET             0x00000001
629 #define  SNDDATAI_MODE_ENABLE            0x00000002
630 #define  SNDDATAI_MODE_STAT_OFLOW_ENAB   0x00000004
631 #define SNDDATAI_STATUS                 0x00000c04
632 #define  SNDDATAI_STATUS_STAT_OFLOW      0x00000004
633 #define SNDDATAI_STATSCTRL              0x00000c08
634 #define  SNDDATAI_SCTRL_ENABLE           0x00000001
635 #define  SNDDATAI_SCTRL_FASTUPD          0x00000002
636 #define  SNDDATAI_SCTRL_CLEAR            0x00000004
637 #define  SNDDATAI_SCTRL_FLUSH            0x00000008
638 #define  SNDDATAI_SCTRL_FORCE_ZERO       0x00000010
639 #define SNDDATAI_STATSENAB              0x00000c0c
640 #define SNDDATAI_STATSINCMASK           0x00000c10
641 /* 0xc14 --> 0xc80 unused */
642 #define SNDDATAI_COS_CNT_0              0x00000c80
643 #define SNDDATAI_COS_CNT_1              0x00000c84
644 #define SNDDATAI_COS_CNT_2              0x00000c88
645 #define SNDDATAI_COS_CNT_3              0x00000c8c
646 #define SNDDATAI_COS_CNT_4              0x00000c90
647 #define SNDDATAI_COS_CNT_5              0x00000c94
648 #define SNDDATAI_COS_CNT_6              0x00000c98
649 #define SNDDATAI_COS_CNT_7              0x00000c9c
650 #define SNDDATAI_COS_CNT_8              0x00000ca0
651 #define SNDDATAI_COS_CNT_9              0x00000ca4
652 #define SNDDATAI_COS_CNT_10             0x00000ca8
653 #define SNDDATAI_COS_CNT_11             0x00000cac
654 #define SNDDATAI_COS_CNT_12             0x00000cb0
655 #define SNDDATAI_COS_CNT_13             0x00000cb4
656 #define SNDDATAI_COS_CNT_14             0x00000cb8
657 #define SNDDATAI_COS_CNT_15             0x00000cbc
658 #define SNDDATAI_DMA_RDQ_FULL_CNT       0x00000cc0
659 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT  0x00000cc4
660 #define SNDDATAI_SDCQ_FULL_CNT          0x00000cc8
661 #define SNDDATAI_NICRNG_SSND_PIDX_CNT   0x00000ccc
662 #define SNDDATAI_STATS_UPDATED_CNT      0x00000cd0
663 #define SNDDATAI_INTERRUPTS_CNT         0x00000cd4
664 #define SNDDATAI_AVOID_INTERRUPTS_CNT   0x00000cd8
665 #define SNDDATAI_SND_THRESH_HIT_CNT     0x00000cdc
666 /* 0xce0 --> 0x1000 unused */
667
668 /* Send data completion control registers */
669 #define SNDDATAC_MODE                   0x00001000
670 #define  SNDDATAC_MODE_RESET             0x00000001
671 #define  SNDDATAC_MODE_ENABLE            0x00000002
672 /* 0x1004 --> 0x1400 unused */
673
674 /* Send BD ring selector */
675 #define SNDBDS_MODE                     0x00001400
676 #define  SNDBDS_MODE_RESET               0x00000001
677 #define  SNDBDS_MODE_ENABLE              0x00000002
678 #define  SNDBDS_MODE_ATTN_ENABLE         0x00000004
679 #define SNDBDS_STATUS                   0x00001404
680 #define  SNDBDS_STATUS_ERROR_ATTN        0x00000004
681 #define SNDBDS_HWDIAG                   0x00001408
682 /* 0x140c --> 0x1440 */
683 #define SNDBDS_SEL_CON_IDX_0            0x00001440
684 #define SNDBDS_SEL_CON_IDX_1            0x00001444
685 #define SNDBDS_SEL_CON_IDX_2            0x00001448
686 #define SNDBDS_SEL_CON_IDX_3            0x0000144c
687 #define SNDBDS_SEL_CON_IDX_4            0x00001450
688 #define SNDBDS_SEL_CON_IDX_5            0x00001454
689 #define SNDBDS_SEL_CON_IDX_6            0x00001458
690 #define SNDBDS_SEL_CON_IDX_7            0x0000145c
691 #define SNDBDS_SEL_CON_IDX_8            0x00001460
692 #define SNDBDS_SEL_CON_IDX_9            0x00001464
693 #define SNDBDS_SEL_CON_IDX_10           0x00001468
694 #define SNDBDS_SEL_CON_IDX_11           0x0000146c
695 #define SNDBDS_SEL_CON_IDX_12           0x00001470
696 #define SNDBDS_SEL_CON_IDX_13           0x00001474
697 #define SNDBDS_SEL_CON_IDX_14           0x00001478
698 #define SNDBDS_SEL_CON_IDX_15           0x0000147c
699 /* 0x1480 --> 0x1800 unused */
700
701 /* Send BD initiator control registers */
702 #define SNDBDI_MODE                     0x00001800
703 #define  SNDBDI_MODE_RESET               0x00000001
704 #define  SNDBDI_MODE_ENABLE              0x00000002
705 #define  SNDBDI_MODE_ATTN_ENABLE         0x00000004
706 #define SNDBDI_STATUS                   0x00001804
707 #define  SNDBDI_STATUS_ERROR_ATTN        0x00000004
708 #define SNDBDI_IN_PROD_IDX_0            0x00001808
709 #define SNDBDI_IN_PROD_IDX_1            0x0000180c
710 #define SNDBDI_IN_PROD_IDX_2            0x00001810
711 #define SNDBDI_IN_PROD_IDX_3            0x00001814
712 #define SNDBDI_IN_PROD_IDX_4            0x00001818
713 #define SNDBDI_IN_PROD_IDX_5            0x0000181c
714 #define SNDBDI_IN_PROD_IDX_6            0x00001820
715 #define SNDBDI_IN_PROD_IDX_7            0x00001824
716 #define SNDBDI_IN_PROD_IDX_8            0x00001828
717 #define SNDBDI_IN_PROD_IDX_9            0x0000182c
718 #define SNDBDI_IN_PROD_IDX_10           0x00001830
719 #define SNDBDI_IN_PROD_IDX_11           0x00001834
720 #define SNDBDI_IN_PROD_IDX_12           0x00001838
721 #define SNDBDI_IN_PROD_IDX_13           0x0000183c
722 #define SNDBDI_IN_PROD_IDX_14           0x00001840
723 #define SNDBDI_IN_PROD_IDX_15           0x00001844
724 /* 0x1848 --> 0x1c00 unused */
725
726 /* Send BD completion control registers */
727 #define SNDBDC_MODE                     0x00001c00
728 #define SNDBDC_MODE_RESET                0x00000001
729 #define SNDBDC_MODE_ENABLE               0x00000002
730 #define SNDBDC_MODE_ATTN_ENABLE          0x00000004
731 /* 0x1c04 --> 0x2000 unused */
732
733 /* Receive list placement control registers */
734 #define RCVLPC_MODE                     0x00002000
735 #define  RCVLPC_MODE_RESET               0x00000001
736 #define  RCVLPC_MODE_ENABLE              0x00000002
737 #define  RCVLPC_MODE_CLASS0_ATTN_ENAB    0x00000004
738 #define  RCVLPC_MODE_MAPOOR_AATTN_ENAB   0x00000008
739 #define  RCVLPC_MODE_STAT_OFLOW_ENAB     0x00000010
740 #define RCVLPC_STATUS                   0x00002004
741 #define  RCVLPC_STATUS_CLASS0            0x00000004
742 #define  RCVLPC_STATUS_MAPOOR            0x00000008
743 #define  RCVLPC_STATUS_STAT_OFLOW        0x00000010
744 #define RCVLPC_LOCK                     0x00002008
745 #define  RCVLPC_LOCK_REQ_MASK            0x0000ffff
746 #define  RCVLPC_LOCK_REQ_SHIFT           0
747 #define  RCVLPC_LOCK_GRANT_MASK          0xffff0000
748 #define  RCVLPC_LOCK_GRANT_SHIFT         16
749 #define RCVLPC_NON_EMPTY_BITS           0x0000200c
750 #define  RCVLPC_NON_EMPTY_BITS_MASK      0x0000ffff
751 #define RCVLPC_CONFIG                   0x00002010
752 #define RCVLPC_STATSCTRL                0x00002014
753 #define  RCVLPC_STATSCTRL_ENABLE         0x00000001
754 #define  RCVLPC_STATSCTRL_FASTUPD        0x00000002
755 #define RCVLPC_STATS_ENABLE             0x00002018
756 #define  RCVLPC_STATSENAB_LNGBRST_RFIX   0x00400000
757 #define RCVLPC_STATS_INCMASK            0x0000201c
758 /* 0x2020 --> 0x2100 unused */
759 #define RCVLPC_SELLST_BASE              0x00002100 /* 16 16-byte entries */
760 #define  SELLST_TAIL                    0x00000004
761 #define  SELLST_CONT                    0x00000008
762 #define  SELLST_UNUSED                  0x0000000c
763 #define RCVLPC_COS_CNTL_BASE            0x00002200 /* 16 4-byte entries */
764 #define RCVLPC_DROP_FILTER_CNT          0x00002240
765 #define RCVLPC_DMA_WQ_FULL_CNT          0x00002244
766 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT   0x00002248
767 #define RCVLPC_NO_RCV_BD_CNT            0x0000224c
768 #define RCVLPC_IN_DISCARDS_CNT          0x00002250
769 #define RCVLPC_IN_ERRORS_CNT            0x00002254
770 #define RCVLPC_RCV_THRESH_HIT_CNT       0x00002258
771 /* 0x225c --> 0x2400 unused */
772
773 /* Receive Data and Receive BD Initiator Control */
774 #define RCVDBDI_MODE                    0x00002400
775 #define  RCVDBDI_MODE_RESET              0x00000001
776 #define  RCVDBDI_MODE_ENABLE             0x00000002
777 #define  RCVDBDI_MODE_JUMBOBD_NEEDED     0x00000004
778 #define  RCVDBDI_MODE_FRM_TOO_BIG        0x00000008
779 #define  RCVDBDI_MODE_INV_RING_SZ        0x00000010
780 #define RCVDBDI_STATUS                  0x00002404
781 #define  RCVDBDI_STATUS_JUMBOBD_NEEDED   0x00000004
782 #define  RCVDBDI_STATUS_FRM_TOO_BIG      0x00000008
783 #define  RCVDBDI_STATUS_INV_RING_SZ      0x00000010
784 #define RCVDBDI_SPLIT_FRAME_MINSZ       0x00002408
785 /* 0x240c --> 0x2440 unused */
786 #define RCVDBDI_JUMBO_BD                0x00002440 /* TG3_BDINFO_... */
787 #define RCVDBDI_STD_BD                  0x00002450 /* TG3_BDINFO_... */
788 #define RCVDBDI_MINI_BD                 0x00002460 /* TG3_BDINFO_... */
789 #define RCVDBDI_JUMBO_CON_IDX           0x00002470
790 #define RCVDBDI_STD_CON_IDX             0x00002474
791 #define RCVDBDI_MINI_CON_IDX            0x00002478
792 /* 0x247c --> 0x2480 unused */
793 #define RCVDBDI_BD_PROD_IDX_0           0x00002480
794 #define RCVDBDI_BD_PROD_IDX_1           0x00002484
795 #define RCVDBDI_BD_PROD_IDX_2           0x00002488
796 #define RCVDBDI_BD_PROD_IDX_3           0x0000248c
797 #define RCVDBDI_BD_PROD_IDX_4           0x00002490
798 #define RCVDBDI_BD_PROD_IDX_5           0x00002494
799 #define RCVDBDI_BD_PROD_IDX_6           0x00002498
800 #define RCVDBDI_BD_PROD_IDX_7           0x0000249c
801 #define RCVDBDI_BD_PROD_IDX_8           0x000024a0
802 #define RCVDBDI_BD_PROD_IDX_9           0x000024a4
803 #define RCVDBDI_BD_PROD_IDX_10          0x000024a8
804 #define RCVDBDI_BD_PROD_IDX_11          0x000024ac
805 #define RCVDBDI_BD_PROD_IDX_12          0x000024b0
806 #define RCVDBDI_BD_PROD_IDX_13          0x000024b4
807 #define RCVDBDI_BD_PROD_IDX_14          0x000024b8
808 #define RCVDBDI_BD_PROD_IDX_15          0x000024bc
809 #define RCVDBDI_HWDIAG                  0x000024c0
810 /* 0x24c4 --> 0x2800 unused */
811
812 /* Receive Data Completion Control */
813 #define RCVDCC_MODE                     0x00002800
814 #define  RCVDCC_MODE_RESET               0x00000001
815 #define  RCVDCC_MODE_ENABLE              0x00000002
816 #define  RCVDCC_MODE_ATTN_ENABLE         0x00000004
817 /* 0x2804 --> 0x2c00 unused */
818
819 /* Receive BD Initiator Control Registers */
820 #define RCVBDI_MODE                     0x00002c00
821 #define  RCVBDI_MODE_RESET               0x00000001
822 #define  RCVBDI_MODE_ENABLE              0x00000002
823 #define  RCVBDI_MODE_RCB_ATTN_ENAB       0x00000004
824 #define RCVBDI_STATUS                   0x00002c04
825 #define  RCVBDI_STATUS_RCB_ATTN          0x00000004
826 #define RCVBDI_JUMBO_PROD_IDX           0x00002c08
827 #define RCVBDI_STD_PROD_IDX             0x00002c0c
828 #define RCVBDI_MINI_PROD_IDX            0x00002c10
829 #define RCVBDI_MINI_THRESH              0x00002c14
830 #define RCVBDI_STD_THRESH               0x00002c18
831 #define RCVBDI_JUMBO_THRESH             0x00002c1c
832 /* 0x2c20 --> 0x3000 unused */
833
834 /* Receive BD Completion Control Registers */
835 #define RCVCC_MODE                      0x00003000
836 #define  RCVCC_MODE_RESET                0x00000001
837 #define  RCVCC_MODE_ENABLE               0x00000002
838 #define  RCVCC_MODE_ATTN_ENABLE          0x00000004
839 #define RCVCC_STATUS                    0x00003004
840 #define  RCVCC_STATUS_ERROR_ATTN         0x00000004
841 #define RCVCC_JUMP_PROD_IDX             0x00003008
842 #define RCVCC_STD_PROD_IDX              0x0000300c
843 #define RCVCC_MINI_PROD_IDX             0x00003010
844 /* 0x3014 --> 0x3400 unused */
845
846 /* Receive list selector control registers */
847 #define RCVLSC_MODE                     0x00003400
848 #define  RCVLSC_MODE_RESET               0x00000001
849 #define  RCVLSC_MODE_ENABLE              0x00000002
850 #define  RCVLSC_MODE_ATTN_ENABLE         0x00000004
851 #define RCVLSC_STATUS                   0x00003404
852 #define  RCVLSC_STATUS_ERROR_ATTN        0x00000004
853 /* 0x3408 --> 0x3800 unused */
854
855 /* Mbuf cluster free registers */
856 #define MBFREE_MODE                     0x00003800
857 #define  MBFREE_MODE_RESET               0x00000001
858 #define  MBFREE_MODE_ENABLE              0x00000002
859 #define MBFREE_STATUS                   0x00003804
860 /* 0x3808 --> 0x3c00 unused */
861
862 /* Host coalescing control registers */
863 #define HOSTCC_MODE                     0x00003c00
864 #define  HOSTCC_MODE_RESET               0x00000001
865 #define  HOSTCC_MODE_ENABLE              0x00000002
866 #define  HOSTCC_MODE_ATTN                0x00000004
867 #define  HOSTCC_MODE_NOW                 0x00000008
868 #define  HOSTCC_MODE_FULL_STATUS         0x00000000
869 #define  HOSTCC_MODE_64BYTE              0x00000080
870 #define  HOSTCC_MODE_32BYTE              0x00000100
871 #define  HOSTCC_MODE_CLRTICK_RXBD        0x00000200
872 #define  HOSTCC_MODE_CLRTICK_TXBD        0x00000400
873 #define  HOSTCC_MODE_NOINT_ON_NOW        0x00000800
874 #define  HOSTCC_MODE_NOINT_ON_FORCE      0x00001000
875 #define HOSTCC_STATUS                   0x00003c04
876 #define  HOSTCC_STATUS_ERROR_ATTN        0x00000004
877 #define HOSTCC_RXCOL_TICKS              0x00003c08
878 #define  LOW_RXCOL_TICKS                 0x00000032
879 #define  LOW_RXCOL_TICKS_CLRTCKS         0x00000014
880 #define  DEFAULT_RXCOL_TICKS             0x00000048
881 #define  HIGH_RXCOL_TICKS                0x00000096
882 #define  MAX_RXCOL_TICKS                 0x000003ff
883 #define HOSTCC_TXCOL_TICKS              0x00003c0c
884 #define  LOW_TXCOL_TICKS                 0x00000096
885 #define  LOW_TXCOL_TICKS_CLRTCKS         0x00000048
886 #define  DEFAULT_TXCOL_TICKS             0x0000012c
887 #define  HIGH_TXCOL_TICKS                0x00000145
888 #define  MAX_TXCOL_TICKS                 0x000003ff
889 #define HOSTCC_RXMAX_FRAMES             0x00003c10
890 #define  LOW_RXMAX_FRAMES                0x00000005
891 #define  DEFAULT_RXMAX_FRAMES            0x00000008
892 #define  HIGH_RXMAX_FRAMES               0x00000012
893 #define  MAX_RXMAX_FRAMES                0x000000ff
894 #define HOSTCC_TXMAX_FRAMES             0x00003c14
895 #define  LOW_TXMAX_FRAMES                0x00000035
896 #define  DEFAULT_TXMAX_FRAMES            0x0000004b
897 #define  HIGH_TXMAX_FRAMES               0x00000052
898 #define  MAX_TXMAX_FRAMES                0x000000ff
899 #define HOSTCC_RXCOAL_TICK_INT          0x00003c18
900 #define  DEFAULT_RXCOAL_TICK_INT         0x00000019
901 #define  DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
902 #define  MAX_RXCOAL_TICK_INT             0x000003ff
903 #define HOSTCC_TXCOAL_TICK_INT          0x00003c1c
904 #define  DEFAULT_TXCOAL_TICK_INT         0x00000019
905 #define  DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
906 #define  MAX_TXCOAL_TICK_INT             0x000003ff
907 #define HOSTCC_RXCOAL_MAXF_INT          0x00003c20
908 #define  DEFAULT_RXCOAL_MAXF_INT         0x00000005
909 #define  MAX_RXCOAL_MAXF_INT             0x000000ff
910 #define HOSTCC_TXCOAL_MAXF_INT          0x00003c24
911 #define  DEFAULT_TXCOAL_MAXF_INT         0x00000005
912 #define  MAX_TXCOAL_MAXF_INT             0x000000ff
913 #define HOSTCC_STAT_COAL_TICKS          0x00003c28
914 #define  DEFAULT_STAT_COAL_TICKS         0x000f4240
915 #define  MAX_STAT_COAL_TICKS             0xd693d400
916 #define  MIN_STAT_COAL_TICKS             0x00000064
917 /* 0x3c2c --> 0x3c30 unused */
918 #define HOSTCC_STATS_BLK_HOST_ADDR      0x00003c30 /* 64-bit */
919 #define HOSTCC_STATUS_BLK_HOST_ADDR     0x00003c38 /* 64-bit */
920 #define HOSTCC_STATS_BLK_NIC_ADDR       0x00003c40
921 #define HOSTCC_STATUS_BLK_NIC_ADDR      0x00003c44
922 #define HOSTCC_FLOW_ATTN                0x00003c48
923 /* 0x3c4c --> 0x3c50 unused */
924 #define HOSTCC_JUMBO_CON_IDX            0x00003c50
925 #define HOSTCC_STD_CON_IDX              0x00003c54
926 #define HOSTCC_MINI_CON_IDX             0x00003c58
927 /* 0x3c5c --> 0x3c80 unused */
928 #define HOSTCC_RET_PROD_IDX_0           0x00003c80
929 #define HOSTCC_RET_PROD_IDX_1           0x00003c84
930 #define HOSTCC_RET_PROD_IDX_2           0x00003c88
931 #define HOSTCC_RET_PROD_IDX_3           0x00003c8c
932 #define HOSTCC_RET_PROD_IDX_4           0x00003c90
933 #define HOSTCC_RET_PROD_IDX_5           0x00003c94
934 #define HOSTCC_RET_PROD_IDX_6           0x00003c98
935 #define HOSTCC_RET_PROD_IDX_7           0x00003c9c
936 #define HOSTCC_RET_PROD_IDX_8           0x00003ca0
937 #define HOSTCC_RET_PROD_IDX_9           0x00003ca4
938 #define HOSTCC_RET_PROD_IDX_10          0x00003ca8
939 #define HOSTCC_RET_PROD_IDX_11          0x00003cac
940 #define HOSTCC_RET_PROD_IDX_12          0x00003cb0
941 #define HOSTCC_RET_PROD_IDX_13          0x00003cb4
942 #define HOSTCC_RET_PROD_IDX_14          0x00003cb8
943 #define HOSTCC_RET_PROD_IDX_15          0x00003cbc
944 #define HOSTCC_SND_CON_IDX_0            0x00003cc0
945 #define HOSTCC_SND_CON_IDX_1            0x00003cc4
946 #define HOSTCC_SND_CON_IDX_2            0x00003cc8
947 #define HOSTCC_SND_CON_IDX_3            0x00003ccc
948 #define HOSTCC_SND_CON_IDX_4            0x00003cd0
949 #define HOSTCC_SND_CON_IDX_5            0x00003cd4
950 #define HOSTCC_SND_CON_IDX_6            0x00003cd8
951 #define HOSTCC_SND_CON_IDX_7            0x00003cdc
952 #define HOSTCC_SND_CON_IDX_8            0x00003ce0
953 #define HOSTCC_SND_CON_IDX_9            0x00003ce4
954 #define HOSTCC_SND_CON_IDX_10           0x00003ce8
955 #define HOSTCC_SND_CON_IDX_11           0x00003cec
956 #define HOSTCC_SND_CON_IDX_12           0x00003cf0
957 #define HOSTCC_SND_CON_IDX_13           0x00003cf4
958 #define HOSTCC_SND_CON_IDX_14           0x00003cf8
959 #define HOSTCC_SND_CON_IDX_15           0x00003cfc
960 /* 0x3d00 --> 0x4000 unused */
961
962 /* Memory arbiter control registers */
963 #define MEMARB_MODE                     0x00004000
964 #define  MEMARB_MODE_RESET               0x00000001
965 #define  MEMARB_MODE_ENABLE              0x00000002
966 #define MEMARB_STATUS                   0x00004004
967 #define MEMARB_TRAP_ADDR_LOW            0x00004008
968 #define MEMARB_TRAP_ADDR_HIGH           0x0000400c
969 /* 0x4010 --> 0x4400 unused */
970
971 /* Buffer manager control registers */
972 #define BUFMGR_MODE                     0x00004400
973 #define  BUFMGR_MODE_RESET               0x00000001
974 #define  BUFMGR_MODE_ENABLE              0x00000002
975 #define  BUFMGR_MODE_ATTN_ENABLE         0x00000004
976 #define  BUFMGR_MODE_BM_TEST             0x00000008
977 #define  BUFMGR_MODE_MBLOW_ATTN_ENAB     0x00000010
978 #define BUFMGR_STATUS                   0x00004404
979 #define  BUFMGR_STATUS_ERROR             0x00000004
980 #define  BUFMGR_STATUS_MBLOW             0x00000010
981 #define BUFMGR_MB_POOL_ADDR             0x00004408
982 #define BUFMGR_MB_POOL_SIZE             0x0000440c
983 #define BUFMGR_MB_RDMA_LOW_WATER        0x00004410
984 #define  DEFAULT_MB_RDMA_LOW_WATER       0x00000050
985 #define  DEFAULT_MB_RDMA_LOW_WATER_5705  0x00000000
986 #define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
987 #define BUFMGR_MB_MACRX_LOW_WATER       0x00004414
988 #define  DEFAULT_MB_MACRX_LOW_WATER       0x00000020
989 #define  DEFAULT_MB_MACRX_LOW_WATER_5705  0x00000010
990 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
991 #define BUFMGR_MB_HIGH_WATER            0x00004418
992 #define  DEFAULT_MB_HIGH_WATER           0x00000060
993 #define  DEFAULT_MB_HIGH_WATER_5705      0x00000060
994 #define  DEFAULT_MB_HIGH_WATER_JUMBO     0x0000017c
995 #define BUFMGR_RX_MB_ALLOC_REQ          0x0000441c
996 #define  BUFMGR_MB_ALLOC_BIT             0x10000000
997 #define BUFMGR_RX_MB_ALLOC_RESP         0x00004420
998 #define BUFMGR_TX_MB_ALLOC_REQ          0x00004424
999 #define BUFMGR_TX_MB_ALLOC_RESP         0x00004428
1000 #define BUFMGR_DMA_DESC_POOL_ADDR       0x0000442c
1001 #define BUFMGR_DMA_DESC_POOL_SIZE       0x00004430
1002 #define BUFMGR_DMA_LOW_WATER            0x00004434
1003 #define  DEFAULT_DMA_LOW_WATER           0x00000005
1004 #define BUFMGR_DMA_HIGH_WATER           0x00004438
1005 #define  DEFAULT_DMA_HIGH_WATER          0x0000000a
1006 #define BUFMGR_RX_DMA_ALLOC_REQ         0x0000443c
1007 #define BUFMGR_RX_DMA_ALLOC_RESP        0x00004440
1008 #define BUFMGR_TX_DMA_ALLOC_REQ         0x00004444
1009 #define BUFMGR_TX_DMA_ALLOC_RESP        0x00004448
1010 #define BUFMGR_HWDIAG_0                 0x0000444c
1011 #define BUFMGR_HWDIAG_1                 0x00004450
1012 #define BUFMGR_HWDIAG_2                 0x00004454
1013 /* 0x4458 --> 0x4800 unused */
1014
1015 /* Read DMA control registers */
1016 #define RDMAC_MODE                      0x00004800
1017 #define  RDMAC_MODE_RESET                0x00000001
1018 #define  RDMAC_MODE_ENABLE               0x00000002
1019 #define  RDMAC_MODE_TGTABORT_ENAB        0x00000004
1020 #define  RDMAC_MODE_MSTABORT_ENAB        0x00000008
1021 #define  RDMAC_MODE_PARITYERR_ENAB       0x00000010
1022 #define  RDMAC_MODE_ADDROFLOW_ENAB       0x00000020
1023 #define  RDMAC_MODE_FIFOOFLOW_ENAB       0x00000040
1024 #define  RDMAC_MODE_FIFOURUN_ENAB        0x00000080
1025 #define  RDMAC_MODE_FIFOOREAD_ENAB       0x00000100
1026 #define  RDMAC_MODE_LNGREAD_ENAB         0x00000200
1027 #define  RDMAC_MODE_SPLIT_ENABLE         0x00000800
1028 #define  RDMAC_MODE_SPLIT_RESET          0x00001000
1029 #define  RDMAC_MODE_FIFO_SIZE_128        0x00020000
1030 #define  RDMAC_MODE_FIFO_LONG_BURST      0x00030000
1031 #define RDMAC_STATUS                    0x00004804
1032 #define  RDMAC_STATUS_TGTABORT           0x00000004
1033 #define  RDMAC_STATUS_MSTABORT           0x00000008
1034 #define  RDMAC_STATUS_PARITYERR          0x00000010
1035 #define  RDMAC_STATUS_ADDROFLOW          0x00000020
1036 #define  RDMAC_STATUS_FIFOOFLOW          0x00000040
1037 #define  RDMAC_STATUS_FIFOURUN           0x00000080
1038 #define  RDMAC_STATUS_FIFOOREAD          0x00000100
1039 #define  RDMAC_STATUS_LNGREAD            0x00000200
1040 /* 0x4808 --> 0x4c00 unused */
1041
1042 /* Write DMA control registers */
1043 #define WDMAC_MODE                      0x00004c00
1044 #define  WDMAC_MODE_RESET                0x00000001
1045 #define  WDMAC_MODE_ENABLE               0x00000002
1046 #define  WDMAC_MODE_TGTABORT_ENAB        0x00000004
1047 #define  WDMAC_MODE_MSTABORT_ENAB        0x00000008
1048 #define  WDMAC_MODE_PARITYERR_ENAB       0x00000010
1049 #define  WDMAC_MODE_ADDROFLOW_ENAB       0x00000020
1050 #define  WDMAC_MODE_FIFOOFLOW_ENAB       0x00000040
1051 #define  WDMAC_MODE_FIFOURUN_ENAB        0x00000080
1052 #define  WDMAC_MODE_FIFOOREAD_ENAB       0x00000100
1053 #define  WDMAC_MODE_LNGREAD_ENAB         0x00000200
1054 #define  WDMAC_MODE_RX_ACCEL             0x00000400
1055 #define WDMAC_STATUS                    0x00004c04
1056 #define  WDMAC_STATUS_TGTABORT           0x00000004
1057 #define  WDMAC_STATUS_MSTABORT           0x00000008
1058 #define  WDMAC_STATUS_PARITYERR          0x00000010
1059 #define  WDMAC_STATUS_ADDROFLOW          0x00000020
1060 #define  WDMAC_STATUS_FIFOOFLOW          0x00000040
1061 #define  WDMAC_STATUS_FIFOURUN           0x00000080
1062 #define  WDMAC_STATUS_FIFOOREAD          0x00000100
1063 #define  WDMAC_STATUS_LNGREAD            0x00000200
1064 /* 0x4c08 --> 0x5000 unused */
1065
1066 /* Per-cpu register offsets (arm9) */
1067 #define CPU_MODE                        0x00000000
1068 #define  CPU_MODE_RESET                  0x00000001
1069 #define  CPU_MODE_HALT                   0x00000400
1070 #define CPU_STATE                       0x00000004
1071 #define CPU_EVTMASK                     0x00000008
1072 /* 0xc --> 0x1c reserved */
1073 #define CPU_PC                          0x0000001c
1074 #define CPU_INSN                        0x00000020
1075 #define CPU_SPAD_UFLOW                  0x00000024
1076 #define CPU_WDOG_CLEAR                  0x00000028
1077 #define CPU_WDOG_VECTOR                 0x0000002c
1078 #define CPU_WDOG_PC                     0x00000030
1079 #define CPU_HW_BP                       0x00000034
1080 /* 0x38 --> 0x44 unused */
1081 #define CPU_WDOG_SAVED_STATE            0x00000044
1082 #define CPU_LAST_BRANCH_ADDR            0x00000048
1083 #define CPU_SPAD_UFLOW_SET              0x0000004c
1084 /* 0x50 --> 0x200 unused */
1085 #define CPU_R0                          0x00000200
1086 #define CPU_R1                          0x00000204
1087 #define CPU_R2                          0x00000208
1088 #define CPU_R3                          0x0000020c
1089 #define CPU_R4                          0x00000210
1090 #define CPU_R5                          0x00000214
1091 #define CPU_R6                          0x00000218
1092 #define CPU_R7                          0x0000021c
1093 #define CPU_R8                          0x00000220
1094 #define CPU_R9                          0x00000224
1095 #define CPU_R10                         0x00000228
1096 #define CPU_R11                         0x0000022c
1097 #define CPU_R12                         0x00000230
1098 #define CPU_R13                         0x00000234
1099 #define CPU_R14                         0x00000238
1100 #define CPU_R15                         0x0000023c
1101 #define CPU_R16                         0x00000240
1102 #define CPU_R17                         0x00000244
1103 #define CPU_R18                         0x00000248
1104 #define CPU_R19                         0x0000024c
1105 #define CPU_R20                         0x00000250
1106 #define CPU_R21                         0x00000254
1107 #define CPU_R22                         0x00000258
1108 #define CPU_R23                         0x0000025c
1109 #define CPU_R24                         0x00000260
1110 #define CPU_R25                         0x00000264
1111 #define CPU_R26                         0x00000268
1112 #define CPU_R27                         0x0000026c
1113 #define CPU_R28                         0x00000270
1114 #define CPU_R29                         0x00000274
1115 #define CPU_R30                         0x00000278
1116 #define CPU_R31                         0x0000027c
1117 /* 0x280 --> 0x400 unused */
1118
1119 #define RX_CPU_BASE                     0x00005000
1120 #define TX_CPU_BASE                     0x00005400
1121
1122 /* Mailboxes */
1123 #define GRCMBOX_INTERRUPT_0             0x00005800 /* 64-bit */
1124 #define GRCMBOX_INTERRUPT_1             0x00005808 /* 64-bit */
1125 #define GRCMBOX_INTERRUPT_2             0x00005810 /* 64-bit */
1126 #define GRCMBOX_INTERRUPT_3             0x00005818 /* 64-bit */
1127 #define GRCMBOX_GENERAL_0               0x00005820 /* 64-bit */
1128 #define GRCMBOX_GENERAL_1               0x00005828 /* 64-bit */
1129 #define GRCMBOX_GENERAL_2               0x00005830 /* 64-bit */
1130 #define GRCMBOX_GENERAL_3               0x00005838 /* 64-bit */
1131 #define GRCMBOX_GENERAL_4               0x00005840 /* 64-bit */
1132 #define GRCMBOX_GENERAL_5               0x00005848 /* 64-bit */
1133 #define GRCMBOX_GENERAL_6               0x00005850 /* 64-bit */
1134 #define GRCMBOX_GENERAL_7               0x00005858 /* 64-bit */
1135 #define GRCMBOX_RELOAD_STAT             0x00005860 /* 64-bit */
1136 #define GRCMBOX_RCVSTD_PROD_IDX         0x00005868 /* 64-bit */
1137 #define GRCMBOX_RCVJUMBO_PROD_IDX       0x00005870 /* 64-bit */
1138 #define GRCMBOX_RCVMINI_PROD_IDX        0x00005878 /* 64-bit */
1139 #define GRCMBOX_RCVRET_CON_IDX_0        0x00005880 /* 64-bit */
1140 #define GRCMBOX_RCVRET_CON_IDX_1        0x00005888 /* 64-bit */
1141 #define GRCMBOX_RCVRET_CON_IDX_2        0x00005890 /* 64-bit */
1142 #define GRCMBOX_RCVRET_CON_IDX_3        0x00005898 /* 64-bit */
1143 #define GRCMBOX_RCVRET_CON_IDX_4        0x000058a0 /* 64-bit */
1144 #define GRCMBOX_RCVRET_CON_IDX_5        0x000058a8 /* 64-bit */
1145 #define GRCMBOX_RCVRET_CON_IDX_6        0x000058b0 /* 64-bit */
1146 #define GRCMBOX_RCVRET_CON_IDX_7        0x000058b8 /* 64-bit */
1147 #define GRCMBOX_RCVRET_CON_IDX_8        0x000058c0 /* 64-bit */
1148 #define GRCMBOX_RCVRET_CON_IDX_9        0x000058c8 /* 64-bit */
1149 #define GRCMBOX_RCVRET_CON_IDX_10       0x000058d0 /* 64-bit */
1150 #define GRCMBOX_RCVRET_CON_IDX_11       0x000058d8 /* 64-bit */
1151 #define GRCMBOX_RCVRET_CON_IDX_12       0x000058e0 /* 64-bit */
1152 #define GRCMBOX_RCVRET_CON_IDX_13       0x000058e8 /* 64-bit */
1153 #define GRCMBOX_RCVRET_CON_IDX_14       0x000058f0 /* 64-bit */
1154 #define GRCMBOX_RCVRET_CON_IDX_15       0x000058f8 /* 64-bit */
1155 #define GRCMBOX_SNDHOST_PROD_IDX_0      0x00005900 /* 64-bit */
1156 #define GRCMBOX_SNDHOST_PROD_IDX_1      0x00005908 /* 64-bit */
1157 #define GRCMBOX_SNDHOST_PROD_IDX_2      0x00005910 /* 64-bit */
1158 #define GRCMBOX_SNDHOST_PROD_IDX_3      0x00005918 /* 64-bit */
1159 #define GRCMBOX_SNDHOST_PROD_IDX_4      0x00005920 /* 64-bit */
1160 #define GRCMBOX_SNDHOST_PROD_IDX_5      0x00005928 /* 64-bit */
1161 #define GRCMBOX_SNDHOST_PROD_IDX_6      0x00005930 /* 64-bit */
1162 #define GRCMBOX_SNDHOST_PROD_IDX_7      0x00005938 /* 64-bit */
1163 #define GRCMBOX_SNDHOST_PROD_IDX_8      0x00005940 /* 64-bit */
1164 #define GRCMBOX_SNDHOST_PROD_IDX_9      0x00005948 /* 64-bit */
1165 #define GRCMBOX_SNDHOST_PROD_IDX_10     0x00005950 /* 64-bit */
1166 #define GRCMBOX_SNDHOST_PROD_IDX_11     0x00005958 /* 64-bit */
1167 #define GRCMBOX_SNDHOST_PROD_IDX_12     0x00005960 /* 64-bit */
1168 #define GRCMBOX_SNDHOST_PROD_IDX_13     0x00005968 /* 64-bit */
1169 #define GRCMBOX_SNDHOST_PROD_IDX_14     0x00005970 /* 64-bit */
1170 #define GRCMBOX_SNDHOST_PROD_IDX_15     0x00005978 /* 64-bit */
1171 #define GRCMBOX_SNDNIC_PROD_IDX_0       0x00005980 /* 64-bit */
1172 #define GRCMBOX_SNDNIC_PROD_IDX_1       0x00005988 /* 64-bit */
1173 #define GRCMBOX_SNDNIC_PROD_IDX_2       0x00005990 /* 64-bit */
1174 #define GRCMBOX_SNDNIC_PROD_IDX_3       0x00005998 /* 64-bit */
1175 #define GRCMBOX_SNDNIC_PROD_IDX_4       0x000059a0 /* 64-bit */
1176 #define GRCMBOX_SNDNIC_PROD_IDX_5       0x000059a8 /* 64-bit */
1177 #define GRCMBOX_SNDNIC_PROD_IDX_6       0x000059b0 /* 64-bit */
1178 #define GRCMBOX_SNDNIC_PROD_IDX_7       0x000059b8 /* 64-bit */
1179 #define GRCMBOX_SNDNIC_PROD_IDX_8       0x000059c0 /* 64-bit */
1180 #define GRCMBOX_SNDNIC_PROD_IDX_9       0x000059c8 /* 64-bit */
1181 #define GRCMBOX_SNDNIC_PROD_IDX_10      0x000059d0 /* 64-bit */
1182 #define GRCMBOX_SNDNIC_PROD_IDX_11      0x000059d8 /* 64-bit */
1183 #define GRCMBOX_SNDNIC_PROD_IDX_12      0x000059e0 /* 64-bit */
1184 #define GRCMBOX_SNDNIC_PROD_IDX_13      0x000059e8 /* 64-bit */
1185 #define GRCMBOX_SNDNIC_PROD_IDX_14      0x000059f0 /* 64-bit */
1186 #define GRCMBOX_SNDNIC_PROD_IDX_15      0x000059f8 /* 64-bit */
1187 #define GRCMBOX_HIGH_PRIO_EV_VECTOR     0x00005a00
1188 #define GRCMBOX_HIGH_PRIO_EV_MASK       0x00005a04
1189 #define GRCMBOX_LOW_PRIO_EV_VEC         0x00005a08
1190 #define GRCMBOX_LOW_PRIO_EV_MASK        0x00005a0c
1191 /* 0x5a10 --> 0x5c00 */
1192
1193 /* Flow Through queues */
1194 #define FTQ_RESET                       0x00005c00
1195 /* 0x5c04 --> 0x5c10 unused */
1196 #define FTQ_DMA_NORM_READ_CTL           0x00005c10
1197 #define FTQ_DMA_NORM_READ_FULL_CNT      0x00005c14
1198 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ   0x00005c18
1199 #define FTQ_DMA_NORM_READ_WRITE_PEEK    0x00005c1c
1200 #define FTQ_DMA_HIGH_READ_CTL           0x00005c20
1201 #define FTQ_DMA_HIGH_READ_FULL_CNT      0x00005c24
1202 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ   0x00005c28
1203 #define FTQ_DMA_HIGH_READ_WRITE_PEEK    0x00005c2c
1204 #define FTQ_DMA_COMP_DISC_CTL           0x00005c30
1205 #define FTQ_DMA_COMP_DISC_FULL_CNT      0x00005c34
1206 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ   0x00005c38
1207 #define FTQ_DMA_COMP_DISC_WRITE_PEEK    0x00005c3c
1208 #define FTQ_SEND_BD_COMP_CTL            0x00005c40
1209 #define FTQ_SEND_BD_COMP_FULL_CNT       0x00005c44
1210 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ    0x00005c48
1211 #define FTQ_SEND_BD_COMP_WRITE_PEEK     0x00005c4c
1212 #define FTQ_SEND_DATA_INIT_CTL          0x00005c50
1213 #define FTQ_SEND_DATA_INIT_FULL_CNT     0x00005c54
1214 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ  0x00005c58
1215 #define FTQ_SEND_DATA_INIT_WRITE_PEEK   0x00005c5c
1216 #define FTQ_DMA_NORM_WRITE_CTL          0x00005c60
1217 #define FTQ_DMA_NORM_WRITE_FULL_CNT     0x00005c64
1218 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ  0x00005c68
1219 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK   0x00005c6c
1220 #define FTQ_DMA_HIGH_WRITE_CTL          0x00005c70
1221 #define FTQ_DMA_HIGH_WRITE_FULL_CNT     0x00005c74
1222 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ  0x00005c78
1223 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK   0x00005c7c
1224 #define FTQ_SWTYPE1_CTL                 0x00005c80
1225 #define FTQ_SWTYPE1_FULL_CNT            0x00005c84
1226 #define FTQ_SWTYPE1_FIFO_ENQDEQ         0x00005c88
1227 #define FTQ_SWTYPE1_WRITE_PEEK          0x00005c8c
1228 #define FTQ_SEND_DATA_COMP_CTL          0x00005c90
1229 #define FTQ_SEND_DATA_COMP_FULL_CNT     0x00005c94
1230 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ  0x00005c98
1231 #define FTQ_SEND_DATA_COMP_WRITE_PEEK   0x00005c9c
1232 #define FTQ_HOST_COAL_CTL               0x00005ca0
1233 #define FTQ_HOST_COAL_FULL_CNT          0x00005ca4
1234 #define FTQ_HOST_COAL_FIFO_ENQDEQ       0x00005ca8
1235 #define FTQ_HOST_COAL_WRITE_PEEK        0x00005cac
1236 #define FTQ_MAC_TX_CTL                  0x00005cb0
1237 #define FTQ_MAC_TX_FULL_CNT             0x00005cb4
1238 #define FTQ_MAC_TX_FIFO_ENQDEQ          0x00005cb8
1239 #define FTQ_MAC_TX_WRITE_PEEK           0x00005cbc
1240 #define FTQ_MB_FREE_CTL                 0x00005cc0
1241 #define FTQ_MB_FREE_FULL_CNT            0x00005cc4
1242 #define FTQ_MB_FREE_FIFO_ENQDEQ         0x00005cc8
1243 #define FTQ_MB_FREE_WRITE_PEEK          0x00005ccc
1244 #define FTQ_RCVBD_COMP_CTL              0x00005cd0
1245 #define FTQ_RCVBD_COMP_FULL_CNT         0x00005cd4
1246 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ      0x00005cd8
1247 #define FTQ_RCVBD_COMP_WRITE_PEEK       0x00005cdc
1248 #define FTQ_RCVLST_PLMT_CTL             0x00005ce0
1249 #define FTQ_RCVLST_PLMT_FULL_CNT        0x00005ce4
1250 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ     0x00005ce8
1251 #define FTQ_RCVLST_PLMT_WRITE_PEEK      0x00005cec
1252 #define FTQ_RCVDATA_INI_CTL             0x00005cf0
1253 #define FTQ_RCVDATA_INI_FULL_CNT        0x00005cf4
1254 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ     0x00005cf8
1255 #define FTQ_RCVDATA_INI_WRITE_PEEK      0x00005cfc
1256 #define FTQ_RCVDATA_COMP_CTL            0x00005d00
1257 #define FTQ_RCVDATA_COMP_FULL_CNT       0x00005d04
1258 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ    0x00005d08
1259 #define FTQ_RCVDATA_COMP_WRITE_PEEK     0x00005d0c
1260 #define FTQ_SWTYPE2_CTL                 0x00005d10
1261 #define FTQ_SWTYPE2_FULL_CNT            0x00005d14
1262 #define FTQ_SWTYPE2_FIFO_ENQDEQ         0x00005d18
1263 #define FTQ_SWTYPE2_WRITE_PEEK          0x00005d1c
1264 /* 0x5d20 --> 0x6000 unused */
1265
1266 /* Message signaled interrupt registers */
1267 #define MSGINT_MODE                     0x00006000
1268 #define  MSGINT_MODE_RESET               0x00000001
1269 #define  MSGINT_MODE_ENABLE              0x00000002
1270 #define MSGINT_STATUS                   0x00006004
1271 #define MSGINT_FIFO                     0x00006008
1272 /* 0x600c --> 0x6400 unused */
1273
1274 /* DMA completion registers */
1275 #define DMAC_MODE                       0x00006400
1276 #define  DMAC_MODE_RESET                 0x00000001
1277 #define  DMAC_MODE_ENABLE                0x00000002
1278 /* 0x6404 --> 0x6800 unused */
1279
1280 /* GRC registers */
1281 #define GRC_MODE                        0x00006800
1282 #define  GRC_MODE_UPD_ON_COAL           0x00000001
1283 #define  GRC_MODE_BSWAP_NONFRM_DATA     0x00000002
1284 #define  GRC_MODE_WSWAP_NONFRM_DATA     0x00000004
1285 #define  GRC_MODE_BSWAP_DATA            0x00000010
1286 #define  GRC_MODE_WSWAP_DATA            0x00000020
1287 #define  GRC_MODE_SPLITHDR              0x00000100
1288 #define  GRC_MODE_NOFRM_CRACKING        0x00000200
1289 #define  GRC_MODE_INCL_CRC              0x00000400
1290 #define  GRC_MODE_ALLOW_BAD_FRMS        0x00000800
1291 #define  GRC_MODE_NOIRQ_ON_SENDS        0x00002000
1292 #define  GRC_MODE_NOIRQ_ON_RCV          0x00004000
1293 #define  GRC_MODE_FORCE_PCI32BIT        0x00008000
1294 #define  GRC_MODE_HOST_STACKUP          0x00010000
1295 #define  GRC_MODE_HOST_SENDBDS          0x00020000
1296 #define  GRC_MODE_NO_TX_PHDR_CSUM       0x00100000
1297 #define  GRC_MODE_NVRAM_WR_ENABLE       0x00200000
1298 #define  GRC_MODE_NO_RX_PHDR_CSUM       0x00800000
1299 #define  GRC_MODE_IRQ_ON_TX_CPU_ATTN    0x01000000
1300 #define  GRC_MODE_IRQ_ON_RX_CPU_ATTN    0x02000000
1301 #define  GRC_MODE_IRQ_ON_MAC_ATTN       0x04000000
1302 #define  GRC_MODE_IRQ_ON_DMA_ATTN       0x08000000
1303 #define  GRC_MODE_IRQ_ON_FLOW_ATTN      0x10000000
1304 #define  GRC_MODE_4X_NIC_SEND_RINGS     0x20000000
1305 #define  GRC_MODE_MCAST_FRM_ENABLE      0x40000000
1306 #define GRC_MISC_CFG                    0x00006804
1307 #define  GRC_MISC_CFG_CORECLK_RESET     0x00000001
1308 #define  GRC_MISC_CFG_PRESCALAR_MASK    0x000000fe
1309 #define  GRC_MISC_CFG_PRESCALAR_SHIFT   1
1310 #define  GRC_MISC_CFG_BOARD_ID_MASK     0x0001e000
1311 #define  GRC_MISC_CFG_BOARD_ID_5700     0x0001e000
1312 #define  GRC_MISC_CFG_BOARD_ID_5701     0x00000000
1313 #define  GRC_MISC_CFG_BOARD_ID_5702FE   0x00004000
1314 #define  GRC_MISC_CFG_BOARD_ID_5703     0x00000000
1315 #define  GRC_MISC_CFG_BOARD_ID_5703S    0x00002000
1316 #define  GRC_MISC_CFG_BOARD_ID_5704     0x00000000
1317 #define  GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1318 #define  GRC_MISC_CFG_BOARD_ID_5704_A2  0x00008000
1319 #define  GRC_MISC_CFG_BOARD_ID_5788     0x00010000
1320 #define  GRC_MISC_CFG_BOARD_ID_5788M    0x00018000
1321 #define  GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1322 #define  GRC_MISC_CFG_KEEP_GPHY_POWER   0x04000000
1323 #define GRC_LOCAL_CTRL                  0x00006808
1324 #define  GRC_LCLCTRL_INT_ACTIVE         0x00000001
1325 #define  GRC_LCLCTRL_CLEARINT           0x00000002
1326 #define  GRC_LCLCTRL_SETINT             0x00000004
1327 #define  GRC_LCLCTRL_INT_ON_ATTN        0x00000008
1328 #define  GRC_LCLCTRL_GPIO_INPUT3        0x00000020
1329 #define  GRC_LCLCTRL_GPIO_OE3           0x00000040
1330 #define  GRC_LCLCTRL_GPIO_OUTPUT3       0x00000080
1331 #define  GRC_LCLCTRL_GPIO_INPUT0        0x00000100
1332 #define  GRC_LCLCTRL_GPIO_INPUT1        0x00000200
1333 #define  GRC_LCLCTRL_GPIO_INPUT2        0x00000400
1334 #define  GRC_LCLCTRL_GPIO_OE0           0x00000800
1335 #define  GRC_LCLCTRL_GPIO_OE1           0x00001000
1336 #define  GRC_LCLCTRL_GPIO_OE2           0x00002000
1337 #define  GRC_LCLCTRL_GPIO_OUTPUT0       0x00004000
1338 #define  GRC_LCLCTRL_GPIO_OUTPUT1       0x00008000
1339 #define  GRC_LCLCTRL_GPIO_OUTPUT2       0x00010000
1340 #define  GRC_LCLCTRL_EXTMEM_ENABLE      0x00020000
1341 #define  GRC_LCLCTRL_MEMSZ_MASK         0x001c0000
1342 #define  GRC_LCLCTRL_MEMSZ_256K         0x00000000
1343 #define  GRC_LCLCTRL_MEMSZ_512K         0x00040000
1344 #define  GRC_LCLCTRL_MEMSZ_1M           0x00080000
1345 #define  GRC_LCLCTRL_MEMSZ_2M           0x000c0000
1346 #define  GRC_LCLCTRL_MEMSZ_4M           0x00100000
1347 #define  GRC_LCLCTRL_MEMSZ_8M           0x00140000
1348 #define  GRC_LCLCTRL_MEMSZ_16M          0x00180000
1349 #define  GRC_LCLCTRL_BANK_SELECT        0x00200000
1350 #define  GRC_LCLCTRL_SSRAM_TYPE         0x00400000
1351 #define  GRC_LCLCTRL_AUTO_SEEPROM       0x01000000
1352 #define GRC_TIMER                       0x0000680c
1353 #define GRC_RX_CPU_EVENT                0x00006810
1354 #define GRC_RX_TIMER_REF                0x00006814
1355 #define GRC_RX_CPU_SEM                  0x00006818
1356 #define GRC_REMOTE_RX_CPU_ATTN          0x0000681c
1357 #define GRC_TX_CPU_EVENT                0x00006820
1358 #define GRC_TX_TIMER_REF                0x00006824
1359 #define GRC_TX_CPU_SEM                  0x00006828
1360 #define GRC_REMOTE_TX_CPU_ATTN          0x0000682c
1361 #define GRC_MEM_POWER_UP                0x00006830 /* 64-bit */
1362 #define GRC_EEPROM_ADDR                 0x00006838
1363 #define  EEPROM_ADDR_WRITE              0x00000000
1364 #define  EEPROM_ADDR_READ               0x80000000
1365 #define  EEPROM_ADDR_COMPLETE           0x40000000
1366 #define  EEPROM_ADDR_FSM_RESET          0x20000000
1367 #define  EEPROM_ADDR_DEVID_MASK         0x1c000000
1368 #define  EEPROM_ADDR_DEVID_SHIFT        26
1369 #define  EEPROM_ADDR_START              0x02000000
1370 #define  EEPROM_ADDR_CLKPERD_SHIFT      16
1371 #define  EEPROM_ADDR_ADDR_MASK          0x0000ffff
1372 #define  EEPROM_ADDR_ADDR_SHIFT         0
1373 #define  EEPROM_DEFAULT_CLOCK_PERIOD    0x60
1374 #define  EEPROM_CHIP_SIZE               (64 * 1024)
1375 #define GRC_EEPROM_DATA                 0x0000683c
1376 #define GRC_EEPROM_CTRL                 0x00006840
1377 #define GRC_MDI_CTRL                    0x00006844
1378 #define GRC_SEEPROM_DELAY               0x00006848
1379 /* 0x684c --> 0x6c00 unused */
1380
1381 /* 0x6c00 --> 0x7000 unused */
1382
1383 /* NVRAM Control registers */
1384 #define NVRAM_CMD                       0x00007000
1385 #define  NVRAM_CMD_RESET                 0x00000001
1386 #define  NVRAM_CMD_DONE                  0x00000008
1387 #define  NVRAM_CMD_GO                    0x00000010
1388 #define  NVRAM_CMD_WR                    0x00000020
1389 #define  NVRAM_CMD_RD                    0x00000000
1390 #define  NVRAM_CMD_ERASE                 0x00000040
1391 #define  NVRAM_CMD_FIRST                 0x00000080
1392 #define  NVRAM_CMD_LAST                  0x00000100
1393 #define  NVRAM_CMD_WREN                  0x00010000
1394 #define  NVRAM_CMD_WRDI                  0x00020000
1395 #define NVRAM_STAT                      0x00007004
1396 #define NVRAM_WRDATA                    0x00007008
1397 #define NVRAM_ADDR                      0x0000700c
1398 #define  NVRAM_ADDR_MSK                 0x00ffffff
1399 #define NVRAM_RDDATA                    0x00007010
1400 #define NVRAM_CFG1                      0x00007014
1401 #define  NVRAM_CFG1_FLASHIF_ENAB         0x00000001
1402 #define  NVRAM_CFG1_BUFFERED_MODE        0x00000002
1403 #define  NVRAM_CFG1_PASS_THRU            0x00000004
1404 #define  NVRAM_CFG1_STATUS_BITS          0x00000070
1405 #define  NVRAM_CFG1_BIT_BANG             0x00000008
1406 #define  NVRAM_CFG1_FLASH_SIZE           0x02000000
1407 #define  NVRAM_CFG1_COMPAT_BYPASS        0x80000000
1408 #define  NVRAM_CFG1_VENDOR_MASK          0x03000003
1409 #define  FLASH_VENDOR_ATMEL_EEPROM       0x02000000
1410 #define  FLASH_VENDOR_ATMEL_FLASH_BUFFERED       0x02000003
1411 #define  FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED     0x00000003
1412 #define  FLASH_VENDOR_ST                         0x03000001
1413 #define  FLASH_VENDOR_SAIFUN             0x01000003
1414 #define  FLASH_VENDOR_SST_SMALL          0x00000001
1415 #define  FLASH_VENDOR_SST_LARGE          0x02000001
1416 #define  NVRAM_CFG1_5752VENDOR_MASK      0x03c00003
1417 #define  FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ     0x00000000
1418 #define  FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ    0x02000000
1419 #define  FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED   0x02000003
1420 #define  FLASH_5752VENDOR_ST_M45PE10     0x02400000
1421 #define  FLASH_5752VENDOR_ST_M45PE20     0x02400002
1422 #define  FLASH_5752VENDOR_ST_M45PE40     0x02400001
1423 #define  NVRAM_CFG1_5752PAGE_SIZE_MASK   0x70000000
1424 #define  FLASH_5752PAGE_SIZE_256         0x00000000
1425 #define  FLASH_5752PAGE_SIZE_512         0x10000000
1426 #define  FLASH_5752PAGE_SIZE_1K          0x20000000
1427 #define  FLASH_5752PAGE_SIZE_2K          0x30000000
1428 #define  FLASH_5752PAGE_SIZE_4K          0x40000000
1429 #define  FLASH_5752PAGE_SIZE_264         0x50000000
1430 #define NVRAM_CFG2                      0x00007018
1431 #define NVRAM_CFG3                      0x0000701c
1432 #define NVRAM_SWARB                     0x00007020
1433 #define  SWARB_REQ_SET0                  0x00000001
1434 #define  SWARB_REQ_SET1                  0x00000002
1435 #define  SWARB_REQ_SET2                  0x00000004
1436 #define  SWARB_REQ_SET3                  0x00000008
1437 #define  SWARB_REQ_CLR0                  0x00000010
1438 #define  SWARB_REQ_CLR1                  0x00000020
1439 #define  SWARB_REQ_CLR2                  0x00000040
1440 #define  SWARB_REQ_CLR3                  0x00000080
1441 #define  SWARB_GNT0                      0x00000100
1442 #define  SWARB_GNT1                      0x00000200
1443 #define  SWARB_GNT2                      0x00000400
1444 #define  SWARB_GNT3                      0x00000800
1445 #define  SWARB_REQ0                      0x00001000
1446 #define  SWARB_REQ1                      0x00002000
1447 #define  SWARB_REQ2                      0x00004000
1448 #define  SWARB_REQ3                      0x00008000
1449 #define NVRAM_ACCESS                    0x00007024
1450 #define  ACCESS_ENABLE                   0x00000001
1451 #define  ACCESS_WR_ENABLE                0x00000002
1452 #define NVRAM_WRITE1                    0x00007028
1453 /* 0x702c --> 0x7400 unused */
1454
1455 /* 0x7400 --> 0x8000 unused */
1456
1457 #define TG3_EEPROM_MAGIC                0x669955aa
1458
1459 /* 32K Window into NIC internal memory */
1460 #define NIC_SRAM_WIN_BASE               0x00008000
1461
1462 /* Offsets into first 32k of NIC internal memory. */
1463 #define NIC_SRAM_PAGE_ZERO              0x00000000
1464 #define NIC_SRAM_SEND_RCB               0x00000100 /* 16 * TG3_BDINFO_... */
1465 #define NIC_SRAM_RCV_RET_RCB            0x00000200 /* 16 * TG3_BDINFO_... */
1466 #define NIC_SRAM_STATS_BLK              0x00000300
1467 #define NIC_SRAM_STATUS_BLK             0x00000b00
1468
1469 #define NIC_SRAM_FIRMWARE_MBOX          0x00000b50
1470 #define  NIC_SRAM_FIRMWARE_MBOX_MAGIC1   0x4B657654
1471 #define  NIC_SRAM_FIRMWARE_MBOX_MAGIC2   0x4861764b /* !dma on linkchg */
1472
1473 #define NIC_SRAM_DATA_SIG               0x00000b54
1474 #define  NIC_SRAM_DATA_SIG_MAGIC         0x4b657654 /* ascii for 'KevT' */
1475
1476 #define NIC_SRAM_DATA_CFG                       0x00000b58
1477 #define  NIC_SRAM_DATA_CFG_LED_MODE_MASK         0x0000000c
1478 #define  NIC_SRAM_DATA_CFG_LED_MODE_MAC          0x00000000
1479 #define  NIC_SRAM_DATA_CFG_LED_MODE_PHY_1        0x00000004
1480 #define  NIC_SRAM_DATA_CFG_LED_MODE_PHY_2        0x00000008
1481 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_MASK         0x00000030
1482 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN      0x00000000
1483 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER       0x00000010
1484 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER        0x00000020
1485 #define  NIC_SRAM_DATA_CFG_WOL_ENABLE            0x00000040
1486 #define  NIC_SRAM_DATA_CFG_ASF_ENABLE            0x00000080
1487 #define  NIC_SRAM_DATA_CFG_EEPROM_WP             0x00000100
1488 #define  NIC_SRAM_DATA_CFG_MINI_PCI              0x00001000
1489 #define  NIC_SRAM_DATA_CFG_FIBER_WOL             0x00004000
1490 #define  NIC_SRAM_DATA_CFG_NO_GPIO2              0x00100000
1491
1492 #define NIC_SRAM_DATA_VER                       0x00000b5c
1493 #define  NIC_SRAM_DATA_VER_SHIFT                 16
1494
1495 #define NIC_SRAM_DATA_PHY_ID            0x00000b74
1496 #define  NIC_SRAM_DATA_PHY_ID1_MASK      0xffff0000
1497 #define  NIC_SRAM_DATA_PHY_ID2_MASK      0x0000ffff
1498
1499 #define NIC_SRAM_FW_CMD_MBOX            0x00000b78
1500 #define  FWCMD_NICDRV_ALIVE              0x00000001
1501 #define  FWCMD_NICDRV_PAUSE_FW           0x00000002
1502 #define  FWCMD_NICDRV_IPV4ADDR_CHG       0x00000003
1503 #define  FWCMD_NICDRV_IPV6ADDR_CHG       0x00000004
1504 #define  FWCMD_NICDRV_FIX_DMAR           0x00000005
1505 #define  FWCMD_NICDRV_FIX_DMAW           0x00000006
1506 #define NIC_SRAM_FW_CMD_LEN_MBOX        0x00000b7c
1507 #define NIC_SRAM_FW_CMD_DATA_MBOX       0x00000b80
1508 #define NIC_SRAM_FW_ASF_STATUS_MBOX     0x00000c00
1509 #define NIC_SRAM_FW_DRV_STATE_MBOX      0x00000c04
1510 #define  DRV_STATE_START                 0x00000001
1511 #define  DRV_STATE_START_DONE            0x80000001
1512 #define  DRV_STATE_UNLOAD                0x00000002
1513 #define  DRV_STATE_UNLOAD_DONE           0x80000002
1514 #define  DRV_STATE_WOL                   0x00000003
1515 #define  DRV_STATE_SUSPEND               0x00000004
1516
1517 #define NIC_SRAM_FW_RESET_TYPE_MBOX     0x00000c08
1518
1519 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX     0x00000c14
1520 #define NIC_SRAM_MAC_ADDR_LOW_MBOX      0x00000c18
1521
1522 #define NIC_SRAM_DATA_CFG_2             0x00000d38
1523
1524 #define  SHASTA_EXT_LED_MODE_MASK        0x00018000
1525 #define  SHASTA_EXT_LED_LEGACY           0x00000000
1526 #define  SHASTA_EXT_LED_SHARED           0x00008000
1527 #define  SHASTA_EXT_LED_MAC              0x00010000
1528 #define  SHASTA_EXT_LED_COMBO            0x00018000
1529
1530 #define NIC_SRAM_RX_MINI_BUFFER_DESC    0x00001000
1531
1532 #define NIC_SRAM_DMA_DESC_POOL_BASE     0x00002000
1533 #define  NIC_SRAM_DMA_DESC_POOL_SIZE     0x00002000
1534 #define NIC_SRAM_TX_BUFFER_DESC         0x00004000 /* 512 entries */
1535 #define NIC_SRAM_RX_BUFFER_DESC         0x00006000 /* 256 entries */
1536 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC   0x00007000 /* 256 entries */
1537 #define NIC_SRAM_MBUF_POOL_BASE         0x00008000
1538 #define  NIC_SRAM_MBUF_POOL_SIZE96       0x00018000
1539 #define  NIC_SRAM_MBUF_POOL_SIZE64       0x00010000
1540 #define  NIC_SRAM_MBUF_POOL_BASE5705    0x00010000
1541 #define  NIC_SRAM_MBUF_POOL_SIZE5705    0x0000e000
1542
1543 /* Currently this is fixed. */
1544 #define PHY_ADDR                0x01
1545
1546 /* Tigon3 specific PHY MII registers. */
1547 #define  TG3_BMCR_SPEED1000             0x0040
1548
1549 #define MII_TG3_CTRL                    0x09 /* 1000-baseT control register */
1550 #define  MII_TG3_CTRL_ADV_1000_HALF     0x0100
1551 #define  MII_TG3_CTRL_ADV_1000_FULL     0x0200
1552 #define  MII_TG3_CTRL_AS_MASTER         0x0800
1553 #define  MII_TG3_CTRL_ENABLE_AS_MASTER  0x1000
1554
1555 #define MII_TG3_EXT_CTRL                0x10 /* Extended control register */
1556 #define  MII_TG3_EXT_CTRL_FIFO_ELASTIC  0x0001
1557 #define  MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
1558 #define  MII_TG3_EXT_CTRL_TBI           0x8000
1559
1560 #define MII_TG3_EXT_STAT                0x11 /* Extended status register */
1561 #define  MII_TG3_EXT_STAT_LPASS         0x0100
1562
1563 #define MII_TG3_DSP_RW_PORT             0x15 /* DSP coefficient read/write port */
1564
1565 #define MII_TG3_DSP_ADDRESS             0x17 /* DSP address register */
1566
1567 #define MII_TG3_AUX_CTRL                0x18 /* auxilliary control register */
1568
1569 #define MII_TG3_AUX_STAT                0x19 /* auxilliary status register */
1570 #define MII_TG3_AUX_STAT_LPASS          0x0004
1571 #define MII_TG3_AUX_STAT_SPDMASK        0x0700
1572 #define MII_TG3_AUX_STAT_10HALF         0x0100
1573 #define MII_TG3_AUX_STAT_10FULL         0x0200
1574 #define MII_TG3_AUX_STAT_100HALF        0x0300
1575 #define MII_TG3_AUX_STAT_100_4          0x0400
1576 #define MII_TG3_AUX_STAT_100FULL        0x0500
1577 #define MII_TG3_AUX_STAT_1000HALF       0x0600
1578 #define MII_TG3_AUX_STAT_1000FULL       0x0700
1579
1580 #define MII_TG3_ISTAT                   0x1a /* IRQ status register */
1581 #define MII_TG3_IMASK                   0x1b /* IRQ mask register */
1582
1583 /* ISTAT/IMASK event bits */
1584 #define MII_TG3_INT_LINKCHG             0x0002
1585 #define MII_TG3_INT_SPEEDCHG            0x0004
1586 #define MII_TG3_INT_DUPLEXCHG           0x0008
1587 #define MII_TG3_INT_ANEG_PAGE_RX        0x0400
1588
1589 /* There are two ways to manage the TX descriptors on the tigon3.
1590  * Either the descriptors are in host DMA'able memory, or they
1591  * exist only in the cards on-chip SRAM.  All 16 send bds are under
1592  * the same mode, they may not be configured individually.
1593  *
1594  * This driver always uses host memory TX descriptors.
1595  *
1596  * To use host memory TX descriptors:
1597  *      1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
1598  *         Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
1599  *      2) Allocate DMA'able memory.
1600  *      3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1601  *         a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
1602  *            obtained in step 2
1603  *         b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
1604  *         c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
1605  *            of TX descriptors.  Leave flags field clear.
1606  *      4) Access TX descriptors via host memory.  The chip
1607  *         will refetch into local SRAM as needed when producer
1608  *         index mailboxes are updated.
1609  *
1610  * To use on-chip TX descriptors:
1611  *      1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
1612  *         Make sure GRC_MODE_HOST_SENDBDS is clear.
1613  *      2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1614  *         a) Set TG3_BDINFO_HOST_ADDR to zero.
1615  *         b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
1616  *         c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
1617  *      3) Access TX descriptors directly in on-chip SRAM
1618  *         using normal {read,write}l().  (and not using
1619  *         pointer dereferencing of ioremap()'d memory like
1620  *         the broken Broadcom driver does)
1621  *
1622  * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
1623  * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
1624  */
1625 struct tg3_tx_buffer_desc {
1626         u32                             addr_hi;
1627         u32                             addr_lo;
1628
1629         u32                             len_flags;
1630 #define TXD_FLAG_TCPUDP_CSUM            0x0001
1631 #define TXD_FLAG_IP_CSUM                0x0002
1632 #define TXD_FLAG_END                    0x0004
1633 #define TXD_FLAG_IP_FRAG                0x0008
1634 #define TXD_FLAG_IP_FRAG_END            0x0010
1635 #define TXD_FLAG_VLAN                   0x0040
1636 #define TXD_FLAG_COAL_NOW               0x0080
1637 #define TXD_FLAG_CPU_PRE_DMA            0x0100
1638 #define TXD_FLAG_CPU_POST_DMA           0x0200
1639 #define TXD_FLAG_ADD_SRC_ADDR           0x1000
1640 #define TXD_FLAG_CHOOSE_SRC_ADDR        0x6000
1641 #define TXD_FLAG_NO_CRC                 0x8000
1642 #define TXD_LEN_SHIFT                   16
1643
1644         u32                             vlan_tag;
1645 #define TXD_VLAN_TAG_SHIFT              0
1646 #define TXD_MSS_SHIFT                   16
1647 };
1648
1649 #define TXD_ADDR                        0x00UL /* 64-bit */
1650 #define TXD_LEN_FLAGS                   0x08UL /* 32-bit (upper 16-bits are len) */
1651 #define TXD_VLAN_TAG                    0x0cUL /* 32-bit (upper 16-bits are tag) */
1652 #define TXD_SIZE                        0x10UL
1653
1654 struct tg3_rx_buffer_desc {
1655         u32                             addr_hi;
1656         u32                             addr_lo;
1657
1658         u32                             idx_len;
1659 #define RXD_IDX_MASK    0xffff0000
1660 #define RXD_IDX_SHIFT   16
1661 #define RXD_LEN_MASK    0x0000ffff
1662 #define RXD_LEN_SHIFT   0
1663
1664         u32                             type_flags;
1665 #define RXD_TYPE_SHIFT  16
1666 #define RXD_FLAGS_SHIFT 0
1667
1668 #define RXD_FLAG_END                    0x0004
1669 #define RXD_FLAG_MINI                   0x0800
1670 #define RXD_FLAG_JUMBO                  0x0020
1671 #define RXD_FLAG_VLAN                   0x0040
1672 #define RXD_FLAG_ERROR                  0x0400
1673 #define RXD_FLAG_IP_CSUM                0x1000
1674 #define RXD_FLAG_TCPUDP_CSUM            0x2000
1675 #define RXD_FLAG_IS_TCP                 0x4000
1676
1677         u32                             ip_tcp_csum;
1678 #define RXD_IPCSUM_MASK         0xffff0000
1679 #define RXD_IPCSUM_SHIFT        16
1680 #define RXD_TCPCSUM_MASK        0x0000ffff
1681 #define RXD_TCPCSUM_SHIFT       0
1682
1683         u32                             err_vlan;
1684
1685 #define RXD_VLAN_MASK                   0x0000ffff
1686
1687 #define RXD_ERR_BAD_CRC                 0x00010000
1688 #define RXD_ERR_COLLISION               0x00020000
1689 #define RXD_ERR_LINK_LOST               0x00040000
1690 #define RXD_ERR_PHY_DECODE              0x00080000
1691 #define RXD_ERR_ODD_NIBBLE_RCVD_MII     0x00100000
1692 #define RXD_ERR_MAC_ABRT                0x00200000
1693 #define RXD_ERR_TOO_SMALL               0x00400000
1694 #define RXD_ERR_NO_RESOURCES            0x00800000
1695 #define RXD_ERR_HUGE_FRAME              0x01000000
1696 #define RXD_ERR_MASK                    0xffff0000
1697
1698         u32                             reserved;
1699         u32                             opaque;
1700 #define RXD_OPAQUE_INDEX_MASK           0x0000ffff
1701 #define RXD_OPAQUE_INDEX_SHIFT          0
1702 #define RXD_OPAQUE_RING_STD             0x00010000
1703 #define RXD_OPAQUE_RING_JUMBO           0x00020000
1704 #define RXD_OPAQUE_RING_MINI            0x00040000
1705 #define RXD_OPAQUE_RING_MASK            0x00070000
1706 };
1707
1708 struct tg3_ext_rx_buffer_desc {
1709         struct {
1710                 u32                     addr_hi;
1711                 u32                     addr_lo;
1712         }                               addrlist[3];
1713         u32                             len2_len1;
1714         u32                             resv_len3;
1715         struct tg3_rx_buffer_desc       std;
1716 };
1717
1718 /* We only use this when testing out the DMA engine
1719  * at probe time.  This is the internal format of buffer
1720  * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
1721  */
1722 struct tg3_internal_buffer_desc {
1723         u32                             addr_hi;
1724         u32                             addr_lo;
1725         u32                             nic_mbuf;
1726         /* XXX FIX THIS */
1727 #ifdef __BIG_ENDIAN
1728         u16                             cqid_sqid;
1729         u16                             len;
1730 #else
1731         u16                             len;
1732         u16                             cqid_sqid;
1733 #endif
1734         u32                             flags;
1735         u32                             __cookie1;
1736         u32                             __cookie2;
1737         u32                             __cookie3;
1738 };
1739
1740 #define TG3_HW_STATUS_SIZE              0x50
1741 struct tg3_hw_status {
1742         u32                             status;
1743 #define SD_STATUS_UPDATED               0x00000001
1744 #define SD_STATUS_LINK_CHG              0x00000002
1745 #define SD_STATUS_ERROR                 0x00000004
1746
1747         u32                             status_tag;
1748
1749 #ifdef __BIG_ENDIAN
1750         u16                             rx_consumer;
1751         u16                             rx_jumbo_consumer;
1752 #else
1753         u16                             rx_jumbo_consumer;
1754         u16                             rx_consumer;
1755 #endif
1756
1757 #ifdef __BIG_ENDIAN
1758         u16                             reserved;
1759         u16                             rx_mini_consumer;
1760 #else
1761         u16                             rx_mini_consumer;
1762         u16                             reserved;
1763 #endif
1764         struct {
1765 #ifdef __BIG_ENDIAN
1766                 u16                     tx_consumer;
1767                 u16                     rx_producer;
1768 #else
1769                 u16                     rx_producer;
1770                 u16                     tx_consumer;
1771 #endif
1772         }                               idx[16];
1773 };
1774
1775 typedef struct {
1776         u32 high, low;
1777 } tg3_stat64_t;
1778
1779 struct tg3_hw_stats {
1780         u8                              __reserved0[0x400-0x300];
1781
1782         /* Statistics maintained by Receive MAC. */
1783         tg3_stat64_t                    rx_octets;
1784         u64                             __reserved1;
1785         tg3_stat64_t                    rx_fragments;
1786         tg3_stat64_t                    rx_ucast_packets;
1787         tg3_stat64_t                    rx_mcast_packets;
1788         tg3_stat64_t                    rx_bcast_packets;
1789         tg3_stat64_t                    rx_fcs_errors;
1790         tg3_stat64_t                    rx_align_errors;
1791         tg3_stat64_t                    rx_xon_pause_rcvd;
1792         tg3_stat64_t                    rx_xoff_pause_rcvd;
1793         tg3_stat64_t                    rx_mac_ctrl_rcvd;
1794         tg3_stat64_t                    rx_xoff_entered;
1795         tg3_stat64_t                    rx_frame_too_long_errors;
1796         tg3_stat64_t                    rx_jabbers;
1797         tg3_stat64_t                    rx_undersize_packets;
1798         tg3_stat64_t                    rx_in_length_errors;
1799         tg3_stat64_t                    rx_out_length_errors;
1800         tg3_stat64_t                    rx_64_or_less_octet_packets;
1801         tg3_stat64_t                    rx_65_to_127_octet_packets;
1802         tg3_stat64_t                    rx_128_to_255_octet_packets;
1803         tg3_stat64_t                    rx_256_to_511_octet_packets;
1804         tg3_stat64_t                    rx_512_to_1023_octet_packets;
1805         tg3_stat64_t                    rx_1024_to_1522_octet_packets;
1806         tg3_stat64_t                    rx_1523_to_2047_octet_packets;
1807         tg3_stat64_t                    rx_2048_to_4095_octet_packets;
1808         tg3_stat64_t                    rx_4096_to_8191_octet_packets;
1809         tg3_stat64_t                    rx_8192_to_9022_octet_packets;
1810
1811         u64                             __unused0[37];
1812
1813         /* Statistics maintained by Transmit MAC. */
1814         tg3_stat64_t                    tx_octets;
1815         u64                             __reserved2;
1816         tg3_stat64_t                    tx_collisions;
1817         tg3_stat64_t                    tx_xon_sent;
1818         tg3_stat64_t                    tx_xoff_sent;
1819         tg3_stat64_t                    tx_flow_control;
1820         tg3_stat64_t                    tx_mac_errors;
1821         tg3_stat64_t                    tx_single_collisions;
1822         tg3_stat64_t                    tx_mult_collisions;
1823         tg3_stat64_t                    tx_deferred;
1824         u64                             __reserved3;
1825         tg3_stat64_t                    tx_excessive_collisions;
1826         tg3_stat64_t                    tx_late_collisions;
1827         tg3_stat64_t                    tx_collide_2times;
1828         tg3_stat64_t                    tx_collide_3times;
1829         tg3_stat64_t                    tx_collide_4times;
1830         tg3_stat64_t                    tx_collide_5times;
1831         tg3_stat64_t                    tx_collide_6times;
1832         tg3_stat64_t                    tx_collide_7times;
1833         tg3_stat64_t                    tx_collide_8times;
1834         tg3_stat64_t                    tx_collide_9times;
1835         tg3_stat64_t                    tx_collide_10times;
1836         tg3_stat64_t                    tx_collide_11times;
1837         tg3_stat64_t                    tx_collide_12times;
1838         tg3_stat64_t                    tx_collide_13times;
1839         tg3_stat64_t                    tx_collide_14times;
1840         tg3_stat64_t                    tx_collide_15times;
1841         tg3_stat64_t                    tx_ucast_packets;
1842         tg3_stat64_t                    tx_mcast_packets;
1843         tg3_stat64_t                    tx_bcast_packets;
1844         tg3_stat64_t                    tx_carrier_sense_errors;
1845         tg3_stat64_t                    tx_discards;
1846         tg3_stat64_t                    tx_errors;
1847
1848         u64                             __unused1[31];
1849
1850         /* Statistics maintained by Receive List Placement. */
1851         tg3_stat64_t                    COS_rx_packets[16];
1852         tg3_stat64_t                    COS_rx_filter_dropped;
1853         tg3_stat64_t                    dma_writeq_full;
1854         tg3_stat64_t                    dma_write_prioq_full;
1855         tg3_stat64_t                    rxbds_empty;
1856         tg3_stat64_t                    rx_discards;
1857         tg3_stat64_t                    rx_errors;
1858         tg3_stat64_t                    rx_threshold_hit;
1859
1860         u64                             __unused2[9];
1861
1862         /* Statistics maintained by Send Data Initiator. */
1863         tg3_stat64_t                    COS_out_packets[16];
1864         tg3_stat64_t                    dma_readq_full;
1865         tg3_stat64_t                    dma_read_prioq_full;
1866         tg3_stat64_t                    tx_comp_queue_full;
1867
1868         /* Statistics maintained by Host Coalescing. */
1869         tg3_stat64_t                    ring_set_send_prod_index;
1870         tg3_stat64_t                    ring_status_update;
1871         tg3_stat64_t                    nic_irqs;
1872         tg3_stat64_t                    nic_avoided_irqs;
1873         tg3_stat64_t                    nic_tx_threshold_hit;
1874
1875         u8                              __reserved4[0xb00-0x9c0];
1876 };
1877
1878 /* 'mapping' is superfluous as the chip does not write into
1879  * the tx/rx post rings so we could just fetch it from there.
1880  * But the cache behavior is better how we are doing it now.
1881  */
1882 struct ring_info {
1883         struct sk_buff                  *skb;
1884         DECLARE_PCI_UNMAP_ADDR(mapping)
1885 };
1886
1887 struct tx_ring_info {
1888         struct sk_buff                  *skb;
1889         DECLARE_PCI_UNMAP_ADDR(mapping)
1890         u32                             prev_vlan_tag;
1891 };
1892
1893 struct tg3_config_info {
1894         u32                             flags;
1895 };
1896
1897 struct tg3_link_config {
1898         /* Describes what we're trying to get. */
1899         u32                             advertising;
1900         u16                             speed;
1901         u8                              duplex;
1902         u8                              autoneg;
1903
1904         /* Describes what we actually have. */
1905         u16                             active_speed;
1906         u8                              active_duplex;
1907 #define SPEED_INVALID           0xffff
1908 #define DUPLEX_INVALID          0xff
1909 #define AUTONEG_INVALID         0xff
1910
1911         /* When we go in and out of low power mode we need
1912          * to swap with this state.
1913          */
1914         int                             phy_is_low_power;
1915         u16                             orig_speed;
1916         u8                              orig_duplex;
1917         u8                              orig_autoneg;
1918 };
1919
1920 struct tg3_bufmgr_config {
1921         u32             mbuf_read_dma_low_water;
1922         u32             mbuf_mac_rx_low_water;
1923         u32             mbuf_high_water;
1924
1925         u32             mbuf_read_dma_low_water_jumbo;
1926         u32             mbuf_mac_rx_low_water_jumbo;
1927         u32             mbuf_high_water_jumbo;
1928
1929         u32             dma_low_water;
1930         u32             dma_high_water;
1931 };
1932
1933 struct tg3_ethtool_stats {
1934         /* Statistics maintained by Receive MAC. */
1935         u64             rx_octets;
1936         u64             rx_fragments;
1937         u64             rx_ucast_packets;
1938         u64             rx_mcast_packets;
1939         u64             rx_bcast_packets;
1940         u64             rx_fcs_errors;
1941         u64             rx_align_errors;
1942         u64             rx_xon_pause_rcvd;
1943         u64             rx_xoff_pause_rcvd;
1944         u64             rx_mac_ctrl_rcvd;
1945         u64             rx_xoff_entered;
1946         u64             rx_frame_too_long_errors;
1947         u64             rx_jabbers;
1948         u64             rx_undersize_packets;
1949         u64             rx_in_length_errors;
1950         u64             rx_out_length_errors;
1951         u64             rx_64_or_less_octet_packets;
1952         u64             rx_65_to_127_octet_packets;
1953         u64             rx_128_to_255_octet_packets;
1954         u64             rx_256_to_511_octet_packets;
1955         u64             rx_512_to_1023_octet_packets;
1956         u64             rx_1024_to_1522_octet_packets;
1957         u64             rx_1523_to_2047_octet_packets;
1958         u64             rx_2048_to_4095_octet_packets;
1959         u64             rx_4096_to_8191_octet_packets;
1960         u64             rx_8192_to_9022_octet_packets;
1961
1962         /* Statistics maintained by Transmit MAC. */
1963         u64             tx_octets;
1964         u64             tx_collisions;
1965         u64             tx_xon_sent;
1966         u64             tx_xoff_sent;
1967         u64             tx_flow_control;
1968         u64             tx_mac_errors;
1969         u64             tx_single_collisions;
1970         u64             tx_mult_collisions;
1971         u64             tx_deferred;
1972         u64             tx_excessive_collisions;
1973         u64             tx_late_collisions;
1974         u64             tx_collide_2times;
1975         u64             tx_collide_3times;
1976         u64             tx_collide_4times;
1977         u64             tx_collide_5times;
1978         u64             tx_collide_6times;
1979         u64             tx_collide_7times;
1980         u64             tx_collide_8times;
1981         u64             tx_collide_9times;
1982         u64             tx_collide_10times;
1983         u64             tx_collide_11times;
1984         u64             tx_collide_12times;
1985         u64             tx_collide_13times;
1986         u64             tx_collide_14times;
1987         u64             tx_collide_15times;
1988         u64             tx_ucast_packets;
1989         u64             tx_mcast_packets;
1990         u64             tx_bcast_packets;
1991         u64             tx_carrier_sense_errors;
1992         u64             tx_discards;
1993         u64             tx_errors;
1994
1995         /* Statistics maintained by Receive List Placement. */
1996         u64             dma_writeq_full;
1997         u64             dma_write_prioq_full;
1998         u64             rxbds_empty;
1999         u64             rx_discards;
2000         u64             rx_errors;
2001         u64             rx_threshold_hit;
2002
2003         /* Statistics maintained by Send Data Initiator. */
2004         u64             dma_readq_full;
2005         u64             dma_read_prioq_full;
2006         u64             tx_comp_queue_full;
2007
2008         /* Statistics maintained by Host Coalescing. */
2009         u64             ring_set_send_prod_index;
2010         u64             ring_status_update;
2011         u64             nic_irqs;
2012         u64             nic_avoided_irqs;
2013         u64             nic_tx_threshold_hit;
2014 };
2015
2016 struct tg3 {
2017         /* begin "general, frequently-used members" cacheline section */
2018
2019         /* If the IRQ handler (which runs lockless) needs to be
2020          * quiesced, the following bitmask state is used.  The
2021          * SYNC flag is set by non-IRQ context code to initiate
2022          * the quiescence.
2023          *
2024          * When the IRQ handler notices that SYNC is set, it
2025          * disables interrupts and returns.
2026          *
2027          * When all outstanding IRQ handlers have returned after
2028          * the SYNC flag has been set, the setter can be assured
2029          * that interrupts will no longer get run.
2030          *
2031          * In this way all SMP driver locks are never acquired
2032          * in hw IRQ context, only sw IRQ context or lower.
2033          */
2034         unsigned int                    irq_sync;
2035
2036         /* SMP locking strategy:
2037          *
2038          * lock: Held during all operations except TX packet
2039          *       processing.
2040          *
2041          * tx_lock: Held during tg3_start_xmit and tg3_tx
2042          *
2043          * Both of these locks are to be held with BH safety.
2044          */
2045         spinlock_t                      lock;
2046         spinlock_t                      indirect_lock;
2047
2048         void __iomem                    *regs;
2049         struct net_device               *dev;
2050         struct pci_dev                  *pdev;
2051
2052         struct tg3_hw_status            *hw_status;
2053         dma_addr_t                      status_mapping;
2054         u32                             last_tag;
2055
2056         u32                             msg_enable;
2057
2058         /* begin "tx thread" cacheline section */
2059         u32                             tx_prod;
2060         u32                             tx_cons;
2061         u32                             tx_pending;
2062
2063         spinlock_t                      tx_lock;
2064
2065         struct tg3_tx_buffer_desc       *tx_ring;
2066         struct tx_ring_info             *tx_buffers;
2067         dma_addr_t                      tx_desc_mapping;
2068
2069         /* begin "rx thread" cacheline section */
2070         u32                             rx_rcb_ptr;
2071         u32                             rx_std_ptr;
2072         u32                             rx_jumbo_ptr;
2073         u32                             rx_pending;
2074         u32                             rx_jumbo_pending;
2075 #if TG3_VLAN_TAG_USED
2076         struct vlan_group               *vlgrp;
2077 #endif
2078
2079         struct tg3_rx_buffer_desc       *rx_std;
2080         struct ring_info                *rx_std_buffers;
2081         dma_addr_t                      rx_std_mapping;
2082
2083         struct tg3_rx_buffer_desc       *rx_jumbo;
2084         struct ring_info                *rx_jumbo_buffers;
2085         dma_addr_t                      rx_jumbo_mapping;
2086
2087         struct tg3_rx_buffer_desc       *rx_rcb;
2088         dma_addr_t                      rx_rcb_mapping;
2089
2090         /* begin "everything else" cacheline(s) section */
2091         struct net_device_stats         net_stats;
2092         struct net_device_stats         net_stats_prev;
2093         struct tg3_ethtool_stats        estats;
2094         struct tg3_ethtool_stats        estats_prev;
2095
2096         unsigned long                   phy_crc_errors;
2097
2098         u32                             rx_offset;
2099         u32                             tg3_flags;
2100 #define TG3_FLAG_TAGGED_STATUS          0x00000001
2101 #define TG3_FLAG_TXD_MBOX_HWBUG         0x00000002
2102 #define TG3_FLAG_RX_CHECKSUMS           0x00000004
2103 #define TG3_FLAG_USE_LINKCHG_REG        0x00000008
2104 #define TG3_FLAG_USE_MI_INTERRUPT       0x00000010
2105 #define TG3_FLAG_ENABLE_ASF             0x00000020
2106 #define TG3_FLAG_5701_REG_WRITE_BUG     0x00000040
2107 #define TG3_FLAG_POLL_SERDES            0x00000080
2108 #if defined(CONFIG_X86)
2109 #define TG3_FLAG_MBOX_WRITE_REORDER     0x00000100
2110 #else
2111 #define TG3_FLAG_MBOX_WRITE_REORDER     0       /* disables code too */
2112 #endif
2113 #define TG3_FLAG_PCIX_TARGET_HWBUG      0x00000200
2114 #define TG3_FLAG_WOL_SPEED_100MB        0x00000400
2115 #define TG3_FLAG_WOL_ENABLE             0x00000800
2116 #define TG3_FLAG_EEPROM_WRITE_PROT      0x00001000
2117 #define TG3_FLAG_NVRAM                  0x00002000
2118 #define TG3_FLAG_NVRAM_BUFFERED         0x00004000
2119 #define TG3_FLAG_RX_PAUSE               0x00008000
2120 #define TG3_FLAG_TX_PAUSE               0x00010000
2121 #define TG3_FLAG_PCIX_MODE              0x00020000
2122 #define TG3_FLAG_PCI_HIGH_SPEED         0x00040000
2123 #define TG3_FLAG_PCI_32BIT              0x00080000
2124 #define TG3_FLAG_NO_TX_PSEUDO_CSUM      0x00100000
2125 #define TG3_FLAG_NO_RX_PSEUDO_CSUM      0x00200000
2126 #define TG3_FLAG_SERDES_WOL_CAP         0x00400000
2127 #define TG3_FLAG_JUMBO_ENABLE           0x00800000
2128 #define TG3_FLAG_10_100_ONLY            0x01000000
2129 #define TG3_FLAG_PAUSE_AUTONEG          0x02000000
2130 #define TG3_FLAG_BROKEN_CHECKSUMS       0x10000000
2131 #define TG3_FLAG_GOT_SERDES_FLOWCTL     0x20000000
2132 #define TG3_FLAG_SPLIT_MODE             0x40000000
2133 #define TG3_FLAG_INIT_COMPLETE          0x80000000
2134         u32                             tg3_flags2;
2135 #define TG3_FLG2_RESTART_TIMER          0x00000001
2136 #define TG3_FLG2_SUN_570X               0x00000002
2137 #define TG3_FLG2_NO_ETH_WIRE_SPEED      0x00000004
2138 #define TG3_FLG2_IS_5788                0x00000008
2139 #define TG3_FLG2_MAX_RXPEND_64          0x00000010
2140 #define TG3_FLG2_TSO_CAPABLE            0x00000020
2141 #define TG3_FLG2_PHY_ADC_BUG            0x00000040
2142 #define TG3_FLG2_PHY_5704_A0_BUG        0x00000080
2143 #define TG3_FLG2_PHY_BER_BUG            0x00000100
2144 #define TG3_FLG2_PCI_EXPRESS            0x00000200
2145 #define TG3_FLG2_ASF_NEW_HANDSHAKE      0x00000400
2146 #define TG3_FLG2_HW_AUTONEG             0x00000800
2147 #define TG3_FLG2_PHY_JUST_INITTED       0x00001000
2148 #define TG3_FLG2_PHY_SERDES             0x00002000
2149 #define TG3_FLG2_CAPACITIVE_COUPLING    0x00004000
2150 #define TG3_FLG2_FLASH                  0x00008000
2151 #define TG3_FLG2_HW_TSO                 0x00010000
2152 #define TG3_FLG2_SERDES_PREEMPHASIS     0x00020000
2153 #define TG3_FLG2_5705_PLUS              0x00040000
2154 #define TG3_FLG2_5750_PLUS              0x00080000
2155 #define TG3_FLG2_PROTECTED_NVRAM        0x00100000
2156 #define TG3_FLG2_USING_MSI              0x00200000
2157
2158         u32                             split_mode_max_reqs;
2159 #define SPLIT_MODE_5704_MAX_REQ         3
2160
2161         struct timer_list               timer;
2162         u16                             timer_counter;
2163         u16                             timer_multiplier;
2164         u32                             timer_offset;
2165         u16                             asf_counter;
2166         u16                             asf_multiplier;
2167
2168         struct tg3_link_config          link_config;
2169         struct tg3_bufmgr_config        bufmgr_config;
2170
2171         /* cache h/w values, often passed straight to h/w */
2172         u32                             rx_mode;
2173         u32                             tx_mode;
2174         u32                             mac_mode;
2175         u32                             mi_mode;
2176         u32                             misc_host_ctrl;
2177         u32                             grc_mode;
2178         u32                             grc_local_ctrl;
2179         u32                             dma_rwctrl;
2180         u32                             coalesce_mode;
2181
2182         /* PCI block */
2183         u16                             pci_chip_rev_id;
2184         u8                              pci_cacheline_sz;
2185         u8                              pci_lat_timer;
2186         u8                              pci_hdr_type;
2187         u8                              pci_bist;
2188
2189         int                             pm_cap;
2190
2191         /* PHY info */
2192         u32                             phy_id;
2193 #define PHY_ID_MASK                     0xfffffff0
2194 #define PHY_ID_BCM5400                  0x60008040
2195 #define PHY_ID_BCM5401                  0x60008050
2196 #define PHY_ID_BCM5411                  0x60008070
2197 #define PHY_ID_BCM5701                  0x60008110
2198 #define PHY_ID_BCM5703                  0x60008160
2199 #define PHY_ID_BCM5704                  0x60008190
2200 #define PHY_ID_BCM5705                  0x600081a0
2201 #define PHY_ID_BCM5750                  0x60008180
2202 #define PHY_ID_BCM5752                  0x60008100
2203 #define PHY_ID_BCM8002                  0x60010140
2204 #define PHY_ID_INVALID                  0xffffffff
2205 #define PHY_ID_REV_MASK                 0x0000000f
2206 #define PHY_REV_BCM5401_B0              0x1
2207 #define PHY_REV_BCM5401_B2              0x3
2208 #define PHY_REV_BCM5401_C0              0x6
2209 #define PHY_REV_BCM5411_X0              0x1 /* Found on Netgear GA302T */
2210
2211         u32                             led_ctrl;
2212
2213         char                            board_part_number[24];
2214         u32                             nic_sram_data_cfg;
2215         u32                             pci_clock_ctrl;
2216         struct pci_dev                  *pdev_peer;
2217
2218         /* This macro assumes the passed PHY ID is already masked
2219          * with PHY_ID_MASK.
2220          */
2221 #define KNOWN_PHY_ID(X)         \
2222         ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
2223          (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
2224          (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
2225          (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
2226          (X) == PHY_ID_BCM8002)
2227
2228         struct tg3_hw_stats             *hw_stats;
2229         dma_addr_t                      stats_mapping;
2230         struct work_struct              reset_task;
2231
2232         u32                             nvram_size;
2233         u32                             nvram_pagesize;
2234         u32                             nvram_jedecnum;
2235
2236 #define JEDEC_ATMEL                     0x1f
2237 #define JEDEC_ST                        0x20
2238 #define JEDEC_SAIFUN                    0x4f
2239 #define JEDEC_SST                       0xbf
2240
2241 #define ATMEL_AT24C64_CHIP_SIZE         (64 * 1024)
2242 #define ATMEL_AT24C64_PAGE_SIZE         (32)
2243
2244 #define ATMEL_AT24C512_CHIP_SIZE        (512 * 1024)
2245 #define ATMEL_AT24C512_PAGE_SIZE        (128)
2246
2247 #define ATMEL_AT45DB0X1B_PAGE_POS       9
2248 #define ATMEL_AT45DB0X1B_PAGE_SIZE      264
2249
2250 #define ATMEL_AT25F512_PAGE_SIZE        256
2251
2252 #define ST_M45PEX0_PAGE_SIZE            256
2253
2254 #define SAIFUN_SA25F0XX_PAGE_SIZE       256
2255
2256 #define SST_25VF0X0_PAGE_SIZE           4098
2257
2258         struct ethtool_coalesce         coal;
2259 };
2260
2261 #endif /* !(_T3_H) */