drivers/net/s2io.c

   1 /************************************************************************
   2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2005 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  *
  13  * Credits:
  14  * Jeff Garzik          : For pointing out the improper error condition
  15  *                        check in the s2io_xmit routine and also some
  16  *                        issues in the Tx watch dog function. Also for
  17  *                        patiently answering all those innumerable
  18  *                        questions regaring the 2.6 porting issues.
  19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
  20  *                        macros available only in 2.6 Kernel.
  21  * Francois Romieu      : For pointing out all code part that were
  22  *                        deprecated and also styling related comments.
  23  * Grant Grundler       : For helping me get rid of some Architecture
  24  *                        dependent code.
  25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
  26  *
  27  * The module loadable parameters that are supported by the driver and a brief
  28  * explaination of all the variables.
  29  *
  30  * rx_ring_num : This can be used to program the number of receive rings used
  31  * in the driver.
  32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
  33  *     This is also an array of size 8.
  34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  35  *              values are 1, 2 and 3.
  36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
  38  * Tx descriptors that can be associated with each corresponding FIFO.
  39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
  40  *     1(MSI), 2(MSI_X). Default value is '0(INTA)'
  41  * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
  42  *     Possible values '1' for enable '0' for disable. Default is '0'
  43  * lro_max_pkts: This parameter defines maximum number of packets can be
  44  *     aggregated as a single large packet
  45  ************************************************************************/
  46
  47 #include <linux/module.h>
  48 #include <linux/types.h>
  49 #include <linux/errno.h>
  50 #include <linux/ioport.h>
  51 #include <linux/pci.h>
  52 #include <linux/dma-mapping.h>
  53 #include <linux/kernel.h>
  54 #include <linux/netdevice.h>
  55 #include <linux/etherdevice.h>
  56 #include <linux/skbuff.h>
  57 #include <linux/init.h>
  58 #include <linux/delay.h>
  59 #include <linux/stddef.h>
  60 #include <linux/ioctl.h>
  61 #include <linux/timex.h>
  62 #include <linux/ethtool.h>
  63 #include <linux/workqueue.h>
  64 #include <linux/if_vlan.h>
  65 #include <linux/ip.h>
  66 #include <linux/tcp.h>
  67 #include <net/tcp.h>
  68
  69 #include <asm/system.h>
  70 #include <asm/uaccess.h>
  71 #include <asm/io.h>
  72 #include <asm/div64.h>
  73 #include <asm/irq.h>
  74
  75 /* local include */
  76 #include "s2io.h"
  77 #include "s2io-regs.h"
  78
  79 #define DRV_VERSION "2.0.16.1"
  80
  81 /* S2io Driver name & version. */
  82 static char s2io_driver_name[] = "Neterion";
  83 static char s2io_driver_version[] = DRV_VERSION;
  84
  85 static int rxd_size[4] = {32,48,48,64};
  86 static int rxd_count[4] = {127,85,85,63};
  87
  88 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
  89 {
  90         int ret;
  91
  92         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
  93                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
  94
  95         return ret;
  96 }
  97
  98 /*
  99  * Cards with following subsystem_id have a link state indication
 100  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
 101  * macro below identifies these cards given the subsystem_id.
 102  */
 103 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
 104         (dev_type == XFRAME_I_DEVICE) ?                 \
 105                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
 106                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
 107
 108 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
 109                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
 110 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
 111 #define PANIC   1
 112 #define LOW     2
 113 static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
 114 {
 115         struct mac_info *mac_control;
 116
 117         mac_control = &sp->mac_control;
 118         if (rxb_size <= rxd_count[sp->rxd_mode])
 119                 return PANIC;
 120         else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
 121                 return  LOW;
 122         return 0;
 123 }
 124
 125 /* Ethtool related variables and Macros. */
 126 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
 127         "Register test\t(offline)",
 128         "Eeprom test\t(offline)",
 129         "Link test\t(online)",
 130         "RLDRAM test\t(offline)",
 131         "BIST Test\t(offline)"
 132 };
 133
 134 static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
 135         {"tmac_frms"},
 136         {"tmac_data_octets"},
 137         {"tmac_drop_frms"},
 138         {"tmac_mcst_frms"},
 139         {"tmac_bcst_frms"},
 140         {"tmac_pause_ctrl_frms"},
 141         {"tmac_ttl_octets"},
 142         {"tmac_ucst_frms"},
 143         {"tmac_nucst_frms"},
 144         {"tmac_any_err_frms"},
 145         {"tmac_ttl_less_fb_octets"},
 146         {"tmac_vld_ip_octets"},
 147         {"tmac_vld_ip"},
 148         {"tmac_drop_ip"},
 149         {"tmac_icmp"},
 150         {"tmac_rst_tcp"},
 151         {"tmac_tcp"},
 152         {"tmac_udp"},
 153         {"rmac_vld_frms"},
 154         {"rmac_data_octets"},
 155         {"rmac_fcs_err_frms"},
 156         {"rmac_drop_frms"},
 157         {"rmac_vld_mcst_frms"},
 158         {"rmac_vld_bcst_frms"},
 159         {"rmac_in_rng_len_err_frms"},
 160         {"rmac_out_rng_len_err_frms"},
 161         {"rmac_long_frms"},
 162         {"rmac_pause_ctrl_frms"},
 163         {"rmac_unsup_ctrl_frms"},
 164         {"rmac_ttl_octets"},
 165         {"rmac_accepted_ucst_frms"},
 166         {"rmac_accepted_nucst_frms"},
 167         {"rmac_discarded_frms"},
 168         {"rmac_drop_events"},
 169         {"rmac_ttl_less_fb_octets"},
 170         {"rmac_ttl_frms"},
 171         {"rmac_usized_frms"},
 172         {"rmac_osized_frms"},
 173         {"rmac_frag_frms"},
 174         {"rmac_jabber_frms"},
 175         {"rmac_ttl_64_frms"},
 176         {"rmac_ttl_65_127_frms"},
 177         {"rmac_ttl_128_255_frms"},
 178         {"rmac_ttl_256_511_frms"},
 179         {"rmac_ttl_512_1023_frms"},
 180         {"rmac_ttl_1024_1518_frms"},
 181         {"rmac_ip"},
 182         {"rmac_ip_octets"},
 183         {"rmac_hdr_err_ip"},
 184         {"rmac_drop_ip"},
 185         {"rmac_icmp"},
 186         {"rmac_tcp"},
 187         {"rmac_udp"},
 188         {"rmac_err_drp_udp"},
 189         {"rmac_xgmii_err_sym"},
 190         {"rmac_frms_q0"},
 191         {"rmac_frms_q1"},
 192         {"rmac_frms_q2"},
 193         {"rmac_frms_q3"},
 194         {"rmac_frms_q4"},
 195         {"rmac_frms_q5"},
 196         {"rmac_frms_q6"},
 197         {"rmac_frms_q7"},
 198         {"rmac_full_q0"},
 199         {"rmac_full_q1"},
 200         {"rmac_full_q2"},
 201         {"rmac_full_q3"},
 202         {"rmac_full_q4"},
 203         {"rmac_full_q5"},
 204         {"rmac_full_q6"},
 205         {"rmac_full_q7"},
 206         {"rmac_pause_cnt"},
 207         {"rmac_xgmii_data_err_cnt"},
 208         {"rmac_xgmii_ctrl_err_cnt"},
 209         {"rmac_accepted_ip"},
 210         {"rmac_err_tcp"},
 211         {"rd_req_cnt"},
 212         {"new_rd_req_cnt"},
 213         {"new_rd_req_rtry_cnt"},
 214         {"rd_rtry_cnt"},
 215         {"wr_rtry_rd_ack_cnt"},
 216         {"wr_req_cnt"},
 217         {"new_wr_req_cnt"},
 218         {"new_wr_req_rtry_cnt"},
 219         {"wr_rtry_cnt"},
 220         {"wr_disc_cnt"},
 221         {"rd_rtry_wr_ack_cnt"},
 222         {"txp_wr_cnt"},
 223         {"txd_rd_cnt"},
 224         {"txd_wr_cnt"},
 225         {"rxd_rd_cnt"},
 226         {"rxd_wr_cnt"},
 227         {"txf_rd_cnt"},
 228         {"rxf_wr_cnt"},
 229         {"rmac_ttl_1519_4095_frms"},
 230         {"rmac_ttl_4096_8191_frms"},
 231         {"rmac_ttl_8192_max_frms"},
 232         {"rmac_ttl_gt_max_frms"},
 233         {"rmac_osized_alt_frms"},
 234         {"rmac_jabber_alt_frms"},
 235         {"rmac_gt_max_alt_frms"},
 236         {"rmac_vlan_frms"},
 237         {"rmac_len_discard"},
 238         {"rmac_fcs_discard"},
 239         {"rmac_pf_discard"},
 240         {"rmac_da_discard"},
 241         {"rmac_red_discard"},
 242         {"rmac_rts_discard"},
 243         {"rmac_ingm_full_discard"},
 244         {"link_fault_cnt"},
 245         {"\n DRIVER STATISTICS"},
 246         {"single_bit_ecc_errs"},
 247         {"double_bit_ecc_errs"},
 248         {"parity_err_cnt"},
 249         {"serious_err_cnt"},
 250         {"soft_reset_cnt"},
 251         {"fifo_full_cnt"},
 252         {"ring_full_cnt"},
 253         ("alarm_transceiver_temp_high"),
 254         ("alarm_transceiver_temp_low"),
 255         ("alarm_laser_bias_current_high"),
 256         ("alarm_laser_bias_current_low"),
 257         ("alarm_laser_output_power_high"),
 258         ("alarm_laser_output_power_low"),
 259         ("warn_transceiver_temp_high"),
 260         ("warn_transceiver_temp_low"),
 261         ("warn_laser_bias_current_high"),
 262         ("warn_laser_bias_current_low"),
 263         ("warn_laser_output_power_high"),
 264         ("warn_laser_output_power_low"),
 265         ("lro_aggregated_pkts"),
 266         ("lro_flush_both_count"),
 267         ("lro_out_of_sequence_pkts"),
 268         ("lro_flush_due_to_max_pkts"),
 269         ("lro_avg_aggr_pkts"),
 270 };
 271
 272 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
 273 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
 274
 275 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
 276 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
 277
 278 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
 279                         init_timer(&timer);                     \
 280                         timer.function = handle;                \
 281                         timer.data = (unsigned long) arg;       \
 282                         mod_timer(&timer, (jiffies + exp))      \
 283
 284 /* Add the vlan */
 285 static void s2io_vlan_rx_register(struct net_device *dev,
 286                                         struct vlan_group *grp)
 287 {
 288         struct s2io_nic *nic = dev->priv;
 289         unsigned long flags;
 290
 291         spin_lock_irqsave(&nic->tx_lock, flags);
 292         nic->vlgrp = grp;
 293         spin_unlock_irqrestore(&nic->tx_lock, flags);
 294 }
 295
 296 /* Unregister the vlan */
 297 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
 298 {
 299         struct s2io_nic *nic = dev->priv;
 300         unsigned long flags;
 301
 302         spin_lock_irqsave(&nic->tx_lock, flags);
 303         if (nic->vlgrp)
 304                 nic->vlgrp->vlan_devices[vid] = NULL;
 305         spin_unlock_irqrestore(&nic->tx_lock, flags);
 306 }
 307
 308 /*
 309  * Constants to be programmed into the Xena's registers, to configure
 310  * the XAUI.
 311  */
 312
 313 #define END_SIGN        0x0
 314 static const u64 herc_act_dtx_cfg[] = {
 315         /* Set address */
 316         0x8000051536750000ULL, 0x80000515367500E0ULL,
 317         /* Write data */
 318         0x8000051536750004ULL, 0x80000515367500E4ULL,
 319         /* Set address */
 320         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
 321         /* Write data */
 322         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
 323         /* Set address */
 324         0x801205150D440000ULL, 0x801205150D4400E0ULL,
 325         /* Write data */
 326         0x801205150D440004ULL, 0x801205150D4400E4ULL,
 327         /* Set address */
 328         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
 329         /* Write data */
 330         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 331         /* Done */
 332         END_SIGN
 333 };
 334
 335 static const u64 xena_dtx_cfg[] = {
 336         /* Set address */
 337         0x8000051500000000ULL, 0x80000515000000E0ULL,
 338         /* Write data */
 339         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
 340         /* Set address */
 341         0x8001051500000000ULL, 0x80010515000000E0ULL,
 342         /* Write data */
 343         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
 344         /* Set address */
 345         0x8002051500000000ULL, 0x80020515000000E0ULL,
 346         /* Write data */
 347         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 348         END_SIGN
 349 };
 350
 351 /*
 352  * Constants for Fixing the MacAddress problem seen mostly on
 353  * Alpha machines.
 354  */
 355 static const u64 fix_mac[] = {
 356         0x0060000000000000ULL, 0x0060600000000000ULL,
 357         0x0040600000000000ULL, 0x0000600000000000ULL,
 358         0x0020600000000000ULL, 0x0060600000000000ULL,
 359         0x0020600000000000ULL, 0x0060600000000000ULL,
 360         0x0020600000000000ULL, 0x0060600000000000ULL,
 361         0x0020600000000000ULL, 0x0060600000000000ULL,
 362         0x0020600000000000ULL, 0x0060600000000000ULL,
 363         0x0020600000000000ULL, 0x0060600000000000ULL,
 364         0x0020600000000000ULL, 0x0060600000000000ULL,
 365         0x0020600000000000ULL, 0x0060600000000000ULL,
 366         0x0020600000000000ULL, 0x0060600000000000ULL,
 367         0x0020600000000000ULL, 0x0060600000000000ULL,
 368         0x0020600000000000ULL, 0x0000600000000000ULL,
 369         0x0040600000000000ULL, 0x0060600000000000ULL,
 370         END_SIGN
 371 };
 372
 373 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
 374 MODULE_LICENSE("GPL");
 375 MODULE_VERSION(DRV_VERSION);
 376
 377
 378 /* Module Loadable parameters. */
 379 S2IO_PARM_INT(tx_fifo_num, 1);
 380 S2IO_PARM_INT(rx_ring_num, 1);
 381
 382
 383 S2IO_PARM_INT(rx_ring_mode, 1);
 384 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
 385 S2IO_PARM_INT(rmac_pause_time, 0x100);
 386 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
 387 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
 388 S2IO_PARM_INT(shared_splits, 0);
 389 S2IO_PARM_INT(tmac_util_period, 5);
 390 S2IO_PARM_INT(rmac_util_period, 5);
 391 S2IO_PARM_INT(bimodal, 0);
 392 S2IO_PARM_INT(l3l4hdr_size, 128);
 393 /* Frequency of Rx desc syncs expressed as power of 2 */
 394 S2IO_PARM_INT(rxsync_frequency, 3);
 395 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
 396 S2IO_PARM_INT(intr_type, 0);
 397 /* Large receive offload feature */
 398 S2IO_PARM_INT(lro, 0);
 399 /* Max pkts to be aggregated by LRO at one time. If not specified,
 400  * aggregation happens until we hit max IP pkt size(64K)
 401  */
 402 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
 403 S2IO_PARM_INT(indicate_max_pkts, 0);
 404
 405 S2IO_PARM_INT(napi, 1);
 406 S2IO_PARM_INT(ufo, 0);
 407
 408 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
 409     {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
 410 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
 411     {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
 412 static unsigned int rts_frm_len[MAX_RX_RINGS] =
 413     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 414
 415 module_param_array(tx_fifo_len, uint, NULL, 0);
 416 module_param_array(rx_ring_sz, uint, NULL, 0);
 417 module_param_array(rts_frm_len, uint, NULL, 0);
 418
 419 /*
 420  * S2IO device table.
 421  * This table lists all the devices that this driver supports.
 422  */
 423 static struct pci_device_id s2io_tbl[] __devinitdata = {
 424         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
 425          PCI_ANY_ID, PCI_ANY_ID},
 426         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
 427          PCI_ANY_ID, PCI_ANY_ID},
 428         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
 429          PCI_ANY_ID, PCI_ANY_ID},
 430         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
 431          PCI_ANY_ID, PCI_ANY_ID},
 432         {0,}
 433 };
 434
 435 MODULE_DEVICE_TABLE(pci, s2io_tbl);
 436
 437 static struct pci_driver s2io_driver = {
 438       .name = "S2IO",
 439       .id_table = s2io_tbl,
 440       .probe = s2io_init_nic,
 441       .remove = __devexit_p(s2io_rem_nic),
 442 };
 443
 444 /* A simplifier macro used both by init and free shared_mem Fns(). */
 445 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
 446
 447 /**
 448  * init_shared_mem - Allocation and Initialization of Memory
 449  * @nic: Device private variable.
 450  * Description: The function allocates all the memory areas shared
 451  * between the NIC and the driver. This includes Tx descriptors,
 452  * Rx descriptors and the statistics block.
 453  */
 454
 455 static int init_shared_mem(struct s2io_nic *nic)
 456 {
 457         u32 size;
 458         void *tmp_v_addr, *tmp_v_addr_next;
 459         dma_addr_t tmp_p_addr, tmp_p_addr_next;
 460         struct RxD_block *pre_rxd_blk = NULL;
 461         int i, j, blk_cnt;
 462         int lst_size, lst_per_page;
 463         struct net_device *dev = nic->dev;
 464         unsigned long tmp;
 465         struct buffAdd *ba;
 466
 467         struct mac_info *mac_control;
 468         struct config_param *config;
 469
 470         mac_control = &nic->mac_control;
 471         config = &nic->config;
 472
 473
 474         /* Allocation and initialization of TXDLs in FIOFs */
 475         size = 0;
 476         for (i = 0; i < config->tx_fifo_num; i++) {
 477                 size += config->tx_cfg[i].fifo_len;
 478         }
 479         if (size > MAX_AVAILABLE_TXDS) {
 480                 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
 481                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
 482                 return -EINVAL;
 483         }
 484
 485         lst_size = (sizeof(struct TxD) * config->max_txds);
 486         lst_per_page = PAGE_SIZE / lst_size;
 487
 488         for (i = 0; i < config->tx_fifo_num; i++) {
 489                 int fifo_len = config->tx_cfg[i].fifo_len;
 490                 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
 491                 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
 492                                                           GFP_KERNEL);
 493                 if (!mac_control->fifos[i].list_info) {
 494                         DBG_PRINT(ERR_DBG,
 495                                   "Malloc failed for list_info\n");
 496                         return -ENOMEM;
 497                 }
 498                 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
 499         }
 500         for (i = 0; i < config->tx_fifo_num; i++) {
 501                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 502                                                 lst_per_page);
 503                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
 504                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
 505                     config->tx_cfg[i].fifo_len - 1;
 506                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
 507                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
 508                     config->tx_cfg[i].fifo_len - 1;
 509                 mac_control->fifos[i].fifo_no = i;
 510                 mac_control->fifos[i].nic = nic;
 511                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
 512
 513                 for (j = 0; j < page_num; j++) {
 514                         int k = 0;
 515                         dma_addr_t tmp_p;
 516                         void *tmp_v;
 517                         tmp_v = pci_alloc_consistent(nic->pdev,
 518                                                      PAGE_SIZE, &tmp_p);
 519                         if (!tmp_v) {
 520                                 DBG_PRINT(ERR_DBG,
 521                                           "pci_alloc_consistent ");
 522                                 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
 523                                 return -ENOMEM;
 524                         }
 525                         /* If we got a zero DMA address(can happen on
 526                          * certain platforms like PPC), reallocate.
 527                          * Store virtual address of page we don't want,
 528                          * to be freed later.
 529                          */
 530                         if (!tmp_p) {
 531                                 mac_control->zerodma_virt_addr = tmp_v;
 532                                 DBG_PRINT(INIT_DBG,
 533                                 "%s: Zero DMA address for TxDL. ", dev->name);
 534                                 DBG_PRINT(INIT_DBG,
 535                                 "Virtual address %p\n", tmp_v);
 536                                 tmp_v = pci_alloc_consistent(nic->pdev,
 537                                                      PAGE_SIZE, &tmp_p);
 538                                 if (!tmp_v) {
 539                                         DBG_PRINT(ERR_DBG,
 540                                           "pci_alloc_consistent ");
 541                                         DBG_PRINT(ERR_DBG, "failed for TxDL\n");
 542                                         return -ENOMEM;
 543                                 }
 544                         }
 545                         while (k < lst_per_page) {
 546                                 int l = (j * lst_per_page) + k;
 547                                 if (l == config->tx_cfg[i].fifo_len)
 548                                         break;
 549                                 mac_control->fifos[i].list_info[l].list_virt_addr =
 550                                     tmp_v + (k * lst_size);
 551                                 mac_control->fifos[i].list_info[l].list_phy_addr =
 552                                     tmp_p + (k * lst_size);
 553                                 k++;
 554                         }
 555                 }
 556         }
 557
 558         nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
 559         if (!nic->ufo_in_band_v)
 560                 return -ENOMEM;
 561
 562         /* Allocation and initialization of RXDs in Rings */
 563         size = 0;
 564         for (i = 0; i < config->rx_ring_num; i++) {
 565                 if (config->rx_cfg[i].num_rxd %
 566                     (rxd_count[nic->rxd_mode] + 1)) {
 567                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
 568                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
 569                                   i);
 570                         DBG_PRINT(ERR_DBG, "RxDs per Block");
 571                         return FAILURE;
 572                 }
 573                 size += config->rx_cfg[i].num_rxd;
 574                 mac_control->rings[i].block_count =
 575                         config->rx_cfg[i].num_rxd /
 576                         (rxd_count[nic->rxd_mode] + 1 );
 577                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
 578                         mac_control->rings[i].block_count;
 579         }
 580         if (nic->rxd_mode == RXD_MODE_1)
 581                 size = (size * (sizeof(struct RxD1)));
 582         else
 583                 size = (size * (sizeof(struct RxD3)));
 584
 585         for (i = 0; i < config->rx_ring_num; i++) {
 586                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
 587                 mac_control->rings[i].rx_curr_get_info.offset = 0;
 588                 mac_control->rings[i].rx_curr_get_info.ring_len =
 589                     config->rx_cfg[i].num_rxd - 1;
 590                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
 591                 mac_control->rings[i].rx_curr_put_info.offset = 0;
 592                 mac_control->rings[i].rx_curr_put_info.ring_len =
 593                     config->rx_cfg[i].num_rxd - 1;
 594                 mac_control->rings[i].nic = nic;
 595                 mac_control->rings[i].ring_no = i;
 596
 597                 blk_cnt = config->rx_cfg[i].num_rxd /
 598                                 (rxd_count[nic->rxd_mode] + 1);
 599                 /*  Allocating all the Rx blocks */
 600                 for (j = 0; j < blk_cnt; j++) {
 601                         struct rx_block_info *rx_blocks;
 602                         int l;
 603
 604                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
 605                         size = SIZE_OF_BLOCK; //size is always page size
 606                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
 607                                                           &tmp_p_addr);
 608                         if (tmp_v_addr == NULL) {
 609                                 /*
 610                                  * In case of failure, free_shared_mem()
 611                                  * is called, which should free any
 612                                  * memory that was alloced till the
 613                                  * failure happened.
 614                                  */
 615                                 rx_blocks->block_virt_addr = tmp_v_addr;
 616                                 return -ENOMEM;
 617                         }
 618                         memset(tmp_v_addr, 0, size);
 619                         rx_blocks->block_virt_addr = tmp_v_addr;
 620                         rx_blocks->block_dma_addr = tmp_p_addr;
 621                         rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
 622                                                   rxd_count[nic->rxd_mode],
 623                                                   GFP_KERNEL);
 624                         if (!rx_blocks->rxds)
 625                                 return -ENOMEM;
 626                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
 627                                 rx_blocks->rxds[l].virt_addr =
 628                                         rx_blocks->block_virt_addr +
 629                                         (rxd_size[nic->rxd_mode] * l);
 630                                 rx_blocks->rxds[l].dma_addr =
 631                                         rx_blocks->block_dma_addr +
 632                                         (rxd_size[nic->rxd_mode] * l);
 633                         }
 634                 }
 635                 /* Interlinking all Rx Blocks */
 636                 for (j = 0; j < blk_cnt; j++) {
 637                         tmp_v_addr =
 638                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
 639                         tmp_v_addr_next =
 640                                 mac_control->rings[i].rx_blocks[(j + 1) %
 641                                               blk_cnt].block_virt_addr;
 642                         tmp_p_addr =
 643                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
 644                         tmp_p_addr_next =
 645                                 mac_control->rings[i].rx_blocks[(j + 1) %
 646                                               blk_cnt].block_dma_addr;
 647
 648                         pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
 649                         pre_rxd_blk->reserved_2_pNext_RxD_block =
 650                             (unsigned long) tmp_v_addr_next;
 651                         pre_rxd_blk->pNext_RxD_Blk_physical =
 652                             (u64) tmp_p_addr_next;
 653                 }
 654         }
 655         if (nic->rxd_mode >= RXD_MODE_3A) {
 656                 /*
 657                  * Allocation of Storages for buffer addresses in 2BUFF mode
 658                  * and the buffers as well.
 659                  */
 660                 for (i = 0; i < config->rx_ring_num; i++) {
 661                         blk_cnt = config->rx_cfg[i].num_rxd /
 662                            (rxd_count[nic->rxd_mode]+ 1);
 663                         mac_control->rings[i].ba =
 664                                 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
 665                                      GFP_KERNEL);
 666                         if (!mac_control->rings[i].ba)
 667                                 return -ENOMEM;
 668                         for (j = 0; j < blk_cnt; j++) {
 669                                 int k = 0;
 670                                 mac_control->rings[i].ba[j] =
 671                                         kmalloc((sizeof(struct buffAdd) *
 672                                                 (rxd_count[nic->rxd_mode] + 1)),
 673                                                 GFP_KERNEL);
 674                                 if (!mac_control->rings[i].ba[j])
 675                                         return -ENOMEM;
 676                                 while (k != rxd_count[nic->rxd_mode]) {
 677                                         ba = &mac_control->rings[i].ba[j][k];
 678
 679                                         ba->ba_0_org = (void *) kmalloc
 680                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
 681                                         if (!ba->ba_0_org)
 682                                                 return -ENOMEM;
 683                                         tmp = (unsigned long)ba->ba_0_org;
 684                                         tmp += ALIGN_SIZE;
 685                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 686                                         ba->ba_0 = (void *) tmp;
 687
 688                                         ba->ba_1_org = (void *) kmalloc
 689                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
 690                                         if (!ba->ba_1_org)
 691                                                 return -ENOMEM;
 692                                         tmp = (unsigned long) ba->ba_1_org;
 693                                         tmp += ALIGN_SIZE;
 694                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 695                                         ba->ba_1 = (void *) tmp;
 696                                         k++;
 697                                 }
 698                         }
 699                 }
 700         }
 701
 702         /* Allocation and initialization of Statistics block */
 703         size = sizeof(struct stat_block);
 704         mac_control->stats_mem = pci_alloc_consistent
 705             (nic->pdev, size, &mac_control->stats_mem_phy);
 706
 707         if (!mac_control->stats_mem) {
 708                 /*
 709                  * In case of failure, free_shared_mem() is called, which
 710                  * should free any memory that was alloced till the
 711                  * failure happened.
 712                  */
 713                 return -ENOMEM;
 714         }
 715         mac_control->stats_mem_sz = size;
 716
 717         tmp_v_addr = mac_control->stats_mem;
 718         mac_control->stats_info = (struct stat_block *) tmp_v_addr;
 719         memset(tmp_v_addr, 0, size);
 720         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
 721                   (unsigned long long) tmp_p_addr);
 722
 723         return SUCCESS;
 724 }
 725
 726 /**
 727  * free_shared_mem - Free the allocated Memory
 728  * @nic:  Device private variable.
 729  * Description: This function is to free all memory locations allocated by
 730  * the init_shared_mem() function and return it to the kernel.
 731  */
 732
 733 static void free_shared_mem(struct s2io_nic *nic)
 734 {
 735         int i, j, blk_cnt, size;
 736         void *tmp_v_addr;
 737         dma_addr_t tmp_p_addr;
 738         struct mac_info *mac_control;
 739         struct config_param *config;
 740         int lst_size, lst_per_page;
 741         struct net_device *dev = nic->dev;
 742
 743         if (!nic)
 744                 return;
 745
 746         mac_control = &nic->mac_control;
 747         config = &nic->config;
 748
 749         lst_size = (sizeof(struct TxD) * config->max_txds);
 750         lst_per_page = PAGE_SIZE / lst_size;
 751
 752         for (i = 0; i < config->tx_fifo_num; i++) {
 753                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 754                                                 lst_per_page);
 755                 for (j = 0; j < page_num; j++) {
 756                         int mem_blks = (j * lst_per_page);
 757                         if (!mac_control->fifos[i].list_info)
 758                                 return;
 759                         if (!mac_control->fifos[i].list_info[mem_blks].
 760                                  list_virt_addr)
 761                                 break;
 762                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 763                                             mac_control->fifos[i].
 764                                             list_info[mem_blks].
 765                                             list_virt_addr,
 766                                             mac_control->fifos[i].
 767                                             list_info[mem_blks].
 768                                             list_phy_addr);
 769                 }
 770                 /* If we got a zero DMA address during allocation,
 771                  * free the page now
 772                  */
 773                 if (mac_control->zerodma_virt_addr) {
 774                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 775                                             mac_control->zerodma_virt_addr,
 776                                             (dma_addr_t)0);
 777                         DBG_PRINT(INIT_DBG,
 778                                 "%s: Freeing TxDL with zero DMA addr. ",
 779                                 dev->name);
 780                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
 781                                 mac_control->zerodma_virt_addr);
 782                 }
 783                 kfree(mac_control->fifos[i].list_info);
 784         }
 785
 786         size = SIZE_OF_BLOCK;
 787         for (i = 0; i < config->rx_ring_num; i++) {
 788                 blk_cnt = mac_control->rings[i].block_count;
 789                 for (j = 0; j < blk_cnt; j++) {
 790                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
 791                                 block_virt_addr;
 792                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
 793                                 block_dma_addr;
 794                         if (tmp_v_addr == NULL)
 795                                 break;
 796                         pci_free_consistent(nic->pdev, size,
 797                                             tmp_v_addr, tmp_p_addr);
 798                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
 799                 }
 800         }
 801
 802         if (nic->rxd_mode >= RXD_MODE_3A) {
 803                 /* Freeing buffer storage addresses in 2BUFF mode. */
 804                 for (i = 0; i < config->rx_ring_num; i++) {
 805                         blk_cnt = config->rx_cfg[i].num_rxd /
 806                             (rxd_count[nic->rxd_mode] + 1);
 807                         for (j = 0; j < blk_cnt; j++) {
 808                                 int k = 0;
 809                                 if (!mac_control->rings[i].ba[j])
 810                                         continue;
 811                                 while (k != rxd_count[nic->rxd_mode]) {
 812                                         struct buffAdd *ba =
 813                                                 &mac_control->rings[i].ba[j][k];
 814                                         kfree(ba->ba_0_org);
 815                                         kfree(ba->ba_1_org);
 816                                         k++;
 817                                 }
 818                                 kfree(mac_control->rings[i].ba[j]);
 819                         }
 820                         kfree(mac_control->rings[i].ba);
 821                 }
 822         }
 823
 824         if (mac_control->stats_mem) {
 825                 pci_free_consistent(nic->pdev,
 826                                     mac_control->stats_mem_sz,
 827                                     mac_control->stats_mem,
 828                                     mac_control->stats_mem_phy);
 829         }
 830         if (nic->ufo_in_band_v)
 831                 kfree(nic->ufo_in_band_v);
 832 }
 833
 834 /**
 835  * s2io_verify_pci_mode -
 836  */
 837
 838 static int s2io_verify_pci_mode(struct s2io_nic *nic)
 839 {
 840         struct XENA_dev_config __iomem *bar0 = nic->bar0;
 841         register u64 val64 = 0;
 842         int     mode;
 843
 844         val64 = readq(&bar0->pci_mode);
 845         mode = (u8)GET_PCI_MODE(val64);
 846
 847         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 848                 return -1;      /* Unknown PCI mode */
 849         return mode;
 850 }
 851
 852 #define NEC_VENID   0x1033
 853 #define NEC_DEVID   0x0125
 854 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
 855 {
 856         struct pci_dev *tdev = NULL;
 857         while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
 858                 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
 859                         if (tdev->bus == s2io_pdev->bus->parent)
 860                                 pci_dev_put(tdev);
 861                                 return 1;
 862                 }
 863         }
 864         return 0;
 865 }
 866
 867 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
 868 /**
 869  * s2io_print_pci_mode -
 870  */
 871 static int s2io_print_pci_mode(struct s2io_nic *nic)
 872 {
 873         struct XENA_dev_config __iomem *bar0 = nic->bar0;
 874         register u64 val64 = 0;
 875         int     mode;
 876         struct config_param *config = &nic->config;
 877
 878         val64 = readq(&bar0->pci_mode);
 879         mode = (u8)GET_PCI_MODE(val64);
 880
 881         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 882                 return -1;      /* Unknown PCI mode */
 883
 884         config->bus_speed = bus_speed[mode];
 885
 886         if (s2io_on_nec_bridge(nic->pdev)) {
 887                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
 888                                                         nic->dev->name);
 889                 return mode;
 890         }
 891
 892         if (val64 & PCI_MODE_32_BITS) {
 893                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
 894         } else {
 895                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
 896         }
 897
 898         switch(mode) {
 899                 case PCI_MODE_PCI_33:
 900                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
 901                         break;
 902                 case PCI_MODE_PCI_66:
 903                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
 904                         break;
 905                 case PCI_MODE_PCIX_M1_66:
 906                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
 907                         break;
 908                 case PCI_MODE_PCIX_M1_100:
 909                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
 910                         break;
 911                 case PCI_MODE_PCIX_M1_133:
 912                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
 913                         break;
 914                 case PCI_MODE_PCIX_M2_66:
 915                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
 916                         break;
 917                 case PCI_MODE_PCIX_M2_100:
 918                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
 919                         break;
 920                 case PCI_MODE_PCIX_M2_133:
 921                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
 922                         break;
 923                 default:
 924                         return -1;      /* Unsupported bus speed */
 925         }
 926
 927         return mode;
 928 }
 929
 930 /**
 931  *  init_nic - Initialization of hardware
 932  *  @nic: device peivate variable
 933  *  Description: The function sequentially configures every block
 934  *  of the H/W from their reset values.
 935  *  Return Value:  SUCCESS on success and
 936  *  '-1' on failure (endian settings incorrect).
 937  */
 938
 939 static int init_nic(struct s2io_nic *nic)
 940 {
 941         struct XENA_dev_config __iomem *bar0 = nic->bar0;
 942         struct net_device *dev = nic->dev;
 943         register u64 val64 = 0;
 944         void __iomem *add;
 945         u32 time;
 946         int i, j;
 947         struct mac_info *mac_control;
 948         struct config_param *config;
 949         int dtx_cnt = 0;
 950         unsigned long long mem_share;
 951         int mem_size;
 952
 953         mac_control = &nic->mac_control;
 954         config = &nic->config;
 955
 956         /* to set the swapper controle on the card */
 957         if(s2io_set_swapper(nic)) {
 958                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
 959                 return -1;
 960         }
 961
 962         /*
 963          * Herc requires EOI to be removed from reset before XGXS, so..
 964          */
 965         if (nic->device_type & XFRAME_II_DEVICE) {
 966                 val64 = 0xA500000000ULL;
 967                 writeq(val64, &bar0->sw_reset);
 968                 msleep(500);
 969                 val64 = readq(&bar0->sw_reset);
 970         }
 971
 972         /* Remove XGXS from reset state */
 973         val64 = 0;
 974         writeq(val64, &bar0->sw_reset);
 975         msleep(500);
 976         val64 = readq(&bar0->sw_reset);
 977
 978         /*  Enable Receiving broadcasts */
 979         add = &bar0->mac_cfg;
 980         val64 = readq(&bar0->mac_cfg);
 981         val64 |= MAC_RMAC_BCAST_ENABLE;
 982         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
 983         writel((u32) val64, add);
 984         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
 985         writel((u32) (val64 >> 32), (add + 4));
 986
 987         /* Read registers in all blocks */
 988         val64 = readq(&bar0->mac_int_mask);
 989         val64 = readq(&bar0->mc_int_mask);
 990         val64 = readq(&bar0->xgxs_int_mask);
 991
 992         /*  Set MTU */
 993         val64 = dev->mtu;
 994         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
 995
 996         if (nic->device_type & XFRAME_II_DEVICE) {
 997                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
 998                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
 999                                           &bar0->dtx_control, UF);
1000                         if (dtx_cnt & 0x1)
1001                                 msleep(1); /* Necessary!! */
1002                         dtx_cnt++;
1003                 }
1004         } else {
1005                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1006                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1007                                           &bar0->dtx_control, UF);
1008                         val64 = readq(&bar0->dtx_control);
1009                         dtx_cnt++;
1010                 }
1011         }
1012
1013         /*  Tx DMA Initialization */
1014         val64 = 0;
1015         writeq(val64, &bar0->tx_fifo_partition_0);
1016         writeq(val64, &bar0->tx_fifo_partition_1);
1017         writeq(val64, &bar0->tx_fifo_partition_2);
1018         writeq(val64, &bar0->tx_fifo_partition_3);
1019
1020
1021         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1022                 val64 |=
1023                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1024                          13) | vBIT(config->tx_cfg[i].fifo_priority,
1025                                     ((i * 32) + 5), 3);
1026
1027                 if (i == (config->tx_fifo_num - 1)) {
1028                         if (i % 2 == 0)
1029                                 i++;
1030                 }
1031
1032                 switch (i) {
1033                 case 1:
1034                         writeq(val64, &bar0->tx_fifo_partition_0);
1035                         val64 = 0;
1036                         break;
1037                 case 3:
1038                         writeq(val64, &bar0->tx_fifo_partition_1);
1039                         val64 = 0;
1040                         break;
1041                 case 5:
1042                         writeq(val64, &bar0->tx_fifo_partition_2);
1043                         val64 = 0;
1044                         break;
1045                 case 7:
1046                         writeq(val64, &bar0->tx_fifo_partition_3);
1047                         break;
1048                 }
1049         }
1050
1051         /*
1052          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1053          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1054          */
1055         if ((nic->device_type == XFRAME_I_DEVICE) &&
1056                 (get_xena_rev_id(nic->pdev) < 4))
1057                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1058
1059         val64 = readq(&bar0->tx_fifo_partition_0);
1060         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1061                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1062
1063         /*
1064          * Initialization of Tx_PA_CONFIG register to ignore packet
1065          * integrity checking.
1066          */
1067         val64 = readq(&bar0->tx_pa_cfg);
1068         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1069             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1070         writeq(val64, &bar0->tx_pa_cfg);
1071
1072         /* Rx DMA intialization. */
1073         val64 = 0;
1074         for (i = 0; i < config->rx_ring_num; i++) {
1075                 val64 |=
1076                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1077                          3);
1078         }
1079         writeq(val64, &bar0->rx_queue_priority);
1080
1081         /*
1082          * Allocating equal share of memory to all the
1083          * configured Rings.
1084          */
1085         val64 = 0;
1086         if (nic->device_type & XFRAME_II_DEVICE)
1087                 mem_size = 32;
1088         else
1089                 mem_size = 64;
1090
1091         for (i = 0; i < config->rx_ring_num; i++) {
1092                 switch (i) {
1093                 case 0:
1094                         mem_share = (mem_size / config->rx_ring_num +
1095                                      mem_size % config->rx_ring_num);
1096                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1097                         continue;
1098                 case 1:
1099                         mem_share = (mem_size / config->rx_ring_num);
1100                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1101                         continue;
1102                 case 2:
1103                         mem_share = (mem_size / config->rx_ring_num);
1104                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1105                         continue;
1106                 case 3:
1107                         mem_share = (mem_size / config->rx_ring_num);
1108                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1109                         continue;
1110                 case 4:
1111                         mem_share = (mem_size / config->rx_ring_num);
1112                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1113                         continue;
1114                 case 5:
1115                         mem_share = (mem_size / config->rx_ring_num);
1116                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1117                         continue;
1118                 case 6:
1119                         mem_share = (mem_size / config->rx_ring_num);
1120                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1121                         continue;
1122                 case 7:
1123                         mem_share = (mem_size / config->rx_ring_num);
1124                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1125                         continue;
1126                 }
1127         }
1128         writeq(val64, &bar0->rx_queue_cfg);
1129
1130         /*
1131          * Filling Tx round robin registers
1132          * as per the number of FIFOs
1133          */
1134         switch (config->tx_fifo_num) {
1135         case 1:
1136                 val64 = 0x0000000000000000ULL;
1137                 writeq(val64, &bar0->tx_w_round_robin_0);
1138                 writeq(val64, &bar0->tx_w_round_robin_1);
1139                 writeq(val64, &bar0->tx_w_round_robin_2);
1140                 writeq(val64, &bar0->tx_w_round_robin_3);
1141                 writeq(val64, &bar0->tx_w_round_robin_4);
1142                 break;
1143         case 2:
1144                 val64 = 0x0000010000010000ULL;
1145                 writeq(val64, &bar0->tx_w_round_robin_0);
1146                 val64 = 0x0100000100000100ULL;
1147                 writeq(val64, &bar0->tx_w_round_robin_1);
1148                 val64 = 0x0001000001000001ULL;
1149                 writeq(val64, &bar0->tx_w_round_robin_2);
1150                 val64 = 0x0000010000010000ULL;
1151                 writeq(val64, &bar0->tx_w_round_robin_3);
1152                 val64 = 0x0100000000000000ULL;
1153                 writeq(val64, &bar0->tx_w_round_robin_4);
1154                 break;
1155         case 3:
1156                 val64 = 0x0001000102000001ULL;
1157                 writeq(val64, &bar0->tx_w_round_robin_0);
1158                 val64 = 0x0001020000010001ULL;
1159                 writeq(val64, &bar0->tx_w_round_robin_1);
1160                 val64 = 0x0200000100010200ULL;
1161                 writeq(val64, &bar0->tx_w_round_robin_2);
1162                 val64 = 0x0001000102000001ULL;
1163                 writeq(val64, &bar0->tx_w_round_robin_3);
1164                 val64 = 0x0001020000000000ULL;
1165                 writeq(val64, &bar0->tx_w_round_robin_4);
1166                 break;
1167         case 4:
1168                 val64 = 0x0001020300010200ULL;
1169                 writeq(val64, &bar0->tx_w_round_robin_0);
1170                 val64 = 0x0100000102030001ULL;
1171                 writeq(val64, &bar0->tx_w_round_robin_1);
1172                 val64 = 0x0200010000010203ULL;
1173                 writeq(val64, &bar0->tx_w_round_robin_2);
1174                 val64 = 0x0001020001000001ULL;
1175                 writeq(val64, &bar0->tx_w_round_robin_3);
1176                 val64 = 0x0203000100000000ULL;
1177                 writeq(val64, &bar0->tx_w_round_robin_4);
1178                 break;
1179         case 5:
1180                 val64 = 0x0001000203000102ULL;
1181                 writeq(val64, &bar0->tx_w_round_robin_0);
1182                 val64 = 0x0001020001030004ULL;
1183                 writeq(val64, &bar0->tx_w_round_robin_1);
1184                 val64 = 0x0001000203000102ULL;
1185                 writeq(val64, &bar0->tx_w_round_robin_2);
1186                 val64 = 0x0001020001030004ULL;
1187                 writeq(val64, &bar0->tx_w_round_robin_3);
1188                 val64 = 0x0001000000000000ULL;
1189                 writeq(val64, &bar0->tx_w_round_robin_4);
1190                 break;
1191         case 6:
1192                 val64 = 0x0001020304000102ULL;
1193                 writeq(val64, &bar0->tx_w_round_robin_0);
1194                 val64 = 0x0304050001020001ULL;
1195                 writeq(val64, &bar0->tx_w_round_robin_1);
1196                 val64 = 0x0203000100000102ULL;
1197                 writeq(val64, &bar0->tx_w_round_robin_2);
1198                 val64 = 0x0304000102030405ULL;
1199                 writeq(val64, &bar0->tx_w_round_robin_3);
1200                 val64 = 0x0001000200000000ULL;
1201                 writeq(val64, &bar0->tx_w_round_robin_4);
1202                 break;
1203         case 7:
1204                 val64 = 0x0001020001020300ULL;
1205                 writeq(val64, &bar0->tx_w_round_robin_0);
1206                 val64 = 0x0102030400010203ULL;
1207                 writeq(val64, &bar0->tx_w_round_robin_1);
1208                 val64 = 0x0405060001020001ULL;
1209                 writeq(val64, &bar0->tx_w_round_robin_2);
1210                 val64 = 0x0304050000010200ULL;
1211                 writeq(val64, &bar0->tx_w_round_robin_3);
1212                 val64 = 0x0102030000000000ULL;
1213                 writeq(val64, &bar0->tx_w_round_robin_4);
1214                 break;
1215         case 8:
1216                 val64 = 0x0001020300040105ULL;
1217                 writeq(val64, &bar0->tx_w_round_robin_0);
1218                 val64 = 0x0200030106000204ULL;
1219                 writeq(val64, &bar0->tx_w_round_robin_1);
1220                 val64 = 0x0103000502010007ULL;
1221                 writeq(val64, &bar0->tx_w_round_robin_2);
1222                 val64 = 0x0304010002060500ULL;
1223                 writeq(val64, &bar0->tx_w_round_robin_3);
1224                 val64 = 0x0103020400000000ULL;
1225                 writeq(val64, &bar0->tx_w_round_robin_4);
1226                 break;
1227         }
1228
1229         /* Enable all configured Tx FIFO partitions */
1230         val64 = readq(&bar0->tx_fifo_partition_0);
1231         val64 |= (TX_FIFO_PARTITION_EN);
1232         writeq(val64, &bar0->tx_fifo_partition_0);
1233
1234         /* Filling the Rx round robin registers as per the
1235          * number of Rings and steering based on QoS.
1236          */
1237         switch (config->rx_ring_num) {
1238         case 1:
1239                 val64 = 0x8080808080808080ULL;
1240                 writeq(val64, &bar0->rts_qos_steering);
1241                 break;
1242         case 2:
1243                 val64 = 0x0000010000010000ULL;
1244                 writeq(val64, &bar0->rx_w_round_robin_0);
1245                 val64 = 0x0100000100000100ULL;
1246                 writeq(val64, &bar0->rx_w_round_robin_1);
1247                 val64 = 0x0001000001000001ULL;
1248                 writeq(val64, &bar0->rx_w_round_robin_2);
1249                 val64 = 0x0000010000010000ULL;
1250                 writeq(val64, &bar0->rx_w_round_robin_3);
1251                 val64 = 0x0100000000000000ULL;
1252                 writeq(val64, &bar0->rx_w_round_robin_4);
1253
1254                 val64 = 0x8080808040404040ULL;
1255                 writeq(val64, &bar0->rts_qos_steering);
1256                 break;
1257         case 3:
1258                 val64 = 0x0001000102000001ULL;
1259                 writeq(val64, &bar0->rx_w_round_robin_0);
1260                 val64 = 0x0001020000010001ULL;
1261                 writeq(val64, &bar0->rx_w_round_robin_1);
1262                 val64 = 0x0200000100010200ULL;
1263                 writeq(val64, &bar0->rx_w_round_robin_2);
1264                 val64 = 0x0001000102000001ULL;
1265                 writeq(val64, &bar0->rx_w_round_robin_3);
1266                 val64 = 0x0001020000000000ULL;
1267                 writeq(val64, &bar0->rx_w_round_robin_4);
1268
1269                 val64 = 0x8080804040402020ULL;
1270                 writeq(val64, &bar0->rts_qos_steering);
1271                 break;
1272         case 4:
1273                 val64 = 0x0001020300010200ULL;
1274                 writeq(val64, &bar0->rx_w_round_robin_0);
1275                 val64 = 0x0100000102030001ULL;
1276                 writeq(val64, &bar0->rx_w_round_robin_1);
1277                 val64 = 0x0200010000010203ULL;
1278                 writeq(val64, &bar0->rx_w_round_robin_2);
1279                 val64 = 0x0001020001000001ULL;
1280                 writeq(val64, &bar0->rx_w_round_robin_3);
1281                 val64 = 0x0203000100000000ULL;
1282                 writeq(val64, &bar0->rx_w_round_robin_4);
1283
1284                 val64 = 0x8080404020201010ULL;
1285                 writeq(val64, &bar0->rts_qos_steering);
1286                 break;
1287         case 5:
1288                 val64 = 0x0001000203000102ULL;
1289                 writeq(val64, &bar0->rx_w_round_robin_0);
1290                 val64 = 0x0001020001030004ULL;
1291                 writeq(val64, &bar0->rx_w_round_robin_1);
1292                 val64 = 0x0001000203000102ULL;
1293                 writeq(val64, &bar0->rx_w_round_robin_2);
1294                 val64 = 0x0001020001030004ULL;
1295                 writeq(val64, &bar0->rx_w_round_robin_3);
1296                 val64 = 0x0001000000000000ULL;
1297                 writeq(val64, &bar0->rx_w_round_robin_4);
1298
1299                 val64 = 0x8080404020201008ULL;
1300                 writeq(val64, &bar0->rts_qos_steering);
1301                 break;
1302         case 6:
1303                 val64 = 0x0001020304000102ULL;
1304                 writeq(val64, &bar0->rx_w_round_robin_0);
1305                 val64 = 0x0304050001020001ULL;
1306                 writeq(val64, &bar0->rx_w_round_robin_1);
1307                 val64 = 0x0203000100000102ULL;
1308                 writeq(val64, &bar0->rx_w_round_robin_2);
1309                 val64 = 0x0304000102030405ULL;
1310                 writeq(val64, &bar0->rx_w_round_robin_3);
1311                 val64 = 0x0001000200000000ULL;
1312                 writeq(val64, &bar0->rx_w_round_robin_4);
1313
1314                 val64 = 0x8080404020100804ULL;
1315                 writeq(val64, &bar0->rts_qos_steering);
1316                 break;
1317         case 7:
1318                 val64 = 0x0001020001020300ULL;
1319                 writeq(val64, &bar0->rx_w_round_robin_0);
1320                 val64 = 0x0102030400010203ULL;
1321                 writeq(val64, &bar0->rx_w_round_robin_1);
1322                 val64 = 0x0405060001020001ULL;
1323                 writeq(val64, &bar0->rx_w_round_robin_2);
1324                 val64 = 0x0304050000010200ULL;
1325                 writeq(val64, &bar0->rx_w_round_robin_3);
1326                 val64 = 0x0102030000000000ULL;
1327                 writeq(val64, &bar0->rx_w_round_robin_4);
1328
1329                 val64 = 0x8080402010080402ULL;
1330                 writeq(val64, &bar0->rts_qos_steering);
1331                 break;
1332         case 8:
1333                 val64 = 0x0001020300040105ULL;
1334                 writeq(val64, &bar0->rx_w_round_robin_0);
1335                 val64 = 0x0200030106000204ULL;
1336                 writeq(val64, &bar0->rx_w_round_robin_1);
1337                 val64 = 0x0103000502010007ULL;
1338                 writeq(val64, &bar0->rx_w_round_robin_2);
1339                 val64 = 0x0304010002060500ULL;
1340                 writeq(val64, &bar0->rx_w_round_robin_3);
1341                 val64 = 0x0103020400000000ULL;
1342                 writeq(val64, &bar0->rx_w_round_robin_4);
1343
1344                 val64 = 0x8040201008040201ULL;
1345                 writeq(val64, &bar0->rts_qos_steering);
1346                 break;
1347         }
1348
1349         /* UDP Fix */
1350         val64 = 0;
1351         for (i = 0; i < 8; i++)
1352                 writeq(val64, &bar0->rts_frm_len_n[i]);
1353
1354         /* Set the default rts frame length for the rings configured */
1355         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1356         for (i = 0 ; i < config->rx_ring_num ; i++)
1357                 writeq(val64, &bar0->rts_frm_len_n[i]);
1358
1359         /* Set the frame length for the configured rings
1360          * desired by the user
1361          */
1362         for (i = 0; i < config->rx_ring_num; i++) {
1363                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1364                  * specified frame length steering.
1365                  * If the user provides the frame length then program
1366                  * the rts_frm_len register for those values or else
1367                  * leave it as it is.
1368                  */
1369                 if (rts_frm_len[i] != 0) {
1370                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1371                                 &bar0->rts_frm_len_n[i]);
1372                 }
1373         }
1374
1375         /* Program statistics memory */
1376         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1377
1378         if (nic->device_type == XFRAME_II_DEVICE) {
1379                 val64 = STAT_BC(0x320);
1380                 writeq(val64, &bar0->stat_byte_cnt);
1381         }
1382
1383         /*
1384          * Initializing the sampling rate for the device to calculate the
1385          * bandwidth utilization.
1386          */
1387         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1388             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1389         writeq(val64, &bar0->mac_link_util);
1390
1391
1392         /*
1393          * Initializing the Transmit and Receive Traffic Interrupt
1394          * Scheme.
1395          */
1396         /*
1397          * TTI Initialization. Default Tx timer gets us about
1398          * 250 interrupts per sec. Continuous interrupts are enabled
1399          * by default.
1400          */
1401         if (nic->device_type == XFRAME_II_DEVICE) {
1402                 int count = (nic->config.bus_speed * 125)/2;
1403                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1404         } else {
1405
1406                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1407         }
1408         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1409             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1410             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1411                 if (use_continuous_tx_intrs)
1412                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1413         writeq(val64, &bar0->tti_data1_mem);
1414
1415         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1416             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1417             TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1418         writeq(val64, &bar0->tti_data2_mem);
1419
1420         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1421         writeq(val64, &bar0->tti_command_mem);
1422
1423         /*
1424          * Once the operation completes, the Strobe bit of the command
1425          * register will be reset. We poll for this particular condition
1426          * We wait for a maximum of 500ms for the operation to complete,
1427          * if it's not complete by then we return error.
1428          */
1429         time = 0;
1430         while (TRUE) {
1431                 val64 = readq(&bar0->tti_command_mem);
1432                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1433                         break;
1434                 }
1435                 if (time > 10) {
1436                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1437                                   dev->name);
1438                         return -1;
1439                 }
1440                 msleep(50);
1441                 time++;
1442         }
1443
1444         if (nic->config.bimodal) {
1445                 int k = 0;
1446                 for (k = 0; k < config->rx_ring_num; k++) {
1447                         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1448                         val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1449                         writeq(val64, &bar0->tti_command_mem);
1450
1451                 /*
1452                  * Once the operation completes, the Strobe bit of the command
1453                  * register will be reset. We poll for this particular condition
1454                  * We wait for a maximum of 500ms for the operation to complete,
1455                  * if it's not complete by then we return error.
1456                 */
1457                         time = 0;
1458                         while (TRUE) {
1459                                 val64 = readq(&bar0->tti_command_mem);
1460                                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1461                                         break;
1462                                 }
1463                                 if (time > 10) {
1464                                         DBG_PRINT(ERR_DBG,
1465                                                 "%s: TTI init Failed\n",
1466                                         dev->name);
1467                                         return -1;
1468                                 }
1469                                 time++;
1470                                 msleep(50);
1471                         }
1472                 }
1473         } else {
1474
1475                 /* RTI Initialization */
1476                 if (nic->device_type == XFRAME_II_DEVICE) {
1477                         /*
1478                          * Programmed to generate Apprx 500 Intrs per
1479                          * second
1480                          */
1481                         int count = (nic->config.bus_speed * 125)/4;
1482                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1483                 } else {
1484                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1485                 }
1486                 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1487                     RTI_DATA1_MEM_RX_URNG_B(0x10) |
1488                     RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1489
1490                 writeq(val64, &bar0->rti_data1_mem);
1491
1492                 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1493                     RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1494                 if (nic->intr_type == MSI_X)
1495                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1496                                 RTI_DATA2_MEM_RX_UFC_D(0x40));
1497                 else
1498                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1499                                 RTI_DATA2_MEM_RX_UFC_D(0x80));
1500                 writeq(val64, &bar0->rti_data2_mem);
1501
1502                 for (i = 0; i < config->rx_ring_num; i++) {
1503                         val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1504                                         | RTI_CMD_MEM_OFFSET(i);
1505                         writeq(val64, &bar0->rti_command_mem);
1506
1507                         /*
1508                          * Once the operation completes, the Strobe bit of the
1509                          * command register will be reset. We poll for this
1510                          * particular condition. We wait for a maximum of 500ms
1511                          * for the operation to complete, if it's not complete
1512                          * by then we return error.
1513                          */
1514                         time = 0;
1515                         while (TRUE) {
1516                                 val64 = readq(&bar0->rti_command_mem);
1517                                 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1518                                         break;
1519                                 }
1520                                 if (time > 10) {
1521                                         DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1522                                                   dev->name);
1523                                         return -1;
1524                                 }
1525                                 time++;
1526                                 msleep(50);
1527                         }
1528                 }
1529         }
1530
1531         /*
1532          * Initializing proper values as Pause threshold into all
1533          * the 8 Queues on Rx side.
1534          */
1535         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1536         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1537
1538         /* Disable RMAC PAD STRIPPING */
1539         add = &bar0->mac_cfg;
1540         val64 = readq(&bar0->mac_cfg);
1541         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1542         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1543         writel((u32) (val64), add);
1544         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1545         writel((u32) (val64 >> 32), (add + 4));
1546         val64 = readq(&bar0->mac_cfg);
1547
1548         /* Enable FCS stripping by adapter */
1549         add = &bar0->mac_cfg;
1550         val64 = readq(&bar0->mac_cfg);
1551         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1552         if (nic->device_type == XFRAME_II_DEVICE)
1553                 writeq(val64, &bar0->mac_cfg);
1554         else {
1555                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1556                 writel((u32) (val64), add);
1557                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1558                 writel((u32) (val64 >> 32), (add + 4));
1559         }
1560
1561         /*
1562          * Set the time value to be inserted in the pause frame
1563          * generated by xena.
1564          */
1565         val64 = readq(&bar0->rmac_pause_cfg);
1566         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1567         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1568         writeq(val64, &bar0->rmac_pause_cfg);
1569
1570         /*
1571          * Set the Threshold Limit for Generating the pause frame
1572          * If the amount of data in any Queue exceeds ratio of
1573          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1574          * pause frame is generated
1575          */
1576         val64 = 0;
1577         for (i = 0; i < 4; i++) {
1578                 val64 |=
1579                     (((u64) 0xFF00 | nic->mac_control.
1580                       mc_pause_threshold_q0q3)
1581                      << (i * 2 * 8));
1582         }
1583         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1584
1585         val64 = 0;
1586         for (i = 0; i < 4; i++) {
1587                 val64 |=
1588                     (((u64) 0xFF00 | nic->mac_control.
1589                       mc_pause_threshold_q4q7)
1590                      << (i * 2 * 8));
1591         }
1592         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1593
1594         /*
1595          * TxDMA will stop Read request if the number of read split has
1596          * exceeded the limit pointed by shared_splits
1597          */
1598         val64 = readq(&bar0->pic_control);
1599         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1600         writeq(val64, &bar0->pic_control);
1601
1602         if (nic->config.bus_speed == 266) {
1603                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1604                 writeq(0x0, &bar0->read_retry_delay);
1605                 writeq(0x0, &bar0->write_retry_delay);
1606         }
1607
1608         /*
1609          * Programming the Herc to split every write transaction
1610          * that does not start on an ADB to reduce disconnects.
1611          */
1612         if (nic->device_type == XFRAME_II_DEVICE) {
1613                 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1614                         MISC_LINK_STABILITY_PRD(3);
1615                 writeq(val64, &bar0->misc_control);
1616                 val64 = readq(&bar0->pic_control2);
1617                 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1618                 writeq(val64, &bar0->pic_control2);
1619         }
1620         if (strstr(nic->product_name, "CX4")) {
1621                 val64 = TMAC_AVG_IPG(0x17);
1622                 writeq(val64, &bar0->tmac_avg_ipg);
1623         }
1624
1625         return SUCCESS;
1626 }
1627 #define LINK_UP_DOWN_INTERRUPT          1
1628 #define MAC_RMAC_ERR_TIMER              2
1629
1630 static int s2io_link_fault_indication(struct s2io_nic *nic)
1631 {
1632         if (nic->intr_type != INTA)
1633                 return MAC_RMAC_ERR_TIMER;
1634         if (nic->device_type == XFRAME_II_DEVICE)
1635                 return LINK_UP_DOWN_INTERRUPT;
1636         else
1637                 return MAC_RMAC_ERR_TIMER;
1638 }
1639
1640 /**
1641  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1642  *  @nic: device private variable,
1643  *  @mask: A mask indicating which Intr block must be modified and,
1644  *  @flag: A flag indicating whether to enable or disable the Intrs.
1645  *  Description: This function will either disable or enable the interrupts
1646  *  depending on the flag argument. The mask argument can be used to
1647  *  enable/disable any Intr block.
1648  *  Return Value: NONE.
1649  */
1650
1651 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1652 {
1653         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1654         register u64 val64 = 0, temp64 = 0;
1655
1656         /*  Top level interrupt classification */
1657         /*  PIC Interrupts */
1658         if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1659                 /*  Enable PIC Intrs in the general intr mask register */
1660                 val64 = TXPIC_INT_M;
1661                 if (flag == ENABLE_INTRS) {
1662                         temp64 = readq(&bar0->general_int_mask);
1663                         temp64 &= ~((u64) val64);
1664                         writeq(temp64, &bar0->general_int_mask);
1665                         /*
1666                          * If Hercules adapter enable GPIO otherwise
1667                          * disable all PCIX, Flash, MDIO, IIC and GPIO
1668                          * interrupts for now.
1669                          * TODO
1670                          */
1671                         if (s2io_link_fault_indication(nic) ==
1672                                         LINK_UP_DOWN_INTERRUPT ) {
1673                                 temp64 = readq(&bar0->pic_int_mask);
1674                                 temp64 &= ~((u64) PIC_INT_GPIO);
1675                                 writeq(temp64, &bar0->pic_int_mask);
1676                                 temp64 = readq(&bar0->gpio_int_mask);
1677                                 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1678                                 writeq(temp64, &bar0->gpio_int_mask);
1679                         } else {
1680                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1681                         }
1682                         /*
1683                          * No MSI Support is available presently, so TTI and
1684                          * RTI interrupts are also disabled.
1685                          */
1686                 } else if (flag == DISABLE_INTRS) {
1687                         /*
1688                          * Disable PIC Intrs in the general
1689                          * intr mask register
1690                          */
1691                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1692                         temp64 = readq(&bar0->general_int_mask);
1693                         val64 |= temp64;
1694                         writeq(val64, &bar0->general_int_mask);
1695                 }
1696         }
1697
1698         /*  MAC Interrupts */
1699         /*  Enabling/Disabling MAC interrupts */
1700         if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1701                 val64 = TXMAC_INT_M | RXMAC_INT_M;
1702                 if (flag == ENABLE_INTRS) {
1703                         temp64 = readq(&bar0->general_int_mask);
1704                         temp64 &= ~((u64) val64);
1705                         writeq(temp64, &bar0->general_int_mask);
1706                         /*
1707                          * All MAC block error interrupts are disabled for now
1708                          * TODO
1709                          */
1710                 } else if (flag == DISABLE_INTRS) {
1711                         /*
1712                          * Disable MAC Intrs in the general intr mask register
1713                          */
1714                         writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1715                         writeq(DISABLE_ALL_INTRS,
1716                                &bar0->mac_rmac_err_mask);
1717
1718                         temp64 = readq(&bar0->general_int_mask);
1719                         val64 |= temp64;
1720                         writeq(val64, &bar0->general_int_mask);
1721                 }
1722         }
1723
1724         /*  Tx traffic interrupts */
1725         if (mask & TX_TRAFFIC_INTR) {
1726                 val64 = TXTRAFFIC_INT_M;
1727                 if (flag == ENABLE_INTRS) {
1728                         temp64 = readq(&bar0->general_int_mask);
1729                         temp64 &= ~((u64) val64);
1730                         writeq(temp64, &bar0->general_int_mask);
1731                         /*
1732                          * Enable all the Tx side interrupts
1733                          * writing 0 Enables all 64 TX interrupt levels
1734                          */
1735                         writeq(0x0, &bar0->tx_traffic_mask);
1736                 } else if (flag == DISABLE_INTRS) {
1737                         /*
1738                          * Disable Tx Traffic Intrs in the general intr mask
1739                          * register.
1740                          */
1741                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1742                         temp64 = readq(&bar0->general_int_mask);
1743                         val64 |= temp64;
1744                         writeq(val64, &bar0->general_int_mask);
1745                 }
1746         }
1747
1748         /*  Rx traffic interrupts */
1749         if (mask & RX_TRAFFIC_INTR) {
1750                 val64 = RXTRAFFIC_INT_M;
1751                 if (flag == ENABLE_INTRS) {
1752                         temp64 = readq(&bar0->general_int_mask);
1753                         temp64 &= ~((u64) val64);
1754                         writeq(temp64, &bar0->general_int_mask);
1755                         /* writing 0 Enables all 8 RX interrupt levels */
1756                         writeq(0x0, &bar0->rx_traffic_mask);
1757                 } else if (flag == DISABLE_INTRS) {
1758                         /*
1759                          * Disable Rx Traffic Intrs in the general intr mask
1760                          * register.
1761                          */
1762                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1763                         temp64 = readq(&bar0->general_int_mask);
1764                         val64 |= temp64;
1765                         writeq(val64, &bar0->general_int_mask);
1766                 }
1767         }
1768 }
1769
1770 /**
1771  *  verify_pcc_quiescent- Checks for PCC quiescent state
1772  *  Return: 1 If PCC is quiescence
1773  *          0 If PCC is not quiescence
1774  */
1775 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
1776 {
1777         int ret = 0, herc;
1778         struct XENA_dev_config __iomem *bar0 = sp->bar0;
1779         u64 val64 = readq(&bar0->adapter_status);
1780
1781         herc = (sp->device_type == XFRAME_II_DEVICE);
1782
1783         if (flag == FALSE) {
1784                 if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
1785                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
1786                                 ret = 1;
1787                 } else {
1788                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
1789                                 ret = 1;
1790                 }
1791         } else {
1792                 if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
1793                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1794                              ADAPTER_STATUS_RMAC_PCC_IDLE))
1795                                 ret = 1;
1796                 } else {
1797                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1798                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
1799                                 ret = 1;
1800                 }
1801         }
1802
1803         return ret;
1804 }
1805 /**
1806  *  verify_xena_quiescence - Checks whether the H/W is ready
1807  *  Description: Returns whether the H/W is ready to go or not. Depending
1808  *  on whether adapter enable bit was written or not the comparison
1809  *  differs and the calling function passes the input argument flag to
1810  *  indicate this.
1811  *  Return: 1 If xena is quiescence
1812  *          0 If Xena is not quiescence
1813  */
1814
1815 static int verify_xena_quiescence(struct s2io_nic *sp)
1816 {
1817         int  mode;
1818         struct XENA_dev_config __iomem *bar0 = sp->bar0;
1819         u64 val64 = readq(&bar0->adapter_status);
1820         mode = s2io_verify_pci_mode(sp);
1821
1822         if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
1823                 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
1824                 return 0;
1825         }
1826         if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
1827         DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
1828                 return 0;
1829         }
1830         if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
1831                 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
1832                 return 0;
1833         }
1834         if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
1835                 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
1836                 return 0;
1837         }
1838         if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
1839                 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
1840                 return 0;
1841         }
1842         if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
1843                 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
1844                 return 0;
1845         }
1846         if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
1847                 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
1848                 return 0;
1849         }
1850         if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
1851                 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
1852                 return 0;
1853         }
1854
1855         /*
1856          * In PCI 33 mode, the P_PLL is not used, and therefore,
1857          * the the P_PLL_LOCK bit in the adapter_status register will
1858          * not be asserted.
1859          */
1860         if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
1861                 sp->device_type == XFRAME_II_DEVICE && mode !=
1862                 PCI_MODE_PCI_33) {
1863                 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
1864                 return 0;
1865         }
1866         if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1867                         ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1868                 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
1869                 return 0;
1870         }
1871         return 1;
1872 }
1873
1874 /**
1875  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
1876  * @sp: Pointer to device specifc structure
1877  * Description :
1878  * New procedure to clear mac address reading  problems on Alpha platforms
1879  *
1880  */
1881
1882 static void fix_mac_address(struct s2io_nic * sp)
1883 {
1884         struct XENA_dev_config __iomem *bar0 = sp->bar0;
1885         u64 val64;
1886         int i = 0;
1887
1888         while (fix_mac[i] != END_SIGN) {
1889                 writeq(fix_mac[i++], &bar0->gpio_control);
1890                 udelay(10);
1891                 val64 = readq(&bar0->gpio_control);
1892         }
1893 }
1894
1895 /**
1896  *  start_nic - Turns the device on
1897  *  @nic : device private variable.
1898  *  Description:
1899  *  This function actually turns the device on. Before this  function is
1900  *  called,all Registers are configured from their reset states
1901  *  and shared memory is allocated but the NIC is still quiescent. On
1902  *  calling this function, the device interrupts are cleared and the NIC is
1903  *  literally switched on by writing into the adapter control register.
1904  *  Return Value:
1905  *  SUCCESS on success and -1 on failure.
1906  */
1907
1908 static int start_nic(struct s2io_nic *nic)
1909 {
1910         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1911         struct net_device *dev = nic->dev;
1912         register u64 val64 = 0;
1913         u16 subid, i;
1914         struct mac_info *mac_control;
1915         struct config_param *config;
1916
1917         mac_control = &nic->mac_control;
1918         config = &nic->config;
1919
1920         /*  PRC Initialization and configuration */
1921         for (i = 0; i < config->rx_ring_num; i++) {
1922                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1923                        &bar0->prc_rxd0_n[i]);
1924
1925                 val64 = readq(&bar0->prc_ctrl_n[i]);
1926                 if (nic->config.bimodal)
1927                         val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
1928                 if (nic->rxd_mode == RXD_MODE_1)
1929                         val64 |= PRC_CTRL_RC_ENABLED;
1930                 else
1931                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
1932                 if (nic->device_type == XFRAME_II_DEVICE)
1933                         val64 |= PRC_CTRL_GROUP_READS;
1934                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
1935                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1936                 writeq(val64, &bar0->prc_ctrl_n[i]);
1937         }
1938
1939         if (nic->rxd_mode == RXD_MODE_3B) {
1940                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
1941                 val64 = readq(&bar0->rx_pa_cfg);
1942                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
1943                 writeq(val64, &bar0->rx_pa_cfg);
1944         }
1945
1946         /*
1947          * Enabling MC-RLDRAM. After enabling the device, we timeout
1948          * for around 100ms, which is approximately the time required
1949          * for the device to be ready for operation.
1950          */
1951         val64 = readq(&bar0->mc_rldram_mrs);
1952         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
1953         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
1954         val64 = readq(&bar0->mc_rldram_mrs);
1955
1956         msleep(100);    /* Delay by around 100 ms. */
1957
1958         /* Enabling ECC Protection. */
1959         val64 = readq(&bar0->adapter_control);
1960         val64 &= ~ADAPTER_ECC_EN;
1961         writeq(val64, &bar0->adapter_control);
1962
1963         /*
1964          * Clearing any possible Link state change interrupts that
1965          * could have popped up just before Enabling the card.
1966          */
1967         val64 = readq(&bar0->mac_rmac_err_reg);
1968         if (val64)
1969                 writeq(val64, &bar0->mac_rmac_err_reg);
1970
1971         /*
1972          * Verify if the device is ready to be enabled, if so enable
1973          * it.
1974          */
1975         val64 = readq(&bar0->adapter_status);
1976         if (!verify_xena_quiescence(nic)) {
1977                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
1978                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
1979                           (unsigned long long) val64);
1980                 return FAILURE;
1981         }
1982
1983         /*
1984          * With some switches, link might be already up at this point.
1985          * Because of this weird behavior, when we enable laser,
1986          * we may not get link. We need to handle this. We cannot
1987          * figure out which switch is misbehaving. So we are forced to
1988          * make a global change.
1989          */
1990
1991         /* Enabling Laser. */
1992         val64 = readq(&bar0->adapter_control);
1993         val64 |= ADAPTER_EOI_TX_ON;
1994         writeq(val64, &bar0->adapter_control);
1995
1996         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
1997                 /*
1998                  * Dont see link state interrupts initally on some switches,
1999                  * so directly scheduling the link state task here.
2000                  */
2001                 schedule_work(&nic->set_link_task);
2002         }
2003         /* SXE-002: Initialize link and activity LED */
2004         subid = nic->pdev->subsystem_device;
2005         if (((subid & 0xFF) >= 0x07) &&
2006             (nic->device_type == XFRAME_I_DEVICE)) {
2007                 val64 = readq(&bar0->gpio_control);
2008                 val64 |= 0x0000800000000000ULL;
2009                 writeq(val64, &bar0->gpio_control);
2010                 val64 = 0x0411040400000000ULL;
2011                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2012         }
2013
2014         return SUCCESS;
2015 }
2016 /**
2017  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2018  */
2019 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2020                                         TxD *txdlp, int get_off)
2021 {
2022         struct s2io_nic *nic = fifo_data->nic;
2023         struct sk_buff *skb;
2024         struct TxD *txds;
2025         u16 j, frg_cnt;
2026
2027         txds = txdlp;
2028         if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2029                 pci_unmap_single(nic->pdev, (dma_addr_t)
2030                         txds->Buffer_Pointer, sizeof(u64),
2031                         PCI_DMA_TODEVICE);
2032                 txds++;
2033         }
2034
2035         skb = (struct sk_buff *) ((unsigned long)
2036                         txds->Host_Control);
2037         if (!skb) {
2038                 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2039                 return NULL;
2040         }
2041         pci_unmap_single(nic->pdev, (dma_addr_t)
2042                          txds->Buffer_Pointer,
2043                          skb->len - skb->data_len,
2044                          PCI_DMA_TODEVICE);
2045         frg_cnt = skb_shinfo(skb)->nr_frags;
2046         if (frg_cnt) {
2047                 txds++;
2048                 for (j = 0; j < frg_cnt; j++, txds++) {
2049                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2050                         if (!txds->Buffer_Pointer)
2051                                 break;
2052                         pci_unmap_page(nic->pdev, (dma_addr_t)
2053                                         txds->Buffer_Pointer,
2054                                        frag->size, PCI_DMA_TODEVICE);
2055                 }
2056         }
2057         memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
2058         return(skb);
2059 }
2060
2061 /**
2062  *  free_tx_buffers - Free all queued Tx buffers
2063  *  @nic : device private variable.
2064  *  Description:
2065  *  Free all queued Tx buffers.
2066  *  Return Value: void
2067 */
2068
2069 static void free_tx_buffers(struct s2io_nic *nic)
2070 {
2071         struct net_device *dev = nic->dev;
2072         struct sk_buff *skb;
2073         struct TxD *txdp;
2074         int i, j;
2075         struct mac_info *mac_control;
2076         struct config_param *config;
2077         int cnt = 0;
2078
2079         mac_control = &nic->mac_control;
2080         config = &nic->config;
2081
2082         for (i = 0; i < config->tx_fifo_num; i++) {
2083                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2084                         txdp = (struct TxD *) mac_control->fifos[i].list_info[j].
2085                             list_virt_addr;
2086                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2087                         if (skb) {
2088                                 dev_kfree_skb(skb);
2089                                 cnt++;
2090                         }
2091                 }
2092                 DBG_PRINT(INTR_DBG,
2093                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2094                           dev->name, cnt, i);
2095                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2096                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2097         }
2098 }
2099
2100 /**
2101  *   stop_nic -  To stop the nic
2102  *   @nic ; device private variable.
2103  *   Description:
2104  *   This function does exactly the opposite of what the start_nic()
2105  *   function does. This function is called to stop the device.
2106  *   Return Value:
2107  *   void.
2108  */
2109
2110 static void stop_nic(struct s2io_nic *nic)
2111 {
2112         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2113         register u64 val64 = 0;
2114         u16 interruptible;
2115         struct mac_info *mac_control;
2116         struct config_param *config;
2117
2118         mac_control = &nic->mac_control;
2119         config = &nic->config;
2120
2121         /*  Disable all interrupts */
2122         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2123         interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2124         interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2125         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2126
2127         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2128         val64 = readq(&bar0->adapter_control);
2129         val64 &= ~(ADAPTER_CNTL_EN);
2130         writeq(val64, &bar0->adapter_control);
2131 }
2132
2133 static int fill_rxd_3buf(struct s2io_nic *nic, struct RxD_t *rxdp, struct \
2134                                 sk_buff *skb)
2135 {
2136         struct net_device *dev = nic->dev;
2137         struct sk_buff *frag_list;
2138         void *tmp;
2139
2140         /* Buffer-1 receives L3/L4 headers */
2141         ((struct RxD3*)rxdp)->Buffer1_ptr = pci_map_single
2142                         (nic->pdev, skb->data, l3l4hdr_size + 4,
2143                         PCI_DMA_FROMDEVICE);
2144
2145         /* skb_shinfo(skb)->frag_list will have L4 data payload */
2146         skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2147         if (skb_shinfo(skb)->frag_list == NULL) {
2148                 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2149                 return -ENOMEM ;
2150         }
2151         frag_list = skb_shinfo(skb)->frag_list;
2152         skb->truesize += frag_list->truesize;
2153         frag_list->next = NULL;
2154         tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2155         frag_list->data = tmp;
2156         frag_list->tail = tmp;
2157
2158         /* Buffer-2 receives L4 data payload */
2159         ((struct RxD3*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2160                                 frag_list->data, dev->mtu,
2161                                 PCI_DMA_FROMDEVICE);
2162         rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2163         rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2164
2165         return SUCCESS;
2166 }
2167
2168 /**
2169  *  fill_rx_buffers - Allocates the Rx side skbs
2170  *  @nic:  device private variable
2171  *  @ring_no: ring number
2172  *  Description:
2173  *  The function allocates Rx side skbs and puts the physical
2174  *  address of these buffers into the RxD buffer pointers, so that the NIC
2175  *  can DMA the received frame into these locations.
2176  *  The NIC supports 3 receive modes, viz
2177  *  1. single buffer,
2178  *  2. three buffer and
2179  *  3. Five buffer modes.
2180  *  Each mode defines how many fragments the received frame will be split
2181  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2182  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2183  *  is split into 3 fragments. As of now only single buffer mode is
2184  *  supported.
2185  *   Return Value:
2186  *  SUCCESS on success or an appropriate -ve value on failure.
2187  */
2188
2189 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2190 {
2191         struct net_device *dev = nic->dev;
2192         struct sk_buff *skb;
2193         struct RxD_t *rxdp;
2194         int off, off1, size, block_no, block_no1;
2195         u32 alloc_tab = 0;
2196         u32 alloc_cnt;
2197         struct mac_info *mac_control;
2198         struct config_param *config;
2199         u64 tmp;
2200         struct buffAdd *ba;
2201         unsigned long flags;
2202         struct RxD_t *first_rxdp = NULL;
2203
2204         mac_control = &nic->mac_control;
2205         config = &nic->config;
2206         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2207             atomic_read(&nic->rx_bufs_left[ring_no]);
2208
2209         block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2210         off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2211         while (alloc_tab < alloc_cnt) {
2212                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2213                     block_index;
2214                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2215
2216                 rxdp = mac_control->rings[ring_no].
2217                                 rx_blocks[block_no].rxds[off].virt_addr;
2218
2219                 if ((block_no == block_no1) && (off == off1) &&
2220                                         (rxdp->Host_Control)) {
2221                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2222                                   dev->name);
2223                         DBG_PRINT(INTR_DBG, " info equated\n");
2224                         goto end;
2225                 }
2226                 if (off && (off == rxd_count[nic->rxd_mode])) {
2227                         mac_control->rings[ring_no].rx_curr_put_info.
2228                             block_index++;
2229                         if (mac_control->rings[ring_no].rx_curr_put_info.
2230                             block_index == mac_control->rings[ring_no].
2231                                         block_count)
2232                                 mac_control->rings[ring_no].rx_curr_put_info.
2233                                         block_index = 0;
2234                         block_no = mac_control->rings[ring_no].
2235                                         rx_curr_put_info.block_index;
2236                         if (off == rxd_count[nic->rxd_mode])
2237                                 off = 0;
2238                         mac_control->rings[ring_no].rx_curr_put_info.
2239                                 offset = off;
2240                         rxdp = mac_control->rings[ring_no].
2241                                 rx_blocks[block_no].block_virt_addr;
2242                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2243                                   dev->name, rxdp);
2244                 }
2245                 if(!napi) {
2246                         spin_lock_irqsave(&nic->put_lock, flags);
2247                         mac_control->rings[ring_no].put_pos =
2248                         (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2249                         spin_unlock_irqrestore(&nic->put_lock, flags);
2250                 } else {
2251                         mac_control->rings[ring_no].put_pos =
2252                         (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2253                 }
2254                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2255                         ((nic->rxd_mode >= RXD_MODE_3A) &&
2256                                 (rxdp->Control_2 & BIT(0)))) {
2257                         mac_control->rings[ring_no].rx_curr_put_info.
2258                                         offset = off;
2259                         goto end;
2260                 }
2261                 /* calculate size of skb based on ring mode */
2262                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2263                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2264                 if (nic->rxd_mode == RXD_MODE_1)
2265                         size += NET_IP_ALIGN;
2266                 else if (nic->rxd_mode == RXD_MODE_3B)
2267                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2268                 else
2269                         size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
2270
2271                 /* allocate skb */
2272                 skb = dev_alloc_skb(size);
2273                 if(!skb) {
2274                         DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2275                         DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
2276                         if (first_rxdp) {
2277                                 wmb();
2278                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2279                         }
2280                         return -ENOMEM ;
2281                 }
2282                 if (nic->rxd_mode == RXD_MODE_1) {
2283                         /* 1 buffer mode - normal operation mode */
2284                         memset(rxdp, 0, sizeof(struct RxD1));
2285                         skb_reserve(skb, NET_IP_ALIGN);
2286                         ((struct RxD1*)rxdp)->Buffer0_ptr = pci_map_single
2287                             (nic->pdev, skb->data, size - NET_IP_ALIGN,
2288                                 PCI_DMA_FROMDEVICE);
2289                         rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2290
2291                 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2292                         /*
2293                          * 2 or 3 buffer mode -
2294                          * Both 2 buffer mode and 3 buffer mode provides 128
2295                          * byte aligned receive buffers.
2296                          *
2297                          * 3 buffer mode provides header separation where in
2298                          * skb->data will have L3/L4 headers where as
2299                          * skb_shinfo(skb)->frag_list will have the L4 data
2300                          * payload
2301                          */
2302
2303                         memset(rxdp, 0, sizeof(struct RxD3));
2304                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2305                         skb_reserve(skb, BUF0_LEN);
2306                         tmp = (u64)(unsigned long) skb->data;
2307                         tmp += ALIGN_SIZE;
2308                         tmp &= ~ALIGN_SIZE;
2309                         skb->data = (void *) (unsigned long)tmp;
2310                         skb->tail = (void *) (unsigned long)tmp;
2311
2312                         if (!(((struct RxD3*)rxdp)->Buffer0_ptr))
2313                                 ((struct RxD3*)rxdp)->Buffer0_ptr =
2314                                    pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2315                                            PCI_DMA_FROMDEVICE);
2316                         else
2317                                 pci_dma_sync_single_for_device(nic->pdev,
2318                                     (dma_addr_t) ((struct RxD3*)rxdp)->Buffer0_ptr,
2319                                     BUF0_LEN, PCI_DMA_FROMDEVICE);
2320                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2321                         if (nic->rxd_mode == RXD_MODE_3B) {
2322                                 /* Two buffer mode */
2323
2324                                 /*
2325                                  * Buffer2 will have L3/L4 header plus
2326                                  * L4 payload
2327                                  */
2328                                 ((struct RxD3*)rxdp)->Buffer2_ptr = pci_map_single
2329                                 (nic->pdev, skb->data, dev->mtu + 4,
2330                                                 PCI_DMA_FROMDEVICE);
2331
2332                                 /* Buffer-1 will be dummy buffer. Not used */
2333                                 if (!(((struct RxD3*)rxdp)->Buffer1_ptr)) {
2334                                         ((struct RxD3*)rxdp)->Buffer1_ptr =
2335                                                 pci_map_single(nic->pdev,
2336                                                 ba->ba_1, BUF1_LEN,
2337                                                 PCI_DMA_FROMDEVICE);
2338                                 }
2339                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2340                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2341                                                                 (dev->mtu + 4);
2342                         } else {
2343                                 /* 3 buffer mode */
2344                                 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2345                                         dev_kfree_skb_irq(skb);
2346                                         if (first_rxdp) {
2347                                                 wmb();
2348                                                 first_rxdp->Control_1 |=
2349                                                         RXD_OWN_XENA;
2350                                         }
2351                                         return -ENOMEM ;
2352                                 }
2353                         }
2354                         rxdp->Control_2 |= BIT(0);
2355                 }
2356                 rxdp->Host_Control = (unsigned long) (skb);
2357                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2358                         rxdp->Control_1 |= RXD_OWN_XENA;
2359                 off++;
2360                 if (off == (rxd_count[nic->rxd_mode] + 1))
2361                         off = 0;
2362                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2363
2364                 rxdp->Control_2 |= SET_RXD_MARKER;
2365                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2366                         if (first_rxdp) {
2367                                 wmb();
2368                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2369                         }
2370                         first_rxdp = rxdp;
2371                 }
2372                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2373                 alloc_tab++;
2374         }
2375
2376       end:
2377         /* Transfer ownership of first descriptor to adapter just before
2378          * exiting. Before that, use memory barrier so that ownership
2379          * and other fields are seen by adapter correctly.
2380          */
2381         if (first_rxdp) {
2382                 wmb();
2383                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2384         }
2385
2386         return SUCCESS;
2387 }
2388
2389 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2390 {
2391         struct net_device *dev = sp->dev;
2392         int j;
2393         struct sk_buff *skb;
2394         struct RxD_t *rxdp;
2395         struct mac_info *mac_control;
2396         struct buffAdd *ba;
2397
2398         mac_control = &sp->mac_control;
2399         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2400                 rxdp = mac_control->rings[ring_no].
2401                                 rx_blocks[blk].rxds[j].virt_addr;
2402                 skb = (struct sk_buff *)
2403                         ((unsigned long) rxdp->Host_Control);
2404                 if (!skb) {
2405                         continue;
2406                 }
2407                 if (sp->rxd_mode == RXD_MODE_1) {
2408                         pci_unmap_single(sp->pdev, (dma_addr_t)
2409                                  ((struct RxD1*)rxdp)->Buffer0_ptr,
2410                                  dev->mtu +
2411                                  HEADER_ETHERNET_II_802_3_SIZE
2412                                  + HEADER_802_2_SIZE +
2413                                  HEADER_SNAP_SIZE,
2414                                  PCI_DMA_FROMDEVICE);
2415                         memset(rxdp, 0, sizeof(struct RxD1));
2416                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2417                         ba = &mac_control->rings[ring_no].
2418                                 ba[blk][j];
2419                         pci_unmap_single(sp->pdev, (dma_addr_t)
2420                                  ((struct RxD3*)rxdp)->Buffer0_ptr,
2421                                  BUF0_LEN,
2422                                  PCI_DMA_FROMDEVICE);
2423                         pci_unmap_single(sp->pdev, (dma_addr_t)
2424                                  ((struct RxD3*)rxdp)->Buffer1_ptr,
2425                                  BUF1_LEN,
2426                                  PCI_DMA_FROMDEVICE);
2427                         pci_unmap_single(sp->pdev, (dma_addr_t)
2428                                  ((struct RxD3*)rxdp)->Buffer2_ptr,
2429                                  dev->mtu + 4,
2430                                  PCI_DMA_FROMDEVICE);
2431                         memset(rxdp, 0, sizeof(struct RxD3));
2432                 } else {
2433                         pci_unmap_single(sp->pdev, (dma_addr_t)
2434                                 ((struct RxD3*)rxdp)->Buffer0_ptr, BUF0_LEN,
2435                                 PCI_DMA_FROMDEVICE);
2436                         pci_unmap_single(sp->pdev, (dma_addr_t)
2437                                 ((struct RxD3*)rxdp)->Buffer1_ptr,
2438                                 l3l4hdr_size + 4,
2439                                 PCI_DMA_FROMDEVICE);
2440                         pci_unmap_single(sp->pdev, (dma_addr_t)
2441                                 ((struct RxD3*)rxdp)->Buffer2_ptr, dev->mtu,
2442                                 PCI_DMA_FROMDEVICE);
2443                         memset(rxdp, 0, sizeof(struct RxD3));
2444                 }
2445                 dev_kfree_skb(skb);
2446                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2447         }
2448 }
2449
2450 /**
2451  *  free_rx_buffers - Frees all Rx buffers
2452  *  @sp: device private variable.
2453  *  Description:
2454  *  This function will free all Rx buffers allocated by host.
2455  *  Return Value:
2456  *  NONE.
2457  */
2458
2459 static void free_rx_buffers(struct s2io_nic *sp)
2460 {
2461         struct net_device *dev = sp->dev;
2462         int i, blk = 0, buf_cnt = 0;
2463         struct mac_info *mac_control;
2464         struct config_param *config;
2465
2466         mac_control = &sp->mac_control;
2467         config = &sp->config;
2468
2469         for (i = 0; i < config->rx_ring_num; i++) {
2470                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2471                         free_rxd_blk(sp,i,blk);
2472
2473                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2474                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2475                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2476                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2477                 atomic_set(&sp->rx_bufs_left[i], 0);
2478                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2479                           dev->name, buf_cnt, i);
2480         }
2481 }
2482
2483 /**
2484  * s2io_poll - Rx interrupt handler for NAPI support
2485  * @dev : pointer to the device structure.
2486  * @budget : The number of packets that were budgeted to be processed
2487  * during  one pass through the 'Poll" function.
2488  * Description:
2489  * Comes into picture only if NAPI support has been incorporated. It does
2490  * the same thing that rx_intr_handler does, but not in a interrupt context
2491  * also It will process only a given number of packets.
2492  * Return value:
2493  * 0 on success and 1 if there are No Rx packets to be processed.
2494  */
2495
2496 static int s2io_poll(struct net_device *dev, int *budget)
2497 {
2498         struct s2io_nic *nic = dev->priv;
2499         int pkt_cnt = 0, org_pkts_to_process;
2500         struct mac_info *mac_control;
2501         struct config_param *config;
2502         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2503         int i;
2504
2505         atomic_inc(&nic->isr_cnt);
2506         mac_control = &nic->mac_control;
2507         config = &nic->config;
2508
2509         nic->pkts_to_process = *budget;
2510         if (nic->pkts_to_process > dev->quota)
2511                 nic->pkts_to_process = dev->quota;
2512         org_pkts_to_process = nic->pkts_to_process;
2513
2514         writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2515         readl(&bar0->rx_traffic_int);
2516
2517         for (i = 0; i < config->rx_ring_num; i++) {
2518                 rx_intr_handler(&mac_control->rings[i]);
2519                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2520                 if (!nic->pkts_to_process) {
2521                         /* Quota for the current iteration has been met */
2522                         goto no_rx;
2523                 }
2524         }
2525         if (!pkt_cnt)
2526                 pkt_cnt = 1;
2527
2528         dev->quota -= pkt_cnt;
2529         *budget -= pkt_cnt;
2530         netif_rx_complete(dev);
2531
2532         for (i = 0; i < config->rx_ring_num; i++) {
2533                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2534                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2535                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2536                         break;
2537                 }
2538         }
2539         /* Re enable the Rx interrupts. */
2540         writeq(0x0, &bar0->rx_traffic_mask);
2541         readl(&bar0->rx_traffic_mask);
2542         atomic_dec(&nic->isr_cnt);
2543         return 0;
2544
2545 no_rx:
2546         dev->quota -= pkt_cnt;
2547         *budget -= pkt_cnt;
2548
2549         for (i = 0; i < config->rx_ring_num; i++) {
2550                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2551                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2552                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2553                         break;
2554                 }
2555         }
2556         atomic_dec(&nic->isr_cnt);
2557         return 1;
2558 }
2559
2560 #ifdef CONFIG_NET_POLL_CONTROLLER
2561 /**
2562  * s2io_netpoll - netpoll event handler entry point
2563  * @dev : pointer to the device structure.
2564  * Description:
2565  *      This function will be called by upper layer to check for events on the
2566  * interface in situations where interrupts are disabled. It is used for
2567  * specific in-kernel networking tasks, such as remote consoles and kernel
2568  * debugging over the network (example netdump in RedHat).
2569  */
2570 static void s2io_netpoll(struct net_device *dev)
2571 {
2572         struct s2io_nic *nic = dev->priv;
2573         struct mac_info *mac_control;
2574         struct config_param *config;
2575         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2576         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2577         int i;
2578
2579         disable_irq(dev->irq);
2580
2581         atomic_inc(&nic->isr_cnt);
2582         mac_control = &nic->mac_control;
2583         config = &nic->config;
2584
2585         writeq(val64, &bar0->rx_traffic_int);
2586         writeq(val64, &bar0->tx_traffic_int);
2587
2588         /* we need to free up the transmitted skbufs or else netpoll will
2589          * run out of skbs and will fail and eventually netpoll application such
2590          * as netdump will fail.
2591          */
2592         for (i = 0; i < config->tx_fifo_num; i++)
2593                 tx_intr_handler(&mac_control->fifos[i]);
2594
2595         /* check for received packet and indicate up to network */
2596         for (i = 0; i < config->rx_ring_num; i++)
2597                 rx_intr_handler(&mac_control->rings[i]);
2598
2599         for (i = 0; i < config->rx_ring_num; i++) {
2600                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2601                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2602                         DBG_PRINT(ERR_DBG, " in Rx Netpoll!!\n");
2603                         break;
2604                 }
2605         }
2606         atomic_dec(&nic->isr_cnt);
2607         enable_irq(dev->irq);
2608         return;
2609 }
2610 #endif
2611
2612 /**
2613  *  rx_intr_handler - Rx interrupt handler
2614  *  @nic: device private variable.
2615  *  Description:
2616  *  If the interrupt is because of a received frame or if the
2617  *  receive ring contains fresh as yet un-processed frames,this function is
2618  *  called. It picks out the RxD at which place the last Rx processing had
2619  *  stopped and sends the skb to the OSM's Rx handler and then increments
2620  *  the offset.
2621  *  Return Value:
2622  *  NONE.
2623  */
2624 static void rx_intr_handler(struct ring_info *ring_data)
2625 {
2626         struct s2io_nic *nic = ring_data->nic;
2627         struct net_device *dev = (struct net_device *) nic->dev;
2628         int get_block, put_block, put_offset;
2629         struct rx_curr_get_info get_info, put_info;
2630         struct RxD_t *rxdp;
2631         struct sk_buff *skb;
2632         int pkt_cnt = 0;
2633         int i;
2634
2635         spin_lock(&nic->rx_lock);
2636         if (atomic_read(&nic->card_state) == CARD_DOWN) {
2637                 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2638                           __FUNCTION__, dev->name);
2639                 spin_unlock(&nic->rx_lock);
2640                 return;
2641         }
2642
2643         get_info = ring_data->rx_curr_get_info;
2644         get_block = get_info.block_index;
2645         memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2646         put_block = put_info.block_index;
2647         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2648         if (!napi) {
2649                 spin_lock(&nic->put_lock);
2650                 put_offset = ring_data->put_pos;
2651                 spin_unlock(&nic->put_lock);
2652         } else
2653                 put_offset = ring_data->put_pos;
2654
2655         while (RXD_IS_UP2DT(rxdp)) {
2656                 /*
2657                  * If your are next to put index then it's
2658                  * FIFO full condition
2659                  */
2660                 if ((get_block == put_block) &&
2661                     (get_info.offset + 1) == put_info.offset) {
2662                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
2663                         break;
2664                 }
2665                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2666                 if (skb == NULL) {
2667                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2668                                   dev->name);
2669                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2670                         spin_unlock(&nic->rx_lock);
2671                         return;
2672                 }
2673                 if (nic->rxd_mode == RXD_MODE_1) {
2674                         pci_unmap_single(nic->pdev, (dma_addr_t)
2675                                  ((struct RxD1*)rxdp)->Buffer0_ptr,
2676                                  dev->mtu +
2677                                  HEADER_ETHERNET_II_802_3_SIZE +
2678                                  HEADER_802_2_SIZE +
2679                                  HEADER_SNAP_SIZE,
2680                                  PCI_DMA_FROMDEVICE);
2681                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2682                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2683                                  ((struct RxD3*)rxdp)->Buffer0_ptr,
2684                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
2685                         pci_unmap_single(nic->pdev, (dma_addr_t)
2686                                  ((struct RxD3*)rxdp)->Buffer2_ptr,
2687                                  dev->mtu + 4,
2688                                  PCI_DMA_FROMDEVICE);
2689                 } else {
2690                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2691                                          ((struct RxD3*)rxdp)->Buffer0_ptr, BUF0_LEN,
2692                                          PCI_DMA_FROMDEVICE);
2693                         pci_unmap_single(nic->pdev, (dma_addr_t)
2694                                          ((struct RxD3*)rxdp)->Buffer1_ptr,
2695                                          l3l4hdr_size + 4,
2696                                          PCI_DMA_FROMDEVICE);
2697                         pci_unmap_single(nic->pdev, (dma_addr_t)
2698                                          ((struct RxD3*)rxdp)->Buffer2_ptr,
2699                                          dev->mtu, PCI_DMA_FROMDEVICE);
2700                 }
2701                 prefetch(skb->data);
2702                 rx_osm_handler(ring_data, rxdp);
2703                 get_info.offset++;
2704                 ring_data->rx_curr_get_info.offset = get_info.offset;
2705                 rxdp = ring_data->rx_blocks[get_block].
2706                                 rxds[get_info.offset].virt_addr;
2707                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2708                         get_info.offset = 0;
2709                         ring_data->rx_curr_get_info.offset = get_info.offset;
2710                         get_block++;
2711                         if (get_block == ring_data->block_count)
2712                                 get_block = 0;
2713                         ring_data->rx_curr_get_info.block_index = get_block;
2714                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2715                 }
2716
2717                 nic->pkts_to_process -= 1;
2718                 if ((napi) && (!nic->pkts_to_process))
2719                         break;
2720                 pkt_cnt++;
2721                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2722                         break;
2723         }
2724         if (nic->lro) {
2725                 /* Clear all LRO sessions before exiting */
2726                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2727                         struct lro *lro = &nic->lro0_n[i];
2728                         if (lro->in_use) {
2729                                 update_L3L4_header(nic, lro);
2730                                 queue_rx_frame(lro->parent);
2731                                 clear_lro_session(lro);
2732                         }
2733                 }
2734         }
2735
2736         spin_unlock(&nic->rx_lock);
2737 }
2738
2739 /**
2740  *  tx_intr_handler - Transmit interrupt handler
2741  *  @nic : device private variable
2742  *  Description:
2743  *  If an interrupt was raised to indicate DMA complete of the
2744  *  Tx packet, this function is called. It identifies the last TxD
2745  *  whose buffer was freed and frees all skbs whose data have already
2746  *  DMA'ed into the NICs internal memory.
2747  *  Return Value:
2748  *  NONE
2749  */
2750
2751 static void tx_intr_handler(struct fifo_info *fifo_data)
2752 {
2753         struct s2io_nic *nic = fifo_data->nic;
2754         struct net_device *dev = (struct net_device *) nic->dev;
2755         struct tx_curr_get_info get_info, put_info;
2756         struct sk_buff *skb;
2757         struct TxD *txdlp;
2758
2759         get_info = fifo_data->tx_curr_get_info;
2760         memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
2761         txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
2762             list_virt_addr;
2763         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2764                (get_info.offset != put_info.offset) &&
2765                (txdlp->Host_Control)) {
2766                 /* Check for TxD errors */
2767                 if (txdlp->Control_1 & TXD_T_CODE) {
2768                         unsigned long long err;
2769                         err = txdlp->Control_1 & TXD_T_CODE;
2770                         if (err & 0x1) {
2771                                 nic->mac_control.stats_info->sw_stat.
2772                                                 parity_err_cnt++;
2773                         }
2774                         if ((err >> 48) == 0xA) {
2775                                 DBG_PRINT(TX_DBG, "TxD returned due \
2776                                                 to loss of link\n");
2777                         }
2778                         else {
2779                                 DBG_PRINT(ERR_DBG, "***TxD error %llx\n", err);
2780                         }
2781                 }
2782
2783                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2784                 if (skb == NULL) {
2785                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
2786                         __FUNCTION__);
2787                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2788                         return;
2789                 }
2790
2791                 /* Updating the statistics block */
2792                 nic->stats.tx_bytes += skb->len;
2793                 dev_kfree_skb_irq(skb);
2794
2795                 get_info.offset++;
2796                 if (get_info.offset == get_info.fifo_len + 1)
2797                         get_info.offset = 0;
2798                 txdlp = (struct TxD *) fifo_data->list_info
2799                     [get_info.offset].list_virt_addr;
2800                 fifo_data->tx_curr_get_info.offset =
2801                     get_info.offset;
2802         }
2803
2804         spin_lock(&nic->tx_lock);
2805         if (netif_queue_stopped(dev))
2806                 netif_wake_queue(dev);
2807         spin_unlock(&nic->tx_lock);
2808 }
2809
2810 /**
2811  *  s2io_mdio_write - Function to write in to MDIO registers
2812  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2813  *  @addr     : address value
2814  *  @value    : data value
2815  *  @dev      : pointer to net_device structure
2816  *  Description:
2817  *  This function is used to write values to the MDIO registers
2818  *  NONE
2819  */
2820 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2821 {
2822         u64 val64 = 0x0;
2823         struct s2io_nic *sp = dev->priv;
2824         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2825
2826         //address transaction
2827         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2828                         | MDIO_MMD_DEV_ADDR(mmd_type)
2829                         | MDIO_MMS_PRT_ADDR(0x0);
2830         writeq(val64, &bar0->mdio_control);
2831         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2832         writeq(val64, &bar0->mdio_control);
2833         udelay(100);
2834
2835         //Data transaction
2836         val64 = 0x0;
2837         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2838                         | MDIO_MMD_DEV_ADDR(mmd_type)
2839                         | MDIO_MMS_PRT_ADDR(0x0)
2840                         | MDIO_MDIO_DATA(value)
2841                         | MDIO_OP(MDIO_OP_WRITE_TRANS);
2842         writeq(val64, &bar0->mdio_control);
2843         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2844         writeq(val64, &bar0->mdio_control);
2845         udelay(100);
2846
2847         val64 = 0x0;
2848         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2849         | MDIO_MMD_DEV_ADDR(mmd_type)
2850         | MDIO_MMS_PRT_ADDR(0x0)
2851         | MDIO_OP(MDIO_OP_READ_TRANS);
2852         writeq(val64, &bar0->mdio_control);
2853         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2854         writeq(val64, &bar0->mdio_control);
2855         udelay(100);
2856
2857 }
2858
2859 /**
2860  *  s2io_mdio_read - Function to write in to MDIO registers
2861  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2862  *  @addr     : address value
2863  *  @dev      : pointer to net_device structure
2864  *  Description:
2865  *  This function is used to read values to the MDIO registers
2866  *  NONE
2867  */
2868 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
2869 {
2870         u64 val64 = 0x0;
2871         u64 rval64 = 0x0;
2872         struct s2io_nic *sp = dev->priv;
2873         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2874
2875         /* address transaction */
2876         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2877                         | MDIO_MMD_DEV_ADDR(mmd_type)
2878                         | MDIO_MMS_PRT_ADDR(0x0);
2879         writeq(val64, &bar0->mdio_control);
2880         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2881         writeq(val64, &bar0->mdio_control);
2882         udelay(100);
2883
2884         /* Data transaction */
2885         val64 = 0x0;
2886         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2887                         | MDIO_MMD_DEV_ADDR(mmd_type)
2888                         | MDIO_MMS_PRT_ADDR(0x0)
2889                         | MDIO_OP(MDIO_OP_READ_TRANS);
2890         writeq(val64, &bar0->mdio_control);
2891         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2892         writeq(val64, &bar0->mdio_control);
2893         udelay(100);
2894
2895         /* Read the value from regs */
2896         rval64 = readq(&bar0->mdio_control);
2897         rval64 = rval64 & 0xFFFF0000;
2898         rval64 = rval64 >> 16;
2899         return rval64;
2900 }
2901 /**
2902  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
2903  *  @counter      : couter value to be updated
2904  *  @flag         : flag to indicate the status
2905  *  @type         : counter type
2906  *  Description:
2907  *  This function is to check the status of the xpak counters value
2908  *  NONE
2909  */
2910
2911 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
2912 {
2913         u64 mask = 0x3;
2914         u64 val64;
2915         int i;
2916         for(i = 0; i <index; i++)
2917                 mask = mask << 0x2;
2918
2919         if(flag > 0)
2920         {
2921                 *counter = *counter + 1;
2922                 val64 = *regs_stat & mask;
2923                 val64 = val64 >> (index * 0x2);
2924                 val64 = val64 + 1;
2925                 if(val64 == 3)
2926                 {
2927                         switch(type)
2928                         {
2929                         case 1:
2930                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
2931                                           "service. Excessive temperatures may "
2932                                           "result in premature transceiver "
2933                                           "failure \n");
2934                         break;
2935                         case 2:
2936                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
2937                                           "service Excessive bias currents may "
2938                                           "indicate imminent laser diode "
2939                                           "failure \n");
2940                         break;
2941                         case 3:
2942                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
2943                                           "service Excessive laser output "
2944                                           "power may saturate far-end "
2945                                           "receiver\n");
2946                         break;
2947                         default:
2948                                 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
2949                                           "type \n");
2950                         }
2951                         val64 = 0x0;
2952                 }
2953                 val64 = val64 << (index * 0x2);
2954                 *regs_stat = (*regs_stat & (~mask)) | (val64);
2955
2956         } else {
2957                 *regs_stat = *regs_stat & (~mask);
2958         }
2959 }
2960
2961 /**
2962  *  s2io_updt_xpak_counter - Function to update the xpak counters
2963  *  @dev         : pointer to net_device struct
2964  *  Description:
2965  *  This function is to upate the status of the xpak counters value
2966  *  NONE
2967  */
2968 static void s2io_updt_xpak_counter(struct net_device *dev)
2969 {
2970         u16 flag  = 0x0;
2971         u16 type  = 0x0;
2972         u16 val16 = 0x0;
2973         u64 val64 = 0x0;
2974         u64 addr  = 0x0;
2975
2976         struct s2io_nic *sp = dev->priv;
2977         struct stat_block *stat_info = sp->mac_control.stats_info;
2978
2979         /* Check the communication with the MDIO slave */
2980         addr = 0x0000;
2981         val64 = 0x0;
2982         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
2983         if((val64 == 0xFFFF) || (val64 == 0x0000))
2984         {
2985                 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
2986                           "Returned %llx\n", (unsigned long long)val64);
2987                 return;
2988         }
2989
2990         /* Check for the expecte value of 2040 at PMA address 0x0000 */
2991         if(val64 != 0x2040)
2992         {
2993                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
2994                 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
2995                           (unsigned long long)val64);
2996                 return;
2997         }
2998
2999         /* Loading the DOM register to MDIO register */
3000         addr = 0xA100;
3001         s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3002         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3003
3004         /* Reading the Alarm flags */
3005         addr = 0xA070;
3006         val64 = 0x0;
3007         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3008
3009         flag = CHECKBIT(val64, 0x7);
3010         type = 1;
3011         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3012                                 &stat_info->xpak_stat.xpak_regs_stat,
3013                                 0x0, flag, type);
3014
3015         if(CHECKBIT(val64, 0x6))
3016                 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3017
3018         flag = CHECKBIT(val64, 0x3);
3019         type = 2;
3020         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3021                                 &stat_info->xpak_stat.xpak_regs_stat,
3022                                 0x2, flag, type);
3023
3024         if(CHECKBIT(val64, 0x2))
3025                 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3026
3027         flag = CHECKBIT(val64, 0x1);
3028         type = 3;
3029         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3030                                 &stat_info->xpak_stat.xpak_regs_stat,
3031                                 0x4, flag, type);
3032
3033         if(CHECKBIT(val64, 0x0))
3034                 stat_info->xpak_stat.alarm_laser_output_power_low++;
3035
3036         /* Reading the Warning flags */
3037         addr = 0xA074;
3038         val64 = 0x0;
3039         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3040
3041         if(CHECKBIT(val64, 0x7))
3042                 stat_info->xpak_stat.warn_transceiver_temp_high++;
3043
3044         if(CHECKBIT(val64, 0x6))
3045                 stat_info->xpak_stat.warn_transceiver_temp_low++;
3046
3047         if(CHECKBIT(val64, 0x3))
3048                 stat_info->xpak_stat.warn_laser_bias_current_high++;
3049
3050         if(CHECKBIT(val64, 0x2))
3051                 stat_info->xpak_stat.warn_laser_bias_current_low++;
3052
3053         if(CHECKBIT(val64, 0x1))
3054                 stat_info->xpak_stat.warn_laser_output_power_high++;
3055
3056         if(CHECKBIT(val64, 0x0))
3057                 stat_info->xpak_stat.warn_laser_output_power_low++;
3058 }
3059
3060 /**
3061  *  alarm_intr_handler - Alarm Interrrupt handler
3062  *  @nic: device private variable
3063  *  Description: If the interrupt was neither because of Rx packet or Tx
3064  *  complete, this function is called. If the interrupt was to indicate
3065  *  a loss of link, the OSM link status handler is invoked for any other
3066  *  alarm interrupt the block that raised the interrupt is displayed
3067  *  and a H/W reset is issued.
3068  *  Return Value:
3069  *  NONE
3070 */
3071
3072 static void alarm_intr_handler(struct s2io_nic *nic)
3073 {
3074         struct net_device *dev = (struct net_device *) nic->dev;
3075         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3076         register u64 val64 = 0, err_reg = 0;
3077         u64 cnt;
3078         int i;
3079         if (atomic_read(&nic->card_state) == CARD_DOWN)
3080                 return;
3081         nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3082         /* Handling the XPAK counters update */
3083         if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3084                 /* waiting for an hour */
3085                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3086         } else {
3087                 s2io_updt_xpak_counter(dev);
3088                 /* reset the count to zero */
3089                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3090         }
3091
3092         /* Handling link status change error Intr */
3093         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3094                 err_reg = readq(&bar0->mac_rmac_err_reg);
3095                 writeq(err_reg, &bar0->mac_rmac_err_reg);
3096                 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3097                         schedule_work(&nic->set_link_task);
3098                 }
3099         }
3100
3101         /* Handling Ecc errors */
3102         val64 = readq(&bar0->mc_err_reg);
3103         writeq(val64, &bar0->mc_err_reg);
3104         if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
3105                 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
3106                         nic->mac_control.stats_info->sw_stat.
3107                                 double_ecc_errs++;
3108                         DBG_PRINT(INIT_DBG, "%s: Device indicates ",
3109                                   dev->name);
3110                         DBG_PRINT(INIT_DBG, "double ECC error!!\n");
3111                         if (nic->device_type != XFRAME_II_DEVICE) {
3112                                 /* Reset XframeI only if critical error */
3113                                 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
3114                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
3115                                         netif_stop_queue(dev);
3116                                         schedule_work(&nic->rst_timer_task);
3117                                         nic->mac_control.stats_info->sw_stat.
3118                                                         soft_reset_cnt++;
3119                                 }
3120                         }
3121                 } else {
3122                         nic->mac_control.stats_info->sw_stat.
3123                                 single_ecc_errs++;
3124                 }
3125         }
3126
3127         /* In case of a serious error, the device will be Reset. */
3128         val64 = readq(&bar0->serr_source);
3129         if (val64 & SERR_SOURCE_ANY) {
3130                 nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
3131                 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
3132                 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
3133                           (unsigned long long)val64);
3134                 netif_stop_queue(dev);
3135                 schedule_work(&nic->rst_timer_task);
3136                 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3137         }
3138
3139         /*
3140          * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3141          * Error occurs, the adapter will be recycled by disabling the
3142          * adapter enable bit and enabling it again after the device
3143          * becomes Quiescent.
3144          */
3145         val64 = readq(&bar0->pcc_err_reg);
3146         writeq(val64, &bar0->pcc_err_reg);
3147         if (val64 & PCC_FB_ECC_DB_ERR) {
3148                 u64 ac = readq(&bar0->adapter_control);
3149                 ac &= ~(ADAPTER_CNTL_EN);
3150                 writeq(ac, &bar0->adapter_control);
3151                 ac = readq(&bar0->adapter_control);
3152                 schedule_work(&nic->set_link_task);
3153         }
3154         /* Check for data parity error */
3155         val64 = readq(&bar0->pic_int_status);
3156         if (val64 & PIC_INT_GPIO) {
3157                 val64 = readq(&bar0->gpio_int_reg);
3158                 if (val64 & GPIO_INT_REG_DP_ERR_INT) {
3159                         nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
3160                         schedule_work(&nic->rst_timer_task);
3161                         nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3162                 }
3163         }
3164
3165         /* Check for ring full counter */
3166         if (nic->device_type & XFRAME_II_DEVICE) {
3167                 val64 = readq(&bar0->ring_bump_counter1);
3168                 for (i=0; i<4; i++) {
3169                         cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3170                         cnt >>= 64 - ((i+1)*16);
3171                         nic->mac_control.stats_info->sw_stat.ring_full_cnt
3172                                 += cnt;
3173                 }
3174
3175                 val64 = readq(&bar0->ring_bump_counter2);
3176                 for (i=0; i<4; i++) {
3177                         cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3178                         cnt >>= 64 - ((i+1)*16);
3179                         nic->mac_control.stats_info->sw_stat.ring_full_cnt
3180                                 += cnt;
3181                 }
3182         }
3183
3184         /* Other type of interrupts are not being handled now,  TODO */
3185 }
3186
3187 /**
3188  *  wait_for_cmd_complete - waits for a command to complete.
3189  *  @sp : private member of the device structure, which is a pointer to the
3190  *  s2io_nic structure.
3191  *  Description: Function that waits for a command to Write into RMAC
3192  *  ADDR DATA registers to be completed and returns either success or
3193  *  error depending on whether the command was complete or not.
3194  *  Return value:
3195  *   SUCCESS on success and FAILURE on failure.
3196  */
3197
3198 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit)
3199 {
3200         int ret = FAILURE, cnt = 0;
3201         u64 val64;
3202
3203         while (TRUE) {
3204                 val64 = readq(addr);
3205                 if (!(val64 & busy_bit)) {
3206                         ret = SUCCESS;
3207                         break;
3208                 }
3209
3210                 if(in_interrupt())
3211                         mdelay(50);
3212                 else
3213                         msleep(50);
3214
3215                 if (cnt++ > 10)
3216                         break;
3217         }
3218         return ret;
3219 }
3220 /*
3221  * check_pci_device_id - Checks if the device id is supported
3222  * @id : device id
3223  * Description: Function to check if the pci device id is supported by driver.
3224  * Return value: Actual device id if supported else PCI_ANY_ID
3225  */
3226 static u16 check_pci_device_id(u16 id)
3227 {
3228         switch (id) {
3229         case PCI_DEVICE_ID_HERC_WIN:
3230         case PCI_DEVICE_ID_HERC_UNI:
3231                 return XFRAME_II_DEVICE;
3232         case PCI_DEVICE_ID_S2IO_UNI:
3233         case PCI_DEVICE_ID_S2IO_WIN:
3234                 return XFRAME_I_DEVICE;
3235         default:
3236                 return PCI_ANY_ID;
3237         }
3238 }
3239
3240 /**
3241  *  s2io_reset - Resets the card.
3242  *  @sp : private member of the device structure.
3243  *  Description: Function to Reset the card. This function then also
3244  *  restores the previously saved PCI configuration space registers as
3245  *  the card reset also resets the configuration space.
3246  *  Return value:
3247  *  void.
3248  */
3249
3250 static void s2io_reset(struct s2io_nic * sp)
3251 {
3252         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3253         u64 val64;
3254         u16 subid, pci_cmd;
3255         int i;
3256         u16 val16;
3257         DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3258                         __FUNCTION__, sp->dev->name);
3259
3260         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3261         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3262
3263         if (sp->device_type == XFRAME_II_DEVICE) {
3264                 int ret;
3265                 ret = pci_set_power_state(sp->pdev, 3);
3266                 if (!ret)
3267                         ret = pci_set_power_state(sp->pdev, 0);
3268                 else {
3269                         DBG_PRINT(ERR_DBG,"%s PME based SW_Reset failed!\n",
3270                                         __FUNCTION__);
3271                         goto old_way;
3272                 }
3273                 msleep(20);
3274                 goto new_way;
3275         }
3276 old_way:
3277         val64 = SW_RESET_ALL;
3278         writeq(val64, &bar0->sw_reset);
3279 new_way:
3280         if (strstr(sp->product_name, "CX4")) {
3281                 msleep(750);
3282         }
3283         msleep(250);
3284         for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3285
3286                 /* Restore the PCI state saved during initialization. */
3287                 pci_restore_state(sp->pdev);
3288                 pci_read_config_word(sp->pdev, 0x2, &val16);
3289                 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3290                         break;
3291                 msleep(200);
3292         }
3293
3294         if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3295                 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3296         }
3297
3298         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3299
3300         s2io_init_pci(sp);
3301
3302         /* Set swapper to enable I/O register access */
3303         s2io_set_swapper(sp);
3304
3305         /* Restore the MSIX table entries from local variables */
3306         restore_xmsi_data(sp);
3307
3308         /* Clear certain PCI/PCI-X fields after reset */
3309         if (sp->device_type == XFRAME_II_DEVICE) {
3310                 /* Clear "detected parity error" bit */
3311                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3312
3313                 /* Clearing PCIX Ecc status register */
3314                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3315
3316                 /* Clearing PCI_STATUS error reflected here */
3317                 writeq(BIT(62), &bar0->txpic_int_reg);
3318         }
3319
3320         /* Reset device statistics maintained by OS */
3321         memset(&sp->stats, 0, sizeof (struct net_device_stats));
3322
3323         /* SXE-002: Configure link and activity LED to turn it off */
3324         subid = sp->pdev->subsystem_device;
3325         if (((subid & 0xFF) >= 0x07) &&
3326             (sp->device_type == XFRAME_I_DEVICE)) {
3327                 val64 = readq(&bar0->gpio_control);
3328                 val64 |= 0x0000800000000000ULL;
3329                 writeq(val64, &bar0->gpio_control);
3330                 val64 = 0x0411040400000000ULL;
3331                 writeq(val64, (void __iomem *)bar0 + 0x2700);
3332         }
3333
3334         /*
3335          * Clear spurious ECC interrupts that would have occured on
3336          * XFRAME II cards after reset.
3337          */
3338         if (sp->device_type == XFRAME_II_DEVICE) {
3339                 val64 = readq(&bar0->pcc_err_reg);
3340                 writeq(val64, &bar0->pcc_err_reg);
3341         }
3342
3343         sp->device_enabled_once = FALSE;
3344 }
3345
3346 /**
3347  *  s2io_set_swapper - to set the swapper controle on the card
3348  *  @sp : private member of the device structure,
3349  *  pointer to the s2io_nic structure.
3350  *  Description: Function to set the swapper control on the card
3351  *  correctly depending on the 'endianness' of the system.
3352  *  Return value:
3353  *  SUCCESS on success and FAILURE on failure.
3354  */
3355
3356 static int s2io_set_swapper(struct s2io_nic * sp)
3357 {
3358         struct net_device *dev = sp->dev;
3359         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3360         u64 val64, valt, valr;
3361
3362         /*
3363          * Set proper endian settings and verify the same by reading
3364          * the PIF Feed-back register.
3365          */
3366
3367         val64 = readq(&bar0->pif_rd_swapper_fb);
3368         if (val64 != 0x0123456789ABCDEFULL) {
3369                 int i = 0;
3370                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
3371                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
3372                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
3373                                 0};                     /* FE=0, SE=0 */
3374
3375                 while(i<4) {
3376                         writeq(value[i], &bar0->swapper_ctrl);
3377                         val64 = readq(&bar0->pif_rd_swapper_fb);
3378                         if (val64 == 0x0123456789ABCDEFULL)
3379                                 break;
3380                         i++;
3381                 }
3382                 if (i == 4) {
3383                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3384                                 dev->name);
3385                         DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3386                                 (unsigned long long) val64);
3387                         return FAILURE;
3388                 }
3389                 valr = value[i];
3390         } else {
3391                 valr = readq(&bar0->swapper_ctrl);
3392         }
3393
3394         valt = 0x0123456789ABCDEFULL;
3395         writeq(valt, &bar0->xmsi_address);
3396         val64 = readq(&bar0->xmsi_address);
3397
3398         if(val64 != valt) {
3399                 int i = 0;
3400                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3401                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
3402                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
3403                                 0};                     /* FE=0, SE=0 */
3404
3405                 while(i<4) {
3406                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3407                         writeq(valt, &bar0->xmsi_address);
3408                         val64 = readq(&bar0->xmsi_address);
3409                         if(val64 == valt)
3410                                 break;
3411                         i++;
3412                 }
3413                 if(i == 4) {
3414                         unsigned long long x = val64;
3415                         DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3416                         DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3417                         return FAILURE;
3418                 }
3419         }
3420         val64 = readq(&bar0->swapper_ctrl);
3421         val64 &= 0xFFFF000000000000ULL;
3422
3423 #ifdef  __BIG_ENDIAN
3424         /*
3425          * The device by default set to a big endian format, so a
3426          * big endian driver need not set anything.
3427          */
3428         val64 |= (SWAPPER_CTRL_TXP_FE |
3429                  SWAPPER_CTRL_TXP_SE |
3430                  SWAPPER_CTRL_TXD_R_FE |
3431                  SWAPPER_CTRL_TXD_W_FE |
3432                  SWAPPER_CTRL_TXF_R_FE |
3433                  SWAPPER_CTRL_RXD_R_FE |
3434                  SWAPPER_CTRL_RXD_W_FE |
3435                  SWAPPER_CTRL_RXF_W_FE |
3436                  SWAPPER_CTRL_XMSI_FE |
3437                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3438         if (sp->intr_type == INTA)
3439                 val64 |= SWAPPER_CTRL_XMSI_SE;
3440         writeq(val64, &bar0->swapper_ctrl);
3441 #else
3442         /*
3443          * Initially we enable all bits to make it accessible by the
3444          * driver, then we selectively enable only those bits that
3445          * we want to set.
3446          */
3447         val64 |= (SWAPPER_CTRL_TXP_FE |
3448                  SWAPPER_CTRL_TXP_SE |
3449                  SWAPPER_CTRL_TXD_R_FE |
3450                  SWAPPER_CTRL_TXD_R_SE |
3451                  SWAPPER_CTRL_TXD_W_FE |
3452                  SWAPPER_CTRL_TXD_W_SE |
3453                  SWAPPER_CTRL_TXF_R_FE |
3454                  SWAPPER_CTRL_RXD_R_FE |
3455                  SWAPPER_CTRL_RXD_R_SE |
3456                  SWAPPER_CTRL_RXD_W_FE |
3457                  SWAPPER_CTRL_RXD_W_SE |
3458                  SWAPPER_CTRL_RXF_W_FE |
3459                  SWAPPER_CTRL_XMSI_FE |
3460                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3461         if (sp->intr_type == INTA)
3462                 val64 |= SWAPPER_CTRL_XMSI_SE;
3463         writeq(val64, &bar0->swapper_ctrl);
3464 #endif
3465         val64 = readq(&bar0->swapper_ctrl);
3466
3467         /*
3468          * Verifying if endian settings are accurate by reading a
3469          * feedback register.
3470          */
3471         val64 = readq(&bar0->pif_rd_swapper_fb);
3472         if (val64 != 0x0123456789ABCDEFULL) {
3473                 /* Endian settings are incorrect, calls for another dekko. */
3474                 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3475                           dev->name);
3476                 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3477                           (unsigned long long) val64);
3478                 return FAILURE;
3479         }
3480
3481         return SUCCESS;
3482 }
3483
3484 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3485 {
3486         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3487         u64 val64;
3488         int ret = 0, cnt = 0;
3489
3490         do {
3491                 val64 = readq(&bar0->xmsi_access);
3492                 if (!(val64 & BIT(15)))
3493                         break;
3494                 mdelay(1);
3495                 cnt++;
3496         } while(cnt < 5);
3497         if (cnt == 5) {
3498                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3499                 ret = 1;
3500         }
3501
3502         return ret;
3503 }
3504
3505 static void restore_xmsi_data(struct s2io_nic *nic)
3506 {
3507         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3508         u64 val64;
3509         int i;
3510
3511         for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3512                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3513                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3514                 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3515                 writeq(val64, &bar0->xmsi_access);
3516                 if (wait_for_msix_trans(nic, i)) {
3517                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3518                         continue;
3519                 }
3520         }
3521 }
3522
3523 static void store_xmsi_data(struct s2io_nic *nic)
3524 {
3525         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3526         u64 val64, addr, data;
3527         int i;
3528
3529         /* Store and display */
3530         for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3531                 val64 = (BIT(15) | vBIT(i, 26, 6));
3532                 writeq(val64, &bar0->xmsi_access);
3533                 if (wait_for_msix_trans(nic, i)) {
3534                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3535                         continue;
3536                 }
3537                 addr = readq(&bar0->xmsi_address);
3538                 data = readq(&bar0->xmsi_data);
3539                 if (addr && data) {
3540                         nic->msix_info[i].addr = addr;
3541                         nic->msix_info[i].data = data;
3542                 }
3543         }
3544 }
3545
3546 int s2io_enable_msi(struct s2io_nic *nic)
3547 {
3548         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3549         u16 msi_ctrl, msg_val;
3550         struct config_param *config = &nic->config;
3551         struct net_device *dev = nic->dev;
3552         u64 val64, tx_mat, rx_mat;
3553         int i, err;
3554
3555         val64 = readq(&bar0->pic_control);
3556         val64 &= ~BIT(1);
3557         writeq(val64, &bar0->pic_control);
3558
3559         err = pci_enable_msi(nic->pdev);
3560         if (err) {
3561                 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3562                           nic->dev->name);
3563                 return err;
3564         }
3565
3566         /*
3567          * Enable MSI and use MSI-1 in stead of the standard MSI-0
3568          * for interrupt handling.
3569          */
3570         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3571         msg_val ^= 0x1;
3572         pci_write_config_word(nic->pdev, 0x4c, msg_val);
3573         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3574
3575         pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3576         msi_ctrl |= 0x10;
3577         pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3578
3579         /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3580         tx_mat = readq(&bar0->tx_mat0_n[0]);
3581         for (i=0; i<config->tx_fifo_num; i++) {
3582                 tx_mat |= TX_MAT_SET(i, 1);
3583         }
3584         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3585
3586         rx_mat = readq(&bar0->rx_mat);
3587         for (i=0; i<config->rx_ring_num; i++) {
3588                 rx_mat |= RX_MAT_SET(i, 1);
3589         }
3590         writeq(rx_mat, &bar0->rx_mat);
3591
3592         dev->irq = nic->pdev->irq;
3593         return 0;
3594 }
3595
3596 static int s2io_enable_msi_x(struct s2io_nic *nic)
3597 {
3598         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3599         u64 tx_mat, rx_mat;
3600         u16 msi_control; /* Temp variable */
3601         int ret, i, j, msix_indx = 1;
3602
3603         nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3604                                GFP_KERNEL);
3605         if (nic->entries == NULL) {
3606                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3607                 return -ENOMEM;
3608         }
3609         memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3610
3611         nic->s2io_entries =
3612                 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3613                                    GFP_KERNEL);
3614         if (nic->s2io_entries == NULL) {
3615                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3616                 kfree(nic->entries);
3617                 return -ENOMEM;
3618         }
3619         memset(nic->s2io_entries, 0,
3620                MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3621
3622         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3623                 nic->entries[i].entry = i;
3624                 nic->s2io_entries[i].entry = i;
3625                 nic->s2io_entries[i].arg = NULL;
3626                 nic->s2io_entries[i].in_use = 0;