s2io: Removed enabling of some of the unused interrupts.
[linux-3.10.git] / drivers / net / s2io.c
1 /************************************************************************
2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3  * Copyright(c) 2002-2005 Neterion Inc.
4
5  * This software may be used and distributed according to the terms of
6  * the GNU General Public License (GPL), incorporated herein by reference.
7  * Drivers based on or derived from this code fall under the GPL and must
8  * retain the authorship, copyright and license notice.  This file is not
9  * a complete program and may only be used when the entire operating
10  * system is licensed under the GPL.
11  * See the file COPYING in this distribution for more information.
12  *
13  * Credits:
14  * Jeff Garzik          : For pointing out the improper error condition
15  *                        check in the s2io_xmit routine and also some
16  *                        issues in the Tx watch dog function. Also for
17  *                        patiently answering all those innumerable
18  *                        questions regaring the 2.6 porting issues.
19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
20  *                        macros available only in 2.6 Kernel.
21  * Francois Romieu      : For pointing out all code part that were
22  *                        deprecated and also styling related comments.
23  * Grant Grundler       : For helping me get rid of some Architecture
24  *                        dependent code.
25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
26  *
27  * The module loadable parameters that are supported by the driver and a brief
28  * explaination of all the variables.
29  *
30  * rx_ring_num : This can be used to program the number of receive rings used
31  * in the driver.
32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
33  *     This is also an array of size 8.
34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35  *              values are 1, 2 and 3.
36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
38  * Tx descriptors that can be associated with each corresponding FIFO.
39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40  *     1(MSI), 2(MSI_X). Default value is '0(INTA)'
41  * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42  *     Possible values '1' for enable '0' for disable. Default is '0'
43  * lro_max_pkts: This parameter defines maximum number of packets can be
44  *     aggregated as a single large packet
45  ************************************************************************/
46
47 #include <linux/module.h>
48 #include <linux/types.h>
49 #include <linux/errno.h>
50 #include <linux/ioport.h>
51 #include <linux/pci.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/kernel.h>
54 #include <linux/netdevice.h>
55 #include <linux/etherdevice.h>
56 #include <linux/skbuff.h>
57 #include <linux/init.h>
58 #include <linux/delay.h>
59 #include <linux/stddef.h>
60 #include <linux/ioctl.h>
61 #include <linux/timex.h>
62 #include <linux/sched.h>
63 #include <linux/ethtool.h>
64 #include <linux/workqueue.h>
65 #include <linux/if_vlan.h>
66 #include <linux/ip.h>
67 #include <linux/tcp.h>
68 #include <net/tcp.h>
69
70 #include <asm/system.h>
71 #include <asm/uaccess.h>
72 #include <asm/io.h>
73 #include <asm/div64.h>
74 #include <asm/irq.h>
75
76 /* local include */
77 #include "s2io.h"
78 #include "s2io-regs.h"
79
80 #define DRV_VERSION "2.0.15.2"
81
82 /* S2io Driver name & version. */
83 static char s2io_driver_name[] = "Neterion";
84 static char s2io_driver_version[] = DRV_VERSION;
85
86 static int rxd_size[4] = {32,48,48,64};
87 static int rxd_count[4] = {127,85,85,63};
88
89 static inline int RXD_IS_UP2DT(RxD_t *rxdp)
90 {
91         int ret;
92
93         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
94                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
95
96         return ret;
97 }
98
99 /*
100  * Cards with following subsystem_id have a link state indication
101  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
102  * macro below identifies these cards given the subsystem_id.
103  */
104 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
105         (dev_type == XFRAME_I_DEVICE) ?                 \
106                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
107                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
108
109 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
110                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
111 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
112 #define PANIC   1
113 #define LOW     2
114 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
115 {
116         mac_info_t *mac_control;
117
118         mac_control = &sp->mac_control;
119         if (rxb_size <= rxd_count[sp->rxd_mode])
120                 return PANIC;
121         else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
122                 return  LOW;
123         return 0;
124 }
125
126 /* Ethtool related variables and Macros. */
127 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
128         "Register test\t(offline)",
129         "Eeprom test\t(offline)",
130         "Link test\t(online)",
131         "RLDRAM test\t(offline)",
132         "BIST Test\t(offline)"
133 };
134
135 static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
136         {"tmac_frms"},
137         {"tmac_data_octets"},
138         {"tmac_drop_frms"},
139         {"tmac_mcst_frms"},
140         {"tmac_bcst_frms"},
141         {"tmac_pause_ctrl_frms"},
142         {"tmac_ttl_octets"},
143         {"tmac_ucst_frms"},
144         {"tmac_nucst_frms"},
145         {"tmac_any_err_frms"},
146         {"tmac_ttl_less_fb_octets"},
147         {"tmac_vld_ip_octets"},
148         {"tmac_vld_ip"},
149         {"tmac_drop_ip"},
150         {"tmac_icmp"},
151         {"tmac_rst_tcp"},
152         {"tmac_tcp"},
153         {"tmac_udp"},
154         {"rmac_vld_frms"},
155         {"rmac_data_octets"},
156         {"rmac_fcs_err_frms"},
157         {"rmac_drop_frms"},
158         {"rmac_vld_mcst_frms"},
159         {"rmac_vld_bcst_frms"},
160         {"rmac_in_rng_len_err_frms"},
161         {"rmac_out_rng_len_err_frms"},
162         {"rmac_long_frms"},
163         {"rmac_pause_ctrl_frms"},
164         {"rmac_unsup_ctrl_frms"},
165         {"rmac_ttl_octets"},
166         {"rmac_accepted_ucst_frms"},
167         {"rmac_accepted_nucst_frms"},
168         {"rmac_discarded_frms"},
169         {"rmac_drop_events"},
170         {"rmac_ttl_less_fb_octets"},
171         {"rmac_ttl_frms"},
172         {"rmac_usized_frms"},
173         {"rmac_osized_frms"},
174         {"rmac_frag_frms"},
175         {"rmac_jabber_frms"},
176         {"rmac_ttl_64_frms"},
177         {"rmac_ttl_65_127_frms"},
178         {"rmac_ttl_128_255_frms"},
179         {"rmac_ttl_256_511_frms"},
180         {"rmac_ttl_512_1023_frms"},
181         {"rmac_ttl_1024_1518_frms"},
182         {"rmac_ip"},
183         {"rmac_ip_octets"},
184         {"rmac_hdr_err_ip"},
185         {"rmac_drop_ip"},
186         {"rmac_icmp"},
187         {"rmac_tcp"},
188         {"rmac_udp"},
189         {"rmac_err_drp_udp"},
190         {"rmac_xgmii_err_sym"},
191         {"rmac_frms_q0"},
192         {"rmac_frms_q1"},
193         {"rmac_frms_q2"},
194         {"rmac_frms_q3"},
195         {"rmac_frms_q4"},
196         {"rmac_frms_q5"},
197         {"rmac_frms_q6"},
198         {"rmac_frms_q7"},
199         {"rmac_full_q0"},
200         {"rmac_full_q1"},
201         {"rmac_full_q2"},
202         {"rmac_full_q3"},
203         {"rmac_full_q4"},
204         {"rmac_full_q5"},
205         {"rmac_full_q6"},
206         {"rmac_full_q7"},
207         {"rmac_pause_cnt"},
208         {"rmac_xgmii_data_err_cnt"},
209         {"rmac_xgmii_ctrl_err_cnt"},
210         {"rmac_accepted_ip"},
211         {"rmac_err_tcp"},
212         {"rd_req_cnt"},
213         {"new_rd_req_cnt"},
214         {"new_rd_req_rtry_cnt"},
215         {"rd_rtry_cnt"},
216         {"wr_rtry_rd_ack_cnt"},
217         {"wr_req_cnt"},
218         {"new_wr_req_cnt"},
219         {"new_wr_req_rtry_cnt"},
220         {"wr_rtry_cnt"},
221         {"wr_disc_cnt"},
222         {"rd_rtry_wr_ack_cnt"},
223         {"txp_wr_cnt"},
224         {"txd_rd_cnt"},
225         {"txd_wr_cnt"},
226         {"rxd_rd_cnt"},
227         {"rxd_wr_cnt"},
228         {"txf_rd_cnt"},
229         {"rxf_wr_cnt"},
230         {"rmac_ttl_1519_4095_frms"},
231         {"rmac_ttl_4096_8191_frms"},
232         {"rmac_ttl_8192_max_frms"},
233         {"rmac_ttl_gt_max_frms"},
234         {"rmac_osized_alt_frms"},
235         {"rmac_jabber_alt_frms"},
236         {"rmac_gt_max_alt_frms"},
237         {"rmac_vlan_frms"},
238         {"rmac_len_discard"},
239         {"rmac_fcs_discard"},
240         {"rmac_pf_discard"},
241         {"rmac_da_discard"},
242         {"rmac_red_discard"},
243         {"rmac_rts_discard"},
244         {"rmac_ingm_full_discard"},
245         {"link_fault_cnt"},
246         {"\n DRIVER STATISTICS"},
247         {"single_bit_ecc_errs"},
248         {"double_bit_ecc_errs"},
249         {"parity_err_cnt"},
250         {"serious_err_cnt"},
251         {"soft_reset_cnt"},
252         {"fifo_full_cnt"},
253         {"ring_full_cnt"},
254         ("alarm_transceiver_temp_high"),
255         ("alarm_transceiver_temp_low"),
256         ("alarm_laser_bias_current_high"),
257         ("alarm_laser_bias_current_low"),
258         ("alarm_laser_output_power_high"),
259         ("alarm_laser_output_power_low"),
260         ("warn_transceiver_temp_high"),
261         ("warn_transceiver_temp_low"),
262         ("warn_laser_bias_current_high"),
263         ("warn_laser_bias_current_low"),
264         ("warn_laser_output_power_high"),
265         ("warn_laser_output_power_low"),
266         ("lro_aggregated_pkts"),
267         ("lro_flush_both_count"),
268         ("lro_out_of_sequence_pkts"),
269         ("lro_flush_due_to_max_pkts"),
270         ("lro_avg_aggr_pkts"),
271 };
272
273 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
274 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
275
276 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
277 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
278
279 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
280                         init_timer(&timer);                     \
281                         timer.function = handle;                \
282                         timer.data = (unsigned long) arg;       \
283                         mod_timer(&timer, (jiffies + exp))      \
284
285 /* Add the vlan */
286 static void s2io_vlan_rx_register(struct net_device *dev,
287                                         struct vlan_group *grp)
288 {
289         nic_t *nic = dev->priv;
290         unsigned long flags;
291
292         spin_lock_irqsave(&nic->tx_lock, flags);
293         nic->vlgrp = grp;
294         spin_unlock_irqrestore(&nic->tx_lock, flags);
295 }
296
297 /* Unregister the vlan */
298 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
299 {
300         nic_t *nic = dev->priv;
301         unsigned long flags;
302
303         spin_lock_irqsave(&nic->tx_lock, flags);
304         if (nic->vlgrp)
305                 nic->vlgrp->vlan_devices[vid] = NULL;
306         spin_unlock_irqrestore(&nic->tx_lock, flags);
307 }
308
309 /*
310  * Constants to be programmed into the Xena's registers, to configure
311  * the XAUI.
312  */
313
314 #define END_SIGN        0x0
315 static const u64 herc_act_dtx_cfg[] = {
316         /* Set address */
317         0x8000051536750000ULL, 0x80000515367500E0ULL,
318         /* Write data */
319         0x8000051536750004ULL, 0x80000515367500E4ULL,
320         /* Set address */
321         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
322         /* Write data */
323         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
324         /* Set address */
325         0x801205150D440000ULL, 0x801205150D4400E0ULL,
326         /* Write data */
327         0x801205150D440004ULL, 0x801205150D4400E4ULL,
328         /* Set address */
329         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
330         /* Write data */
331         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
332         /* Done */
333         END_SIGN
334 };
335
336 static const u64 xena_dtx_cfg[] = {
337         /* Set address */
338         0x8000051500000000ULL, 0x80000515000000E0ULL,
339         /* Write data */
340         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
341         /* Set address */
342         0x8001051500000000ULL, 0x80010515000000E0ULL,
343         /* Write data */
344         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
345         /* Set address */
346         0x8002051500000000ULL, 0x80020515000000E0ULL,
347         /* Write data */
348         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
349         END_SIGN
350 };
351
352 /*
353  * Constants for Fixing the MacAddress problem seen mostly on
354  * Alpha machines.
355  */
356 static const u64 fix_mac[] = {
357         0x0060000000000000ULL, 0x0060600000000000ULL,
358         0x0040600000000000ULL, 0x0000600000000000ULL,
359         0x0020600000000000ULL, 0x0060600000000000ULL,
360         0x0020600000000000ULL, 0x0060600000000000ULL,
361         0x0020600000000000ULL, 0x0060600000000000ULL,
362         0x0020600000000000ULL, 0x0060600000000000ULL,
363         0x0020600000000000ULL, 0x0060600000000000ULL,
364         0x0020600000000000ULL, 0x0060600000000000ULL,
365         0x0020600000000000ULL, 0x0060600000000000ULL,
366         0x0020600000000000ULL, 0x0060600000000000ULL,
367         0x0020600000000000ULL, 0x0060600000000000ULL,
368         0x0020600000000000ULL, 0x0060600000000000ULL,
369         0x0020600000000000ULL, 0x0000600000000000ULL,
370         0x0040600000000000ULL, 0x0060600000000000ULL,
371         END_SIGN
372 };
373
374 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
375 MODULE_LICENSE("GPL");
376 MODULE_VERSION(DRV_VERSION);
377
378
379 /* Module Loadable parameters. */
380 S2IO_PARM_INT(tx_fifo_num, 1);
381 S2IO_PARM_INT(rx_ring_num, 1);
382
383
384 S2IO_PARM_INT(rx_ring_mode, 1);
385 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
386 S2IO_PARM_INT(rmac_pause_time, 0x100);
387 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
388 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
389 S2IO_PARM_INT(shared_splits, 0);
390 S2IO_PARM_INT(tmac_util_period, 5);
391 S2IO_PARM_INT(rmac_util_period, 5);
392 S2IO_PARM_INT(bimodal, 0);
393 S2IO_PARM_INT(l3l4hdr_size, 128);
394 /* Frequency of Rx desc syncs expressed as power of 2 */
395 S2IO_PARM_INT(rxsync_frequency, 3);
396 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
397 S2IO_PARM_INT(intr_type, 0);
398 /* Large receive offload feature */
399 S2IO_PARM_INT(lro, 0);
400 /* Max pkts to be aggregated by LRO at one time. If not specified,
401  * aggregation happens until we hit max IP pkt size(64K)
402  */
403 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
404 S2IO_PARM_INT(indicate_max_pkts, 0);
405
406 S2IO_PARM_INT(napi, 1);
407 S2IO_PARM_INT(ufo, 0);
408
409 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
410     {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
411 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
412     {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
413 static unsigned int rts_frm_len[MAX_RX_RINGS] =
414     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
415
416 module_param_array(tx_fifo_len, uint, NULL, 0);
417 module_param_array(rx_ring_sz, uint, NULL, 0);
418 module_param_array(rts_frm_len, uint, NULL, 0);
419
420 /*
421  * S2IO device table.
422  * This table lists all the devices that this driver supports.
423  */
424 static struct pci_device_id s2io_tbl[] __devinitdata = {
425         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
426          PCI_ANY_ID, PCI_ANY_ID},
427         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
428          PCI_ANY_ID, PCI_ANY_ID},
429         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
430          PCI_ANY_ID, PCI_ANY_ID},
431         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
432          PCI_ANY_ID, PCI_ANY_ID},
433         {0,}
434 };
435
436 MODULE_DEVICE_TABLE(pci, s2io_tbl);
437
438 static struct pci_driver s2io_driver = {
439       .name = "S2IO",
440       .id_table = s2io_tbl,
441       .probe = s2io_init_nic,
442       .remove = __devexit_p(s2io_rem_nic),
443 };
444
445 /* A simplifier macro used both by init and free shared_mem Fns(). */
446 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
447
448 /**
449  * init_shared_mem - Allocation and Initialization of Memory
450  * @nic: Device private variable.
451  * Description: The function allocates all the memory areas shared
452  * between the NIC and the driver. This includes Tx descriptors,
453  * Rx descriptors and the statistics block.
454  */
455
456 static int init_shared_mem(struct s2io_nic *nic)
457 {
458         u32 size;
459         void *tmp_v_addr, *tmp_v_addr_next;
460         dma_addr_t tmp_p_addr, tmp_p_addr_next;
461         RxD_block_t *pre_rxd_blk = NULL;
462         int i, j, blk_cnt;
463         int lst_size, lst_per_page;
464         struct net_device *dev = nic->dev;
465         unsigned long tmp;
466         buffAdd_t *ba;
467
468         mac_info_t *mac_control;
469         struct config_param *config;
470
471         mac_control = &nic->mac_control;
472         config = &nic->config;
473
474
475         /* Allocation and initialization of TXDLs in FIOFs */
476         size = 0;
477         for (i = 0; i < config->tx_fifo_num; i++) {
478                 size += config->tx_cfg[i].fifo_len;
479         }
480         if (size > MAX_AVAILABLE_TXDS) {
481                 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
482                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
483                 return -EINVAL;
484         }
485
486         lst_size = (sizeof(TxD_t) * config->max_txds);
487         lst_per_page = PAGE_SIZE / lst_size;
488
489         for (i = 0; i < config->tx_fifo_num; i++) {
490                 int fifo_len = config->tx_cfg[i].fifo_len;
491                 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
492                 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
493                                                           GFP_KERNEL);
494                 if (!mac_control->fifos[i].list_info) {
495                         DBG_PRINT(ERR_DBG,
496                                   "Malloc failed for list_info\n");
497                         return -ENOMEM;
498                 }
499                 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
500         }
501         for (i = 0; i < config->tx_fifo_num; i++) {
502                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
503                                                 lst_per_page);
504                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
505                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
506                     config->tx_cfg[i].fifo_len - 1;
507                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
508                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
509                     config->tx_cfg[i].fifo_len - 1;
510                 mac_control->fifos[i].fifo_no = i;
511                 mac_control->fifos[i].nic = nic;
512                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
513
514                 for (j = 0; j < page_num; j++) {
515                         int k = 0;
516                         dma_addr_t tmp_p;
517                         void *tmp_v;
518                         tmp_v = pci_alloc_consistent(nic->pdev,
519                                                      PAGE_SIZE, &tmp_p);
520                         if (!tmp_v) {
521                                 DBG_PRINT(ERR_DBG,
522                                           "pci_alloc_consistent ");
523                                 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
524                                 return -ENOMEM;
525                         }
526                         /* If we got a zero DMA address(can happen on
527                          * certain platforms like PPC), reallocate.
528                          * Store virtual address of page we don't want,
529                          * to be freed later.
530                          */
531                         if (!tmp_p) {
532                                 mac_control->zerodma_virt_addr = tmp_v;
533                                 DBG_PRINT(INIT_DBG,
534                                 "%s: Zero DMA address for TxDL. ", dev->name);
535                                 DBG_PRINT(INIT_DBG,
536                                 "Virtual address %p\n", tmp_v);
537                                 tmp_v = pci_alloc_consistent(nic->pdev,
538                                                      PAGE_SIZE, &tmp_p);
539                                 if (!tmp_v) {
540                                         DBG_PRINT(ERR_DBG,
541                                           "pci_alloc_consistent ");
542                                         DBG_PRINT(ERR_DBG, "failed for TxDL\n");
543                                         return -ENOMEM;
544                                 }
545                         }
546                         while (k < lst_per_page) {
547                                 int l = (j * lst_per_page) + k;
548                                 if (l == config->tx_cfg[i].fifo_len)
549                                         break;
550                                 mac_control->fifos[i].list_info[l].list_virt_addr =
551                                     tmp_v + (k * lst_size);
552                                 mac_control->fifos[i].list_info[l].list_phy_addr =
553                                     tmp_p + (k * lst_size);
554                                 k++;
555                         }
556                 }
557         }
558
559         nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
560         if (!nic->ufo_in_band_v)
561                 return -ENOMEM;
562
563         /* Allocation and initialization of RXDs in Rings */
564         size = 0;
565         for (i = 0; i < config->rx_ring_num; i++) {
566                 if (config->rx_cfg[i].num_rxd %
567                     (rxd_count[nic->rxd_mode] + 1)) {
568                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
569                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
570                                   i);
571                         DBG_PRINT(ERR_DBG, "RxDs per Block");
572                         return FAILURE;
573                 }
574                 size += config->rx_cfg[i].num_rxd;
575                 mac_control->rings[i].block_count =
576                         config->rx_cfg[i].num_rxd /
577                         (rxd_count[nic->rxd_mode] + 1 );
578                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
579                         mac_control->rings[i].block_count;
580         }
581         if (nic->rxd_mode == RXD_MODE_1)
582                 size = (size * (sizeof(RxD1_t)));
583         else
584                 size = (size * (sizeof(RxD3_t)));
585
586         for (i = 0; i < config->rx_ring_num; i++) {
587                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
588                 mac_control->rings[i].rx_curr_get_info.offset = 0;
589                 mac_control->rings[i].rx_curr_get_info.ring_len =
590                     config->rx_cfg[i].num_rxd - 1;
591                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
592                 mac_control->rings[i].rx_curr_put_info.offset = 0;
593                 mac_control->rings[i].rx_curr_put_info.ring_len =
594                     config->rx_cfg[i].num_rxd - 1;
595                 mac_control->rings[i].nic = nic;
596                 mac_control->rings[i].ring_no = i;
597
598                 blk_cnt = config->rx_cfg[i].num_rxd /
599                                 (rxd_count[nic->rxd_mode] + 1);
600                 /*  Allocating all the Rx blocks */
601                 for (j = 0; j < blk_cnt; j++) {
602                         rx_block_info_t *rx_blocks;
603                         int l;
604
605                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
606                         size = SIZE_OF_BLOCK; //size is always page size
607                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
608                                                           &tmp_p_addr);
609                         if (tmp_v_addr == NULL) {
610                                 /*
611                                  * In case of failure, free_shared_mem()
612                                  * is called, which should free any
613                                  * memory that was alloced till the
614                                  * failure happened.
615                                  */
616                                 rx_blocks->block_virt_addr = tmp_v_addr;
617                                 return -ENOMEM;
618                         }
619                         memset(tmp_v_addr, 0, size);
620                         rx_blocks->block_virt_addr = tmp_v_addr;
621                         rx_blocks->block_dma_addr = tmp_p_addr;
622                         rx_blocks->rxds = kmalloc(sizeof(rxd_info_t)*
623                                                   rxd_count[nic->rxd_mode],
624                                                   GFP_KERNEL);
625                         if (!rx_blocks->rxds)
626                                 return -ENOMEM;
627                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
628                                 rx_blocks->rxds[l].virt_addr =
629                                         rx_blocks->block_virt_addr +
630                                         (rxd_size[nic->rxd_mode] * l);
631                                 rx_blocks->rxds[l].dma_addr =
632                                         rx_blocks->block_dma_addr +
633                                         (rxd_size[nic->rxd_mode] * l);
634                         }
635                 }
636                 /* Interlinking all Rx Blocks */
637                 for (j = 0; j < blk_cnt; j++) {
638                         tmp_v_addr =
639                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
640                         tmp_v_addr_next =
641                                 mac_control->rings[i].rx_blocks[(j + 1) %
642                                               blk_cnt].block_virt_addr;
643                         tmp_p_addr =
644                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
645                         tmp_p_addr_next =
646                                 mac_control->rings[i].rx_blocks[(j + 1) %
647                                               blk_cnt].block_dma_addr;
648
649                         pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
650                         pre_rxd_blk->reserved_2_pNext_RxD_block =
651                             (unsigned long) tmp_v_addr_next;
652                         pre_rxd_blk->pNext_RxD_Blk_physical =
653                             (u64) tmp_p_addr_next;
654                 }
655         }
656         if (nic->rxd_mode >= RXD_MODE_3A) {
657                 /*
658                  * Allocation of Storages for buffer addresses in 2BUFF mode
659                  * and the buffers as well.
660                  */
661                 for (i = 0; i < config->rx_ring_num; i++) {
662                         blk_cnt = config->rx_cfg[i].num_rxd /
663                            (rxd_count[nic->rxd_mode]+ 1);
664                         mac_control->rings[i].ba =
665                                 kmalloc((sizeof(buffAdd_t *) * blk_cnt),
666                                      GFP_KERNEL);
667                         if (!mac_control->rings[i].ba)
668                                 return -ENOMEM;
669                         for (j = 0; j < blk_cnt; j++) {
670                                 int k = 0;
671                                 mac_control->rings[i].ba[j] =
672                                         kmalloc((sizeof(buffAdd_t) *
673                                                 (rxd_count[nic->rxd_mode] + 1)),
674                                                 GFP_KERNEL);
675                                 if (!mac_control->rings[i].ba[j])
676                                         return -ENOMEM;
677                                 while (k != rxd_count[nic->rxd_mode]) {
678                                         ba = &mac_control->rings[i].ba[j][k];
679
680                                         ba->ba_0_org = (void *) kmalloc
681                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
682                                         if (!ba->ba_0_org)
683                                                 return -ENOMEM;
684                                         tmp = (unsigned long)ba->ba_0_org;
685                                         tmp += ALIGN_SIZE;
686                                         tmp &= ~((unsigned long) ALIGN_SIZE);
687                                         ba->ba_0 = (void *) tmp;
688
689                                         ba->ba_1_org = (void *) kmalloc
690                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
691                                         if (!ba->ba_1_org)
692                                                 return -ENOMEM;
693                                         tmp = (unsigned long) ba->ba_1_org;
694                                         tmp += ALIGN_SIZE;
695                                         tmp &= ~((unsigned long) ALIGN_SIZE);
696                                         ba->ba_1 = (void *) tmp;
697                                         k++;
698                                 }
699                         }
700                 }
701         }
702
703         /* Allocation and initialization of Statistics block */
704         size = sizeof(StatInfo_t);
705         mac_control->stats_mem = pci_alloc_consistent
706             (nic->pdev, size, &mac_control->stats_mem_phy);
707
708         if (!mac_control->stats_mem) {
709                 /*
710                  * In case of failure, free_shared_mem() is called, which
711                  * should free any memory that was alloced till the
712                  * failure happened.
713                  */
714                 return -ENOMEM;
715         }
716         mac_control->stats_mem_sz = size;
717
718         tmp_v_addr = mac_control->stats_mem;
719         mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
720         memset(tmp_v_addr, 0, size);
721         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
722                   (unsigned long long) tmp_p_addr);
723
724         return SUCCESS;
725 }
726
727 /**
728  * free_shared_mem - Free the allocated Memory
729  * @nic:  Device private variable.
730  * Description: This function is to free all memory locations allocated by
731  * the init_shared_mem() function and return it to the kernel.
732  */
733
734 static void free_shared_mem(struct s2io_nic *nic)
735 {
736         int i, j, blk_cnt, size;
737         void *tmp_v_addr;
738         dma_addr_t tmp_p_addr;
739         mac_info_t *mac_control;
740         struct config_param *config;
741         int lst_size, lst_per_page;
742         struct net_device *dev = nic->dev;
743
744         if (!nic)
745                 return;
746
747         mac_control = &nic->mac_control;
748         config = &nic->config;
749
750         lst_size = (sizeof(TxD_t) * config->max_txds);
751         lst_per_page = PAGE_SIZE / lst_size;
752
753         for (i = 0; i < config->tx_fifo_num; i++) {
754                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
755                                                 lst_per_page);
756                 for (j = 0; j < page_num; j++) {
757                         int mem_blks = (j * lst_per_page);
758                         if (!mac_control->fifos[i].list_info)
759                                 return;
760                         if (!mac_control->fifos[i].list_info[mem_blks].
761                                  list_virt_addr)
762                                 break;
763                         pci_free_consistent(nic->pdev, PAGE_SIZE,
764                                             mac_control->fifos[i].
765                                             list_info[mem_blks].
766                                             list_virt_addr,
767                                             mac_control->fifos[i].
768                                             list_info[mem_blks].
769                                             list_phy_addr);
770                 }
771                 /* If we got a zero DMA address during allocation,
772                  * free the page now
773                  */
774                 if (mac_control->zerodma_virt_addr) {
775                         pci_free_consistent(nic->pdev, PAGE_SIZE,
776                                             mac_control->zerodma_virt_addr,
777                                             (dma_addr_t)0);
778                         DBG_PRINT(INIT_DBG,
779                                 "%s: Freeing TxDL with zero DMA addr. ",
780                                 dev->name);
781                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
782                                 mac_control->zerodma_virt_addr);
783                 }
784                 kfree(mac_control->fifos[i].list_info);
785         }
786
787         size = SIZE_OF_BLOCK;
788         for (i = 0; i < config->rx_ring_num; i++) {
789                 blk_cnt = mac_control->rings[i].block_count;
790                 for (j = 0; j < blk_cnt; j++) {
791                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
792                                 block_virt_addr;
793                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
794                                 block_dma_addr;
795                         if (tmp_v_addr == NULL)
796                                 break;
797                         pci_free_consistent(nic->pdev, size,
798                                             tmp_v_addr, tmp_p_addr);
799                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
800                 }
801         }
802
803         if (nic->rxd_mode >= RXD_MODE_3A) {
804                 /* Freeing buffer storage addresses in 2BUFF mode. */
805                 for (i = 0; i < config->rx_ring_num; i++) {
806                         blk_cnt = config->rx_cfg[i].num_rxd /
807                             (rxd_count[nic->rxd_mode] + 1);
808                         for (j = 0; j < blk_cnt; j++) {
809                                 int k = 0;
810                                 if (!mac_control->rings[i].ba[j])
811                                         continue;
812                                 while (k != rxd_count[nic->rxd_mode]) {
813                                         buffAdd_t *ba =
814                                                 &mac_control->rings[i].ba[j][k];
815                                         kfree(ba->ba_0_org);
816                                         kfree(ba->ba_1_org);
817                                         k++;
818                                 }
819                                 kfree(mac_control->rings[i].ba[j]);
820                         }
821                         kfree(mac_control->rings[i].ba);
822                 }
823         }
824
825         if (mac_control->stats_mem) {
826                 pci_free_consistent(nic->pdev,
827                                     mac_control->stats_mem_sz,
828                                     mac_control->stats_mem,
829                                     mac_control->stats_mem_phy);
830         }
831         if (nic->ufo_in_band_v)
832                 kfree(nic->ufo_in_band_v);
833 }
834
835 /**
836  * s2io_verify_pci_mode -
837  */
838
839 static int s2io_verify_pci_mode(nic_t *nic)
840 {
841         XENA_dev_config_t __iomem *bar0 = nic->bar0;
842         register u64 val64 = 0;
843         int     mode;
844
845         val64 = readq(&bar0->pci_mode);
846         mode = (u8)GET_PCI_MODE(val64);
847
848         if ( val64 & PCI_MODE_UNKNOWN_MODE)
849                 return -1;      /* Unknown PCI mode */
850         return mode;
851 }
852
853 #define NEC_VENID   0x1033
854 #define NEC_DEVID   0x0125
855 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
856 {
857         struct pci_dev *tdev = NULL;
858         while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
859                 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
860                         if (tdev->bus == s2io_pdev->bus->parent)
861                                 pci_dev_put(tdev);
862                                 return 1;
863                 }
864         }
865         return 0;
866 }
867
868 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
869 /**
870  * s2io_print_pci_mode -
871  */
872 static int s2io_print_pci_mode(nic_t *nic)
873 {
874         XENA_dev_config_t __iomem *bar0 = nic->bar0;
875         register u64 val64 = 0;
876         int     mode;
877         struct config_param *config = &nic->config;
878
879         val64 = readq(&bar0->pci_mode);
880         mode = (u8)GET_PCI_MODE(val64);
881
882         if ( val64 & PCI_MODE_UNKNOWN_MODE)
883                 return -1;      /* Unknown PCI mode */
884
885         config->bus_speed = bus_speed[mode];
886
887         if (s2io_on_nec_bridge(nic->pdev)) {
888                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
889                                                         nic->dev->name);
890                 return mode;
891         }
892
893         if (val64 & PCI_MODE_32_BITS) {
894                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
895         } else {
896                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
897         }
898
899         switch(mode) {
900                 case PCI_MODE_PCI_33:
901                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
902                         break;
903                 case PCI_MODE_PCI_66:
904                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
905                         break;
906                 case PCI_MODE_PCIX_M1_66:
907                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
908                         break;
909                 case PCI_MODE_PCIX_M1_100:
910                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
911                         break;
912                 case PCI_MODE_PCIX_M1_133:
913                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
914                         break;
915                 case PCI_MODE_PCIX_M2_66:
916                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
917                         break;
918                 case PCI_MODE_PCIX_M2_100:
919                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
920                         break;
921                 case PCI_MODE_PCIX_M2_133:
922                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
923                         break;
924                 default:
925                         return -1;      /* Unsupported bus speed */
926         }
927
928         return mode;
929 }
930
931 /**
932  *  init_nic - Initialization of hardware
933  *  @nic: device peivate variable
934  *  Description: The function sequentially configures every block
935  *  of the H/W from their reset values.
936  *  Return Value:  SUCCESS on success and
937  *  '-1' on failure (endian settings incorrect).
938  */
939
940 static int init_nic(struct s2io_nic *nic)
941 {
942         XENA_dev_config_t __iomem *bar0 = nic->bar0;
943         struct net_device *dev = nic->dev;
944         register u64 val64 = 0;
945         void __iomem *add;
946         u32 time;
947         int i, j;
948         mac_info_t *mac_control;
949         struct config_param *config;
950         int dtx_cnt = 0;
951         unsigned long long mem_share;
952         int mem_size;
953
954         mac_control = &nic->mac_control;
955         config = &nic->config;
956
957         /* to set the swapper controle on the card */
958         if(s2io_set_swapper(nic)) {
959                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
960                 return -1;
961         }
962
963         /*
964          * Herc requires EOI to be removed from reset before XGXS, so..
965          */
966         if (nic->device_type & XFRAME_II_DEVICE) {
967                 val64 = 0xA500000000ULL;
968                 writeq(val64, &bar0->sw_reset);
969                 msleep(500);
970                 val64 = readq(&bar0->sw_reset);
971         }
972
973         /* Remove XGXS from reset state */
974         val64 = 0;
975         writeq(val64, &bar0->sw_reset);
976         msleep(500);
977         val64 = readq(&bar0->sw_reset);
978
979         /*  Enable Receiving broadcasts */
980         add = &bar0->mac_cfg;
981         val64 = readq(&bar0->mac_cfg);
982         val64 |= MAC_RMAC_BCAST_ENABLE;
983         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
984         writel((u32) val64, add);
985         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
986         writel((u32) (val64 >> 32), (add + 4));
987
988         /* Read registers in all blocks */
989         val64 = readq(&bar0->mac_int_mask);
990         val64 = readq(&bar0->mc_int_mask);
991         val64 = readq(&bar0->xgxs_int_mask);
992
993         /*  Set MTU */
994         val64 = dev->mtu;
995         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
996
997         if (nic->device_type & XFRAME_II_DEVICE) {
998                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
999                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1000                                           &bar0->dtx_control, UF);
1001                         if (dtx_cnt & 0x1)
1002                                 msleep(1); /* Necessary!! */
1003                         dtx_cnt++;
1004                 }
1005         } else {
1006                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1007                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1008                                           &bar0->dtx_control, UF);
1009                         val64 = readq(&bar0->dtx_control);
1010                         dtx_cnt++;
1011                 }
1012         }
1013
1014         /*  Tx DMA Initialization */
1015         val64 = 0;
1016         writeq(val64, &bar0->tx_fifo_partition_0);
1017         writeq(val64, &bar0->tx_fifo_partition_1);
1018         writeq(val64, &bar0->tx_fifo_partition_2);
1019         writeq(val64, &bar0->tx_fifo_partition_3);
1020
1021
1022         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1023                 val64 |=
1024                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1025                          13) | vBIT(config->tx_cfg[i].fifo_priority,
1026                                     ((i * 32) + 5), 3);
1027
1028                 if (i == (config->tx_fifo_num - 1)) {
1029                         if (i % 2 == 0)
1030                                 i++;
1031                 }
1032
1033                 switch (i) {
1034                 case 1:
1035                         writeq(val64, &bar0->tx_fifo_partition_0);
1036                         val64 = 0;
1037                         break;
1038                 case 3:
1039                         writeq(val64, &bar0->tx_fifo_partition_1);
1040                         val64 = 0;
1041                         break;
1042                 case 5:
1043                         writeq(val64, &bar0->tx_fifo_partition_2);
1044                         val64 = 0;
1045                         break;
1046                 case 7:
1047                         writeq(val64, &bar0->tx_fifo_partition_3);
1048                         break;
1049                 }
1050         }
1051
1052         /*
1053          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1054          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1055          */
1056         if ((nic->device_type == XFRAME_I_DEVICE) &&
1057                 (get_xena_rev_id(nic->pdev) < 4))
1058                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1059
1060         val64 = readq(&bar0->tx_fifo_partition_0);
1061         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1062                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1063
1064         /*
1065          * Initialization of Tx_PA_CONFIG register to ignore packet
1066          * integrity checking.
1067          */
1068         val64 = readq(&bar0->tx_pa_cfg);
1069         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1070             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1071         writeq(val64, &bar0->tx_pa_cfg);
1072
1073         /* Rx DMA intialization. */
1074         val64 = 0;
1075         for (i = 0; i < config->rx_ring_num; i++) {
1076                 val64 |=
1077                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1078                          3);
1079         }
1080         writeq(val64, &bar0->rx_queue_priority);
1081
1082         /*
1083          * Allocating equal share of memory to all the
1084          * configured Rings.
1085          */
1086         val64 = 0;
1087         if (nic->device_type & XFRAME_II_DEVICE)
1088                 mem_size = 32;
1089         else
1090                 mem_size = 64;
1091
1092         for (i = 0; i < config->rx_ring_num; i++) {
1093                 switch (i) {
1094                 case 0:
1095                         mem_share = (mem_size / config->rx_ring_num +
1096                                      mem_size % config->rx_ring_num);
1097                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1098                         continue;
1099                 case 1:
1100                         mem_share = (mem_size / config->rx_ring_num);
1101                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1102                         continue;
1103                 case 2:
1104                         mem_share = (mem_size / config->rx_ring_num);
1105                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1106                         continue;
1107                 case 3:
1108                         mem_share = (mem_size / config->rx_ring_num);
1109                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1110                         continue;
1111                 case 4:
1112                         mem_share = (mem_size / config->rx_ring_num);
1113                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1114                         continue;
1115                 case 5:
1116                         mem_share = (mem_size / config->rx_ring_num);
1117                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1118                         continue;
1119                 case 6:
1120                         mem_share = (mem_size / config->rx_ring_num);
1121                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1122                         continue;
1123                 case 7:
1124                         mem_share = (mem_size / config->rx_ring_num);
1125                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1126                         continue;
1127                 }
1128         }
1129         writeq(val64, &bar0->rx_queue_cfg);
1130
1131         /*
1132          * Filling Tx round robin registers
1133          * as per the number of FIFOs
1134          */
1135         switch (config->tx_fifo_num) {
1136         case 1:
1137                 val64 = 0x0000000000000000ULL;
1138                 writeq(val64, &bar0->tx_w_round_robin_0);
1139                 writeq(val64, &bar0->tx_w_round_robin_1);
1140                 writeq(val64, &bar0->tx_w_round_robin_2);
1141                 writeq(val64, &bar0->tx_w_round_robin_3);
1142                 writeq(val64, &bar0->tx_w_round_robin_4);
1143                 break;
1144         case 2:
1145                 val64 = 0x0000010000010000ULL;
1146                 writeq(val64, &bar0->tx_w_round_robin_0);
1147                 val64 = 0x0100000100000100ULL;
1148                 writeq(val64, &bar0->tx_w_round_robin_1);
1149                 val64 = 0x0001000001000001ULL;
1150                 writeq(val64, &bar0->tx_w_round_robin_2);
1151                 val64 = 0x0000010000010000ULL;
1152                 writeq(val64, &bar0->tx_w_round_robin_3);
1153                 val64 = 0x0100000000000000ULL;
1154                 writeq(val64, &bar0->tx_w_round_robin_4);
1155                 break;
1156         case 3:
1157                 val64 = 0x0001000102000001ULL;
1158                 writeq(val64, &bar0->tx_w_round_robin_0);
1159                 val64 = 0x0001020000010001ULL;
1160                 writeq(val64, &bar0->tx_w_round_robin_1);
1161                 val64 = 0x0200000100010200ULL;
1162                 writeq(val64, &bar0->tx_w_round_robin_2);
1163                 val64 = 0x0001000102000001ULL;
1164                 writeq(val64, &bar0->tx_w_round_robin_3);
1165                 val64 = 0x0001020000000000ULL;
1166                 writeq(val64, &bar0->tx_w_round_robin_4);
1167                 break;
1168         case 4:
1169                 val64 = 0x0001020300010200ULL;
1170                 writeq(val64, &bar0->tx_w_round_robin_0);
1171                 val64 = 0x0100000102030001ULL;
1172                 writeq(val64, &bar0->tx_w_round_robin_1);
1173                 val64 = 0x0200010000010203ULL;
1174                 writeq(val64, &bar0->tx_w_round_robin_2);
1175                 val64 = 0x0001020001000001ULL;
1176                 writeq(val64, &bar0->tx_w_round_robin_3);
1177                 val64 = 0x0203000100000000ULL;
1178                 writeq(val64, &bar0->tx_w_round_robin_4);
1179                 break;
1180         case 5:
1181                 val64 = 0x0001000203000102ULL;
1182                 writeq(val64, &bar0->tx_w_round_robin_0);
1183                 val64 = 0x0001020001030004ULL;
1184                 writeq(val64, &bar0->tx_w_round_robin_1);
1185                 val64 = 0x0001000203000102ULL;
1186                 writeq(val64, &bar0->tx_w_round_robin_2);
1187                 val64 = 0x0001020001030004ULL;
1188                 writeq(val64, &bar0->tx_w_round_robin_3);
1189                 val64 = 0x0001000000000000ULL;
1190                 writeq(val64, &bar0->tx_w_round_robin_4);
1191                 break;
1192         case 6:
1193                 val64 = 0x0001020304000102ULL;
1194                 writeq(val64, &bar0->tx_w_round_robin_0);
1195                 val64 = 0x0304050001020001ULL;
1196                 writeq(val64, &bar0->tx_w_round_robin_1);
1197                 val64 = 0x0203000100000102ULL;
1198                 writeq(val64, &bar0->tx_w_round_robin_2);
1199                 val64 = 0x0304000102030405ULL;
1200                 writeq(val64, &bar0->tx_w_round_robin_3);
1201                 val64 = 0x0001000200000000ULL;
1202                 writeq(val64, &bar0->tx_w_round_robin_4);
1203                 break;
1204         case 7:
1205                 val64 = 0x0001020001020300ULL;
1206                 writeq(val64, &bar0->tx_w_round_robin_0);
1207                 val64 = 0x0102030400010203ULL;
1208                 writeq(val64, &bar0->tx_w_round_robin_1);
1209                 val64 = 0x0405060001020001ULL;
1210                 writeq(val64, &bar0->tx_w_round_robin_2);
1211                 val64 = 0x0304050000010200ULL;
1212                 writeq(val64, &bar0->tx_w_round_robin_3);
1213                 val64 = 0x0102030000000000ULL;
1214                 writeq(val64, &bar0->tx_w_round_robin_4);
1215                 break;
1216         case 8:
1217                 val64 = 0x0001020300040105ULL;
1218                 writeq(val64, &bar0->tx_w_round_robin_0);
1219                 val64 = 0x0200030106000204ULL;
1220                 writeq(val64, &bar0->tx_w_round_robin_1);
1221                 val64 = 0x0103000502010007ULL;
1222                 writeq(val64, &bar0->tx_w_round_robin_2);
1223                 val64 = 0x0304010002060500ULL;
1224                 writeq(val64, &bar0->tx_w_round_robin_3);
1225                 val64 = 0x0103020400000000ULL;
1226                 writeq(val64, &bar0->tx_w_round_robin_4);
1227                 break;
1228         }
1229
1230         /* Enable all configured Tx FIFO partitions */
1231         val64 = readq(&bar0->tx_fifo_partition_0);
1232         val64 |= (TX_FIFO_PARTITION_EN);
1233         writeq(val64, &bar0->tx_fifo_partition_0);
1234
1235         /* Filling the Rx round robin registers as per the
1236          * number of Rings and steering based on QoS.
1237          */
1238         switch (config->rx_ring_num) {
1239         case 1:
1240                 val64 = 0x8080808080808080ULL;
1241                 writeq(val64, &bar0->rts_qos_steering);
1242                 break;
1243         case 2:
1244                 val64 = 0x0000010000010000ULL;
1245                 writeq(val64, &bar0->rx_w_round_robin_0);
1246                 val64 = 0x0100000100000100ULL;
1247                 writeq(val64, &bar0->rx_w_round_robin_1);
1248                 val64 = 0x0001000001000001ULL;
1249                 writeq(val64, &bar0->rx_w_round_robin_2);
1250                 val64 = 0x0000010000010000ULL;
1251                 writeq(val64, &bar0->rx_w_round_robin_3);
1252                 val64 = 0x0100000000000000ULL;
1253                 writeq(val64, &bar0->rx_w_round_robin_4);
1254
1255                 val64 = 0x8080808040404040ULL;
1256                 writeq(val64, &bar0->rts_qos_steering);
1257                 break;
1258         case 3:
1259                 val64 = 0x0001000102000001ULL;
1260                 writeq(val64, &bar0->rx_w_round_robin_0);
1261                 val64 = 0x0001020000010001ULL;
1262                 writeq(val64, &bar0->rx_w_round_robin_1);
1263                 val64 = 0x0200000100010200ULL;
1264                 writeq(val64, &bar0->rx_w_round_robin_2);
1265                 val64 = 0x0001000102000001ULL;
1266                 writeq(val64, &bar0->rx_w_round_robin_3);
1267                 val64 = 0x0001020000000000ULL;
1268                 writeq(val64, &bar0->rx_w_round_robin_4);
1269
1270                 val64 = 0x8080804040402020ULL;
1271                 writeq(val64, &bar0->rts_qos_steering);
1272                 break;
1273         case 4:
1274                 val64 = 0x0001020300010200ULL;
1275                 writeq(val64, &bar0->rx_w_round_robin_0);
1276                 val64 = 0x0100000102030001ULL;
1277                 writeq(val64, &bar0->rx_w_round_robin_1);
1278                 val64 = 0x0200010000010203ULL;
1279                 writeq(val64, &bar0->rx_w_round_robin_2);
1280                 val64 = 0x0001020001000001ULL;
1281                 writeq(val64, &bar0->rx_w_round_robin_3);
1282                 val64 = 0x0203000100000000ULL;
1283                 writeq(val64, &bar0->rx_w_round_robin_4);
1284
1285                 val64 = 0x8080404020201010ULL;
1286                 writeq(val64, &bar0->rts_qos_steering);
1287                 break;
1288         case 5:
1289                 val64 = 0x0001000203000102ULL;
1290                 writeq(val64, &bar0->rx_w_round_robin_0);
1291                 val64 = 0x0001020001030004ULL;
1292                 writeq(val64, &bar0->rx_w_round_robin_1);
1293                 val64 = 0x0001000203000102ULL;
1294                 writeq(val64, &bar0->rx_w_round_robin_2);
1295                 val64 = 0x0001020001030004ULL;
1296                 writeq(val64, &bar0->rx_w_round_robin_3);
1297                 val64 = 0x0001000000000000ULL;
1298                 writeq(val64, &bar0->rx_w_round_robin_4);
1299
1300                 val64 = 0x8080404020201008ULL;
1301                 writeq(val64, &bar0->rts_qos_steering);
1302                 break;
1303         case 6:
1304                 val64 = 0x0001020304000102ULL;
1305                 writeq(val64, &bar0->rx_w_round_robin_0);
1306                 val64 = 0x0304050001020001ULL;
1307                 writeq(val64, &bar0->rx_w_round_robin_1);
1308                 val64 = 0x0203000100000102ULL;
1309                 writeq(val64, &bar0->rx_w_round_robin_2);
1310                 val64 = 0x0304000102030405ULL;
1311                 writeq(val64, &bar0->rx_w_round_robin_3);
1312                 val64 = 0x0001000200000000ULL;
1313                 writeq(val64, &bar0->rx_w_round_robin_4);
1314
1315                 val64 = 0x8080404020100804ULL;
1316                 writeq(val64, &bar0->rts_qos_steering);
1317                 break;
1318         case 7:
1319                 val64 = 0x0001020001020300ULL;
1320                 writeq(val64, &bar0->rx_w_round_robin_0);
1321                 val64 = 0x0102030400010203ULL;
1322                 writeq(val64, &bar0->rx_w_round_robin_1);
1323                 val64 = 0x0405060001020001ULL;
1324                 writeq(val64, &bar0->rx_w_round_robin_2);
1325                 val64 = 0x0304050000010200ULL;
1326                 writeq(val64, &bar0->rx_w_round_robin_3);
1327                 val64 = 0x0102030000000000ULL;
1328                 writeq(val64, &bar0->rx_w_round_robin_4);
1329
1330                 val64 = 0x8080402010080402ULL;
1331                 writeq(val64, &bar0->rts_qos_steering);
1332                 break;
1333         case 8:
1334                 val64 = 0x0001020300040105ULL;
1335                 writeq(val64, &bar0->rx_w_round_robin_0);
1336                 val64 = 0x0200030106000204ULL;
1337                 writeq(val64, &bar0->rx_w_round_robin_1);
1338                 val64 = 0x0103000502010007ULL;
1339                 writeq(val64, &bar0->rx_w_round_robin_2);
1340                 val64 = 0x0304010002060500ULL;
1341                 writeq(val64, &bar0->rx_w_round_robin_3);
1342                 val64 = 0x0103020400000000ULL;
1343                 writeq(val64, &bar0->rx_w_round_robin_4);
1344
1345                 val64 = 0x8040201008040201ULL;
1346                 writeq(val64, &bar0->rts_qos_steering);
1347                 break;
1348         }
1349
1350         /* UDP Fix */
1351         val64 = 0;
1352         for (i = 0; i < 8; i++)
1353                 writeq(val64, &bar0->rts_frm_len_n[i]);
1354
1355         /* Set the default rts frame length for the rings configured */
1356         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1357         for (i = 0 ; i < config->rx_ring_num ; i++)
1358                 writeq(val64, &bar0->rts_frm_len_n[i]);
1359
1360         /* Set the frame length for the configured rings
1361          * desired by the user
1362          */
1363         for (i = 0; i < config->rx_ring_num; i++) {
1364                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1365                  * specified frame length steering.
1366                  * If the user provides the frame length then program
1367                  * the rts_frm_len register for those values or else
1368                  * leave it as it is.
1369                  */
1370                 if (rts_frm_len[i] != 0) {
1371                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1372                                 &bar0->rts_frm_len_n[i]);
1373                 }
1374         }
1375
1376         /* Program statistics memory */
1377         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1378
1379         if (nic->device_type == XFRAME_II_DEVICE) {
1380                 val64 = STAT_BC(0x320);
1381                 writeq(val64, &bar0->stat_byte_cnt);
1382         }
1383
1384         /*
1385          * Initializing the sampling rate for the device to calculate the
1386          * bandwidth utilization.
1387          */
1388         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1389             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1390         writeq(val64, &bar0->mac_link_util);
1391
1392
1393         /*
1394          * Initializing the Transmit and Receive Traffic Interrupt
1395          * Scheme.
1396          */
1397         /*
1398          * TTI Initialization. Default Tx timer gets us about
1399          * 250 interrupts per sec. Continuous interrupts are enabled
1400          * by default.
1401          */
1402         if (nic->device_type == XFRAME_II_DEVICE) {
1403                 int count = (nic->config.bus_speed * 125)/2;
1404                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1405         } else {
1406
1407                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1408         }
1409         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1410             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1411             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1412                 if (use_continuous_tx_intrs)
1413                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1414         writeq(val64, &bar0->tti_data1_mem);
1415
1416         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1417             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1418             TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1419         writeq(val64, &bar0->tti_data2_mem);
1420
1421         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1422         writeq(val64, &bar0->tti_command_mem);
1423
1424         /*
1425          * Once the operation completes, the Strobe bit of the command
1426          * register will be reset. We poll for this particular condition
1427          * We wait for a maximum of 500ms for the operation to complete,
1428          * if it's not complete by then we return error.
1429          */
1430         time = 0;
1431         while (TRUE) {
1432                 val64 = readq(&bar0->tti_command_mem);
1433                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1434                         break;
1435                 }
1436                 if (time > 10) {
1437                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1438                                   dev->name);
1439                         return -1;
1440                 }
1441                 msleep(50);
1442                 time++;
1443         }
1444
1445         if (nic->config.bimodal) {
1446                 int k = 0;
1447                 for (k = 0; k < config->rx_ring_num; k++) {
1448                         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1449                         val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1450                         writeq(val64, &bar0->tti_command_mem);
1451
1452                 /*
1453                  * Once the operation completes, the Strobe bit of the command
1454                  * register will be reset. We poll for this particular condition
1455                  * We wait for a maximum of 500ms for the operation to complete,
1456                  * if it's not complete by then we return error.
1457                 */
1458                         time = 0;
1459                         while (TRUE) {
1460                                 val64 = readq(&bar0->tti_command_mem);
1461                                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1462                                         break;
1463                                 }
1464                                 if (time > 10) {
1465                                         DBG_PRINT(ERR_DBG,
1466                                                 "%s: TTI init Failed\n",
1467                                         dev->name);
1468                                         return -1;
1469                                 }
1470                                 time++;
1471                                 msleep(50);
1472                         }
1473                 }
1474         } else {
1475
1476                 /* RTI Initialization */
1477                 if (nic->device_type == XFRAME_II_DEVICE) {
1478                         /*
1479                          * Programmed to generate Apprx 500 Intrs per
1480                          * second
1481                          */
1482                         int count = (nic->config.bus_speed * 125)/4;
1483                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1484                 } else {
1485                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1486                 }
1487                 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1488                     RTI_DATA1_MEM_RX_URNG_B(0x10) |
1489                     RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1490
1491                 writeq(val64, &bar0->rti_data1_mem);
1492
1493                 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1494                     RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1495                 if (nic->intr_type == MSI_X)
1496                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1497                                 RTI_DATA2_MEM_RX_UFC_D(0x40));
1498                 else
1499                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1500                                 RTI_DATA2_MEM_RX_UFC_D(0x80));
1501                 writeq(val64, &bar0->rti_data2_mem);
1502
1503                 for (i = 0; i < config->rx_ring_num; i++) {
1504                         val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1505                                         | RTI_CMD_MEM_OFFSET(i);
1506                         writeq(val64, &bar0->rti_command_mem);
1507
1508                         /*
1509                          * Once the operation completes, the Strobe bit of the
1510                          * command register will be reset. We poll for this
1511                          * particular condition. We wait for a maximum of 500ms
1512                          * for the operation to complete, if it's not complete
1513                          * by then we return error.
1514                          */
1515                         time = 0;
1516                         while (TRUE) {
1517                                 val64 = readq(&bar0->rti_command_mem);
1518                                 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1519                                         break;
1520                                 }
1521                                 if (time > 10) {
1522                                         DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1523                                                   dev->name);
1524                                         return -1;
1525                                 }
1526                                 time++;
1527                                 msleep(50);
1528                         }
1529                 }
1530         }
1531
1532         /*
1533          * Initializing proper values as Pause threshold into all
1534          * the 8 Queues on Rx side.
1535          */
1536         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1537         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1538
1539         /* Disable RMAC PAD STRIPPING */
1540         add = &bar0->mac_cfg;
1541         val64 = readq(&bar0->mac_cfg);
1542         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1543         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1544         writel((u32) (val64), add);
1545         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1546         writel((u32) (val64 >> 32), (add + 4));
1547         val64 = readq(&bar0->mac_cfg);
1548
1549         /* Enable FCS stripping by adapter */
1550         add = &bar0->mac_cfg;
1551         val64 = readq(&bar0->mac_cfg);
1552         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1553         if (nic->device_type == XFRAME_II_DEVICE)
1554                 writeq(val64, &bar0->mac_cfg);
1555         else {
1556                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1557                 writel((u32) (val64), add);
1558                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1559                 writel((u32) (val64 >> 32), (add + 4));
1560         }
1561
1562         /*
1563          * Set the time value to be inserted in the pause frame
1564          * generated by xena.
1565          */
1566         val64 = readq(&bar0->rmac_pause_cfg);
1567         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1568         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1569         writeq(val64, &bar0->rmac_pause_cfg);
1570
1571         /*
1572          * Set the Threshold Limit for Generating the pause frame
1573          * If the amount of data in any Queue exceeds ratio of
1574          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1575          * pause frame is generated
1576          */
1577         val64 = 0;
1578         for (i = 0; i < 4; i++) {
1579                 val64 |=
1580                     (((u64) 0xFF00 | nic->mac_control.
1581                       mc_pause_threshold_q0q3)
1582                      << (i * 2 * 8));
1583         }
1584         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1585
1586         val64 = 0;
1587         for (i = 0; i < 4; i++) {
1588                 val64 |=
1589                     (((u64) 0xFF00 | nic->mac_control.
1590                       mc_pause_threshold_q4q7)
1591                      << (i * 2 * 8));
1592         }
1593         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1594
1595         /*
1596          * TxDMA will stop Read request if the number of read split has
1597          * exceeded the limit pointed by shared_splits
1598          */
1599         val64 = readq(&bar0->pic_control);
1600         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1601         writeq(val64, &bar0->pic_control);
1602
1603         if (nic->config.bus_speed == 266) {
1604                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1605                 writeq(0x0, &bar0->read_retry_delay);
1606                 writeq(0x0, &bar0->write_retry_delay);
1607         }
1608
1609         /*
1610          * Programming the Herc to split every write transaction
1611          * that does not start on an ADB to reduce disconnects.
1612          */
1613         if (nic->device_type == XFRAME_II_DEVICE) {
1614                 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1615                         MISC_LINK_STABILITY_PRD(3);
1616                 writeq(val64, &bar0->misc_control);
1617                 val64 = readq(&bar0->pic_control2);
1618                 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1619                 writeq(val64, &bar0->pic_control2);
1620         }
1621         if (strstr(nic->product_name, "CX4")) {
1622                 val64 = TMAC_AVG_IPG(0x17);
1623                 writeq(val64, &bar0->tmac_avg_ipg);
1624         }
1625
1626         return SUCCESS;
1627 }
1628 #define LINK_UP_DOWN_INTERRUPT          1
1629 #define MAC_RMAC_ERR_TIMER              2
1630
1631 static int s2io_link_fault_indication(nic_t *nic)
1632 {
1633         if (nic->intr_type != INTA)
1634                 return MAC_RMAC_ERR_TIMER;
1635         if (nic->device_type == XFRAME_II_DEVICE)
1636                 return LINK_UP_DOWN_INTERRUPT;
1637         else
1638                 return MAC_RMAC_ERR_TIMER;
1639 }
1640
1641 /**
1642  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1643  *  @nic: device private variable,
1644  *  @mask: A mask indicating which Intr block must be modified and,
1645  *  @flag: A flag indicating whether to enable or disable the Intrs.
1646  *  Description: This function will either disable or enable the interrupts
1647  *  depending on the flag argument. The mask argument can be used to
1648  *  enable/disable any Intr block.
1649  *  Return Value: NONE.
1650  */
1651
1652 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1653 {
1654         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1655         register u64 val64 = 0, temp64 = 0;
1656
1657         /*  Top level interrupt classification */
1658         /*  PIC Interrupts */
1659         if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1660                 /*  Enable PIC Intrs in the general intr mask register */
1661                 val64 = TXPIC_INT_M;
1662                 if (flag == ENABLE_INTRS) {
1663                         temp64 = readq(&bar0->general_int_mask);
1664                         temp64 &= ~((u64) val64);
1665                         writeq(temp64, &bar0->general_int_mask);
1666                         /*
1667                          * If Hercules adapter enable GPIO otherwise
1668                          * disable all PCIX, Flash, MDIO, IIC and GPIO
1669                          * interrupts for now.
1670                          * TODO
1671                          */
1672                         if (s2io_link_fault_indication(nic) ==
1673                                         LINK_UP_DOWN_INTERRUPT ) {
1674                                 temp64 = readq(&bar0->pic_int_mask);
1675                                 temp64 &= ~((u64) PIC_INT_GPIO);
1676                                 writeq(temp64, &bar0->pic_int_mask);
1677                                 temp64 = readq(&bar0->gpio_int_mask);
1678                                 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1679                                 writeq(temp64, &bar0->gpio_int_mask);
1680                         } else {
1681                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1682                         }
1683                         /*
1684                          * No MSI Support is available presently, so TTI and
1685                          * RTI interrupts are also disabled.
1686                          */
1687                 } else if (flag == DISABLE_INTRS) {
1688                         /*
1689                          * Disable PIC Intrs in the general
1690                          * intr mask register
1691                          */
1692                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1693                         temp64 = readq(&bar0->general_int_mask);
1694                         val64 |= temp64;
1695                         writeq(val64, &bar0->general_int_mask);
1696                 }
1697         }
1698
1699         /*  MAC Interrupts */
1700         /*  Enabling/Disabling MAC interrupts */
1701         if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1702                 val64 = TXMAC_INT_M | RXMAC_INT_M;
1703                 if (flag == ENABLE_INTRS) {
1704                         temp64 = readq(&bar0->general_int_mask);
1705                         temp64 &= ~((u64) val64);
1706                         writeq(temp64, &bar0->general_int_mask);
1707                         /*
1708                          * All MAC block error interrupts are disabled for now
1709                          * TODO
1710                          */
1711                 } else if (flag == DISABLE_INTRS) {
1712                         /*
1713                          * Disable MAC Intrs in the general intr mask register
1714                          */
1715                         writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1716                         writeq(DISABLE_ALL_INTRS,
1717                                &bar0->mac_rmac_err_mask);
1718
1719                         temp64 = readq(&bar0->general_int_mask);
1720                         val64 |= temp64;
1721                         writeq(val64, &bar0->general_int_mask);
1722                 }
1723         }
1724
1725         /*  Tx traffic interrupts */
1726         if (mask & TX_TRAFFIC_INTR) {
1727                 val64 = TXTRAFFIC_INT_M;
1728                 if (flag == ENABLE_INTRS) {
1729                         temp64 = readq(&bar0->general_int_mask);
1730                         temp64 &= ~((u64) val64);
1731                         writeq(temp64, &bar0->general_int_mask);
1732                         /*
1733                          * Enable all the Tx side interrupts
1734                          * writing 0 Enables all 64 TX interrupt levels
1735                          */
1736                         writeq(0x0, &bar0->tx_traffic_mask);
1737                 } else if (flag == DISABLE_INTRS) {
1738                         /*
1739                          * Disable Tx Traffic Intrs in the general intr mask
1740                          * register.
1741                          */
1742                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1743                         temp64 = readq(&bar0->general_int_mask);
1744                         val64 |= temp64;
1745                         writeq(val64, &bar0->general_int_mask);
1746                 }
1747         }
1748
1749         /*  Rx traffic interrupts */
1750         if (mask & RX_TRAFFIC_INTR) {
1751                 val64 = RXTRAFFIC_INT_M;
1752                 if (flag == ENABLE_INTRS) {
1753                         temp64 = readq(&bar0->general_int_mask);
1754                         temp64 &= ~((u64) val64);
1755                         writeq(temp64, &bar0->general_int_mask);
1756                         /* writing 0 Enables all 8 RX interrupt levels */
1757                         writeq(0x0, &bar0->rx_traffic_mask);
1758                 } else if (flag == DISABLE_INTRS) {
1759                         /*
1760                          * Disable Rx Traffic Intrs in the general intr mask
1761                          * register.
1762                          */
1763                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1764                         temp64 = readq(&bar0->general_int_mask);
1765                         val64 |= temp64;
1766                         writeq(val64, &bar0->general_int_mask);
1767                 }
1768         }
1769 }
1770
1771 /**
1772  *  verify_pcc_quiescent- Checks for PCC quiescent state
1773  *  Return: 1 If PCC is quiescence
1774  *          0 If PCC is not quiescence
1775  */
1776 static int verify_pcc_quiescent(nic_t *sp, int flag)
1777 {
1778         int ret = 0, herc;
1779         XENA_dev_config_t __iomem *bar0 = sp->bar0;
1780         u64 val64 = readq(&bar0->adapter_status);
1781         
1782         herc = (sp->device_type == XFRAME_II_DEVICE);
1783
1784         if (flag == FALSE) {
1785                 if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
1786                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
1787                                 ret = 1;
1788                 } else {
1789                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
1790                                 ret = 1;
1791                 }
1792         } else {
1793                 if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
1794                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1795                              ADAPTER_STATUS_RMAC_PCC_IDLE))
1796                                 ret = 1;
1797                 } else {
1798                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1799                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
1800                                 ret = 1;
1801                 }
1802         }
1803
1804         return ret;
1805 }
1806 /**
1807  *  verify_xena_quiescence - Checks whether the H/W is ready
1808  *  Description: Returns whether the H/W is ready to go or not. Depending
1809  *  on whether adapter enable bit was written or not the comparison
1810  *  differs and the calling function passes the input argument flag to
1811  *  indicate this.
1812  *  Return: 1 If xena is quiescence
1813  *          0 If Xena is not quiescence
1814  */
1815
1816 static int verify_xena_quiescence(nic_t *sp)
1817 {
1818         int  mode;
1819         XENA_dev_config_t __iomem *bar0 = sp->bar0;
1820         u64 val64 = readq(&bar0->adapter_status);
1821         mode = s2io_verify_pci_mode(sp);
1822
1823         if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
1824                 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
1825                 return 0;
1826         }
1827         if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
1828         DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
1829                 return 0;
1830         }
1831         if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
1832                 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
1833                 return 0;
1834         }
1835         if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
1836                 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
1837                 return 0;
1838         }
1839         if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
1840                 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
1841                 return 0;
1842         }
1843         if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
1844                 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
1845                 return 0;
1846         }
1847         if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
1848                 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
1849                 return 0;
1850         }
1851         if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
1852                 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
1853                 return 0;
1854         }
1855
1856         /*
1857          * In PCI 33 mode, the P_PLL is not used, and therefore,
1858          * the the P_PLL_LOCK bit in the adapter_status register will
1859          * not be asserted.
1860          */
1861         if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
1862                 sp->device_type == XFRAME_II_DEVICE && mode !=
1863                 PCI_MODE_PCI_33) {
1864                 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
1865                 return 0;
1866         }
1867         if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1868                         ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1869                 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
1870                 return 0;
1871         }
1872         return 1;
1873 }
1874
1875 /**
1876  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
1877  * @sp: Pointer to device specifc structure
1878  * Description :
1879  * New procedure to clear mac address reading  problems on Alpha platforms
1880  *
1881  */
1882
1883 static void fix_mac_address(nic_t * sp)
1884 {
1885         XENA_dev_config_t __iomem *bar0 = sp->bar0;
1886         u64 val64;
1887         int i = 0;
1888
1889         while (fix_mac[i] != END_SIGN) {
1890                 writeq(fix_mac[i++], &bar0->gpio_control);
1891                 udelay(10);
1892                 val64 = readq(&bar0->gpio_control);
1893         }
1894 }
1895
1896 /**
1897  *  start_nic - Turns the device on
1898  *  @nic : device private variable.
1899  *  Description:
1900  *  This function actually turns the device on. Before this  function is
1901  *  called,all Registers are configured from their reset states
1902  *  and shared memory is allocated but the NIC is still quiescent. On
1903  *  calling this function, the device interrupts are cleared and the NIC is
1904  *  literally switched on by writing into the adapter control register.
1905  *  Return Value:
1906  *  SUCCESS on success and -1 on failure.
1907  */
1908
1909 static int start_nic(struct s2io_nic *nic)
1910 {
1911         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1912         struct net_device *dev = nic->dev;
1913         register u64 val64 = 0;
1914         u16 subid, i;
1915         mac_info_t *mac_control;
1916         struct config_param *config;
1917
1918         mac_control = &nic->mac_control;
1919         config = &nic->config;
1920
1921         /*  PRC Initialization and configuration */
1922         for (i = 0; i < config->rx_ring_num; i++) {
1923                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1924                        &bar0->prc_rxd0_n[i]);
1925
1926                 val64 = readq(&bar0->prc_ctrl_n[i]);
1927                 if (nic->config.bimodal)
1928                         val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
1929                 if (nic->rxd_mode == RXD_MODE_1)
1930                         val64 |= PRC_CTRL_RC_ENABLED;
1931                 else
1932                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
1933                 if (nic->device_type == XFRAME_II_DEVICE)
1934                         val64 |= PRC_CTRL_GROUP_READS;
1935                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
1936                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1937                 writeq(val64, &bar0->prc_ctrl_n[i]);
1938         }
1939
1940         if (nic->rxd_mode == RXD_MODE_3B) {
1941                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
1942                 val64 = readq(&bar0->rx_pa_cfg);
1943                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
1944                 writeq(val64, &bar0->rx_pa_cfg);
1945         }
1946
1947         /*
1948          * Enabling MC-RLDRAM. After enabling the device, we timeout
1949          * for around 100ms, which is approximately the time required
1950          * for the device to be ready for operation.
1951          */
1952         val64 = readq(&bar0->mc_rldram_mrs);
1953         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
1954         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
1955         val64 = readq(&bar0->mc_rldram_mrs);
1956
1957         msleep(100);    /* Delay by around 100 ms. */
1958
1959         /* Enabling ECC Protection. */
1960         val64 = readq(&bar0->adapter_control);
1961         val64 &= ~ADAPTER_ECC_EN;
1962         writeq(val64, &bar0->adapter_control);
1963
1964         /*
1965          * Clearing any possible Link state change interrupts that
1966          * could have popped up just before Enabling the card.
1967          */
1968         val64 = readq(&bar0->mac_rmac_err_reg);
1969         if (val64)
1970                 writeq(val64, &bar0->mac_rmac_err_reg);
1971
1972         /*
1973          * Verify if the device is ready to be enabled, if so enable
1974          * it.
1975          */
1976         val64 = readq(&bar0->adapter_status);
1977         if (!verify_xena_quiescence(nic)) {
1978                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
1979                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
1980                           (unsigned long long) val64);
1981                 return FAILURE;
1982         }
1983
1984         /*
1985          * With some switches, link might be already up at this point.
1986          * Because of this weird behavior, when we enable laser,
1987          * we may not get link. We need to handle this. We cannot
1988          * figure out which switch is misbehaving. So we are forced to
1989          * make a global change.
1990          */
1991
1992         /* Enabling Laser. */
1993         val64 = readq(&bar0->adapter_control);
1994         val64 |= ADAPTER_EOI_TX_ON;
1995         writeq(val64, &bar0->adapter_control);
1996
1997         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
1998                 /*
1999                  * Dont see link state interrupts initally on some switches,
2000                  * so directly scheduling the link state task here.
2001                  */
2002                 schedule_work(&nic->set_link_task);
2003         }
2004         /* SXE-002: Initialize link and activity LED */
2005         subid = nic->pdev->subsystem_device;
2006         if (((subid & 0xFF) >= 0x07) &&
2007             (nic->device_type == XFRAME_I_DEVICE)) {
2008                 val64 = readq(&bar0->gpio_control);
2009                 val64 |= 0x0000800000000000ULL;
2010                 writeq(val64, &bar0->gpio_control);
2011                 val64 = 0x0411040400000000ULL;
2012                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2013         }
2014
2015         return SUCCESS;
2016 }
2017 /**
2018  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2019  */
2020 static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, int get_off)
2021 {
2022         nic_t *nic = fifo_data->nic;
2023         struct sk_buff *skb;
2024         TxD_t *txds;
2025         u16 j, frg_cnt;
2026
2027         txds = txdlp;
2028         if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2029                 pci_unmap_single(nic->pdev, (dma_addr_t)
2030                         txds->Buffer_Pointer, sizeof(u64),
2031                         PCI_DMA_TODEVICE);
2032                 txds++;
2033         }
2034
2035         skb = (struct sk_buff *) ((unsigned long)
2036                         txds->Host_Control);
2037         if (!skb) {
2038                 memset(txdlp, 0, (sizeof(TxD_t) * fifo_data->max_txds));
2039                 return NULL;
2040         }
2041         pci_unmap_single(nic->pdev, (dma_addr_t)
2042                          txds->Buffer_Pointer,
2043                          skb->len - skb->data_len,
2044                          PCI_DMA_TODEVICE);
2045         frg_cnt = skb_shinfo(skb)->nr_frags;
2046         if (frg_cnt) {
2047                 txds++;
2048                 for (j = 0; j < frg_cnt; j++, txds++) {
2049                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2050                         if (!txds->Buffer_Pointer)
2051                                 break;
2052                         pci_unmap_page(nic->pdev, (dma_addr_t)
2053                                         txds->Buffer_Pointer,
2054                                        frag->size, PCI_DMA_TODEVICE);
2055                 }
2056         }
2057         memset(txdlp,0, (sizeof(TxD_t) * fifo_data->max_txds));
2058         return(skb);
2059 }
2060
2061 /**
2062  *  free_tx_buffers - Free all queued Tx buffers
2063  *  @nic : device private variable.
2064  *  Description:
2065  *  Free all queued Tx buffers.
2066  *  Return Value: void
2067 */
2068
2069 static void free_tx_buffers(struct s2io_nic *nic)
2070 {
2071         struct net_device *dev = nic->dev;
2072         struct sk_buff *skb;
2073         TxD_t *txdp;
2074         int i, j;
2075         mac_info_t *mac_control;
2076         struct config_param *config;
2077         int cnt = 0;
2078
2079         mac_control = &nic->mac_control;
2080         config = &nic->config;
2081
2082         for (i = 0; i < config->tx_fifo_num; i++) {
2083                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2084                         txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
2085                             list_virt_addr;
2086                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2087                         if (skb) {
2088                                 dev_kfree_skb(skb);
2089                                 cnt++;
2090                         }
2091                 }
2092                 DBG_PRINT(INTR_DBG,
2093                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2094                           dev->name, cnt, i);
2095                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2096                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2097         }
2098 }
2099
2100 /**
2101  *   stop_nic -  To stop the nic
2102  *   @nic ; device private variable.
2103  *   Description:
2104  *   This function does exactly the opposite of what the start_nic()
2105  *   function does. This function is called to stop the device.
2106  *   Return Value:
2107  *   void.
2108  */
2109
2110 static void stop_nic(struct s2io_nic *nic)
2111 {
2112         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2113         register u64 val64 = 0;
2114         u16 interruptible;
2115         mac_info_t *mac_control;
2116         struct config_param *config;
2117
2118         mac_control = &nic->mac_control;
2119         config = &nic->config;
2120
2121         /*  Disable all interrupts */
2122         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2123         interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2124         interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2125         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2126
2127         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2128         val64 = readq(&bar0->adapter_control);
2129         val64 &= ~(ADAPTER_CNTL_EN);
2130         writeq(val64, &bar0->adapter_control);
2131 }
2132
2133 static int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
2134 {
2135         struct net_device *dev = nic->dev;
2136         struct sk_buff *frag_list;
2137         void *tmp;
2138
2139         /* Buffer-1 receives L3/L4 headers */
2140         ((RxD3_t*)rxdp)->Buffer1_ptr = pci_map_single
2141                         (nic->pdev, skb->data, l3l4hdr_size + 4,
2142                         PCI_DMA_FROMDEVICE);
2143
2144         /* skb_shinfo(skb)->frag_list will have L4 data payload */
2145         skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2146         if (skb_shinfo(skb)->frag_list == NULL) {
2147                 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2148                 return -ENOMEM ;
2149         }
2150         frag_list = skb_shinfo(skb)->frag_list;
2151         skb->truesize += frag_list->truesize;
2152         frag_list->next = NULL;
2153         tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2154         frag_list->data = tmp;
2155         frag_list->tail = tmp;
2156
2157         /* Buffer-2 receives L4 data payload */
2158         ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2159                                 frag_list->data, dev->mtu,
2160                                 PCI_DMA_FROMDEVICE);
2161         rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2162         rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2163
2164         return SUCCESS;
2165 }
2166
2167 /**
2168  *  fill_rx_buffers - Allocates the Rx side skbs
2169  *  @nic:  device private variable
2170  *  @ring_no: ring number
2171  *  Description:
2172  *  The function allocates Rx side skbs and puts the physical
2173  *  address of these buffers into the RxD buffer pointers, so that the NIC
2174  *  can DMA the received frame into these locations.
2175  *  The NIC supports 3 receive modes, viz
2176  *  1. single buffer,
2177  *  2. three buffer and
2178  *  3. Five buffer modes.
2179  *  Each mode defines how many fragments the received frame will be split
2180  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2181  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2182  *  is split into 3 fragments. As of now only single buffer mode is
2183  *  supported.
2184  *   Return Value:
2185  *  SUCCESS on success or an appropriate -ve value on failure.
2186  */
2187
2188 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2189 {
2190         struct net_device *dev = nic->dev;
2191         struct sk_buff *skb;
2192         RxD_t *rxdp;
2193         int off, off1, size, block_no, block_no1;
2194         u32 alloc_tab = 0;
2195         u32 alloc_cnt;
2196         mac_info_t *mac_control;
2197         struct config_param *config;
2198         u64 tmp;
2199         buffAdd_t *ba;
2200         unsigned long flags;
2201         RxD_t *first_rxdp = NULL;
2202
2203         mac_control = &nic->mac_control;
2204         config = &nic->config;
2205         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2206             atomic_read(&nic->rx_bufs_left[ring_no]);
2207
2208         block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2209         off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2210         while (alloc_tab < alloc_cnt) {
2211                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2212                     block_index;
2213                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2214
2215                 rxdp = mac_control->rings[ring_no].
2216                                 rx_blocks[block_no].rxds[off].virt_addr;
2217
2218                 if ((block_no == block_no1) && (off == off1) &&
2219                                         (rxdp->Host_Control)) {
2220                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2221                                   dev->name);
2222                         DBG_PRINT(INTR_DBG, " info equated\n");
2223                         goto end;
2224                 }
2225                 if (off && (off == rxd_count[nic->rxd_mode])) {
2226                         mac_control->rings[ring_no].rx_curr_put_info.
2227                             block_index++;
2228                         if (mac_control->rings[ring_no].rx_curr_put_info.
2229                             block_index == mac_control->rings[ring_no].
2230                                         block_count)
2231                                 mac_control->rings[ring_no].rx_curr_put_info.
2232                                         block_index = 0;
2233                         block_no = mac_control->rings[ring_no].
2234                                         rx_curr_put_info.block_index;
2235                         if (off == rxd_count[nic->rxd_mode])
2236                                 off = 0;
2237                         mac_control->rings[ring_no].rx_curr_put_info.
2238                                 offset = off;
2239                         rxdp = mac_control->rings[ring_no].
2240                                 rx_blocks[block_no].block_virt_addr;
2241                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2242                                   dev->name, rxdp);
2243                 }
2244                 if(!napi) {
2245                         spin_lock_irqsave(&nic->put_lock, flags);
2246                         mac_control->rings[ring_no].put_pos =
2247                         (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2248                         spin_unlock_irqrestore(&nic->put_lock, flags);
2249                 } else {
2250                         mac_control->rings[ring_no].put_pos =
2251                         (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2252                 }
2253                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2254                         ((nic->rxd_mode >= RXD_MODE_3A) &&
2255                                 (rxdp->Control_2 & BIT(0)))) {
2256                         mac_control->rings[ring_no].rx_curr_put_info.
2257                                         offset = off;
2258                         goto end;
2259                 }
2260                 /* calculate size of skb based on ring mode */
2261                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2262                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2263                 if (nic->rxd_mode == RXD_MODE_1)
2264                         size += NET_IP_ALIGN;
2265                 else if (nic->rxd_mode == RXD_MODE_3B)
2266                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2267                 else
2268                         size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
2269
2270                 /* allocate skb */
2271                 skb = dev_alloc_skb(size);
2272                 if(!skb) {
2273                         DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2274                         DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
2275                         if (first_rxdp) {
2276                                 wmb();
2277                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2278                         }
2279                         return -ENOMEM ;
2280                 }
2281                 if (nic->rxd_mode == RXD_MODE_1) {
2282                         /* 1 buffer mode - normal operation mode */
2283                         memset(rxdp, 0, sizeof(RxD1_t));
2284                         skb_reserve(skb, NET_IP_ALIGN);
2285                         ((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single
2286                             (nic->pdev, skb->data, size - NET_IP_ALIGN,
2287                                 PCI_DMA_FROMDEVICE);
2288                         rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2289
2290                 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2291                         /*
2292                          * 2 or 3 buffer mode -
2293                          * Both 2 buffer mode and 3 buffer mode provides 128
2294                          * byte aligned receive buffers.
2295                          *
2296                          * 3 buffer mode provides header separation where in
2297                          * skb->data will have L3/L4 headers where as
2298                          * skb_shinfo(skb)->frag_list will have the L4 data
2299                          * payload
2300                          */
2301
2302                         memset(rxdp, 0, sizeof(RxD3_t));
2303                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2304                         skb_reserve(skb, BUF0_LEN);
2305                         tmp = (u64)(unsigned long) skb->data;
2306                         tmp += ALIGN_SIZE;
2307                         tmp &= ~ALIGN_SIZE;
2308                         skb->data = (void *) (unsigned long)tmp;
2309                         skb->tail = (void *) (unsigned long)tmp;
2310
2311                         if (!(((RxD3_t*)rxdp)->Buffer0_ptr))
2312                                 ((RxD3_t*)rxdp)->Buffer0_ptr =
2313                                    pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2314                                            PCI_DMA_FROMDEVICE);
2315                         else
2316                                 pci_dma_sync_single_for_device(nic->pdev,
2317                                     (dma_addr_t) ((RxD3_t*)rxdp)->Buffer0_ptr,
2318                                     BUF0_LEN, PCI_DMA_FROMDEVICE);
2319                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2320                         if (nic->rxd_mode == RXD_MODE_3B) {
2321                                 /* Two buffer mode */
2322
2323                                 /*
2324                                  * Buffer2 will have L3/L4 header plus
2325                                  * L4 payload
2326                                  */
2327                                 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single
2328                                 (nic->pdev, skb->data, dev->mtu + 4,
2329                                                 PCI_DMA_FROMDEVICE);
2330
2331                                 /* Buffer-1 will be dummy buffer. Not used */
2332                                 if (!(((RxD3_t*)rxdp)->Buffer1_ptr)) {
2333                                         ((RxD3_t*)rxdp)->Buffer1_ptr =
2334                                                 pci_map_single(nic->pdev,
2335                                                 ba->ba_1, BUF1_LEN,
2336                                                 PCI_DMA_FROMDEVICE);
2337                                 }
2338                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2339                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2340                                                                 (dev->mtu + 4);
2341                         } else {
2342                                 /* 3 buffer mode */
2343                                 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2344                                         dev_kfree_skb_irq(skb);
2345                                         if (first_rxdp) {
2346                                                 wmb();
2347                                                 first_rxdp->Control_1 |=
2348                                                         RXD_OWN_XENA;
2349                                         }
2350                                         return -ENOMEM ;
2351                                 }
2352                         }
2353                         rxdp->Control_2 |= BIT(0);
2354                 }
2355                 rxdp->Host_Control = (unsigned long) (skb);
2356                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2357                         rxdp->Control_1 |= RXD_OWN_XENA;
2358                 off++;
2359                 if (off == (rxd_count[nic->rxd_mode] + 1))
2360                         off = 0;
2361                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2362
2363                 rxdp->Control_2 |= SET_RXD_MARKER;
2364                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2365                         if (first_rxdp) {
2366                                 wmb();
2367                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2368                         }
2369                         first_rxdp = rxdp;
2370                 }
2371                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2372                 alloc_tab++;
2373         }
2374
2375       end:
2376         /* Transfer ownership of first descriptor to adapter just before
2377          * exiting. Before that, use memory barrier so that ownership
2378          * and other fields are seen by adapter correctly.
2379          */
2380         if (first_rxdp) {
2381                 wmb();
2382                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2383         }
2384
2385         return SUCCESS;
2386 }
2387
2388 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2389 {
2390         struct net_device *dev = sp->dev;
2391         int j;
2392         struct sk_buff *skb;
2393         RxD_t *rxdp;
2394         mac_info_t *mac_control;
2395         buffAdd_t *ba;
2396
2397         mac_control = &sp->mac_control;
2398         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2399                 rxdp = mac_control->rings[ring_no].
2400                                 rx_blocks[blk].rxds[j].virt_addr;
2401                 skb = (struct sk_buff *)
2402                         ((unsigned long) rxdp->Host_Control);
2403                 if (!skb) {
2404                         continue;
2405                 }
2406                 if (sp->rxd_mode == RXD_MODE_1) {
2407                         pci_unmap_single(sp->pdev, (dma_addr_t)
2408                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2409                                  dev->mtu +
2410                                  HEADER_ETHERNET_II_802_3_SIZE
2411                                  + HEADER_802_2_SIZE +
2412                                  HEADER_SNAP_SIZE,
2413                                  PCI_DMA_FROMDEVICE);
2414                         memset(rxdp, 0, sizeof(RxD1_t));
2415                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2416                         ba = &mac_control->rings[ring_no].
2417                                 ba[blk][j];
2418                         pci_unmap_single(sp->pdev, (dma_addr_t)
2419                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2420                                  BUF0_LEN,
2421                                  PCI_DMA_FROMDEVICE);
2422                         pci_unmap_single(sp->pdev, (dma_addr_t)
2423                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2424                                  BUF1_LEN,
2425                                  PCI_DMA_FROMDEVICE);
2426                         pci_unmap_single(sp->pdev, (dma_addr_t)
2427                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2428                                  dev->mtu + 4,
2429                                  PCI_DMA_FROMDEVICE);
2430                         memset(rxdp, 0, sizeof(RxD3_t));
2431                 } else {
2432                         pci_unmap_single(sp->pdev, (dma_addr_t)
2433                                 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2434                                 PCI_DMA_FROMDEVICE);
2435                         pci_unmap_single(sp->pdev, (dma_addr_t)
2436                                 ((RxD3_t*)rxdp)->Buffer1_ptr,
2437                                 l3l4hdr_size + 4,
2438                                 PCI_DMA_FROMDEVICE);
2439                         pci_unmap_single(sp->pdev, (dma_addr_t)
2440                                 ((RxD3_t*)rxdp)->Buffer2_ptr, dev->mtu,
2441                                 PCI_DMA_FROMDEVICE);
2442                         memset(rxdp, 0, sizeof(RxD3_t));
2443                 }
2444                 dev_kfree_skb(skb);
2445                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2446         }
2447 }
2448
2449 /**
2450  *  free_rx_buffers - Frees all Rx buffers
2451  *  @sp: device private variable.
2452  *  Description:
2453  *  This function will free all Rx buffers allocated by host.
2454  *  Return Value:
2455  *  NONE.
2456  */
2457
2458 static void free_rx_buffers(struct s2io_nic *sp)
2459 {
2460         struct net_device *dev = sp->dev;
2461         int i, blk = 0, buf_cnt = 0;
2462         mac_info_t *mac_control;
2463         struct config_param *config;
2464
2465         mac_control = &sp->mac_control;
2466         config = &sp->config;
2467
2468         for (i = 0; i < config->rx_ring_num; i++) {
2469                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2470                         free_rxd_blk(sp,i,blk);
2471
2472                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2473                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2474                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2475                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2476                 atomic_set(&sp->rx_bufs_left[i], 0);
2477                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2478                           dev->name, buf_cnt, i);
2479         }
2480 }
2481
2482 /**
2483  * s2io_poll - Rx interrupt handler for NAPI support
2484  * @dev : pointer to the device structure.
2485  * @budget : The number of packets that were budgeted to be processed
2486  * during  one pass through the 'Poll" function.
2487  * Description:
2488  * Comes into picture only if NAPI support has been incorporated. It does
2489  * the same thing that rx_intr_handler does, but not in a interrupt context
2490  * also It will process only a given number of packets.
2491  * Return value:
2492  * 0 on success and 1 if there are No Rx packets to be processed.
2493  */
2494
2495 static int s2io_poll(struct net_device *dev, int *budget)
2496 {
2497         nic_t *nic = dev->priv;
2498         int pkt_cnt = 0, org_pkts_to_process;
2499         mac_info_t *mac_control;
2500         struct config_param *config;
2501         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2502         int i;
2503
2504         atomic_inc(&nic->isr_cnt);
2505         mac_control = &nic->mac_control;
2506         config = &nic->config;
2507
2508         nic->pkts_to_process = *budget;
2509         if (nic->pkts_to_process > dev->quota)
2510                 nic->pkts_to_process = dev->quota;
2511         org_pkts_to_process = nic->pkts_to_process;
2512
2513         writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2514         readl(&bar0->rx_traffic_int);
2515
2516         for (i = 0; i < config->rx_ring_num; i++) {
2517                 rx_intr_handler(&mac_control->rings[i]);
2518                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2519                 if (!nic->pkts_to_process) {
2520                         /* Quota for the current iteration has been met */
2521                         goto no_rx;
2522                 }
2523         }
2524         if (!pkt_cnt)
2525                 pkt_cnt = 1;
2526
2527         dev->quota -= pkt_cnt;
2528         *budget -= pkt_cnt;
2529         netif_rx_complete(dev);
2530
2531         for (i = 0; i < config->rx_ring_num; i++) {
2532                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2533                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2534                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2535                         break;
2536                 }
2537         }
2538         /* Re enable the Rx interrupts. */
2539         writeq(0x0, &bar0->rx_traffic_mask);
2540         readl(&bar0->rx_traffic_mask);
2541         atomic_dec(&nic->isr_cnt);
2542         return 0;
2543
2544 no_rx:
2545         dev->quota -= pkt_cnt;
2546         *budget -= pkt_cnt;
2547
2548         for (i = 0; i < config->rx_ring_num; i++) {
2549                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2550                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2551                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2552                         break;
2553                 }
2554         }
2555         atomic_dec(&nic->isr_cnt);
2556         return 1;
2557 }
2558
2559 #ifdef CONFIG_NET_POLL_CONTROLLER
2560 /**
2561  * s2io_netpoll - netpoll event handler entry point
2562  * @dev : pointer to the device structure.
2563  * Description:
2564  *      This function will be called by upper layer to check for events on the
2565  * interface in situations where interrupts are disabled. It is used for
2566  * specific in-kernel networking tasks, such as remote consoles and kernel
2567  * debugging over the network (example netdump in RedHat).
2568  */
2569 static void s2io_netpoll(struct net_device *dev)
2570 {
2571         nic_t *nic = dev->priv;
2572         mac_info_t *mac_control;
2573         struct config_param *config;
2574         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2575         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2576         int i;
2577
2578         disable_irq(dev->irq);
2579
2580         atomic_inc(&nic->isr_cnt);
2581         mac_control = &nic->mac_control;
2582         config = &nic->config;
2583
2584         writeq(val64, &bar0->rx_traffic_int);
2585         writeq(val64, &bar0->tx_traffic_int);
2586
2587         /* we need to free up the transmitted skbufs or else netpoll will
2588          * run out of skbs and will fail and eventually netpoll application such
2589          * as netdump will fail.
2590          */
2591         for (i = 0; i < config->tx_fifo_num; i++)
2592                 tx_intr_handler(&mac_control->fifos[i]);
2593
2594         /* check for received packet and indicate up to network */
2595         for (i = 0; i < config->rx_ring_num; i++)
2596                 rx_intr_handler(&mac_control->rings[i]);
2597
2598         for (i = 0; i < config->rx_ring_num; i++) {
2599                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2600                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2601                         DBG_PRINT(ERR_DBG, " in Rx Netpoll!!\n");
2602                         break;
2603                 }
2604         }
2605         atomic_dec(&nic->isr_cnt);
2606         enable_irq(dev->irq);
2607         return;
2608 }
2609 #endif
2610
2611 /**
2612  *  rx_intr_handler - Rx interrupt handler
2613  *  @nic: device private variable.
2614  *  Description:
2615  *  If the interrupt is because of a received frame or if the
2616  *  receive ring contains fresh as yet un-processed frames,this function is
2617  *  called. It picks out the RxD at which place the last Rx processing had
2618  *  stopped and sends the skb to the OSM's Rx handler and then increments
2619  *  the offset.
2620  *  Return Value:
2621  *  NONE.
2622  */
2623 static void rx_intr_handler(ring_info_t *ring_data)
2624 {
2625         nic_t *nic = ring_data->nic;
2626         struct net_device *dev = (struct net_device *) nic->dev;
2627         int get_block, put_block, put_offset;
2628         rx_curr_get_info_t get_info, put_info;
2629         RxD_t *rxdp;
2630         struct sk_buff *skb;
2631         int pkt_cnt = 0;
2632         int i;
2633
2634         spin_lock(&nic->rx_lock);
2635         if (atomic_read(&nic->card_state) == CARD_DOWN) {
2636                 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2637                           __FUNCTION__, dev->name);
2638                 spin_unlock(&nic->rx_lock);
2639                 return;
2640         }
2641
2642         get_info = ring_data->rx_curr_get_info;
2643         get_block = get_info.block_index;
2644         put_info = ring_data->rx_curr_put_info;
2645         put_block = put_info.block_index;
2646         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2647         if (!napi) {
2648                 spin_lock(&nic->put_lock);
2649                 put_offset = ring_data->put_pos;
2650                 spin_unlock(&nic->put_lock);
2651         } else
2652                 put_offset = ring_data->put_pos;
2653
2654         while (RXD_IS_UP2DT(rxdp)) {
2655                 /*
2656                  * If your are next to put index then it's
2657                  * FIFO full condition
2658                  */
2659                 if ((get_block == put_block) &&
2660                     (get_info.offset + 1) == put_info.offset) {
2661                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
2662                         break;
2663                 }
2664                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2665                 if (skb == NULL) {
2666                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2667                                   dev->name);
2668                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2669                         spin_unlock(&nic->rx_lock);
2670                         return;
2671                 }
2672                 if (nic->rxd_mode == RXD_MODE_1) {
2673                         pci_unmap_single(nic->pdev, (dma_addr_t)
2674                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2675                                  dev->mtu +
2676                                  HEADER_ETHERNET_II_802_3_SIZE +
2677                                  HEADER_802_2_SIZE +
2678                                  HEADER_SNAP_SIZE,
2679                                  PCI_DMA_FROMDEVICE);
2680                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2681                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2682                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2683                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
2684                         pci_unmap_single(nic->pdev, (dma_addr_t)
2685                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2686                                  dev->mtu + 4,
2687                                  PCI_DMA_FROMDEVICE);
2688                 } else {
2689                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2690                                          ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2691                                          PCI_DMA_FROMDEVICE);
2692                         pci_unmap_single(nic->pdev, (dma_addr_t)
2693                                          ((RxD3_t*)rxdp)->Buffer1_ptr,
2694                                          l3l4hdr_size + 4,
2695                                          PCI_DMA_FROMDEVICE);
2696                         pci_unmap_single(nic->pdev, (dma_addr_t)
2697                                          ((RxD3_t*)rxdp)->Buffer2_ptr,
2698                                          dev->mtu, PCI_DMA_FROMDEVICE);
2699                 }
2700                 prefetch(skb->data);
2701                 rx_osm_handler(ring_data, rxdp);
2702                 get_info.offset++;
2703                 ring_data->rx_curr_get_info.offset = get_info.offset;
2704                 rxdp = ring_data->rx_blocks[get_block].
2705                                 rxds[get_info.offset].virt_addr;
2706                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2707                         get_info.offset = 0;
2708                         ring_data->rx_curr_get_info.offset = get_info.offset;
2709                         get_block++;
2710                         if (get_block == ring_data->block_count)
2711                                 get_block = 0;
2712                         ring_data->rx_curr_get_info.block_index = get_block;
2713                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2714                 }
2715
2716                 nic->pkts_to_process -= 1;
2717                 if ((napi) && (!nic->pkts_to_process))
2718                         break;
2719                 pkt_cnt++;
2720                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2721                         break;
2722         }
2723         if (nic->lro) {
2724                 /* Clear all LRO sessions before exiting */
2725                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2726                         lro_t *lro = &nic->lro0_n[i];
2727                         if (lro->in_use) {
2728                                 update_L3L4_header(nic, lro);
2729                                 queue_rx_frame(lro->parent);
2730                                 clear_lro_session(lro);
2731                         }
2732                 }
2733         }
2734
2735         spin_unlock(&nic->rx_lock);
2736 }
2737
2738 /**
2739  *  tx_intr_handler - Transmit interrupt handler
2740  *  @nic : device private variable
2741  *  Description:
2742  *  If an interrupt was raised to indicate DMA complete of the
2743  *  Tx packet, this function is called. It identifies the last TxD
2744  *  whose buffer was freed and frees all skbs whose data have already
2745  *  DMA'ed into the NICs internal memory.
2746  *  Return Value:
2747  *  NONE
2748  */
2749
2750 static void tx_intr_handler(fifo_info_t *fifo_data)
2751 {
2752         nic_t *nic = fifo_data->nic;
2753         struct net_device *dev = (struct net_device *) nic->dev;
2754         tx_curr_get_info_t get_info, put_info;
2755         struct sk_buff *skb;
2756         TxD_t *txdlp;
2757
2758         get_info = fifo_data->tx_curr_get_info;
2759         put_info = fifo_data->tx_curr_put_info;
2760         txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2761             list_virt_addr;
2762         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2763                (get_info.offset != put_info.offset) &&
2764                (txdlp->Host_Control)) {
2765                 /* Check for TxD errors */
2766                 if (txdlp->Control_1 & TXD_T_CODE) {
2767                         unsigned long long err;
2768                         err = txdlp->Control_1 & TXD_T_CODE;
2769                         if (err & 0x1) {
2770                                 nic->mac_control.stats_info->sw_stat.
2771                                                 parity_err_cnt++;
2772                         }
2773                         if ((err >> 48) == 0xA) {
2774                                 DBG_PRINT(TX_DBG, "TxD returned due \
2775                                                 to loss of link\n");
2776                         }
2777                         else {
2778                                 DBG_PRINT(ERR_DBG, "***TxD error %llx\n", err);
2779                         }
2780                 }
2781
2782                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2783                 if (skb == NULL) {
2784                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
2785                         __FUNCTION__);
2786                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2787                         return;
2788                 }
2789
2790                 /* Updating the statistics block */
2791                 nic->stats.tx_bytes += skb->len;
2792                 dev_kfree_skb_irq(skb);
2793
2794                 get_info.offset++;
2795                 if (get_info.offset == get_info.fifo_len + 1)
2796                         get_info.offset = 0;
2797                 txdlp = (TxD_t *) fifo_data->list_info
2798                     [get_info.offset].list_virt_addr;
2799                 fifo_data->tx_curr_get_info.offset =
2800                     get_info.offset;
2801         }
2802
2803         spin_lock(&nic->tx_lock);
2804         if (netif_queue_stopped(dev))
2805                 netif_wake_queue(dev);
2806         spin_unlock(&nic->tx_lock);
2807 }
2808
2809 /**
2810  *  s2io_mdio_write - Function to write in to MDIO registers
2811  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2812  *  @addr     : address value
2813  *  @value    : data value
2814  *  @dev      : pointer to net_device structure
2815  *  Description:
2816  *  This function is used to write values to the MDIO registers
2817  *  NONE
2818  */
2819 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2820 {
2821         u64 val64 = 0x0;
2822         nic_t *sp = dev->priv;
2823         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2824
2825         //address transaction
2826         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2827                         | MDIO_MMD_DEV_ADDR(mmd_type)
2828                         | MDIO_MMS_PRT_ADDR(0x0);
2829         writeq(val64, &bar0->mdio_control);
2830         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2831         writeq(val64, &bar0->mdio_control);
2832         udelay(100);
2833
2834         //Data transaction
2835         val64 = 0x0;
2836         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2837                         | MDIO_MMD_DEV_ADDR(mmd_type)
2838                         | MDIO_MMS_PRT_ADDR(0x0)
2839                         | MDIO_MDIO_DATA(value)
2840                         | MDIO_OP(MDIO_OP_WRITE_TRANS);
2841         writeq(val64, &bar0->mdio_control);
2842         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2843         writeq(val64, &bar0->mdio_control);
2844         udelay(100);
2845
2846         val64 = 0x0;
2847         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2848         | MDIO_MMD_DEV_ADDR(mmd_type)
2849         | MDIO_MMS_PRT_ADDR(0x0)
2850         | MDIO_OP(MDIO_OP_READ_TRANS);
2851         writeq(val64, &bar0->mdio_control);
2852         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2853         writeq(val64, &bar0->mdio_control);
2854         udelay(100);
2855
2856 }
2857
2858 /**
2859  *  s2io_mdio_read - Function to write in to MDIO registers
2860  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2861  *  @addr     : address value
2862  *  @dev      : pointer to net_device structure
2863  *  Description:
2864  *  This function is used to read values to the MDIO registers
2865  *  NONE
2866  */
2867 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
2868 {
2869         u64 val64 = 0x0;
2870         u64 rval64 = 0x0;
2871         nic_t *sp = dev->priv;
2872         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2873
2874         /* address transaction */
2875         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2876                         | MDIO_MMD_DEV_ADDR(mmd_type)
2877                         | MDIO_MMS_PRT_ADDR(0x0);
2878         writeq(val64, &bar0->mdio_control);
2879         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2880         writeq(val64, &bar0->mdio_control);
2881         udelay(100);
2882
2883         /* Data transaction */
2884         val64 = 0x0;
2885         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2886                         | MDIO_MMD_DEV_ADDR(mmd_type)
2887                         | MDIO_MMS_PRT_ADDR(0x0)
2888                         | MDIO_OP(MDIO_OP_READ_TRANS);
2889         writeq(val64, &bar0->mdio_control);
2890         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2891         writeq(val64, &bar0->mdio_control);
2892         udelay(100);
2893
2894         /* Read the value from regs */
2895         rval64 = readq(&bar0->mdio_control);
2896         rval64 = rval64 & 0xFFFF0000;
2897         rval64 = rval64 >> 16;
2898         return rval64;
2899 }
2900 /**
2901  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
2902  *  @counter      : couter value to be updated
2903  *  @flag         : flag to indicate the status
2904  *  @type         : counter type
2905  *  Description:
2906  *  This function is to check the status of the xpak counters value
2907  *  NONE
2908  */
2909
2910 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
2911 {
2912         u64 mask = 0x3;
2913         u64 val64;
2914         int i;
2915         for(i = 0; i <index; i++)
2916                 mask = mask << 0x2;
2917
2918         if(flag > 0)
2919         {
2920                 *counter = *counter + 1;
2921                 val64 = *regs_stat & mask;
2922                 val64 = val64 >> (index * 0x2);
2923                 val64 = val64 + 1;
2924                 if(val64 == 3)
2925                 {
2926                         switch(type)
2927                         {
2928                         case 1:
2929                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
2930                                           "service. Excessive temperatures may "
2931                                           "result in premature transceiver "
2932                                           "failure \n");
2933                         break;
2934                         case 2:
2935                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
2936                                           "service Excessive bias currents may "
2937                                           "indicate imminent laser diode "
2938                                           "failure \n");
2939                         break;
2940                         case 3:
2941                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
2942                                           "service Excessive laser output "
2943                                           "power may saturate far-end "
2944                                           "receiver\n");
2945                         break;
2946                         default:
2947                                 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
2948                                           "type \n");
2949                         }
2950                         val64 = 0x0;
2951                 }
2952                 val64 = val64 << (index * 0x2);
2953                 *regs_stat = (*regs_stat & (~mask)) | (val64);
2954
2955         } else {
2956                 *regs_stat = *regs_stat & (~mask);
2957         }
2958 }
2959
2960 /**
2961  *  s2io_updt_xpak_counter - Function to update the xpak counters
2962  *  @dev         : pointer to net_device struct
2963  *  Description:
2964  *  This function is to upate the status of the xpak counters value
2965  *  NONE
2966  */
2967 static void s2io_updt_xpak_counter(struct net_device *dev)
2968 {
2969         u16 flag  = 0x0;
2970         u16 type  = 0x0;
2971         u16 val16 = 0x0;
2972         u64 val64 = 0x0;
2973         u64 addr  = 0x0;
2974
2975         nic_t *sp = dev->priv;
2976         StatInfo_t *stat_info = sp->mac_control.stats_info;
2977
2978         /* Check the communication with the MDIO slave */
2979         addr = 0x0000;
2980         val64 = 0x0;
2981         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
2982         if((val64 == 0xFFFF) || (val64 == 0x0000))
2983         {
2984                 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
2985                           "Returned %llx\n", (unsigned long long)val64);
2986                 return;
2987         }
2988
2989         /* Check for the expecte value of 2040 at PMA address 0x0000 */
2990         if(val64 != 0x2040)
2991         {
2992                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
2993                 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
2994                           (unsigned long long)val64);
2995                 return;
2996         }
2997
2998         /* Loading the DOM register to MDIO register */
2999         addr = 0xA100;
3000         s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3001         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3002
3003         /* Reading the Alarm flags */
3004         addr = 0xA070;
3005         val64 = 0x0;
3006         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3007
3008         flag = CHECKBIT(val64, 0x7);
3009         type = 1;
3010         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3011                                 &stat_info->xpak_stat.xpak_regs_stat,
3012                                 0x0, flag, type);
3013
3014         if(CHECKBIT(val64, 0x6))
3015                 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3016
3017         flag = CHECKBIT(val64, 0x3);
3018         type = 2;
3019         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3020                                 &stat_info->xpak_stat.xpak_regs_stat,
3021                                 0x2, flag, type);
3022
3023         if(CHECKBIT(val64, 0x2))
3024                 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3025
3026         flag = CHECKBIT(val64, 0x1);
3027         type = 3;
3028         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3029                                 &stat_info->xpak_stat.xpak_regs_stat,
3030                                 0x4, flag, type);
3031
3032         if(CHECKBIT(val64, 0x0))
3033                 stat_info->xpak_stat.alarm_laser_output_power_low++;
3034
3035         /* Reading the Warning flags */
3036         addr = 0xA074;
3037         val64 = 0x0;
3038         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3039
3040         if(CHECKBIT(val64, 0x7))
3041                 stat_info->xpak_stat.warn_transceiver_temp_high++;
3042
3043         if(CHECKBIT(val64, 0x6))
3044                 stat_info->xpak_stat.warn_transceiver_temp_low++;
3045
3046         if(CHECKBIT(val64, 0x3))
3047                 stat_info->xpak_stat.warn_laser_bias_current_high++;
3048
3049         if(CHECKBIT(val64, 0x2))
3050                 stat_info->xpak_stat.warn_laser_bias_current_low++;
3051
3052         if(CHECKBIT(val64, 0x1))
3053                 stat_info->xpak_stat.warn_laser_output_power_high++;
3054
3055         if(CHECKBIT(val64, 0x0))
3056                 stat_info->xpak_stat.warn_laser_output_power_low++;
3057 }
3058
3059 /**
3060  *  alarm_intr_handler - Alarm Interrrupt handler
3061  *  @nic: device private variable
3062  *  Description: If the interrupt was neither because of Rx packet or Tx
3063  *  complete, this function is called. If the interrupt was to indicate
3064  *  a loss of link, the OSM link status handler is invoked for any other
3065  *  alarm interrupt the block that raised the interrupt is displayed
3066  *  and a H/W reset is issued.
3067  *  Return Value:
3068  *  NONE
3069 */
3070
3071 static void alarm_intr_handler(struct s2io_nic *nic)
3072 {
3073         struct net_device *dev = (struct net_device *) nic->dev;
3074         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3075         register u64 val64 = 0, err_reg = 0;
3076         u64 cnt;
3077         int i;
3078         if (atomic_read(&nic->card_state) == CARD_DOWN)
3079                 return;
3080         nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3081         /* Handling the XPAK counters update */
3082         if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3083                 /* waiting for an hour */
3084                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3085         } else {
3086                 s2io_updt_xpak_counter(dev);
3087                 /* reset the count to zero */
3088                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3089         }
3090
3091         /* Handling link status change error Intr */
3092         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3093                 err_reg = readq(&bar0->mac_rmac_err_reg);
3094                 writeq(err_reg, &bar0->mac_rmac_err_reg);
3095                 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3096                         schedule_work(&nic->set_link_task);
3097                 }
3098         }
3099
3100         /* Handling Ecc errors */
3101         val64 = readq(&bar0->mc_err_reg);
3102         writeq(val64, &bar0->mc_err_reg);
3103         if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
3104                 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
3105                         nic->mac_control.stats_info->sw_stat.
3106                                 double_ecc_errs++;
3107                         DBG_PRINT(INIT_DBG, "%s: Device indicates ",
3108                                   dev->name);
3109                         DBG_PRINT(INIT_DBG, "double ECC error!!\n");
3110                         if (nic->device_type != XFRAME_II_DEVICE) {
3111                                 /* Reset XframeI only if critical error */
3112                                 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
3113                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
3114                                         netif_stop_queue(dev);
3115                                         schedule_work(&nic->rst_timer_task);
3116                                         nic->mac_control.stats_info->sw_stat.
3117                                                         soft_reset_cnt++;
3118                                 }
3119                         }
3120                 } else {
3121                         nic->mac_control.stats_info->sw_stat.
3122                                 single_ecc_errs++;
3123                 }
3124         }
3125
3126         /* In case of a serious error, the device will be Reset. */