9b9b28e85a7d272dbd690c0744a158bbb05976f0
[linux-3.10.git] / drivers / net / s2io.c
1 /************************************************************************
2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3  * Copyright(c) 2002-2005 Neterion Inc.
4
5  * This software may be used and distributed according to the terms of
6  * the GNU General Public License (GPL), incorporated herein by reference.
7  * Drivers based on or derived from this code fall under the GPL and must
8  * retain the authorship, copyright and license notice.  This file is not
9  * a complete program and may only be used when the entire operating
10  * system is licensed under the GPL.
11  * See the file COPYING in this distribution for more information.
12  *
13  * Credits:
14  * Jeff Garzik          : For pointing out the improper error condition
15  *                        check in the s2io_xmit routine and also some
16  *                        issues in the Tx watch dog function. Also for
17  *                        patiently answering all those innumerable
18  *                        questions regaring the 2.6 porting issues.
19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
20  *                        macros available only in 2.6 Kernel.
21  * Francois Romieu      : For pointing out all code part that were
22  *                        deprecated and also styling related comments.
23  * Grant Grundler       : For helping me get rid of some Architecture
24  *                        dependent code.
25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
26  *
27  * The module loadable parameters that are supported by the driver and a brief
28  * explaination of all the variables.
29  *
30  * rx_ring_num : This can be used to program the number of receive rings used
31  * in the driver.
32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
33  *     This is also an array of size 8.
34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35  *              values are 1, 2 and 3.
36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
38  * Tx descriptors that can be associated with each corresponding FIFO.
39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40  *     1(MSI), 2(MSI_X). Default value is '0(INTA)'
41  * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42  *     Possible values '1' for enable '0' for disable. Default is '0'
43  * lro_max_pkts: This parameter defines maximum number of packets can be
44  *     aggregated as a single large packet
45  ************************************************************************/
46
47 #include <linux/module.h>
48 #include <linux/types.h>
49 #include <linux/errno.h>
50 #include <linux/ioport.h>
51 #include <linux/pci.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/kernel.h>
54 #include <linux/netdevice.h>
55 #include <linux/etherdevice.h>
56 #include <linux/skbuff.h>
57 #include <linux/init.h>
58 #include <linux/delay.h>
59 #include <linux/stddef.h>
60 #include <linux/ioctl.h>
61 #include <linux/timex.h>
62 #include <linux/sched.h>
63 #include <linux/ethtool.h>
64 #include <linux/workqueue.h>
65 #include <linux/if_vlan.h>
66 #include <linux/ip.h>
67 #include <linux/tcp.h>
68 #include <net/tcp.h>
69
70 #include <asm/system.h>
71 #include <asm/uaccess.h>
72 #include <asm/io.h>
73 #include <asm/div64.h>
74 #include <asm/irq.h>
75
76 /* local include */
77 #include "s2io.h"
78 #include "s2io-regs.h"
79
80 #define DRV_VERSION "2.0.15.2"
81
82 /* S2io Driver name & version. */
83 static char s2io_driver_name[] = "Neterion";
84 static char s2io_driver_version[] = DRV_VERSION;
85
86 static int rxd_size[4] = {32,48,48,64};
87 static int rxd_count[4] = {127,85,85,63};
88
89 static inline int RXD_IS_UP2DT(RxD_t *rxdp)
90 {
91         int ret;
92
93         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
94                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
95
96         return ret;
97 }
98
99 /*
100  * Cards with following subsystem_id have a link state indication
101  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
102  * macro below identifies these cards given the subsystem_id.
103  */
104 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
105         (dev_type == XFRAME_I_DEVICE) ?                 \
106                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
107                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
108
109 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
110                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
111 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
112 #define PANIC   1
113 #define LOW     2
114 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
115 {
116         mac_info_t *mac_control;
117
118         mac_control = &sp->mac_control;
119         if (rxb_size <= rxd_count[sp->rxd_mode])
120                 return PANIC;
121         else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
122                 return  LOW;
123         return 0;
124 }
125
126 /* Ethtool related variables and Macros. */
127 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
128         "Register test\t(offline)",
129         "Eeprom test\t(offline)",
130         "Link test\t(online)",
131         "RLDRAM test\t(offline)",
132         "BIST Test\t(offline)"
133 };
134
135 static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
136         {"tmac_frms"},
137         {"tmac_data_octets"},
138         {"tmac_drop_frms"},
139         {"tmac_mcst_frms"},
140         {"tmac_bcst_frms"},
141         {"tmac_pause_ctrl_frms"},
142         {"tmac_ttl_octets"},
143         {"tmac_ucst_frms"},
144         {"tmac_nucst_frms"},
145         {"tmac_any_err_frms"},
146         {"tmac_ttl_less_fb_octets"},
147         {"tmac_vld_ip_octets"},
148         {"tmac_vld_ip"},
149         {"tmac_drop_ip"},
150         {"tmac_icmp"},
151         {"tmac_rst_tcp"},
152         {"tmac_tcp"},
153         {"tmac_udp"},
154         {"rmac_vld_frms"},
155         {"rmac_data_octets"},
156         {"rmac_fcs_err_frms"},
157         {"rmac_drop_frms"},
158         {"rmac_vld_mcst_frms"},
159         {"rmac_vld_bcst_frms"},
160         {"rmac_in_rng_len_err_frms"},
161         {"rmac_out_rng_len_err_frms"},
162         {"rmac_long_frms"},
163         {"rmac_pause_ctrl_frms"},
164         {"rmac_unsup_ctrl_frms"},
165         {"rmac_ttl_octets"},
166         {"rmac_accepted_ucst_frms"},
167         {"rmac_accepted_nucst_frms"},
168         {"rmac_discarded_frms"},
169         {"rmac_drop_events"},
170         {"rmac_ttl_less_fb_octets"},
171         {"rmac_ttl_frms"},
172         {"rmac_usized_frms"},
173         {"rmac_osized_frms"},
174         {"rmac_frag_frms"},
175         {"rmac_jabber_frms"},
176         {"rmac_ttl_64_frms"},
177         {"rmac_ttl_65_127_frms"},
178         {"rmac_ttl_128_255_frms"},
179         {"rmac_ttl_256_511_frms"},
180         {"rmac_ttl_512_1023_frms"},
181         {"rmac_ttl_1024_1518_frms"},
182         {"rmac_ip"},
183         {"rmac_ip_octets"},
184         {"rmac_hdr_err_ip"},
185         {"rmac_drop_ip"},
186         {"rmac_icmp"},
187         {"rmac_tcp"},
188         {"rmac_udp"},
189         {"rmac_err_drp_udp"},
190         {"rmac_xgmii_err_sym"},
191         {"rmac_frms_q0"},
192         {"rmac_frms_q1"},
193         {"rmac_frms_q2"},
194         {"rmac_frms_q3"},
195         {"rmac_frms_q4"},
196         {"rmac_frms_q5"},
197         {"rmac_frms_q6"},
198         {"rmac_frms_q7"},
199         {"rmac_full_q0"},
200         {"rmac_full_q1"},
201         {"rmac_full_q2"},
202         {"rmac_full_q3"},
203         {"rmac_full_q4"},
204         {"rmac_full_q5"},
205         {"rmac_full_q6"},
206         {"rmac_full_q7"},
207         {"rmac_pause_cnt"},
208         {"rmac_xgmii_data_err_cnt"},
209         {"rmac_xgmii_ctrl_err_cnt"},
210         {"rmac_accepted_ip"},
211         {"rmac_err_tcp"},
212         {"rd_req_cnt"},
213         {"new_rd_req_cnt"},
214         {"new_rd_req_rtry_cnt"},
215         {"rd_rtry_cnt"},
216         {"wr_rtry_rd_ack_cnt"},
217         {"wr_req_cnt"},
218         {"new_wr_req_cnt"},
219         {"new_wr_req_rtry_cnt"},
220         {"wr_rtry_cnt"},
221         {"wr_disc_cnt"},
222         {"rd_rtry_wr_ack_cnt"},
223         {"txp_wr_cnt"},
224         {"txd_rd_cnt"},
225         {"txd_wr_cnt"},
226         {"rxd_rd_cnt"},
227         {"rxd_wr_cnt"},
228         {"txf_rd_cnt"},
229         {"rxf_wr_cnt"},
230         {"rmac_ttl_1519_4095_frms"},
231         {"rmac_ttl_4096_8191_frms"},
232         {"rmac_ttl_8192_max_frms"},
233         {"rmac_ttl_gt_max_frms"},
234         {"rmac_osized_alt_frms"},
235         {"rmac_jabber_alt_frms"},
236         {"rmac_gt_max_alt_frms"},
237         {"rmac_vlan_frms"},
238         {"rmac_len_discard"},
239         {"rmac_fcs_discard"},
240         {"rmac_pf_discard"},
241         {"rmac_da_discard"},
242         {"rmac_red_discard"},
243         {"rmac_rts_discard"},
244         {"rmac_ingm_full_discard"},
245         {"link_fault_cnt"},
246         {"\n DRIVER STATISTICS"},
247         {"single_bit_ecc_errs"},
248         {"double_bit_ecc_errs"},
249         {"parity_err_cnt"},
250         {"serious_err_cnt"},
251         {"soft_reset_cnt"},
252         {"fifo_full_cnt"},
253         {"ring_full_cnt"},
254         ("alarm_transceiver_temp_high"),
255         ("alarm_transceiver_temp_low"),
256         ("alarm_laser_bias_current_high"),
257         ("alarm_laser_bias_current_low"),
258         ("alarm_laser_output_power_high"),
259         ("alarm_laser_output_power_low"),
260         ("warn_transceiver_temp_high"),
261         ("warn_transceiver_temp_low"),
262         ("warn_laser_bias_current_high"),
263         ("warn_laser_bias_current_low"),
264         ("warn_laser_output_power_high"),
265         ("warn_laser_output_power_low"),
266         ("lro_aggregated_pkts"),
267         ("lro_flush_both_count"),
268         ("lro_out_of_sequence_pkts"),
269         ("lro_flush_due_to_max_pkts"),
270         ("lro_avg_aggr_pkts"),
271 };
272
273 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
274 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
275
276 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
277 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
278
279 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
280                         init_timer(&timer);                     \
281                         timer.function = handle;                \
282                         timer.data = (unsigned long) arg;       \
283                         mod_timer(&timer, (jiffies + exp))      \
284
285 /* Add the vlan */
286 static void s2io_vlan_rx_register(struct net_device *dev,
287                                         struct vlan_group *grp)
288 {
289         nic_t *nic = dev->priv;
290         unsigned long flags;
291
292         spin_lock_irqsave(&nic->tx_lock, flags);
293         nic->vlgrp = grp;
294         spin_unlock_irqrestore(&nic->tx_lock, flags);
295 }
296
297 /* Unregister the vlan */
298 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
299 {
300         nic_t *nic = dev->priv;
301         unsigned long flags;
302
303         spin_lock_irqsave(&nic->tx_lock, flags);
304         if (nic->vlgrp)
305                 nic->vlgrp->vlan_devices[vid] = NULL;
306         spin_unlock_irqrestore(&nic->tx_lock, flags);
307 }
308
309 /*
310  * Constants to be programmed into the Xena's registers, to configure
311  * the XAUI.
312  */
313
314 #define END_SIGN        0x0
315 static const u64 herc_act_dtx_cfg[] = {
316         /* Set address */
317         0x8000051536750000ULL, 0x80000515367500E0ULL,
318         /* Write data */
319         0x8000051536750004ULL, 0x80000515367500E4ULL,
320         /* Set address */
321         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
322         /* Write data */
323         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
324         /* Set address */
325         0x801205150D440000ULL, 0x801205150D4400E0ULL,
326         /* Write data */
327         0x801205150D440004ULL, 0x801205150D4400E4ULL,
328         /* Set address */
329         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
330         /* Write data */
331         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
332         /* Done */
333         END_SIGN
334 };
335
336 static const u64 xena_dtx_cfg[] = {
337         /* Set address */
338         0x8000051500000000ULL, 0x80000515000000E0ULL,
339         /* Write data */
340         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
341         /* Set address */
342         0x8001051500000000ULL, 0x80010515000000E0ULL,
343         /* Write data */
344         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
345         /* Set address */
346         0x8002051500000000ULL, 0x80020515000000E0ULL,
347         /* Write data */
348         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
349         END_SIGN
350 };
351
352 /*
353  * Constants for Fixing the MacAddress problem seen mostly on
354  * Alpha machines.
355  */
356 static const u64 fix_mac[] = {
357         0x0060000000000000ULL, 0x0060600000000000ULL,
358         0x0040600000000000ULL, 0x0000600000000000ULL,
359         0x0020600000000000ULL, 0x0060600000000000ULL,
360         0x0020600000000000ULL, 0x0060600000000000ULL,
361         0x0020600000000000ULL, 0x0060600000000000ULL,
362         0x0020600000000000ULL, 0x0060600000000000ULL,
363         0x0020600000000000ULL, 0x0060600000000000ULL,
364         0x0020600000000000ULL, 0x0060600000000000ULL,
365         0x0020600000000000ULL, 0x0060600000000000ULL,
366         0x0020600000000000ULL, 0x0060600000000000ULL,
367         0x0020600000000000ULL, 0x0060600000000000ULL,
368         0x0020600000000000ULL, 0x0060600000000000ULL,
369         0x0020600000000000ULL, 0x0000600000000000ULL,
370         0x0040600000000000ULL, 0x0060600000000000ULL,
371         END_SIGN
372 };
373
374 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
375 MODULE_LICENSE("GPL");
376 MODULE_VERSION(DRV_VERSION);
377
378
379 /* Module Loadable parameters. */
380 S2IO_PARM_INT(tx_fifo_num, 1);
381 S2IO_PARM_INT(rx_ring_num, 1);
382
383
384 S2IO_PARM_INT(rx_ring_mode, 1);
385 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
386 S2IO_PARM_INT(rmac_pause_time, 0x100);
387 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
388 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
389 S2IO_PARM_INT(shared_splits, 0);
390 S2IO_PARM_INT(tmac_util_period, 5);
391 S2IO_PARM_INT(rmac_util_period, 5);
392 S2IO_PARM_INT(bimodal, 0);
393 S2IO_PARM_INT(l3l4hdr_size, 128);
394 /* Frequency of Rx desc syncs expressed as power of 2 */
395 S2IO_PARM_INT(rxsync_frequency, 3);
396 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
397 S2IO_PARM_INT(intr_type, 0);
398 /* Large receive offload feature */
399 S2IO_PARM_INT(lro, 0);
400 /* Max pkts to be aggregated by LRO at one time. If not specified,
401  * aggregation happens until we hit max IP pkt size(64K)
402  */
403 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
404 S2IO_PARM_INT(indicate_max_pkts, 0);
405
406 S2IO_PARM_INT(napi, 1);
407 S2IO_PARM_INT(ufo, 0);
408
409 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
410     {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
411 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
412     {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
413 static unsigned int rts_frm_len[MAX_RX_RINGS] =
414     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
415
416 module_param_array(tx_fifo_len, uint, NULL, 0);
417 module_param_array(rx_ring_sz, uint, NULL, 0);
418 module_param_array(rts_frm_len, uint, NULL, 0);
419
420 /*
421  * S2IO device table.
422  * This table lists all the devices that this driver supports.
423  */
424 static struct pci_device_id s2io_tbl[] __devinitdata = {
425         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
426          PCI_ANY_ID, PCI_ANY_ID},
427         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
428          PCI_ANY_ID, PCI_ANY_ID},
429         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
430          PCI_ANY_ID, PCI_ANY_ID},
431         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
432          PCI_ANY_ID, PCI_ANY_ID},
433         {0,}
434 };
435
436 MODULE_DEVICE_TABLE(pci, s2io_tbl);
437
438 static struct pci_driver s2io_driver = {
439       .name = "S2IO",
440       .id_table = s2io_tbl,
441       .probe = s2io_init_nic,
442       .remove = __devexit_p(s2io_rem_nic),
443 };
444
445 /* A simplifier macro used both by init and free shared_mem Fns(). */
446 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
447
448 /**
449  * init_shared_mem - Allocation and Initialization of Memory
450  * @nic: Device private variable.
451  * Description: The function allocates all the memory areas shared
452  * between the NIC and the driver. This includes Tx descriptors,
453  * Rx descriptors and the statistics block.
454  */
455
456 static int init_shared_mem(struct s2io_nic *nic)
457 {
458         u32 size;
459         void *tmp_v_addr, *tmp_v_addr_next;
460         dma_addr_t tmp_p_addr, tmp_p_addr_next;
461         RxD_block_t *pre_rxd_blk = NULL;
462         int i, j, blk_cnt;
463         int lst_size, lst_per_page;
464         struct net_device *dev = nic->dev;
465         unsigned long tmp;
466         buffAdd_t *ba;
467
468         mac_info_t *mac_control;
469         struct config_param *config;
470
471         mac_control = &nic->mac_control;
472         config = &nic->config;
473
474
475         /* Allocation and initialization of TXDLs in FIOFs */
476         size = 0;
477         for (i = 0; i < config->tx_fifo_num; i++) {
478                 size += config->tx_cfg[i].fifo_len;
479         }
480         if (size > MAX_AVAILABLE_TXDS) {
481                 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
482                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
483                 return -EINVAL;
484         }
485
486         lst_size = (sizeof(TxD_t) * config->max_txds);
487         lst_per_page = PAGE_SIZE / lst_size;
488
489         for (i = 0; i < config->tx_fifo_num; i++) {
490                 int fifo_len = config->tx_cfg[i].fifo_len;
491                 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
492                 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
493                                                           GFP_KERNEL);
494                 if (!mac_control->fifos[i].list_info) {
495                         DBG_PRINT(ERR_DBG,
496                                   "Malloc failed for list_info\n");
497                         return -ENOMEM;
498                 }
499                 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
500         }
501         for (i = 0; i < config->tx_fifo_num; i++) {
502                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
503                                                 lst_per_page);
504                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
505                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
506                     config->tx_cfg[i].fifo_len - 1;
507                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
508                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
509                     config->tx_cfg[i].fifo_len - 1;
510                 mac_control->fifos[i].fifo_no = i;
511                 mac_control->fifos[i].nic = nic;
512                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
513
514                 for (j = 0; j < page_num; j++) {
515                         int k = 0;
516                         dma_addr_t tmp_p;
517                         void *tmp_v;
518                         tmp_v = pci_alloc_consistent(nic->pdev,
519                                                      PAGE_SIZE, &tmp_p);
520                         if (!tmp_v) {
521                                 DBG_PRINT(ERR_DBG,
522                                           "pci_alloc_consistent ");
523                                 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
524                                 return -ENOMEM;
525                         }
526                         /* If we got a zero DMA address(can happen on
527                          * certain platforms like PPC), reallocate.
528                          * Store virtual address of page we don't want,
529                          * to be freed later.
530                          */
531                         if (!tmp_p) {
532                                 mac_control->zerodma_virt_addr = tmp_v;
533                                 DBG_PRINT(INIT_DBG,
534                                 "%s: Zero DMA address for TxDL. ", dev->name);
535                                 DBG_PRINT(INIT_DBG,
536                                 "Virtual address %p\n", tmp_v);
537                                 tmp_v = pci_alloc_consistent(nic->pdev,
538                                                      PAGE_SIZE, &tmp_p);
539                                 if (!tmp_v) {
540                                         DBG_PRINT(ERR_DBG,
541                                           "pci_alloc_consistent ");
542                                         DBG_PRINT(ERR_DBG, "failed for TxDL\n");
543                                         return -ENOMEM;
544                                 }
545                         }
546                         while (k < lst_per_page) {
547                                 int l = (j * lst_per_page) + k;
548                                 if (l == config->tx_cfg[i].fifo_len)
549                                         break;
550                                 mac_control->fifos[i].list_info[l].list_virt_addr =
551                                     tmp_v + (k * lst_size);
552                                 mac_control->fifos[i].list_info[l].list_phy_addr =
553                                     tmp_p + (k * lst_size);
554                                 k++;
555                         }
556                 }
557         }
558
559         nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
560         if (!nic->ufo_in_band_v)
561                 return -ENOMEM;
562
563         /* Allocation and initialization of RXDs in Rings */
564         size = 0;
565         for (i = 0; i < config->rx_ring_num; i++) {
566                 if (config->rx_cfg[i].num_rxd %
567                     (rxd_count[nic->rxd_mode] + 1)) {
568                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
569                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
570                                   i);
571                         DBG_PRINT(ERR_DBG, "RxDs per Block");
572                         return FAILURE;
573                 }
574                 size += config->rx_cfg[i].num_rxd;
575                 mac_control->rings[i].block_count =
576                         config->rx_cfg[i].num_rxd /
577                         (rxd_count[nic->rxd_mode] + 1 );
578                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
579                         mac_control->rings[i].block_count;
580         }
581         if (nic->rxd_mode == RXD_MODE_1)
582                 size = (size * (sizeof(RxD1_t)));
583         else
584                 size = (size * (sizeof(RxD3_t)));
585
586         for (i = 0; i < config->rx_ring_num; i++) {
587                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
588                 mac_control->rings[i].rx_curr_get_info.offset = 0;
589                 mac_control->rings[i].rx_curr_get_info.ring_len =
590                     config->rx_cfg[i].num_rxd - 1;
591                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
592                 mac_control->rings[i].rx_curr_put_info.offset = 0;
593                 mac_control->rings[i].rx_curr_put_info.ring_len =
594                     config->rx_cfg[i].num_rxd - 1;
595                 mac_control->rings[i].nic = nic;
596                 mac_control->rings[i].ring_no = i;
597
598                 blk_cnt = config->rx_cfg[i].num_rxd /
599                                 (rxd_count[nic->rxd_mode] + 1);
600                 /*  Allocating all the Rx blocks */
601                 for (j = 0; j < blk_cnt; j++) {
602                         rx_block_info_t *rx_blocks;
603                         int l;
604
605                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
606                         size = SIZE_OF_BLOCK; //size is always page size
607                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
608                                                           &tmp_p_addr);
609                         if (tmp_v_addr == NULL) {
610                                 /*
611                                  * In case of failure, free_shared_mem()
612                                  * is called, which should free any
613                                  * memory that was alloced till the
614                                  * failure happened.
615                                  */
616                                 rx_blocks->block_virt_addr = tmp_v_addr;
617                                 return -ENOMEM;
618                         }
619                         memset(tmp_v_addr, 0, size);
620                         rx_blocks->block_virt_addr = tmp_v_addr;
621                         rx_blocks->block_dma_addr = tmp_p_addr;
622                         rx_blocks->rxds = kmalloc(sizeof(rxd_info_t)*
623                                                   rxd_count[nic->rxd_mode],
624                                                   GFP_KERNEL);
625                         if (!rx_blocks->rxds)
626                                 return -ENOMEM;
627                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
628                                 rx_blocks->rxds[l].virt_addr =
629                                         rx_blocks->block_virt_addr +
630                                         (rxd_size[nic->rxd_mode] * l);
631                                 rx_blocks->rxds[l].dma_addr =
632                                         rx_blocks->block_dma_addr +
633                                         (rxd_size[nic->rxd_mode] * l);
634                         }
635                 }
636                 /* Interlinking all Rx Blocks */
637                 for (j = 0; j < blk_cnt; j++) {
638                         tmp_v_addr =
639                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
640                         tmp_v_addr_next =
641                                 mac_control->rings[i].rx_blocks[(j + 1) %
642                                               blk_cnt].block_virt_addr;
643                         tmp_p_addr =
644                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
645                         tmp_p_addr_next =
646                                 mac_control->rings[i].rx_blocks[(j + 1) %
647                                               blk_cnt].block_dma_addr;
648
649                         pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
650                         pre_rxd_blk->reserved_2_pNext_RxD_block =
651                             (unsigned long) tmp_v_addr_next;
652                         pre_rxd_blk->pNext_RxD_Blk_physical =
653                             (u64) tmp_p_addr_next;
654                 }
655         }
656         if (nic->rxd_mode >= RXD_MODE_3A) {
657                 /*
658                  * Allocation of Storages for buffer addresses in 2BUFF mode
659                  * and the buffers as well.
660                  */
661                 for (i = 0; i < config->rx_ring_num; i++) {
662                         blk_cnt = config->rx_cfg[i].num_rxd /
663                            (rxd_count[nic->rxd_mode]+ 1);
664                         mac_control->rings[i].ba =
665                                 kmalloc((sizeof(buffAdd_t *) * blk_cnt),
666                                      GFP_KERNEL);
667                         if (!mac_control->rings[i].ba)
668                                 return -ENOMEM;
669                         for (j = 0; j < blk_cnt; j++) {
670                                 int k = 0;
671                                 mac_control->rings[i].ba[j] =
672                                         kmalloc((sizeof(buffAdd_t) *
673                                                 (rxd_count[nic->rxd_mode] + 1)),
674                                                 GFP_KERNEL);
675                                 if (!mac_control->rings[i].ba[j])
676                                         return -ENOMEM;
677                                 while (k != rxd_count[nic->rxd_mode]) {
678                                         ba = &mac_control->rings[i].ba[j][k];
679
680                                         ba->ba_0_org = (void *) kmalloc
681                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
682                                         if (!ba->ba_0_org)
683                                                 return -ENOMEM;
684                                         tmp = (unsigned long)ba->ba_0_org;
685                                         tmp += ALIGN_SIZE;
686                                         tmp &= ~((unsigned long) ALIGN_SIZE);
687                                         ba->ba_0 = (void *) tmp;
688
689                                         ba->ba_1_org = (void *) kmalloc
690                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
691                                         if (!ba->ba_1_org)
692                                                 return -ENOMEM;
693                                         tmp = (unsigned long) ba->ba_1_org;
694                                         tmp += ALIGN_SIZE;
695                                         tmp &= ~((unsigned long) ALIGN_SIZE);
696                                         ba->ba_1 = (void *) tmp;
697                                         k++;
698                                 }
699                         }
700                 }
701         }
702
703         /* Allocation and initialization of Statistics block */
704         size = sizeof(StatInfo_t);
705         mac_control->stats_mem = pci_alloc_consistent
706             (nic->pdev, size, &mac_control->stats_mem_phy);
707
708         if (!mac_control->stats_mem) {
709                 /*
710                  * In case of failure, free_shared_mem() is called, which
711                  * should free any memory that was alloced till the
712                  * failure happened.
713                  */
714                 return -ENOMEM;
715         }
716         mac_control->stats_mem_sz = size;
717
718         tmp_v_addr = mac_control->stats_mem;
719         mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
720         memset(tmp_v_addr, 0, size);
721         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
722                   (unsigned long long) tmp_p_addr);
723
724         return SUCCESS;
725 }
726
727 /**
728  * free_shared_mem - Free the allocated Memory
729  * @nic:  Device private variable.
730  * Description: This function is to free all memory locations allocated by
731  * the init_shared_mem() function and return it to the kernel.
732  */
733
734 static void free_shared_mem(struct s2io_nic *nic)
735 {
736         int i, j, blk_cnt, size;
737         void *tmp_v_addr;
738         dma_addr_t tmp_p_addr;
739         mac_info_t *mac_control;
740         struct config_param *config;
741         int lst_size, lst_per_page;
742         struct net_device *dev = nic->dev;
743
744         if (!nic)
745                 return;
746
747         mac_control = &nic->mac_control;
748         config = &nic->config;
749
750         lst_size = (sizeof(TxD_t) * config->max_txds);
751         lst_per_page = PAGE_SIZE / lst_size;
752
753         for (i = 0; i < config->tx_fifo_num; i++) {
754                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
755                                                 lst_per_page);
756                 for (j = 0; j < page_num; j++) {
757                         int mem_blks = (j * lst_per_page);
758                         if (!mac_control->fifos[i].list_info)
759                                 return;
760                         if (!mac_control->fifos[i].list_info[mem_blks].
761                                  list_virt_addr)
762                                 break;
763                         pci_free_consistent(nic->pdev, PAGE_SIZE,
764                                             mac_control->fifos[i].
765                                             list_info[mem_blks].
766                                             list_virt_addr,
767                                             mac_control->fifos[i].
768                                             list_info[mem_blks].
769                                             list_phy_addr);
770                 }
771                 /* If we got a zero DMA address during allocation,
772                  * free the page now
773                  */
774                 if (mac_control->zerodma_virt_addr) {
775                         pci_free_consistent(nic->pdev, PAGE_SIZE,
776                                             mac_control->zerodma_virt_addr,
777                                             (dma_addr_t)0);
778                         DBG_PRINT(INIT_DBG,
779                                 "%s: Freeing TxDL with zero DMA addr. ",
780                                 dev->name);
781                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
782                                 mac_control->zerodma_virt_addr);
783                 }
784                 kfree(mac_control->fifos[i].list_info);
785         }
786
787         size = SIZE_OF_BLOCK;
788         for (i = 0; i < config->rx_ring_num; i++) {
789                 blk_cnt = mac_control->rings[i].block_count;
790                 for (j = 0; j < blk_cnt; j++) {
791                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
792                                 block_virt_addr;
793                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
794                                 block_dma_addr;
795                         if (tmp_v_addr == NULL)
796                                 break;
797                         pci_free_consistent(nic->pdev, size,
798                                             tmp_v_addr, tmp_p_addr);
799                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
800                 }
801         }
802
803         if (nic->rxd_mode >= RXD_MODE_3A) {
804                 /* Freeing buffer storage addresses in 2BUFF mode. */
805                 for (i = 0; i < config->rx_ring_num; i++) {
806                         blk_cnt = config->rx_cfg[i].num_rxd /
807                             (rxd_count[nic->rxd_mode] + 1);
808                         for (j = 0; j < blk_cnt; j++) {
809                                 int k = 0;
810                                 if (!mac_control->rings[i].ba[j])
811                                         continue;
812                                 while (k != rxd_count[nic->rxd_mode]) {
813                                         buffAdd_t *ba =
814                                                 &mac_control->rings[i].ba[j][k];
815                                         kfree(ba->ba_0_org);
816                                         kfree(ba->ba_1_org);
817                                         k++;
818                                 }
819                                 kfree(mac_control->rings[i].ba[j]);
820                         }
821                         kfree(mac_control->rings[i].ba);
822                 }
823         }
824
825         if (mac_control->stats_mem) {
826                 pci_free_consistent(nic->pdev,
827                                     mac_control->stats_mem_sz,
828                                     mac_control->stats_mem,
829                                     mac_control->stats_mem_phy);
830         }
831         if (nic->ufo_in_band_v)
832                 kfree(nic->ufo_in_band_v);
833 }
834
835 /**
836  * s2io_verify_pci_mode -
837  */
838
839 static int s2io_verify_pci_mode(nic_t *nic)
840 {
841         XENA_dev_config_t __iomem *bar0 = nic->bar0;
842         register u64 val64 = 0;
843         int     mode;
844
845         val64 = readq(&bar0->pci_mode);
846         mode = (u8)GET_PCI_MODE(val64);
847
848         if ( val64 & PCI_MODE_UNKNOWN_MODE)
849                 return -1;      /* Unknown PCI mode */
850         return mode;
851 }
852
853 #define NEC_VENID   0x1033
854 #define NEC_DEVID   0x0125
855 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
856 {
857         struct pci_dev *tdev = NULL;
858         while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
859                 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
860                         if (tdev->bus == s2io_pdev->bus->parent)
861                                 pci_dev_put(tdev);
862                                 return 1;
863                 }
864         }
865         return 0;
866 }
867
868 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
869 /**
870  * s2io_print_pci_mode -
871  */
872 static int s2io_print_pci_mode(nic_t *nic)
873 {
874         XENA_dev_config_t __iomem *bar0 = nic->bar0;
875         register u64 val64 = 0;
876         int     mode;
877         struct config_param *config = &nic->config;
878
879         val64 = readq(&bar0->pci_mode);
880         mode = (u8)GET_PCI_MODE(val64);
881
882         if ( val64 & PCI_MODE_UNKNOWN_MODE)
883                 return -1;      /* Unknown PCI mode */
884
885         config->bus_speed = bus_speed[mode];
886
887         if (s2io_on_nec_bridge(nic->pdev)) {
888                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
889                                                         nic->dev->name);
890                 return mode;
891         }
892
893         if (val64 & PCI_MODE_32_BITS) {
894                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
895         } else {
896                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
897         }
898
899         switch(mode) {
900                 case PCI_MODE_PCI_33:
901                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
902                         break;
903                 case PCI_MODE_PCI_66:
904                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
905                         break;
906                 case PCI_MODE_PCIX_M1_66:
907                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
908                         break;
909                 case PCI_MODE_PCIX_M1_100:
910                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
911                         break;
912                 case PCI_MODE_PCIX_M1_133:
913                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
914                         break;
915                 case PCI_MODE_PCIX_M2_66:
916                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
917                         break;
918                 case PCI_MODE_PCIX_M2_100:
919                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
920                         break;
921                 case PCI_MODE_PCIX_M2_133:
922                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
923                         break;
924                 default:
925                         return -1;      /* Unsupported bus speed */
926         }
927
928         return mode;
929 }
930
931 /**
932  *  init_nic - Initialization of hardware
933  *  @nic: device peivate variable
934  *  Description: The function sequentially configures every block
935  *  of the H/W from their reset values.
936  *  Return Value:  SUCCESS on success and
937  *  '-1' on failure (endian settings incorrect).
938  */
939
940 static int init_nic(struct s2io_nic *nic)
941 {
942         XENA_dev_config_t __iomem *bar0 = nic->bar0;
943         struct net_device *dev = nic->dev;
944         register u64 val64 = 0;
945         void __iomem *add;
946         u32 time;
947         int i, j;
948         mac_info_t *mac_control;
949         struct config_param *config;
950         int dtx_cnt = 0;
951         unsigned long long mem_share;
952         int mem_size;
953
954         mac_control = &nic->mac_control;
955         config = &nic->config;
956
957         /* to set the swapper controle on the card */
958         if(s2io_set_swapper(nic)) {
959                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
960                 return -1;
961         }
962
963         /*
964          * Herc requires EOI to be removed from reset before XGXS, so..
965          */
966         if (nic->device_type & XFRAME_II_DEVICE) {
967                 val64 = 0xA500000000ULL;
968                 writeq(val64, &bar0->sw_reset);
969                 msleep(500);
970                 val64 = readq(&bar0->sw_reset);
971         }
972
973         /* Remove XGXS from reset state */
974         val64 = 0;
975         writeq(val64, &bar0->sw_reset);
976         msleep(500);
977         val64 = readq(&bar0->sw_reset);
978
979         /*  Enable Receiving broadcasts */
980         add = &bar0->mac_cfg;
981         val64 = readq(&bar0->mac_cfg);
982         val64 |= MAC_RMAC_BCAST_ENABLE;
983         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
984         writel((u32) val64, add);
985         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
986         writel((u32) (val64 >> 32), (add + 4));
987
988         /* Read registers in all blocks */
989         val64 = readq(&bar0->mac_int_mask);
990         val64 = readq(&bar0->mc_int_mask);
991         val64 = readq(&bar0->xgxs_int_mask);
992
993         /*  Set MTU */
994         val64 = dev->mtu;
995         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
996
997         if (nic->device_type & XFRAME_II_DEVICE) {
998                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
999                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1000                                           &bar0->dtx_control, UF);
1001                         if (dtx_cnt & 0x1)
1002                                 msleep(1); /* Necessary!! */
1003                         dtx_cnt++;
1004                 }
1005         } else {
1006                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1007                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1008                                           &bar0->dtx_control, UF);
1009                         val64 = readq(&bar0->dtx_control);
1010                         dtx_cnt++;
1011                 }
1012         }
1013
1014         /*  Tx DMA Initialization */
1015         val64 = 0;
1016         writeq(val64, &bar0->tx_fifo_partition_0);
1017         writeq(val64, &bar0->tx_fifo_partition_1);
1018         writeq(val64, &bar0->tx_fifo_partition_2);
1019         writeq(val64, &bar0->tx_fifo_partition_3);
1020
1021
1022         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1023                 val64 |=
1024                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1025                          13) | vBIT(config->tx_cfg[i].fifo_priority,
1026                                     ((i * 32) + 5), 3);
1027
1028                 if (i == (config->tx_fifo_num - 1)) {
1029                         if (i % 2 == 0)
1030                                 i++;
1031                 }
1032
1033                 switch (i) {
1034                 case 1:
1035                         writeq(val64, &bar0->tx_fifo_partition_0);
1036                         val64 = 0;
1037                         break;
1038                 case 3:
1039                         writeq(val64, &bar0->tx_fifo_partition_1);
1040                         val64 = 0;
1041                         break;
1042                 case 5:
1043                         writeq(val64, &bar0->tx_fifo_partition_2);
1044                         val64 = 0;
1045                         break;
1046                 case 7:
1047                         writeq(val64, &bar0->tx_fifo_partition_3);
1048                         break;
1049                 }
1050         }
1051
1052         /*
1053          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1054          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1055          */
1056         if ((nic->device_type == XFRAME_I_DEVICE) &&
1057                 (get_xena_rev_id(nic->pdev) < 4))
1058                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1059
1060         val64 = readq(&bar0->tx_fifo_partition_0);
1061         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1062                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1063
1064         /*
1065          * Initialization of Tx_PA_CONFIG register to ignore packet
1066          * integrity checking.
1067          */
1068         val64 = readq(&bar0->tx_pa_cfg);
1069         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1070             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1071         writeq(val64, &bar0->tx_pa_cfg);
1072
1073         /* Rx DMA intialization. */
1074         val64 = 0;
1075         for (i = 0; i < config->rx_ring_num; i++) {
1076                 val64 |=
1077                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1078                          3);
1079         }
1080         writeq(val64, &bar0->rx_queue_priority);
1081
1082         /*
1083          * Allocating equal share of memory to all the
1084          * configured Rings.
1085          */
1086         val64 = 0;
1087         if (nic->device_type & XFRAME_II_DEVICE)
1088                 mem_size = 32;
1089         else
1090                 mem_size = 64;
1091
1092         for (i = 0; i < config->rx_ring_num; i++) {
1093                 switch (i) {
1094                 case 0:
1095                         mem_share = (mem_size / config->rx_ring_num +
1096                                      mem_size % config->rx_ring_num);
1097                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1098                         continue;
1099                 case 1:
1100                         mem_share = (mem_size / config->rx_ring_num);
1101                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1102                         continue;
1103                 case 2:
1104                         mem_share = (mem_size / config->rx_ring_num);
1105                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1106                         continue;
1107                 case 3:
1108                         mem_share = (mem_size / config->rx_ring_num);
1109                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1110                         continue;
1111                 case 4:
1112                         mem_share = (mem_size / config->rx_ring_num);
1113                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1114                         continue;
1115                 case 5:
1116                         mem_share = (mem_size / config->rx_ring_num);
1117                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1118                         continue;
1119                 case 6:
1120                         mem_share = (mem_size / config->rx_ring_num);
1121                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1122                         continue;
1123                 case 7:
1124                         mem_share = (mem_size / config->rx_ring_num);
1125                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1126                         continue;
1127                 }
1128         }
1129         writeq(val64, &bar0->rx_queue_cfg);
1130
1131         /*
1132          * Filling Tx round robin registers
1133          * as per the number of FIFOs
1134          */
1135         switch (config->tx_fifo_num) {
1136         case 1:
1137                 val64 = 0x0000000000000000ULL;
1138                 writeq(val64, &bar0->tx_w_round_robin_0);
1139                 writeq(val64, &bar0->tx_w_round_robin_1);
1140                 writeq(val64, &bar0->tx_w_round_robin_2);
1141                 writeq(val64, &bar0->tx_w_round_robin_3);
1142                 writeq(val64, &bar0->tx_w_round_robin_4);
1143                 break;
1144         case 2:
1145                 val64 = 0x0000010000010000ULL;
1146                 writeq(val64, &bar0->tx_w_round_robin_0);
1147                 val64 = 0x0100000100000100ULL;
1148                 writeq(val64, &bar0->tx_w_round_robin_1);
1149                 val64 = 0x0001000001000001ULL;
1150                 writeq(val64, &bar0->tx_w_round_robin_2);
1151                 val64 = 0x0000010000010000ULL;
1152                 writeq(val64, &bar0->tx_w_round_robin_3);
1153                 val64 = 0x0100000000000000ULL;
1154                 writeq(val64, &bar0->tx_w_round_robin_4);
1155                 break;
1156         case 3:
1157                 val64 = 0x0001000102000001ULL;
1158                 writeq(val64, &bar0->tx_w_round_robin_0);
1159                 val64 = 0x0001020000010001ULL;
1160                 writeq(val64, &bar0->tx_w_round_robin_1);
1161                 val64 = 0x0200000100010200ULL;
1162                 writeq(val64, &bar0->tx_w_round_robin_2);
1163                 val64 = 0x0001000102000001ULL;
1164                 writeq(val64, &bar0->tx_w_round_robin_3);
1165                 val64 = 0x0001020000000000ULL;
1166                 writeq(val64, &bar0->tx_w_round_robin_4);
1167                 break;
1168         case 4:
1169                 val64 = 0x0001020300010200ULL;
1170                 writeq(val64, &bar0->tx_w_round_robin_0);
1171                 val64 = 0x0100000102030001ULL;
1172                 writeq(val64, &bar0->tx_w_round_robin_1);
1173                 val64 = 0x0200010000010203ULL;
1174                 writeq(val64, &bar0->tx_w_round_robin_2);
1175                 val64 = 0x0001020001000001ULL;
1176                 writeq(val64, &bar0->tx_w_round_robin_3);
1177                 val64 = 0x0203000100000000ULL;
1178                 writeq(val64, &bar0->tx_w_round_robin_4);
1179                 break;
1180         case 5:
1181                 val64 = 0x0001000203000102ULL;
1182                 writeq(val64, &bar0->tx_w_round_robin_0);
1183                 val64 = 0x0001020001030004ULL;
1184                 writeq(val64, &bar0->tx_w_round_robin_1);
1185                 val64 = 0x0001000203000102ULL;
1186                 writeq(val64, &bar0->tx_w_round_robin_2);
1187                 val64 = 0x0001020001030004ULL;
1188                 writeq(val64, &bar0->tx_w_round_robin_3);
1189                 val64 = 0x0001000000000000ULL;
1190                 writeq(val64, &bar0->tx_w_round_robin_4);
1191                 break;
1192         case 6:
1193                 val64 = 0x0001020304000102ULL;
1194                 writeq(val64, &bar0->tx_w_round_robin_0);
1195                 val64 = 0x0304050001020001ULL;
1196                 writeq(val64, &bar0->tx_w_round_robin_1);
1197                 val64 = 0x0203000100000102ULL;
1198                 writeq(val64, &bar0->tx_w_round_robin_2);
1199                 val64 = 0x0304000102030405ULL;
1200                 writeq(val64, &bar0->tx_w_round_robin_3);
1201                 val64 = 0x0001000200000000ULL;
1202                 writeq(val64, &bar0->tx_w_round_robin_4);
1203                 break;
1204         case 7:
1205                 val64 = 0x0001020001020300ULL;
1206                 writeq(val64, &bar0->tx_w_round_robin_0);
1207                 val64 = 0x0102030400010203ULL;
1208                 writeq(val64, &bar0->tx_w_round_robin_1);
1209                 val64 = 0x0405060001020001ULL;
1210                 writeq(val64, &bar0->tx_w_round_robin_2);
1211                 val64 = 0x0304050000010200ULL;
1212                 writeq(val64, &bar0->tx_w_round_robin_3);
1213                 val64 = 0x0102030000000000ULL;
1214                 writeq(val64, &bar0->tx_w_round_robin_4);
1215                 break;
1216         case 8:
1217                 val64 = 0x0001020300040105ULL;
1218                 writeq(val64, &bar0->tx_w_round_robin_0);
1219                 val64 = 0x0200030106000204ULL;
1220                 writeq(val64, &bar0->tx_w_round_robin_1);
1221                 val64 = 0x0103000502010007ULL;
1222                 writeq(val64, &bar0->tx_w_round_robin_2);
1223                 val64 = 0x0304010002060500ULL;
1224                 writeq(val64, &bar0->tx_w_round_robin_3);
1225                 val64 = 0x0103020400000000ULL;
1226                 writeq(val64, &bar0->tx_w_round_robin_4);
1227                 break;
1228         }
1229
1230         /* Enable all configured Tx FIFO partitions */
1231         val64 = readq(&bar0->tx_fifo_partition_0);
1232         val64 |= (TX_FIFO_PARTITION_EN);
1233         writeq(val64, &bar0->tx_fifo_partition_0);
1234
1235         /* Filling the Rx round robin registers as per the
1236          * number of Rings and steering based on QoS.
1237          */
1238         switch (config->rx_ring_num) {
1239         case 1:
1240                 val64 = 0x8080808080808080ULL;
1241                 writeq(val64, &bar0->rts_qos_steering);
1242                 break;
1243         case 2:
1244                 val64 = 0x0000010000010000ULL;
1245                 writeq(val64, &bar0->rx_w_round_robin_0);
1246                 val64 = 0x0100000100000100ULL;
1247                 writeq(val64, &bar0->rx_w_round_robin_1);
1248                 val64 = 0x0001000001000001ULL;
1249                 writeq(val64, &bar0->rx_w_round_robin_2);
1250                 val64 = 0x0000010000010000ULL;
1251                 writeq(val64, &bar0->rx_w_round_robin_3);
1252                 val64 = 0x0100000000000000ULL;
1253                 writeq(val64, &bar0->rx_w_round_robin_4);
1254
1255                 val64 = 0x8080808040404040ULL;
1256                 writeq(val64, &bar0->rts_qos_steering);
1257                 break;
1258         case 3:
1259                 val64 = 0x0001000102000001ULL;
1260                 writeq(val64, &bar0->rx_w_round_robin_0);
1261                 val64 = 0x0001020000010001ULL;
1262                 writeq(val64, &bar0->rx_w_round_robin_1);
1263                 val64 = 0x0200000100010200ULL;
1264                 writeq(val64, &bar0->rx_w_round_robin_2);
1265                 val64 = 0x0001000102000001ULL;
1266                 writeq(val64, &bar0->rx_w_round_robin_3);
1267                 val64 = 0x0001020000000000ULL;
1268                 writeq(val64, &bar0->rx_w_round_robin_4);
1269
1270                 val64 = 0x8080804040402020ULL;
1271                 writeq(val64, &bar0->rts_qos_steering);
1272                 break;
1273         case 4:
1274                 val64 = 0x0001020300010200ULL;
1275                 writeq(val64, &bar0->rx_w_round_robin_0);
1276                 val64 = 0x0100000102030001ULL;
1277                 writeq(val64, &bar0->rx_w_round_robin_1);
1278                 val64 = 0x0200010000010203ULL;
1279                 writeq(val64, &bar0->rx_w_round_robin_2);
1280                 val64 = 0x0001020001000001ULL;
1281                 writeq(val64, &bar0->rx_w_round_robin_3);
1282                 val64 = 0x0203000100000000ULL;
1283                 writeq(val64, &bar0->rx_w_round_robin_4);
1284
1285                 val64 = 0x8080404020201010ULL;
1286                 writeq(val64, &bar0->rts_qos_steering);
1287                 break;
1288         case 5:
1289                 val64 = 0x0001000203000102ULL;
1290                 writeq(val64, &bar0->rx_w_round_robin_0);
1291                 val64 = 0x0001020001030004ULL;
1292                 writeq(val64, &bar0->rx_w_round_robin_1);
1293                 val64 = 0x0001000203000102ULL;
1294                 writeq(val64, &bar0->rx_w_round_robin_2);
1295                 val64 = 0x0001020001030004ULL;
1296                 writeq(val64, &bar0->rx_w_round_robin_3);
1297                 val64 = 0x0001000000000000ULL;
1298                 writeq(val64, &bar0->rx_w_round_robin_4);
1299
1300                 val64 = 0x8080404020201008ULL;
1301                 writeq(val64, &bar0->rts_qos_steering);
1302                 break;
1303         case 6:
1304                 val64 = 0x0001020304000102ULL;
1305                 writeq(val64, &bar0->rx_w_round_robin_0);
1306                 val64 = 0x0304050001020001ULL;
1307                 writeq(val64, &bar0->rx_w_round_robin_1);
1308                 val64 = 0x0203000100000102ULL;
1309                 writeq(val64, &bar0->rx_w_round_robin_2);
1310                 val64 = 0x0304000102030405ULL;
1311                 writeq(val64, &bar0->rx_w_round_robin_3);
1312                 val64 = 0x0001000200000000ULL;
1313                 writeq(val64, &bar0->rx_w_round_robin_4);
1314
1315                 val64 = 0x8080404020100804ULL;
1316                 writeq(val64, &bar0->rts_qos_steering);
1317                 break;
1318         case 7:
1319                 val64 = 0x0001020001020300ULL;
1320                 writeq(val64, &bar0->rx_w_round_robin_0);
1321                 val64 = 0x0102030400010203ULL;
1322                 writeq(val64, &bar0->rx_w_round_robin_1);
1323                 val64 = 0x0405060001020001ULL;
1324                 writeq(val64, &bar0->rx_w_round_robin_2);
1325                 val64 = 0x0304050000010200ULL;
1326                 writeq(val64, &bar0->rx_w_round_robin_3);
1327                 val64 = 0x0102030000000000ULL;
1328                 writeq(val64, &bar0->rx_w_round_robin_4);
1329
1330                 val64 = 0x8080402010080402ULL;
1331                 writeq(val64, &bar0->rts_qos_steering);
1332                 break;
1333         case 8:
1334                 val64 = 0x0001020300040105ULL;
1335                 writeq(val64, &bar0->rx_w_round_robin_0);
1336                 val64 = 0x0200030106000204ULL;
1337                 writeq(val64, &bar0->rx_w_round_robin_1);
1338                 val64 = 0x0103000502010007ULL;
1339                 writeq(val64, &bar0->rx_w_round_robin_2);
1340                 val64 = 0x0304010002060500ULL;
1341                 writeq(val64, &bar0->rx_w_round_robin_3);
1342                 val64 = 0x0103020400000000ULL;
1343                 writeq(val64, &bar0->rx_w_round_robin_4);
1344
1345                 val64 = 0x8040201008040201ULL;
1346                 writeq(val64, &bar0->rts_qos_steering);
1347                 break;
1348         }
1349
1350         /* UDP Fix */
1351         val64 = 0;
1352         for (i = 0; i < 8; i++)
1353                 writeq(val64, &bar0->rts_frm_len_n[i]);
1354
1355         /* Set the default rts frame length for the rings configured */
1356         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1357         for (i = 0 ; i < config->rx_ring_num ; i++)
1358                 writeq(val64, &bar0->rts_frm_len_n[i]);
1359
1360         /* Set the frame length for the configured rings
1361          * desired by the user
1362          */
1363         for (i = 0; i < config->rx_ring_num; i++) {
1364                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1365                  * specified frame length steering.
1366                  * If the user provides the frame length then program
1367                  * the rts_frm_len register for those values or else
1368                  * leave it as it is.
1369                  */
1370                 if (rts_frm_len[i] != 0) {
1371                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1372                                 &bar0->rts_frm_len_n[i]);
1373                 }
1374         }
1375
1376         /* Program statistics memory */
1377         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1378
1379         if (nic->device_type == XFRAME_II_DEVICE) {
1380                 val64 = STAT_BC(0x320);
1381                 writeq(val64, &bar0->stat_byte_cnt);
1382         }
1383
1384         /*
1385          * Initializing the sampling rate for the device to calculate the
1386          * bandwidth utilization.
1387          */
1388         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1389             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1390         writeq(val64, &bar0->mac_link_util);
1391
1392
1393         /*
1394          * Initializing the Transmit and Receive Traffic Interrupt
1395          * Scheme.
1396          */
1397         /*
1398          * TTI Initialization. Default Tx timer gets us about
1399          * 250 interrupts per sec. Continuous interrupts are enabled
1400          * by default.
1401          */
1402         if (nic->device_type == XFRAME_II_DEVICE) {
1403                 int count = (nic->config.bus_speed * 125)/2;
1404                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1405         } else {
1406
1407                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1408         }
1409         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1410             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1411             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1412                 if (use_continuous_tx_intrs)
1413                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1414         writeq(val64, &bar0->tti_data1_mem);
1415
1416         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1417             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1418             TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1419         writeq(val64, &bar0->tti_data2_mem);
1420
1421         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1422         writeq(val64, &bar0->tti_command_mem);
1423
1424         /*
1425          * Once the operation completes, the Strobe bit of the command
1426          * register will be reset. We poll for this particular condition
1427          * We wait for a maximum of 500ms for the operation to complete,
1428          * if it's not complete by then we return error.
1429          */
1430         time = 0;
1431         while (TRUE) {
1432                 val64 = readq(&bar0->tti_command_mem);
1433                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1434                         break;
1435                 }
1436                 if (time > 10) {
1437                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1438                                   dev->name);
1439                         return -1;
1440                 }
1441                 msleep(50);
1442                 time++;
1443         }
1444
1445         if (nic->config.bimodal) {
1446                 int k = 0;
1447                 for (k = 0; k < config->rx_ring_num; k++) {
1448                         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1449                         val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1450                         writeq(val64, &bar0->tti_command_mem);
1451
1452                 /*
1453                  * Once the operation completes, the Strobe bit of the command
1454                  * register will be reset. We poll for this particular condition
1455                  * We wait for a maximum of 500ms for the operation to complete,
1456                  * if it's not complete by then we return error.
1457                 */
1458                         time = 0;
1459                         while (TRUE) {
1460                                 val64 = readq(&bar0->tti_command_mem);
1461                                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1462                                         break;
1463                                 }
1464                                 if (time > 10) {
1465                                         DBG_PRINT(ERR_DBG,
1466                                                 "%s: TTI init Failed\n",
1467                                         dev->name);
1468                                         return -1;
1469                                 }
1470                                 time++;
1471                                 msleep(50);
1472                         }
1473                 }
1474         } else {
1475
1476                 /* RTI Initialization */
1477                 if (nic->device_type == XFRAME_II_DEVICE) {
1478                         /*
1479                          * Programmed to generate Apprx 500 Intrs per
1480                          * second
1481                          */
1482                         int count = (nic->config.bus_speed * 125)/4;
1483                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1484                 } else {
1485                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1486                 }
1487                 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1488                     RTI_DATA1_MEM_RX_URNG_B(0x10) |
1489                     RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1490
1491                 writeq(val64, &bar0->rti_data1_mem);
1492
1493                 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1494                     RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1495                 if (nic->intr_type == MSI_X)
1496                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1497                                 RTI_DATA2_MEM_RX_UFC_D(0x40));
1498                 else
1499                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1500                                 RTI_DATA2_MEM_RX_UFC_D(0x80));
1501                 writeq(val64, &bar0->rti_data2_mem);
1502
1503                 for (i = 0; i < config->rx_ring_num; i++) {
1504                         val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1505                                         | RTI_CMD_MEM_OFFSET(i);
1506                         writeq(val64, &bar0->rti_command_mem);
1507
1508                         /*
1509                          * Once the operation completes, the Strobe bit of the
1510                          * command register will be reset. We poll for this
1511                          * particular condition. We wait for a maximum of 500ms
1512                          * for the operation to complete, if it's not complete
1513                          * by then we return error.
1514                          */
1515                         time = 0;
1516                         while (TRUE) {
1517                                 val64 = readq(&bar0->rti_command_mem);
1518                                 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1519                                         break;
1520                                 }
1521                                 if (time > 10) {
1522                                         DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1523                                                   dev->name);
1524                                         return -1;
1525                                 }
1526                                 time++;
1527                                 msleep(50);
1528                         }
1529                 }
1530         }
1531
1532         /*
1533          * Initializing proper values as Pause threshold into all
1534          * the 8 Queues on Rx side.
1535          */
1536         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1537         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1538
1539         /* Disable RMAC PAD STRIPPING */
1540         add = &bar0->mac_cfg;
1541         val64 = readq(&bar0->mac_cfg);
1542         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1543         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1544         writel((u32) (val64), add);
1545         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1546         writel((u32) (val64 >> 32), (add + 4));
1547         val64 = readq(&bar0->mac_cfg);
1548
1549         /* Enable FCS stripping by adapter */
1550         add = &bar0->mac_cfg;
1551         val64 = readq(&bar0->mac_cfg);
1552         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1553         if (nic->device_type == XFRAME_II_DEVICE)
1554                 writeq(val64, &bar0->mac_cfg);
1555         else {
1556                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1557                 writel((u32) (val64), add);
1558                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1559                 writel((u32) (val64 >> 32), (add + 4));
1560         }
1561
1562         /*
1563          * Set the time value to be inserted in the pause frame
1564          * generated by xena.
1565          */
1566         val64 = readq(&bar0->rmac_pause_cfg);
1567         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1568         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1569         writeq(val64, &bar0->rmac_pause_cfg);
1570
1571         /*
1572          * Set the Threshold Limit for Generating the pause frame
1573          * If the amount of data in any Queue exceeds ratio of
1574          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1575          * pause frame is generated
1576          */
1577         val64 = 0;
1578         for (i = 0; i < 4; i++) {
1579                 val64 |=
1580                     (((u64) 0xFF00 | nic->mac_control.
1581                       mc_pause_threshold_q0q3)
1582                      << (i * 2 * 8));
1583         }
1584         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1585
1586         val64 = 0;
1587         for (i = 0; i < 4; i++) {
1588                 val64 |=
1589                     (((u64) 0xFF00 | nic->mac_control.
1590                       mc_pause_threshold_q4q7)
1591                      << (i * 2 * 8));
1592         }
1593         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1594
1595         /*
1596          * TxDMA will stop Read request if the number of read split has
1597          * exceeded the limit pointed by shared_splits
1598          */
1599         val64 = readq(&bar0->pic_control);
1600         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1601         writeq(val64, &bar0->pic_control);
1602
1603         if (nic->config.bus_speed == 266) {
1604                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1605                 writeq(0x0, &bar0->read_retry_delay);
1606                 writeq(0x0, &bar0->write_retry_delay);
1607         }
1608
1609         /*
1610          * Programming the Herc to split every write transaction
1611          * that does not start on an ADB to reduce disconnects.
1612          */
1613         if (nic->device_type == XFRAME_II_DEVICE) {
1614                 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1615                         MISC_LINK_STABILITY_PRD(3);
1616                 writeq(val64, &bar0->misc_control);
1617                 val64 = readq(&bar0->pic_control2);
1618                 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1619                 writeq(val64, &bar0->pic_control2);
1620         }
1621         if (strstr(nic->product_name, "CX4")) {
1622                 val64 = TMAC_AVG_IPG(0x17);
1623                 writeq(val64, &bar0->tmac_avg_ipg);
1624         }
1625
1626         return SUCCESS;
1627 }
1628 #define LINK_UP_DOWN_INTERRUPT          1
1629 #define MAC_RMAC_ERR_TIMER              2
1630
1631 static int s2io_link_fault_indication(nic_t *nic)
1632 {
1633         if (nic->intr_type != INTA)
1634                 return MAC_RMAC_ERR_TIMER;
1635         if (nic->device_type == XFRAME_II_DEVICE)
1636                 return LINK_UP_DOWN_INTERRUPT;
1637         else
1638                 return MAC_RMAC_ERR_TIMER;
1639 }
1640
1641 /**
1642  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1643  *  @nic: device private variable,
1644  *  @mask: A mask indicating which Intr block must be modified and,
1645  *  @flag: A flag indicating whether to enable or disable the Intrs.
1646  *  Description: This function will either disable or enable the interrupts
1647  *  depending on the flag argument. The mask argument can be used to
1648  *  enable/disable any Intr block.
1649  *  Return Value: NONE.
1650  */
1651
1652 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1653 {
1654         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1655         register u64 val64 = 0, temp64 = 0;
1656
1657         /*  Top level interrupt classification */
1658         /*  PIC Interrupts */
1659         if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1660                 /*  Enable PIC Intrs in the general intr mask register */
1661                 val64 = TXPIC_INT_M | PIC_RX_INT_M;
1662                 if (flag == ENABLE_INTRS) {
1663                         temp64 = readq(&bar0->general_int_mask);
1664                         temp64 &= ~((u64) val64);
1665                         writeq(temp64, &bar0->general_int_mask);
1666                         /*
1667                          * If Hercules adapter enable GPIO otherwise
1668                          * disable all PCIX, Flash, MDIO, IIC and GPIO
1669                          * interrupts for now.
1670                          * TODO
1671                          */
1672                         if (s2io_link_fault_indication(nic) ==
1673                                         LINK_UP_DOWN_INTERRUPT ) {
1674                                 temp64 = readq(&bar0->pic_int_mask);
1675                                 temp64 &= ~((u64) PIC_INT_GPIO);
1676                                 writeq(temp64, &bar0->pic_int_mask);
1677                                 temp64 = readq(&bar0->gpio_int_mask);
1678                                 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1679                                 writeq(temp64, &bar0->gpio_int_mask);
1680                         } else {
1681                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1682                         }
1683                         /*
1684                          * No MSI Support is available presently, so TTI and
1685                          * RTI interrupts are also disabled.
1686                          */
1687                 } else if (flag == DISABLE_INTRS) {
1688                         /*
1689                          * Disable PIC Intrs in the general
1690                          * intr mask register
1691                          */
1692                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1693                         temp64 = readq(&bar0->general_int_mask);
1694                         val64 |= temp64;
1695                         writeq(val64, &bar0->general_int_mask);
1696                 }
1697         }
1698
1699         /*  DMA Interrupts */
1700         /*  Enabling/Disabling Tx DMA interrupts */
1701         if (mask & TX_DMA_INTR) {
1702                 /* Enable TxDMA Intrs in the general intr mask register */
1703                 val64 = TXDMA_INT_M;
1704                 if (flag == ENABLE_INTRS) {
1705                         temp64 = readq(&bar0->general_int_mask);
1706                         temp64 &= ~((u64) val64);
1707                         writeq(temp64, &bar0->general_int_mask);
1708                         /*
1709                          * Keep all interrupts other than PFC interrupt
1710                          * and PCC interrupt disabled in DMA level.
1711                          */
1712                         val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1713                                                       TXDMA_PCC_INT_M);
1714                         writeq(val64, &bar0->txdma_int_mask);
1715                         /*
1716                          * Enable only the MISC error 1 interrupt in PFC block
1717                          */
1718                         val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1719                         writeq(val64, &bar0->pfc_err_mask);
1720                         /*
1721                          * Enable only the FB_ECC error interrupt in PCC block
1722                          */
1723                         val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1724                         writeq(val64, &bar0->pcc_err_mask);
1725                 } else if (flag == DISABLE_INTRS) {
1726                         /*
1727                          * Disable TxDMA Intrs in the general intr mask
1728                          * register
1729                          */
1730                         writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1731                         writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
1732                         temp64 = readq(&bar0->general_int_mask);
1733                         val64 |= temp64;
1734                         writeq(val64, &bar0->general_int_mask);
1735                 }
1736         }
1737
1738         /*  Enabling/Disabling Rx DMA interrupts */
1739         if (mask & RX_DMA_INTR) {
1740                 /*  Enable RxDMA Intrs in the general intr mask register */
1741                 val64 = RXDMA_INT_M;
1742                 if (flag == ENABLE_INTRS) {
1743                         temp64 = readq(&bar0->general_int_mask);
1744                         temp64 &= ~((u64) val64);
1745                         writeq(temp64, &bar0->general_int_mask);
1746                         /*
1747                          * All RxDMA block interrupts are disabled for now
1748                          * TODO
1749                          */
1750                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1751                 } else if (flag == DISABLE_INTRS) {
1752                         /*
1753                          * Disable RxDMA Intrs in the general intr mask
1754                          * register
1755                          */
1756                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1757                         temp64 = readq(&bar0->general_int_mask);
1758                         val64 |= temp64;
1759                         writeq(val64, &bar0->general_int_mask);
1760                 }
1761         }
1762
1763         /*  MAC Interrupts */
1764         /*  Enabling/Disabling MAC interrupts */
1765         if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1766                 val64 = TXMAC_INT_M | RXMAC_INT_M;
1767                 if (flag == ENABLE_INTRS) {
1768                         temp64 = readq(&bar0->general_int_mask);
1769                         temp64 &= ~((u64) val64);
1770                         writeq(temp64, &bar0->general_int_mask);
1771                         /*
1772                          * All MAC block error interrupts are disabled for now
1773                          * TODO
1774                          */
1775                 } else if (flag == DISABLE_INTRS) {
1776                         /*
1777                          * Disable MAC Intrs in the general intr mask register
1778                          */
1779                         writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1780                         writeq(DISABLE_ALL_INTRS,
1781                                &bar0->mac_rmac_err_mask);
1782
1783                         temp64 = readq(&bar0->general_int_mask);
1784                         val64 |= temp64;
1785                         writeq(val64, &bar0->general_int_mask);
1786                 }
1787         }
1788
1789         /*  XGXS Interrupts */
1790         if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
1791                 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
1792                 if (flag == ENABLE_INTRS) {
1793                         temp64 = readq(&bar0->general_int_mask);
1794                         temp64 &= ~((u64) val64);
1795                         writeq(temp64, &bar0->general_int_mask);
1796                         /*
1797                          * All XGXS block error interrupts are disabled for now
1798                          * TODO
1799                          */
1800                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1801                 } else if (flag == DISABLE_INTRS) {
1802                         /*
1803                          * Disable MC Intrs in the general intr mask register
1804                          */
1805                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1806                         temp64 = readq(&bar0->general_int_mask);
1807                         val64 |= temp64;
1808                         writeq(val64, &bar0->general_int_mask);
1809                 }
1810         }
1811
1812         /*  Memory Controller(MC) interrupts */
1813         if (mask & MC_INTR) {
1814                 val64 = MC_INT_M;
1815                 if (flag == ENABLE_INTRS) {
1816                         temp64 = readq(&bar0->general_int_mask);
1817                         temp64 &= ~((u64) val64);
1818                         writeq(temp64, &bar0->general_int_mask);
1819                         /*
1820                          * Enable all MC Intrs.
1821                          */
1822                         writeq(0x0, &bar0->mc_int_mask);
1823                         writeq(0x0, &bar0->mc_err_mask);
1824                 } else if (flag == DISABLE_INTRS) {
1825                         /*
1826                          * Disable MC Intrs in the general intr mask register
1827                          */
1828                         writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1829                         temp64 = readq(&bar0->general_int_mask);
1830                         val64 |= temp64;
1831                         writeq(val64, &bar0->general_int_mask);
1832                 }
1833         }
1834
1835
1836         /*  Tx traffic interrupts */
1837         if (mask & TX_TRAFFIC_INTR) {
1838                 val64 = TXTRAFFIC_INT_M;
1839                 if (flag == ENABLE_INTRS) {
1840                         temp64 = readq(&bar0->general_int_mask);
1841                         temp64 &= ~((u64) val64);
1842                         writeq(temp64, &bar0->general_int_mask);
1843                         /*
1844                          * Enable all the Tx side interrupts
1845                          * writing 0 Enables all 64 TX interrupt levels
1846                          */
1847                         writeq(0x0, &bar0->tx_traffic_mask);
1848                 } else if (flag == DISABLE_INTRS) {
1849                         /*
1850                          * Disable Tx Traffic Intrs in the general intr mask
1851                          * register.
1852                          */
1853                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1854                         temp64 = readq(&bar0->general_int_mask);
1855                         val64 |= temp64;
1856                         writeq(val64, &bar0->general_int_mask);
1857                 }
1858         }
1859
1860         /*  Rx traffic interrupts */
1861         if (mask & RX_TRAFFIC_INTR) {
1862                 val64 = RXTRAFFIC_INT_M;
1863                 if (flag == ENABLE_INTRS) {
1864                         temp64 = readq(&bar0->general_int_mask);
1865                         temp64 &= ~((u64) val64);
1866                         writeq(temp64, &bar0->general_int_mask);
1867                         /* writing 0 Enables all 8 RX interrupt levels */
1868                         writeq(0x0, &bar0->rx_traffic_mask);
1869                 } else if (flag == DISABLE_INTRS) {
1870                         /*
1871                          * Disable Rx Traffic Intrs in the general intr mask
1872                          * register.
1873                          */
1874                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1875                         temp64 = readq(&bar0->general_int_mask);
1876                         val64 |= temp64;
1877                         writeq(val64, &bar0->general_int_mask);
1878                 }
1879         }
1880 }
1881
1882 /**
1883  *  verify_pcc_quiescent- Checks for PCC quiescent state
1884  *  Return: 1 If PCC is quiescence
1885  *          0 If PCC is not quiescence
1886  */
1887 static int verify_pcc_quiescent(nic_t *sp, int flag)
1888 {
1889         int ret = 0, herc;
1890         XENA_dev_config_t __iomem *bar0 = sp->bar0;
1891         u64 val64 = readq(&bar0->adapter_status);
1892         
1893         herc = (sp->device_type == XFRAME_II_DEVICE);
1894
1895         if (flag == FALSE) {
1896                 if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
1897                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
1898                                 ret = 1;
1899                 } else {
1900                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
1901                                 ret = 1;
1902                 }
1903         } else {
1904                 if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
1905                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1906                              ADAPTER_STATUS_RMAC_PCC_IDLE))
1907                                 ret = 1;
1908                 } else {
1909                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1910                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
1911                                 ret = 1;
1912                 }
1913         }
1914
1915         return ret;
1916 }
1917 /**
1918  *  verify_xena_quiescence - Checks whether the H/W is ready
1919  *  Description: Returns whether the H/W is ready to go or not. Depending
1920  *  on whether adapter enable bit was written or not the comparison
1921  *  differs and the calling function passes the input argument flag to
1922  *  indicate this.
1923  *  Return: 1 If xena is quiescence
1924  *          0 If Xena is not quiescence
1925  */
1926
1927 static int verify_xena_quiescence(nic_t *sp)
1928 {
1929         int  mode;
1930         XENA_dev_config_t __iomem *bar0 = sp->bar0;
1931         u64 val64 = readq(&bar0->adapter_status);
1932         mode = s2io_verify_pci_mode(sp);
1933
1934         if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
1935                 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
1936                 return 0;
1937         }
1938         if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
1939         DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
1940                 return 0;
1941         }
1942         if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
1943                 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
1944                 return 0;
1945         }
1946         if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
1947                 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
1948                 return 0;
1949         }
1950         if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
1951                 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
1952                 return 0;
1953         }
1954         if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
1955                 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
1956                 return 0;
1957         }
1958         if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
1959                 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
1960                 return 0;
1961         }
1962         if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
1963                 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
1964                 return 0;
1965         }
1966
1967         /*
1968          * In PCI 33 mode, the P_PLL is not used, and therefore,
1969          * the the P_PLL_LOCK bit in the adapter_status register will
1970          * not be asserted.
1971          */
1972         if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
1973                 sp->device_type == XFRAME_II_DEVICE && mode !=
1974                 PCI_MODE_PCI_33) {
1975                 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
1976                 return 0;
1977         }
1978         if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1979                         ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1980                 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
1981                 return 0;
1982         }
1983         return 1;
1984 }
1985
1986 /**
1987  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
1988  * @sp: Pointer to device specifc structure
1989  * Description :
1990  * New procedure to clear mac address reading  problems on Alpha platforms
1991  *
1992  */
1993
1994 static void fix_mac_address(nic_t * sp)
1995 {
1996         XENA_dev_config_t __iomem *bar0 = sp->bar0;
1997         u64 val64;
1998         int i = 0;
1999
2000         while (fix_mac[i] != END_SIGN) {
2001                 writeq(fix_mac[i++], &bar0->gpio_control);
2002                 udelay(10);
2003                 val64 = readq(&bar0->gpio_control);
2004         }
2005 }
2006
2007 /**
2008  *  start_nic - Turns the device on
2009  *  @nic : device private variable.
2010  *  Description:
2011  *  This function actually turns the device on. Before this  function is
2012  *  called,all Registers are configured from their reset states
2013  *  and shared memory is allocated but the NIC is still quiescent. On
2014  *  calling this function, the device interrupts are cleared and the NIC is
2015  *  literally switched on by writing into the adapter control register.
2016  *  Return Value:
2017  *  SUCCESS on success and -1 on failure.
2018  */
2019
2020 static int start_nic(struct s2io_nic *nic)
2021 {
2022         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2023         struct net_device *dev = nic->dev;
2024         register u64 val64 = 0;
2025         u16 subid, i;
2026         mac_info_t *mac_control;
2027         struct config_param *config;
2028
2029         mac_control = &nic->mac_control;
2030         config = &nic->config;
2031
2032         /*  PRC Initialization and configuration */
2033         for (i = 0; i < config->rx_ring_num; i++) {
2034                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2035                        &bar0->prc_rxd0_n[i]);
2036
2037                 val64 = readq(&bar0->prc_ctrl_n[i]);
2038                 if (nic->config.bimodal)
2039                         val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
2040                 if (nic->rxd_mode == RXD_MODE_1)
2041                         val64 |= PRC_CTRL_RC_ENABLED;
2042                 else
2043                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2044                 if (nic->device_type == XFRAME_II_DEVICE)
2045                         val64 |= PRC_CTRL_GROUP_READS;
2046                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2047                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2048                 writeq(val64, &bar0->prc_ctrl_n[i]);
2049         }
2050
2051         if (nic->rxd_mode == RXD_MODE_3B) {
2052                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2053                 val64 = readq(&bar0->rx_pa_cfg);
2054                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2055                 writeq(val64, &bar0->rx_pa_cfg);
2056         }
2057
2058         /*
2059          * Enabling MC-RLDRAM. After enabling the device, we timeout
2060          * for around 100ms, which is approximately the time required
2061          * for the device to be ready for operation.
2062          */
2063         val64 = readq(&bar0->mc_rldram_mrs);
2064         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2065         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2066         val64 = readq(&bar0->mc_rldram_mrs);
2067
2068         msleep(100);    /* Delay by around 100 ms. */
2069
2070         /* Enabling ECC Protection. */
2071         val64 = readq(&bar0->adapter_control);
2072         val64 &= ~ADAPTER_ECC_EN;
2073         writeq(val64, &bar0->adapter_control);
2074
2075         /*
2076          * Clearing any possible Link state change interrupts that
2077          * could have popped up just before Enabling the card.
2078          */
2079         val64 = readq(&bar0->mac_rmac_err_reg);
2080         if (val64)
2081                 writeq(val64, &bar0->mac_rmac_err_reg);
2082
2083         /*
2084          * Verify if the device is ready to be enabled, if so enable
2085          * it.
2086          */
2087         val64 = readq(&bar0->adapter_status);
2088         if (!verify_xena_quiescence(nic)) {
2089                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2090                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2091                           (unsigned long long) val64);
2092                 return FAILURE;
2093         }
2094
2095         /*
2096          * With some switches, link might be already up at this point.
2097          * Because of this weird behavior, when we enable laser,
2098          * we may not get link. We need to handle this. We cannot
2099          * figure out which switch is misbehaving. So we are forced to
2100          * make a global change.
2101          */
2102
2103         /* Enabling Laser. */
2104         val64 = readq(&bar0->adapter_control);
2105         val64 |= ADAPTER_EOI_TX_ON;
2106         writeq(val64, &bar0->adapter_control);
2107
2108         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2109                 /*
2110                  * Dont see link state interrupts initally on some switches,
2111                  * so directly scheduling the link state task here.
2112                  */
2113                 schedule_work(&nic->set_link_task);
2114         }
2115         /* SXE-002: Initialize link and activity LED */
2116         subid = nic->pdev->subsystem_device;
2117         if (((subid & 0xFF) >= 0x07) &&
2118             (nic->device_type == XFRAME_I_DEVICE)) {
2119                 val64 = readq(&bar0->gpio_control);
2120                 val64 |= 0x0000800000000000ULL;
2121                 writeq(val64, &bar0->gpio_control);
2122                 val64 = 0x0411040400000000ULL;
2123                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2124         }
2125
2126         return SUCCESS;
2127 }
2128 /**
2129  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2130  */
2131 static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, int get_off)
2132 {
2133         nic_t *nic = fifo_data->nic;
2134         struct sk_buff *skb;
2135         TxD_t *txds;
2136         u16 j, frg_cnt;
2137
2138         txds = txdlp;
2139         if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2140                 pci_unmap_single(nic->pdev, (dma_addr_t)
2141                         txds->Buffer_Pointer, sizeof(u64),
2142                         PCI_DMA_TODEVICE);
2143                 txds++;
2144         }
2145
2146         skb = (struct sk_buff *) ((unsigned long)
2147                         txds->Host_Control);
2148         if (!skb) {
2149                 memset(txdlp, 0, (sizeof(TxD_t) * fifo_data->max_txds));
2150                 return NULL;
2151         }
2152         pci_unmap_single(nic->pdev, (dma_addr_t)
2153                          txds->Buffer_Pointer,
2154                          skb->len - skb->data_len,
2155                          PCI_DMA_TODEVICE);
2156         frg_cnt = skb_shinfo(skb)->nr_frags;
2157         if (frg_cnt) {
2158                 txds++;
2159                 for (j = 0; j < frg_cnt; j++, txds++) {
2160                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2161                         if (!txds->Buffer_Pointer)
2162                                 break;
2163                         pci_unmap_page(nic->pdev, (dma_addr_t)
2164                                         txds->Buffer_Pointer,
2165                                        frag->size, PCI_DMA_TODEVICE);
2166                 }
2167         }
2168         memset(txdlp,0, (sizeof(TxD_t) * fifo_data->max_txds));
2169         return(skb);
2170 }
2171
2172 /**
2173  *  free_tx_buffers - Free all queued Tx buffers
2174  *  @nic : device private variable.
2175  *  Description:
2176  *  Free all queued Tx buffers.
2177  *  Return Value: void
2178 */
2179
2180 static void free_tx_buffers(struct s2io_nic *nic)
2181 {
2182         struct net_device *dev = nic->dev;
2183         struct sk_buff *skb;
2184         TxD_t *txdp;
2185         int i, j;
2186         mac_info_t *mac_control;
2187         struct config_param *config;
2188         int cnt = 0;
2189
2190         mac_control = &nic->mac_control;
2191         config = &nic->config;
2192
2193         for (i = 0; i < config->tx_fifo_num; i++) {
2194                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2195                         txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
2196                             list_virt_addr;
2197                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2198                         if (skb) {
2199                                 dev_kfree_skb(skb);
2200                                 cnt++;
2201                         }
2202                 }
2203                 DBG_PRINT(INTR_DBG,
2204                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2205                           dev->name, cnt, i);
2206                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2207                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2208         }
2209 }
2210
2211 /**
2212  *   stop_nic -  To stop the nic
2213  *   @nic ; device private variable.
2214  *   Description:
2215  *   This function does exactly the opposite of what the start_nic()
2216  *   function does. This function is called to stop the device.
2217  *   Return Value:
2218  *   void.
2219  */
2220
2221 static void stop_nic(struct s2io_nic *nic)
2222 {
2223         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2224         register u64 val64 = 0;
2225         u16 interruptible;
2226         mac_info_t *mac_control;
2227         struct config_param *config;
2228
2229         mac_control = &nic->mac_control;
2230         config = &nic->config;
2231
2232         /*  Disable all interrupts */
2233         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2234         interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2235         interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2236         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2237
2238         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2239         val64 = readq(&bar0->adapter_control);
2240         val64 &= ~(ADAPTER_CNTL_EN);
2241         writeq(val64, &bar0->adapter_control);
2242 }
2243
2244 static int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
2245 {
2246         struct net_device *dev = nic->dev;
2247         struct sk_buff *frag_list;
2248         void *tmp;
2249
2250         /* Buffer-1 receives L3/L4 headers */
2251         ((RxD3_t*)rxdp)->Buffer1_ptr = pci_map_single
2252                         (nic->pdev, skb->data, l3l4hdr_size + 4,
2253                         PCI_DMA_FROMDEVICE);
2254
2255         /* skb_shinfo(skb)->frag_list will have L4 data payload */
2256         skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2257         if (skb_shinfo(skb)->frag_list == NULL) {
2258                 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2259                 return -ENOMEM ;
2260         }
2261         frag_list = skb_shinfo(skb)->frag_list;
2262         skb->truesize += frag_list->truesize;
2263         frag_list->next = NULL;
2264         tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2265         frag_list->data = tmp;
2266         frag_list->tail = tmp;
2267
2268         /* Buffer-2 receives L4 data payload */
2269         ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2270                                 frag_list->data, dev->mtu,
2271                                 PCI_DMA_FROMDEVICE);
2272         rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2273         rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2274
2275         return SUCCESS;
2276 }
2277
2278 /**
2279  *  fill_rx_buffers - Allocates the Rx side skbs
2280  *  @nic:  device private variable
2281  *  @ring_no: ring number
2282  *  Description:
2283  *  The function allocates Rx side skbs and puts the physical
2284  *  address of these buffers into the RxD buffer pointers, so that the NIC
2285  *  can DMA the received frame into these locations.
2286  *  The NIC supports 3 receive modes, viz
2287  *  1. single buffer,
2288  *  2. three buffer and
2289  *  3. Five buffer modes.
2290  *  Each mode defines how many fragments the received frame will be split
2291  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2292  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2293  *  is split into 3 fragments. As of now only single buffer mode is
2294  *  supported.
2295  *   Return Value:
2296  *  SUCCESS on success or an appropriate -ve value on failure.
2297  */
2298
2299 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2300 {
2301         struct net_device *dev = nic->dev;
2302         struct sk_buff *skb;
2303         RxD_t *rxdp;
2304         int off, off1, size, block_no, block_no1;
2305         u32 alloc_tab = 0;
2306         u32 alloc_cnt;
2307         mac_info_t *mac_control;
2308         struct config_param *config;
2309         u64 tmp;
2310         buffAdd_t *ba;
2311         unsigned long flags;
2312         RxD_t *first_rxdp = NULL;
2313
2314         mac_control = &nic->mac_control;
2315         config = &nic->config;
2316         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2317             atomic_read(&nic->rx_bufs_left[ring_no]);
2318
2319         block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2320         off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2321         while (alloc_tab < alloc_cnt) {
2322                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2323                     block_index;
2324                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2325
2326                 rxdp = mac_control->rings[ring_no].
2327                                 rx_blocks[block_no].rxds[off].virt_addr;
2328
2329                 if ((block_no == block_no1) && (off == off1) &&
2330                                         (rxdp->Host_Control)) {
2331                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2332                                   dev->name);
2333                         DBG_PRINT(INTR_DBG, " info equated\n");
2334                         goto end;
2335                 }
2336                 if (off && (off == rxd_count[nic->rxd_mode])) {
2337                         mac_control->rings[ring_no].rx_curr_put_info.
2338                             block_index++;
2339                         if (mac_control->rings[ring_no].rx_curr_put_info.
2340                             block_index == mac_control->rings[ring_no].
2341                                         block_count)
2342                                 mac_control->rings[ring_no].rx_curr_put_info.
2343                                         block_index = 0;
2344                         block_no = mac_control->rings[ring_no].
2345                                         rx_curr_put_info.block_index;
2346                         if (off == rxd_count[nic->rxd_mode])
2347                                 off = 0;
2348                         mac_control->rings[ring_no].rx_curr_put_info.
2349                                 offset = off;
2350                         rxdp = mac_control->rings[ring_no].
2351                                 rx_blocks[block_no].block_virt_addr;
2352                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2353                                   dev->name, rxdp);
2354                 }
2355                 if(!napi) {
2356                         spin_lock_irqsave(&nic->put_lock, flags);
2357                         mac_control->rings[ring_no].put_pos =
2358                         (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2359                         spin_unlock_irqrestore(&nic->put_lock, flags);
2360                 } else {
2361                         mac_control->rings[ring_no].put_pos =
2362                         (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2363                 }
2364                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2365                         ((nic->rxd_mode >= RXD_MODE_3A) &&
2366                                 (rxdp->Control_2 & BIT(0)))) {
2367                         mac_control->rings[ring_no].rx_curr_put_info.
2368                                         offset = off;
2369                         goto end;
2370                 }
2371                 /* calculate size of skb based on ring mode */
2372                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2373                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2374                 if (nic->rxd_mode == RXD_MODE_1)
2375                         size += NET_IP_ALIGN;
2376                 else if (nic->rxd_mode == RXD_MODE_3B)
2377                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2378                 else
2379                         size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
2380
2381                 /* allocate skb */
2382                 skb = dev_alloc_skb(size);
2383                 if(!skb) {
2384                         DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2385                         DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
2386                         if (first_rxdp) {
2387                                 wmb();
2388                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2389                         }
2390                         return -ENOMEM ;
2391                 }
2392                 if (nic->rxd_mode == RXD_MODE_1) {
2393                         /* 1 buffer mode - normal operation mode */
2394                         memset(rxdp, 0, sizeof(RxD1_t));
2395                         skb_reserve(skb, NET_IP_ALIGN);
2396                         ((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single
2397                             (nic->pdev, skb->data, size - NET_IP_ALIGN,
2398                                 PCI_DMA_FROMDEVICE);
2399                         rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2400
2401                 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2402                         /*
2403                          * 2 or 3 buffer mode -
2404                          * Both 2 buffer mode and 3 buffer mode provides 128
2405                          * byte aligned receive buffers.
2406                          *
2407                          * 3 buffer mode provides header separation where in
2408                          * skb->data will have L3/L4 headers where as
2409                          * skb_shinfo(skb)->frag_list will have the L4 data
2410                          * payload
2411                          */
2412
2413                         memset(rxdp, 0, sizeof(RxD3_t));
2414                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2415                         skb_reserve(skb, BUF0_LEN);
2416                         tmp = (u64)(unsigned long) skb->data;
2417                         tmp += ALIGN_SIZE;
2418                         tmp &= ~ALIGN_SIZE;
2419                         skb->data = (void *) (unsigned long)tmp;
2420                         skb->tail = (void *) (unsigned long)tmp;
2421
2422                         if (!(((RxD3_t*)rxdp)->Buffer0_ptr))
2423                                 ((RxD3_t*)rxdp)->Buffer0_ptr =
2424                                    pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2425                                            PCI_DMA_FROMDEVICE);
2426                         else
2427                                 pci_dma_sync_single_for_device(nic->pdev,
2428                                     (dma_addr_t) ((RxD3_t*)rxdp)->Buffer0_ptr,
2429                                     BUF0_LEN, PCI_DMA_FROMDEVICE);
2430                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2431                         if (nic->rxd_mode == RXD_MODE_3B) {
2432                                 /* Two buffer mode */
2433
2434                                 /*
2435                                  * Buffer2 will have L3/L4 header plus
2436                                  * L4 payload
2437                                  */
2438                                 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single
2439                                 (nic->pdev, skb->data, dev->mtu + 4,
2440                                                 PCI_DMA_FROMDEVICE);
2441
2442                                 /* Buffer-1 will be dummy buffer. Not used */
2443                                 if (!(((RxD3_t*)rxdp)->Buffer1_ptr)) {
2444                                         ((RxD3_t*)rxdp)->Buffer1_ptr =
2445                                                 pci_map_single(nic->pdev,
2446                                                 ba->ba_1, BUF1_LEN,
2447                                                 PCI_DMA_FROMDEVICE);
2448                                 }
2449                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2450                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2451                                                                 (dev->mtu + 4);
2452                         } else {
2453                                 /* 3 buffer mode */
2454                                 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2455                                         dev_kfree_skb_irq(skb);
2456                                         if (first_rxdp) {
2457                                                 wmb();
2458                                                 first_rxdp->Control_1 |=
2459                                                         RXD_OWN_XENA;
2460                                         }
2461                                         return -ENOMEM ;
2462                                 }
2463                         }
2464                         rxdp->Control_2 |= BIT(0);
2465                 }
2466                 rxdp->Host_Control = (unsigned long) (skb);
2467                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2468                         rxdp->Control_1 |= RXD_OWN_XENA;
2469                 off++;
2470                 if (off == (rxd_count[nic->rxd_mode] + 1))
2471                         off = 0;
2472                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2473
2474                 rxdp->Control_2 |= SET_RXD_MARKER;
2475                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2476                         if (first_rxdp) {
2477                                 wmb();
2478                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2479                         }
2480                         first_rxdp = rxdp;
2481                 }
2482                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2483                 alloc_tab++;
2484         }
2485
2486       end:
2487         /* Transfer ownership of first descriptor to adapter just before
2488          * exiting. Before that, use memory barrier so that ownership
2489          * and other fields are seen by adapter correctly.
2490          */
2491         if (first_rxdp) {
2492                 wmb();
2493                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2494         }
2495
2496         return SUCCESS;
2497 }
2498
2499 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2500 {
2501         struct net_device *dev = sp->dev;
2502         int j;
2503         struct sk_buff *skb;
2504         RxD_t *rxdp;
2505         mac_info_t *mac_control;
2506         buffAdd_t *ba;
2507
2508         mac_control = &sp->mac_control;
2509         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2510                 rxdp = mac_control->rings[ring_no].
2511                                 rx_blocks[blk].rxds[j].virt_addr;
2512                 skb = (struct sk_buff *)
2513                         ((unsigned long) rxdp->Host_Control);
2514                 if (!skb) {
2515                         continue;
2516                 }
2517                 if (sp->rxd_mode == RXD_MODE_1) {
2518                         pci_unmap_single(sp->pdev, (dma_addr_t)
2519                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2520                                  dev->mtu +
2521                                  HEADER_ETHERNET_II_802_3_SIZE
2522                                  + HEADER_802_2_SIZE +
2523                                  HEADER_SNAP_SIZE,
2524                                  PCI_DMA_FROMDEVICE);
2525                         memset(rxdp, 0, sizeof(RxD1_t));
2526                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2527                         ba = &mac_control->rings[ring_no].
2528                                 ba[blk][j];
2529                         pci_unmap_single(sp->pdev, (dma_addr_t)
2530                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2531                                  BUF0_LEN,
2532                                  PCI_DMA_FROMDEVICE);
2533                         pci_unmap_single(sp->pdev, (dma_addr_t)
2534                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2535                                  BUF1_LEN,
2536                                  PCI_DMA_FROMDEVICE);
2537                         pci_unmap_single(sp->pdev, (dma_addr_t)
2538                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2539                                  dev->mtu + 4,
2540                                  PCI_DMA_FROMDEVICE);
2541                         memset(rxdp, 0, sizeof(RxD3_t));
2542                 } else {
2543                         pci_unmap_single(sp->pdev, (dma_addr_t)
2544                                 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2545                                 PCI_DMA_FROMDEVICE);
2546                         pci_unmap_single(sp->pdev, (dma_addr_t)
2547                                 ((RxD3_t*)rxdp)->Buffer1_ptr,
2548                                 l3l4hdr_size + 4,
2549                                 PCI_DMA_FROMDEVICE);
2550                         pci_unmap_single(sp->pdev, (dma_addr_t)
2551                                 ((RxD3_t*)rxdp)->Buffer2_ptr, dev->mtu,
2552                                 PCI_DMA_FROMDEVICE);
2553                         memset(rxdp, 0, sizeof(RxD3_t));
2554                 }
2555                 dev_kfree_skb(skb);
2556                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2557         }
2558 }
2559
2560 /**
2561  *  free_rx_buffers - Frees all Rx buffers
2562  *  @sp: device private variable.
2563  *  Description:
2564  *  This function will free all Rx buffers allocated by host.
2565  *  Return Value:
2566  *  NONE.
2567  */
2568
2569 static void free_rx_buffers(struct s2io_nic *sp)
2570 {
2571         struct net_device *dev = sp->dev;
2572         int i, blk = 0, buf_cnt = 0;
2573         mac_info_t *mac_control;
2574         struct config_param *config;
2575
2576         mac_control = &sp->mac_control;
2577         config = &sp->config;
2578
2579         for (i = 0; i < config->rx_ring_num; i++) {
2580                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2581                         free_rxd_blk(sp,i,blk);
2582
2583                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2584                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2585                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2586                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2587                 atomic_set(&sp->rx_bufs_left[i], 0);
2588                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2589                           dev->name, buf_cnt, i);
2590         }
2591 }
2592
2593 /**
2594  * s2io_poll - Rx interrupt handler for NAPI support
2595  * @dev : pointer to the device structure.
2596  * @budget : The number of packets that were budgeted to be processed
2597  * during  one pass through the 'Poll" function.
2598  * Description:
2599  * Comes into picture only if NAPI support has been incorporated. It does
2600  * the same thing that rx_intr_handler does, but not in a interrupt context
2601  * also It will process only a given number of packets.
2602  * Return value:
2603  * 0 on success and 1 if there are No Rx packets to be processed.
2604  */
2605
2606 static int s2io_poll(struct net_device *dev, int *budget)
2607 {
2608         nic_t *nic = dev->priv;
2609         int pkt_cnt = 0, org_pkts_to_process;
2610         mac_info_t *mac_control;
2611         struct config_param *config;
2612         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2613         int i;
2614
2615         atomic_inc(&nic->isr_cnt);
2616         mac_control = &nic->mac_control;
2617         config = &nic->config;
2618
2619         nic->pkts_to_process = *budget;
2620         if (nic->pkts_to_process > dev->quota)
2621                 nic->pkts_to_process = dev->quota;
2622         org_pkts_to_process = nic->pkts_to_process;
2623
2624         writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2625         readl(&bar0->rx_traffic_int);
2626
2627         for (i = 0; i < config->rx_ring_num; i++) {
2628                 rx_intr_handler(&mac_control->rings[i]);
2629                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2630                 if (!nic->pkts_to_process) {
2631                         /* Quota for the current iteration has been met */
2632                         goto no_rx;
2633                 }
2634         }
2635         if (!pkt_cnt)
2636                 pkt_cnt = 1;
2637
2638         dev->quota -= pkt_cnt;
2639         *budget -= pkt_cnt;
2640         netif_rx_complete(dev);
2641
2642         for (i = 0; i < config->rx_ring_num; i++) {
2643                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2644                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2645                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2646                         break;
2647                 }
2648         }
2649         /* Re enable the Rx interrupts. */
2650         writeq(0x0, &bar0->rx_traffic_mask);
2651         readl(&bar0->rx_traffic_mask);
2652         atomic_dec(&nic->isr_cnt);
2653         return 0;
2654
2655 no_rx:
2656         dev->quota -= pkt_cnt;
2657         *budget -= pkt_cnt;
2658
2659         for (i = 0; i < config->rx_ring_num; i++) {
2660                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2661                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2662                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2663                         break;
2664                 }
2665         }
2666         atomic_dec(&nic->isr_cnt);
2667         return 1;
2668 }
2669
2670 #ifdef CONFIG_NET_POLL_CONTROLLER
2671 /**
2672  * s2io_netpoll - netpoll event handler entry point
2673  * @dev : pointer to the device structure.
2674  * Description:
2675  *      This function will be called by upper layer to check for events on the
2676  * interface in situations where interrupts are disabled. It is used for
2677  * specific in-kernel networking tasks, such as remote consoles and kernel
2678  * debugging over the network (example netdump in RedHat).
2679  */
2680 static void s2io_netpoll(struct net_device *dev)
2681 {
2682         nic_t *nic = dev->priv;
2683         mac_info_t *mac_control;
2684         struct config_param *config;
2685         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2686         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2687         int i;
2688
2689         disable_irq(dev->irq);
2690
2691         atomic_inc(&nic->isr_cnt);
2692         mac_control = &nic->mac_control;
2693         config = &nic->config;
2694
2695         writeq(val64, &bar0->rx_traffic_int);
2696         writeq(val64, &bar0->tx_traffic_int);
2697
2698         /* we need to free up the transmitted skbufs or else netpoll will
2699          * run out of skbs and will fail and eventually netpoll application such
2700          * as netdump will fail.
2701          */
2702         for (i = 0; i < config->tx_fifo_num; i++)
2703                 tx_intr_handler(&mac_control->fifos[i]);
2704
2705         /* check for received packet and indicate up to network */
2706         for (i = 0; i < config->rx_ring_num; i++)
2707                 rx_intr_handler(&mac_control->rings[i]);
2708
2709         for (i = 0; i < config->rx_ring_num; i++) {
2710                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2711                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2712                         DBG_PRINT(ERR_DBG, " in Rx Netpoll!!\n");
2713                         break;
2714                 }
2715         }
2716         atomic_dec(&nic->isr_cnt);
2717         enable_irq(dev->irq);
2718         return;
2719 }
2720 #endif
2721
2722 /**
2723  *  rx_intr_handler - Rx interrupt handler
2724  *  @nic: device private variable.
2725  *  Description:
2726  *  If the interrupt is because of a received frame or if the
2727  *  receive ring contains fresh as yet un-processed frames,this function is
2728  *  called. It picks out the RxD at which place the last Rx processing had
2729  *  stopped and sends the skb to the OSM's Rx handler and then increments
2730  *  the offset.
2731  *  Return Value:
2732  *  NONE.
2733  */
2734 static void rx_intr_handler(ring_info_t *ring_data)
2735 {
2736         nic_t *nic = ring_data->nic;
2737         struct net_device *dev = (struct net_device *) nic->dev;
2738         int get_block, put_block, put_offset;
2739         rx_curr_get_info_t get_info, put_info;
2740         RxD_t *rxdp;
2741         struct sk_buff *skb;
2742         int pkt_cnt = 0;
2743         int i;
2744
2745         spin_lock(&nic->rx_lock);
2746         if (atomic_read(&nic->card_state) == CARD_DOWN) {
2747                 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2748                           __FUNCTION__, dev->name);
2749                 spin_unlock(&nic->rx_lock);
2750                 return;
2751         }
2752
2753         get_info = ring_data->rx_curr_get_info;
2754         get_block = get_info.block_index;
2755         put_info = ring_data->rx_curr_put_info;
2756         put_block = put_info.block_index;
2757         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2758         if (!napi) {
2759                 spin_lock(&nic->put_lock);
2760                 put_offset = ring_data->put_pos;
2761                 spin_unlock(&nic->put_lock);
2762         } else
2763                 put_offset = ring_data->put_pos;
2764
2765         while (RXD_IS_UP2DT(rxdp)) {
2766                 /*
2767                  * If your are next to put index then it's
2768                  * FIFO full condition
2769                  */
2770                 if ((get_block == put_block) &&
2771                     (get_info.offset + 1) == put_info.offset) {
2772                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
2773                         break;
2774                 }
2775                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2776                 if (skb == NULL) {
2777                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2778                                   dev->name);
2779                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2780                         spin_unlock(&nic->rx_lock);
2781                         return;
2782                 }
2783                 if (nic->rxd_mode == RXD_MODE_1) {
2784                         pci_unmap_single(nic->pdev, (dma_addr_t)
2785                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2786                                  dev->mtu +
2787                                  HEADER_ETHERNET_II_802_3_SIZE +
2788                                  HEADER_802_2_SIZE +
2789                                  HEADER_SNAP_SIZE,
2790                                  PCI_DMA_FROMDEVICE);
2791                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2792                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2793                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2794                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
2795                         pci_unmap_single(nic->pdev, (dma_addr_t)
2796                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2797                                  dev->mtu + 4,
2798                                  PCI_DMA_FROMDEVICE);
2799                 } else {
2800                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2801                                          ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2802                                          PCI_DMA_FROMDEVICE);
2803                         pci_unmap_single(nic->pdev, (dma_addr_t)
2804                                          ((RxD3_t*)rxdp)->Buffer1_ptr,
2805                                          l3l4hdr_size + 4,
2806                                          PCI_DMA_FROMDEVICE);
2807                         pci_unmap_single(nic->pdev, (dma_addr_t)
2808                                          ((RxD3_t*)rxdp)->Buffer2_ptr,
2809                                          dev->mtu, PCI_DMA_FROMDEVICE);
2810                 }
2811                 prefetch(skb->data);
2812                 rx_osm_handler(ring_data, rxdp);
2813                 get_info.offset++;
2814                 ring_data->rx_curr_get_info.offset = get_info.offset;
2815                 rxdp = ring_data->rx_blocks[get_block].
2816                                 rxds[get_info.offset].virt_addr;
2817                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2818                         get_info.offset = 0;
2819                         ring_data->rx_curr_get_info.offset = get_info.offset;
2820                         get_block++;
2821                         if (get_block == ring_data->block_count)
2822                                 get_block = 0;
2823                         ring_data->rx_curr_get_info.block_index = get_block;
2824                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2825                 }
2826
2827                 nic->pkts_to_process -= 1;
2828                 if ((napi) && (!nic->pkts_to_process))
2829                         break;
2830                 pkt_cnt++;
2831                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2832                         break;
2833         }
2834         if (nic->lro) {
2835                 /* Clear all LRO sessions before exiting */
2836                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2837                         lro_t *lro = &nic->lro0_n[i];
2838                         if (lro->in_use) {
2839                                 update_L3L4_header(nic, lro);
2840                                 queue_rx_frame(lro->parent);
2841                                 clear_lro_session(lro);
2842                         }
2843                 }
2844         }
2845
2846         spin_unlock(&nic->rx_lock);
2847 }
2848
2849 /**
2850  *  tx_intr_handler - Transmit interrupt handler
2851  *  @nic : device private variable
2852  *  Description:
2853  *  If an interrupt was raised to indicate DMA complete of the
2854  *  Tx packet, this function is called. It identifies the last TxD
2855  *  whose buffer was freed and frees all skbs whose data have already
2856  *  DMA'ed into the NICs internal memory.
2857  *  Return Value:
2858  *  NONE
2859  */
2860
2861 static void tx_intr_handler(fifo_info_t *fifo_data)
2862 {
2863         nic_t *nic = fifo_data->nic;
2864         struct net_device *dev = (struct net_device *) nic->dev;
2865         tx_curr_get_info_t get_info, put_info;
2866         struct sk_buff *skb;
2867         TxD_t *txdlp;
2868
2869         get_info = fifo_data->tx_curr_get_info;
2870         put_info = fifo_data->tx_curr_put_info;
2871         txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2872             list_virt_addr;
2873         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2874                (get_info.offset != put_info.offset) &&
2875                (txdlp->Host_Control)) {
2876                 /* Check for TxD errors */
2877                 if (txdlp->Control_1 & TXD_T_CODE) {
2878                         unsigned long long err;
2879                         err = txdlp->Control_1 & TXD_T_CODE;
2880                         if (err & 0x1) {
2881                                 nic->mac_control.stats_info->sw_stat.
2882                                                 parity_err_cnt++;
2883                         }
2884                         if ((err >> 48) == 0xA) {
2885                                 DBG_PRINT(TX_DBG, "TxD returned due \
2886                                                 to loss of link\n");
2887                         }
2888                         else {
2889                                 DBG_PRINT(ERR_DBG, "***TxD error %llx\n", err);
2890                         }
2891                 }
2892
2893                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2894                 if (skb == NULL) {
2895                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
2896                         __FUNCTION__);
2897                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2898                         return;
2899                 }
2900
2901                 /* Updating the statistics block */
2902                 nic->stats.tx_bytes += skb->len;
2903                 dev_kfree_skb_irq(skb);
2904
2905                 get_info.offset++;
2906                 if (get_info.offset == get_info.fifo_len + 1)
2907                         get_info.offset = 0;
2908                 txdlp = (TxD_t *) fifo_data->list_info
2909                     [get_info.offset].list_virt_addr;
2910                 fifo_data->tx_curr_get_info.offset =
2911                     get_info.offset;
2912         }
2913
2914         spin_lock(&nic->tx_lock);
2915         if (netif_queue_stopped(dev))
2916                 netif_wake_queue(dev);
2917         spin_unlock(&nic->tx_lock);
2918 }
2919
2920 /**
2921  *  s2io_mdio_write - Function to write in to MDIO registers
2922  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2923  *  @addr     : address value
2924  *  @value    : data value
2925  *  @dev      : pointer to net_device structure
2926  *  Description:
2927  *  This function is used to write values to the MDIO registers
2928  *  NONE
2929  */
2930 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2931 {
2932         u64 val64 = 0x0;
2933         nic_t *sp = dev->priv;
2934         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2935
2936         //address transaction
2937         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2938                         | MDIO_MMD_DEV_ADDR(mmd_type)
2939                         | MDIO_MMS_PRT_ADDR(0x0);
2940         writeq(val64, &bar0->mdio_control);
2941         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2942         writeq(val64, &bar0->mdio_control);
2943         udelay(100);
2944
2945         //Data transaction
2946         val64 = 0x0;
2947         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2948                         | MDIO_MMD_DEV_ADDR(mmd_type)
2949                         | MDIO_MMS_PRT_ADDR(0x0)
2950                         | MDIO_MDIO_DATA(value)
2951                         | MDIO_OP(MDIO_OP_WRITE_TRANS);
2952         writeq(val64, &bar0->mdio_control);
2953         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2954         writeq(val64, &bar0->mdio_control);
2955         udelay(100);
2956
2957         val64 = 0x0;
2958         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2959         | MDIO_MMD_DEV_ADDR(mmd_type)
2960         | MDIO_MMS_PRT_ADDR(0x0)
2961         | MDIO_OP(MDIO_OP_READ_TRANS);
2962         writeq(val64, &bar0->mdio_control);
2963         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2964         writeq(val64, &bar0->mdio_control);
2965         udelay(100);
2966
2967 }
2968
2969 /**
2970  *  s2io_mdio_read - Function to write in to MDIO registers
2971  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2972  *  @addr     : address value
2973  *  @dev      : pointer to net_device structure
2974  *  Description:
2975  *  This function is used to read values to the MDIO registers
2976  *  NONE
2977  */
2978 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
2979 {
2980         u64 val64 = 0x0;
2981         u64 rval64 = 0x0;
2982         nic_t *sp = dev->priv;
2983         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2984
2985         /* address transaction */
2986         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2987                         | MDIO_MMD_DEV_ADDR(mmd_type)
2988                         | MDIO_MMS_PRT_ADDR(0x0);
2989         writeq(val64, &bar0->mdio_control);
2990         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2991         writeq(val64, &bar0->mdio_control);
2992         udelay(100);
2993
2994         /* Data transaction */
2995         val64 = 0x0;
2996         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2997                         | MDIO_MMD_DEV_ADDR(mmd_type)
2998                         | MDIO_MMS_PRT_ADDR(0x0)
2999                         | MDIO_OP(MDIO_OP_READ_TRANS);
3000         writeq(val64, &bar0->mdio_control);
3001         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3002         writeq(val64, &bar0->mdio_control);
3003         udelay(100);
3004
3005         /* Read the value from regs */
3006         rval64 = readq(&bar0->mdio_control);
3007         rval64 = rval64 & 0xFFFF0000;
3008         rval64 = rval64 >> 16;
3009         return rval64;
3010 }
3011 /**
3012  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
3013  *  @counter      : couter value to be updated
3014  *  @flag         : flag to indicate the status
3015  *  @type         : counter type
3016  *  Description:
3017  *  This function is to check the status of the xpak counters value
3018  *  NONE
3019  */
3020
3021 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3022 {
3023         u64 mask = 0x3;
3024         u64 val64;
3025         int i;
3026         for(i = 0; i <index; i++)
3027                 mask = mask << 0x2;
3028
3029         if(flag > 0)
3030         {
3031                 *counter = *counter + 1;
3032                 val64 = *regs_stat & mask;
3033                 val64 = val64 >> (index * 0x2);
3034                 val64 = val64 + 1;
3035                 if(val64 == 3)
3036                 {
3037                         switch(type)
3038                         {
3039                         case 1:
3040                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3041                                           "service. Excessive temperatures may "
3042                                           "result in premature transceiver "
3043                                           "failure \n");
3044                         break;
3045                         case 2:
3046                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3047                                           "service Excessive bias currents may "
3048                                           "indicate imminent laser diode "
3049                                           "failure \n");
3050                         break;
3051                         case 3:
3052                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3053                                           "service Excessive laser output "
3054                                           "power may saturate far-end "
3055                                           "receiver\n");
3056                         break;
3057                         default:
3058                                 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3059                                           "type \n");
3060                         }
3061                         val64 = 0x0;
3062                 }
3063                 val64 = val64 << (index * 0x2);
3064                 *regs_stat = (*regs_stat & (~mask)) | (val64);
3065
3066         } else {
3067                 *regs_stat = *regs_stat & (~mask);
3068         }
3069 }
3070
3071 /**
3072  *  s2io_updt_xpak_counter - Function to update the xpak counters
3073  *  @dev         : pointer to net_device struct
3074  *  Description:
3075  *  This function is to upate the status of the xpak counters value
3076  *  NONE
3077  */
3078 static void s2io_updt_xpak_counter(struct net_device *dev)
3079 {
3080         u16 flag  = 0x0;
3081         u16 type  = 0x0;
3082         u16 val16 = 0x0;
3083         u64 val64 = 0x0;
3084         u64 addr  = 0x0;
3085
3086         nic_t *sp = dev->priv;
3087         StatInfo_t *stat_info = sp->mac_control.stats_info;
3088
3089         /* Check the communication with the MDIO slave */
3090         addr = 0x0000;
3091         val64 = 0x0;
3092         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3093         if((val64 == 0xFFFF) || (val64 == 0x0000))
3094         {
3095                 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3096                           "Returned %llx\n", (unsigned long long)val64);
3097                 return;
3098         }
3099
3100         /* Check for the expecte value of 2040 at PMA address 0x0000 */
3101         if(val64 != 0x2040)
3102         {
3103                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3104                 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3105                           (unsigned long long)val64);
3106                 return;
3107         }
3108
3109         /* Loading the DOM register to MDIO register */
3110         addr = 0xA100;
3111         s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3112         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3113
3114         /* Reading the Alarm flags */
3115         addr = 0xA070;
3116         val64 = 0x0;
3117         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3118
3119         flag = CHECKBIT(val64, 0x7);
3120         type = 1;
3121         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3122                                 &stat_info->xpak_stat.xpak_regs_stat,
3123                                 0x0, flag, type);
3124
3125         if(CHECKBIT(val64, 0x6))
3126                 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3127
3128         flag = CHECKBIT(val64, 0x3);
3129         type = 2;
3130         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3131                                 &stat_info->xpak_stat.xpak_regs_stat,
3132                                 0x2, flag, type);
3133
3134         if(CHECKBIT(val64, 0x2))
3135                 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3136
3137         flag = CHECKBIT(val64, 0x1);
3138         type = 3;
3139         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3140                                 &stat_info->xpak_stat.xpak_regs_stat,
3141                                 0x4, flag, type);
3142
3143         if(CHECKBIT(val64, 0x0))
3144                 stat_info->xpak_stat.alarm_laser_output_power_low++;
3145
3146         /* Reading the Warning flags */
3147         addr = 0xA074;
3148         val64 = 0x0;
3149         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3150
3151         if(CHECKBIT(val64, 0x7))
3152                 stat_info->xpak_stat.warn_transceiver_temp_high++;
3153
3154         if(CHECKBIT(val64, 0x6))
3155                 stat_info->xpak_stat.warn_transceiver_temp_low++;
3156
3157         if(CHECKBIT(val64, 0x3))
3158                 stat_info->xpak_stat.warn_laser_bias_current_high++;
3159
3160         if(CHECKBIT(val64, 0x2))
3161                 stat_info->xpak_stat.warn_laser_bias_current_low++;
3162
3163         if(CHECKBIT(val64, 0x1))
3164                 stat_info->xpak_stat.warn_laser_output_power_high++;
3165
3166         if(CHECKBIT(val64, 0x0))
3167                 stat_info->xpak_stat.warn_laser_output_power_low++;
3168 }
3169
3170 /**
3171  *  alarm_intr_handler - Alarm Interrrupt handler
3172  *  @nic: device private variable
3173  *  Description: If the interrupt was neither because of Rx packet or Tx
3174  *  complete, this function is called. If the interrupt was to indicate
3175  *  a loss of link, the OSM link status handler is invoked for any other
3176  *  alarm interrupt the block that raised the interrupt is displayed
3177  *  and a H/W reset is issued.
3178  *  Return Value:
3179  *  NONE
3180 */
3181
3182 static void alarm_intr_handler(struct s2io_nic *nic)
3183 {
3184         struct net_device *dev = (struct net_device *) nic->dev;
3185         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3186         register u64 val64 = 0, err_reg = 0;
3187         u64 cnt;
3188         int i;
3189         if (atomic_read(&nic->card_state) == CARD_DOWN)
3190                 return;
3191         nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3192         /* Handling the XPAK counters update */
3193         if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3194                 /* waiting for an hour */
3195                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3196         } else {
3197                 s2io_updt_xpak_counter(dev);
3198                 /* reset the count to zero */
3199                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3200         }
3201
3202         /* Handling link status change error Intr */
3203         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3204                 err_reg = readq(&bar0->mac_rmac_err_reg);
3205                 writeq(err_reg, &bar0->mac_rmac_err_reg);
3206                 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3207                         schedule_work(&nic->set_link_task);
3208                 }
3209         }
3210
3211         /* Handling Ecc errors */
3212         val64 = readq(&bar0->mc_err_reg);
3213         writeq(val64, &bar0->mc_err_reg);
3214         if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
3215                 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
3216                         nic->mac_control.stats_info->sw_stat.
3217                                 double_ecc_errs++;
3218                         DBG_PRINT(INIT_DBG, "%s: Device indicates ",
3219                                   dev->name);
3220                         DBG_PRINT(INIT_DBG, "double ECC error!!\n");
3221                         if (nic->device_type != XFRAME_II_DEVICE) {
3222                                 /* Reset XframeI only if critical error */
3223                                 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
3224                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
3225                                         netif_stop_queue(dev);
3226                                         schedule_work(&nic->rst_timer_task);
3227                                         nic->mac_control.stats_info->sw_stat.
3228                                                         soft_reset_cnt++;
3229                                 }
3230                         }
3231                 } else {
3232                         nic->mac_control.stats_info->sw_stat.
3233                                 single_ecc_errs++;
3234                 }
3235         }
3236
3237         /* In case of a serious error, the device will be Reset. */
3238         val64 = readq(&bar0->serr_source);
3239         if (val64 & SERR_SOURCE_ANY) {
3240                 nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
3241                 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
3242                 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
3243                           (unsigned long long)val64);
3244                 netif_stop_queue(dev);
3245                 schedule_work(&nic->rst_timer_task);
3246                 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3247         }
3248
3249         /*
3250          * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3251          * Error occurs, the adapter will be recycled by disabling the
3252          * adapter enable bit and enabling it again after the device
3253          * becomes Quiescent.
3254          */
3255         val64 = readq(&bar0->pcc_err_reg);
3256         writeq(val64, &bar0->pcc_err_reg);
3257         if (val64 & PCC_FB_ECC_DB_ERR) {
3258                 u64 ac = readq(&bar0->adapter_control);
3259                 ac &= ~(ADAPTER_CNTL_EN);
3260                 writeq(ac, &bar0->adapter_control);
3261                 ac = readq(&bar0->adapter_control);
3262                 schedule_work(&nic->set_link_task);
3263         }
3264         /* Check for data parity error */
3265         val64 = readq(&bar0->pic_int_status);
3266         if (val64 & PIC_INT_GPIO) {
3267                 val64 = readq(&bar0->gpio_int_reg);
3268                 if (val64 & GPIO_INT_REG_DP_ERR_INT) {
3269                         nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
3270                         schedule_work(&nic->rst_timer_task);
3271                         nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3272                 }
3273         }
3274
3275         /* Check for ring full counter */
3276         if (nic->device_type & XFRAME_II_DEVICE) {
3277                 val64 = readq(&bar0->ring_bump_counter1);
3278                 for (i=0; i<4; i++) {
3279                         cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3280                         cnt >>= 64 - ((i+1)*16);
3281                         nic->mac_control.stats_info->sw_stat.ring_full_cnt
3282                                 += cnt;
3283                 }
3284
3285                 val64 = readq(&bar0->ring_bump_counter2);
3286                 for (i=0; i<4; i++) {
3287                         cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3288                         cnt >>= 64 - ((i+1)*16);
3289                         nic->mac_control.stats_info->sw_stat.ring_full_cnt
3290                                 += cnt;
3291                 }
3292         }
3293
3294         /* Other type of interrupts are not being handled now,  TODO */
3295 }
3296
3297 /**
3298  *  wait_for_cmd_complete - waits for a command to complete.
3299  *  @sp : private member of the device structure, which is a pointer to the
3300  *  s2io_nic structure.
3301  *  Description: Function that waits for a command to Write into RMAC
3302  *  ADDR DATA registers to be completed and returns either success or
3303  *  error depending on whether the command was complete or not.
3304  *  Return value:
3305  *   SUCCESS on success and FAILURE on failure.
3306  */
3307
3308 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit)
3309 {
3310         int ret = FAILURE, cnt = 0;
3311         u64 val64;
3312
3313         while (TRUE) {
3314                 val64 = readq(addr);
3315                 if (!(val64 & busy_bit)) {
3316                         ret = SUCCESS;
3317                         break;
3318                 }
3319
3320                 if(in_interrupt())
3321                         mdelay(50);
3322                 else
3323                         msleep(50);
3324
3325                 if (cnt++ > 10)
3326                         break;
3327         }
3328         return ret;
3329 }
3330 /*
3331  * check_pci_device_id - Checks if the device id is supported
3332  * @id : device id
3333  * Description: Function to check if the pci device id is supported by driver.
3334  * Return value: Actual device id if supported else PCI_ANY_ID
3335  */
3336 static u16 check_pci_device_id(u16 id)
3337 {
3338         switch (id) {
3339         case PCI_DEVICE_ID_HERC_WIN:
3340         case PCI_DEVICE_ID_HERC_UNI:
3341                 return XFRAME_II_DEVICE;
3342         case PCI_DEVICE_ID_S2IO_UNI:
3343         case PCI_DEVICE_ID_S2IO_WIN:
3344                 return XFRAME_I_DEVICE;
3345         default:
3346                 return PCI_ANY_ID;
3347         }
3348 }
3349
3350 /**
3351  *  s2io_reset - Resets the card.
3352  *  @sp : private member of the device structure.
3353  *  Description: Function to Reset the card. This function then also
3354  *  restores the previously saved PCI configuration space registers as
3355  *  the card reset also resets the configuration space.
3356  *  Return value:
3357  *  void.
3358  */
3359
3360 static void s2io_reset(nic_t * sp)
3361 {
3362         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3363         u64 val64;
3364         u16 subid, pci_cmd;
3365         int i;
3366         u16 val16;
3367         DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3368                         __FUNCTION__, sp->dev->name);
3369
3370         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3371         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3372
3373         if (sp->device_type == XFRAME_II_DEVICE) {
3374                 int ret;
3375                 ret = pci_set_power_state(sp->pdev, 3);
3376                 if (!ret)
3377                         ret = pci_set_power_state(sp->pdev, 0);
3378                 else {
3379                         DBG_PRINT(ERR_DBG,"%s PME based SW_Reset failed!\n",
3380                                         __FUNCTION__);
3381                         goto old_way;
3382                 }
3383                 msleep(20);
3384                 goto new_way;
3385         }
3386 old_way:
3387         val64 = SW_RESET_ALL;
3388         writeq(val64, &bar0->sw_reset);
3389 new_way:
3390         if (strstr(sp->product_name, "CX4")) {
3391                 msleep(750);
3392         }
3393         msleep(250);
3394         for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3395
3396                 /* Restore the PCI state saved during initialization. */
3397                 pci_restore_state(sp->pdev);
3398                 pci_read_config_word(sp->pdev, 0x2, &val16);
3399                 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3400                         break;
3401                 msleep(200);
3402         }
3403
3404         if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3405                 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3406         }
3407
3408         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3409
3410         s2io_init_pci(sp);
3411
3412         /* Set swapper to enable I/O register access */
3413         s2io_set_swapper(sp);
3414
3415         /* Restore the MSIX table entries from local variables */
3416         restore_xmsi_data(sp);
3417
3418         /* Clear certain PCI/PCI-X fields after reset */
3419         if (sp->device_type == XFRAME_II_DEVICE) {
3420                 /* Clear "detected parity error" bit */
3421                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3422
3423                 /* Clearing PCIX Ecc status register */
3424                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3425
3426                 /* Clearing PCI_STATUS error reflected here */
3427                 writeq(BIT(62), &bar0->txpic_int_reg);
3428         }
3429
3430         /* Reset device statistics maintained by OS */
3431         memset(&sp->stats, 0, sizeof (struct net_device_stats));
3432
3433         /* SXE-002: Configure link and activity LED to turn it off */
3434         subid = sp->pdev->subsystem_device;
3435         if (((subid & 0xFF) >= 0x07) &&
3436             (sp->device_type == XFRAME_I_DEVICE)) {
3437                 val64 = readq(&bar0->gpio_control);
3438                 val64 |= 0x0000800000000000ULL;
3439                 writeq(val64, &bar0->gpio_control);
3440                 val64 = 0x0411040400000000ULL;
3441                 writeq(val64, (void __iomem *)bar0 + 0x2700);
3442         }
3443
3444         /*
3445          * Clear spurious ECC interrupts that would have occured on
3446          * XFRAME II cards after reset.
3447          */
3448         if (sp->device_type == XFRAME_II_DEVICE) {
3449                 val64 = readq(&bar0->pcc_err_reg);
3450                 writeq(val64, &bar0->pcc_err_reg);
3451         }
3452
3453         sp->device_enabled_once = FALSE;
3454 }
3455
3456 /**
3457  *  s2io_set_swapper - to set the swapper controle on the card
3458  *  @sp : private member of the device structure,
3459  *  pointer to the s2io_nic structure.
3460  *  Description: Function to set the swapper control on the card
3461  *  correctly depending on the 'endianness' of the system.
3462  *  Return value:
3463  *  SUCCESS on success and FAILURE on failure.
3464  */
3465
3466 static int s2io_set_swapper(nic_t * sp)
3467 {
3468         struct net_device *dev = sp->dev;
3469         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3470         u64 val64, valt, valr;
3471
3472         /*
3473          * Set proper endian settings and verify the same by reading
3474          * the PIF Feed-back register.
3475          */
3476
3477         val64 = readq(&bar0->pif_rd_swapper_fb);
3478         if (val64 != 0x0123456789ABCDEFULL) {
3479                 int i = 0;
3480                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
3481                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
3482                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
3483                                 0};                     /* FE=0, SE=0 */
3484
3485                 while(i<4) {
3486                         writeq(value[i], &bar0->swapper_ctrl);
3487                         val64 = readq(&bar0->pif_rd_swapper_fb);
3488                         if (val64 == 0x0123456789ABCDEFULL)
3489                                 break;
3490                         i++;
3491                 }
3492                 if (i == 4) {
3493                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3494                                 dev->name);
3495                         DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3496                                 (unsigned long long) val64);
3497                         return FAILURE;
3498                 }
3499                 valr = value[i];
3500         } else {
3501                 valr = readq(&bar0->swapper_ctrl);
3502         }
3503
3504         valt = 0x0123456789ABCDEFULL;
3505         writeq(valt, &bar0->xmsi_address);
3506         val64 = readq(&bar0->xmsi_address);
3507
3508         if(val64 != valt) {
3509                 int i = 0;
3510                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3511                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
3512                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
3513                                 0};                     /* FE=0, SE=0 */
3514
3515                 while(i<4) {
3516                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3517                         writeq(valt, &bar0->xmsi_address);
3518                         val64 = readq(&bar0->xmsi_address);
3519                         if(val64 == valt)
3520                                 break;
3521                         i++;
3522                 }
3523                 if(i == 4) {
3524                         unsigned long long x = val64;
3525                         DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3526                         DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3527                         return FAILURE;
3528                 }
3529         }
3530         val64 = readq(&bar0->swapper_ctrl);
3531         val64 &= 0xFFFF000000000000ULL;
3532
3533 #ifdef  __BIG_ENDIAN
3534         /*
3535          * The device by default set to a big endian format, so a
3536          * big endian driver need not set anything.
3537          */
3538         val64 |= (SWAPPER_CTRL_TXP_FE |
3539                  SWAPPER_CTRL_TXP_SE |
3540                  SWAPPER_CTRL_TXD_R_FE |
3541                  SWAPPER_CTRL_TXD_W_FE |
3542                  SWAPPER_CTRL_TXF_R_FE |
3543                  SWAPPER_CTRL_RXD_R_FE |
3544                  SWAPPER_CTRL_RXD_W_FE |
3545                  SWAPPER_CTRL_RXF_W_FE |
3546                  SWAPPER_CTRL_XMSI_FE |
3547                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3548         if (sp->intr_type == INTA)
3549                 val64 |= SWAPPER_CTRL_XMSI_SE;
3550         writeq(val64, &bar0->swapper_ctrl);
3551 #else
3552         /*
3553          * Initially we enable all bits to make it accessible by the
3554          * driver, then we selectively enable only those bits that
3555          * we want to set.
3556          */
3557         val64 |= (SWAPPER_CTRL_TXP_FE |
3558                  SWAPPER_CTRL_TXP_SE |
3559                  SWAPPER_CTRL_TXD_R_FE |
3560                  SWAPPER_CTRL_TXD_R_SE |
3561                  SWAPPER_CTRL_TXD_W_FE |
3562                  SWAPPER_CTRL_TXD_W_SE |
3563                  SWAPPER_CTRL_TXF_R_FE |
3564                  SWAPPER_CTRL_RXD_R_FE |
3565                  SWAPPER_CTRL_RXD_R_SE |
3566                  SWAPPER_CTRL_RXD_W_FE |
3567                  SWAPPER_CTRL_RXD_W_SE |
3568                  SWAPPER_CTRL_RXF_W_FE |
3569                  SWAPPER_CTRL_XMSI_FE |
3570                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3571         if (sp->intr_type == INTA)
3572                 val64 |= SWAPPER_CTRL_XMSI_SE;
3573         writeq(val64, &bar0->swapper_ctrl);
3574 #endif
3575         val64 = readq(&bar0->swapper_ctrl);
3576
3577         /*
3578          * Verifying if endian settings are accurate by reading a
3579          * feedback register.
3580          */
3581         val64 = readq(&bar0->pif_rd_swapper_fb);
3582         if (val64 != 0x0123456789ABCDEFULL) {
3583                 /* Endian settings are incorrect, calls for another dekko. */
3584                 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3585                           dev->name);
3586                 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3587                           (unsigned long long) val64);
3588                 return FAILURE;
3589         }
3590
3591         return SUCCESS;
3592 }
3593
3594 static int wait_for_msix_trans(nic_t *nic, int i)
3595 {
3596         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3597         u64 val64;
3598         int ret = 0, cnt = 0;
3599
3600         do {
3601                 val64 = readq(&bar0->xmsi_access);
3602                 if (!(val64 & BIT(15)))
3603                         break;