forcedeth: tx locking
[linux-3.10.git] / drivers / net / forcedeth.c
1 /*
2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3  *
4  * Note: This driver is a cleanroom reimplementation based on reverse
5  *      engineered documentation written by Carl-Daniel Hailfinger
6  *      and Andrew de Quincey.
7  *
8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9  * trademarks of NVIDIA Corporation in the United States and other
10  * countries.
11  *
12  * Copyright (C) 2003,4,5 Manfred Spraul
13  * Copyright (C) 2004 Andrew de Quincey (wol support)
14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
16  * Copyright (c) 2004,5,6 NVIDIA Corporation
17  *
18  * This program is free software; you can redistribute it and/or modify
19  * it under the terms of the GNU General Public License as published by
20  * the Free Software Foundation; either version 2 of the License, or
21  * (at your option) any later version.
22  *
23  * This program is distributed in the hope that it will be useful,
24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26  * GNU General Public License for more details.
27  *
28  * You should have received a copy of the GNU General Public License
29  * along with this program; if not, write to the Free Software
30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
31  *
32  * Changelog:
33  *      0.01: 05 Oct 2003: First release that compiles without warnings.
34  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
35  *                         Check all PCI BARs for the register window.
36  *                         udelay added to mii_rw.
37  *      0.03: 06 Oct 2003: Initialize dev->irq.
38  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
39  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
40  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
41  *                         irq mask updated
42  *      0.07: 14 Oct 2003: Further irq mask updates.
43  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
44  *                         added into irq handler, NULL check for drain_ring.
45  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
46  *                         requested interrupt sources.
47  *      0.10: 20 Oct 2003: First cleanup for release.
48  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
49  *                         MAC Address init fix, set_multicast cleanup.
50  *      0.12: 23 Oct 2003: Cleanups for release.
51  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
52  *                         Set link speed correctly. start rx before starting
53  *                         tx (nv_start_rx sets the link speed).
54  *      0.14: 25 Oct 2003: Nic dependant irq mask.
55  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
56  *                         open.
57  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
58  *                         increased to 1628 bytes.
59  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
60  *                         the tx length.
61  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
62  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
63  *                         addresses, really stop rx if already running
64  *                         in nv_start_rx, clean up a bit.
65  *      0.20: 07 Dec 2003: alloc fixes
66  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
67  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
68  *                         on close.
69  *      0.23: 26 Jan 2004: various small cleanups
70  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
71  *      0.25: 09 Mar 2004: wol support
72  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
73  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
74  *                         added CK804/MCP04 device IDs, code fixes
75  *                         for registers, link status and other minor fixes.
76  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
77  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
78  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
79  *                         into nv_close, otherwise reenabling for wol can
80  *                         cause DMA to kfree'd memory.
81  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
82  *                         capabilities.
83  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
84  *      0.33: 16 May 2005: Support for MCP51 added.
85  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
86  *      0.35: 26 Jun 2005: Support for MCP55 added.
87  *      0.36: 28 Jun 2005: Add jumbo frame support.
88  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
89  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
90  *                         per-packet flags.
91  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
92  *      0.40: 19 Jul 2005: Add support for mac address change.
93  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
94  *                         of nv_remove
95  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
96  *                         in the second (and later) nv_open call
97  *      0.43: 10 Aug 2005: Add support for tx checksum.
98  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
99  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
100  *      0.46: 20 Oct 2005: Add irq optimization modes.
101  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
102  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
103  *      0.49: 10 Dec 2005: Fix tso for large buffers.
104  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
105  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
106  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
107  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
108  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
109  *      0.55: 22 Mar 2006: Add flow control (pause frame).
110  *      0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
111  *      0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
112  *      0.58: 30 Oct 2006: Added support for sideband management unit.
113  *      0.59: 30 Oct 2006: Added support for recoverable error.
114  *
115  * Known bugs:
116  * We suspect that on some hardware no TX done interrupts are generated.
117  * This means recovery from netif_stop_queue only happens if the hw timer
118  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
119  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
120  * If your hardware reliably generates tx done interrupts, then you can remove
121  * DEV_NEED_TIMERIRQ from the driver_data flags.
122  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
123  * superfluous timer interrupts from the nic.
124  */
125 #ifdef CONFIG_FORCEDETH_NAPI
126 #define DRIVERNAPI "-NAPI"
127 #else
128 #define DRIVERNAPI
129 #endif
130 #define FORCEDETH_VERSION               "0.59"
131 #define DRV_NAME                        "forcedeth"
132
133 #include <linux/module.h>
134 #include <linux/types.h>
135 #include <linux/pci.h>
136 #include <linux/interrupt.h>
137 #include <linux/netdevice.h>
138 #include <linux/etherdevice.h>
139 #include <linux/delay.h>
140 #include <linux/spinlock.h>
141 #include <linux/ethtool.h>
142 #include <linux/timer.h>
143 #include <linux/skbuff.h>
144 #include <linux/mii.h>
145 #include <linux/random.h>
146 #include <linux/init.h>
147 #include <linux/if_vlan.h>
148 #include <linux/dma-mapping.h>
149
150 #include <asm/irq.h>
151 #include <asm/io.h>
152 #include <asm/uaccess.h>
153 #include <asm/system.h>
154
155 #if 0
156 #define dprintk                 printk
157 #else
158 #define dprintk(x...)           do { } while (0)
159 #endif
160
161
162 /*
163  * Hardware access:
164  */
165
166 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
167 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
168 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
169 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
170 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
171 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
172 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
173 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
174 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
175 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
176 #define DEV_HAS_STATISTICS      0x0400  /* device supports hw statistics */
177 #define DEV_HAS_TEST_EXTENDED   0x0800  /* device supports extended diagnostic test */
178 #define DEV_HAS_MGMT_UNIT       0x1000  /* device supports management unit */
179
180 enum {
181         NvRegIrqStatus = 0x000,
182 #define NVREG_IRQSTAT_MIIEVENT  0x040
183 #define NVREG_IRQSTAT_MASK              0x81ff
184         NvRegIrqMask = 0x004,
185 #define NVREG_IRQ_RX_ERROR              0x0001
186 #define NVREG_IRQ_RX                    0x0002
187 #define NVREG_IRQ_RX_NOBUF              0x0004
188 #define NVREG_IRQ_TX_ERR                0x0008
189 #define NVREG_IRQ_TX_OK                 0x0010
190 #define NVREG_IRQ_TIMER                 0x0020
191 #define NVREG_IRQ_LINK                  0x0040
192 #define NVREG_IRQ_RX_FORCED             0x0080
193 #define NVREG_IRQ_TX_FORCED             0x0100
194 #define NVREG_IRQ_RECOVER_ERROR         0x8000
195 #define NVREG_IRQMASK_THROUGHPUT        0x00df
196 #define NVREG_IRQMASK_CPU               0x0040
197 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
198 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
199 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
200
201 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
202                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
203                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
204
205         NvRegUnknownSetupReg6 = 0x008,
206 #define NVREG_UNKSETUP6_VAL             3
207
208 /*
209  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
210  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
211  */
212         NvRegPollingInterval = 0x00c,
213 #define NVREG_POLL_DEFAULT_THROUGHPUT   970
214 #define NVREG_POLL_DEFAULT_CPU  13
215         NvRegMSIMap0 = 0x020,
216         NvRegMSIMap1 = 0x024,
217         NvRegMSIIrqMask = 0x030,
218 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
219         NvRegMisc1 = 0x080,
220 #define NVREG_MISC1_PAUSE_TX    0x01
221 #define NVREG_MISC1_HD          0x02
222 #define NVREG_MISC1_FORCE       0x3b0f3c
223
224         NvRegMacReset = 0x3c,
225 #define NVREG_MAC_RESET_ASSERT  0x0F3
226         NvRegTransmitterControl = 0x084,
227 #define NVREG_XMITCTL_START     0x01
228 #define NVREG_XMITCTL_MGMT_ST   0x40000000
229 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
230 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
231 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
232 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
233 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
234 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
235 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
236 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
237 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
238         NvRegTransmitterStatus = 0x088,
239 #define NVREG_XMITSTAT_BUSY     0x01
240
241         NvRegPacketFilterFlags = 0x8c,
242 #define NVREG_PFF_PAUSE_RX      0x08
243 #define NVREG_PFF_ALWAYS        0x7F0000
244 #define NVREG_PFF_PROMISC       0x80
245 #define NVREG_PFF_MYADDR        0x20
246 #define NVREG_PFF_LOOPBACK      0x10
247
248         NvRegOffloadConfig = 0x90,
249 #define NVREG_OFFLOAD_HOMEPHY   0x601
250 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
251         NvRegReceiverControl = 0x094,
252 #define NVREG_RCVCTL_START      0x01
253 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
254         NvRegReceiverStatus = 0x98,
255 #define NVREG_RCVSTAT_BUSY      0x01
256
257         NvRegRandomSeed = 0x9c,
258 #define NVREG_RNDSEED_MASK      0x00ff
259 #define NVREG_RNDSEED_FORCE     0x7f00
260 #define NVREG_RNDSEED_FORCE2    0x2d00
261 #define NVREG_RNDSEED_FORCE3    0x7400
262
263         NvRegTxDeferral = 0xA0,
264 #define NVREG_TX_DEFERRAL_DEFAULT       0x15050f
265 #define NVREG_TX_DEFERRAL_RGMII_10_100  0x16070f
266 #define NVREG_TX_DEFERRAL_RGMII_1000    0x14050f
267         NvRegRxDeferral = 0xA4,
268 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
269         NvRegMacAddrA = 0xA8,
270         NvRegMacAddrB = 0xAC,
271         NvRegMulticastAddrA = 0xB0,
272 #define NVREG_MCASTADDRA_FORCE  0x01
273         NvRegMulticastAddrB = 0xB4,
274         NvRegMulticastMaskA = 0xB8,
275         NvRegMulticastMaskB = 0xBC,
276
277         NvRegPhyInterface = 0xC0,
278 #define PHY_RGMII               0x10000000
279
280         NvRegTxRingPhysAddr = 0x100,
281         NvRegRxRingPhysAddr = 0x104,
282         NvRegRingSizes = 0x108,
283 #define NVREG_RINGSZ_TXSHIFT 0
284 #define NVREG_RINGSZ_RXSHIFT 16
285         NvRegTransmitPoll = 0x10c,
286 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
287         NvRegLinkSpeed = 0x110,
288 #define NVREG_LINKSPEED_FORCE 0x10000
289 #define NVREG_LINKSPEED_10      1000
290 #define NVREG_LINKSPEED_100     100
291 #define NVREG_LINKSPEED_1000    50
292 #define NVREG_LINKSPEED_MASK    (0xFFF)
293         NvRegUnknownSetupReg5 = 0x130,
294 #define NVREG_UNKSETUP5_BIT31   (1<<31)
295         NvRegTxWatermark = 0x13c,
296 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
297 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
298 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
299         NvRegTxRxControl = 0x144,
300 #define NVREG_TXRXCTL_KICK      0x0001
301 #define NVREG_TXRXCTL_BIT1      0x0002
302 #define NVREG_TXRXCTL_BIT2      0x0004
303 #define NVREG_TXRXCTL_IDLE      0x0008
304 #define NVREG_TXRXCTL_RESET     0x0010
305 #define NVREG_TXRXCTL_RXCHECK   0x0400
306 #define NVREG_TXRXCTL_DESC_1    0
307 #define NVREG_TXRXCTL_DESC_2    0x002100
308 #define NVREG_TXRXCTL_DESC_3    0xc02200
309 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
310 #define NVREG_TXRXCTL_VLANINS   0x00080
311         NvRegTxRingPhysAddrHigh = 0x148,
312         NvRegRxRingPhysAddrHigh = 0x14C,
313         NvRegTxPauseFrame = 0x170,
314 #define NVREG_TX_PAUSEFRAME_DISABLE     0x1ff0080
315 #define NVREG_TX_PAUSEFRAME_ENABLE      0x0c00030
316         NvRegMIIStatus = 0x180,
317 #define NVREG_MIISTAT_ERROR             0x0001
318 #define NVREG_MIISTAT_LINKCHANGE        0x0008
319 #define NVREG_MIISTAT_MASK              0x000f
320 #define NVREG_MIISTAT_MASK2             0x000f
321         NvRegMIIMask = 0x184,
322 #define NVREG_MII_LINKCHANGE            0x0008
323
324         NvRegAdapterControl = 0x188,
325 #define NVREG_ADAPTCTL_START    0x02
326 #define NVREG_ADAPTCTL_LINKUP   0x04
327 #define NVREG_ADAPTCTL_PHYVALID 0x40000
328 #define NVREG_ADAPTCTL_RUNNING  0x100000
329 #define NVREG_ADAPTCTL_PHYSHIFT 24
330         NvRegMIISpeed = 0x18c,
331 #define NVREG_MIISPEED_BIT8     (1<<8)
332 #define NVREG_MIIDELAY  5
333         NvRegMIIControl = 0x190,
334 #define NVREG_MIICTL_INUSE      0x08000
335 #define NVREG_MIICTL_WRITE      0x00400
336 #define NVREG_MIICTL_ADDRSHIFT  5
337         NvRegMIIData = 0x194,
338         NvRegWakeUpFlags = 0x200,
339 #define NVREG_WAKEUPFLAGS_VAL           0x7770
340 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
341 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
342 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
343 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
344 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
345 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
346 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
347 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
348 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
349 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
350
351         NvRegPatternCRC = 0x204,
352         NvRegPatternMask = 0x208,
353         NvRegPowerCap = 0x268,
354 #define NVREG_POWERCAP_D3SUPP   (1<<30)
355 #define NVREG_POWERCAP_D2SUPP   (1<<26)
356 #define NVREG_POWERCAP_D1SUPP   (1<<25)
357         NvRegPowerState = 0x26c,
358 #define NVREG_POWERSTATE_POWEREDUP      0x8000
359 #define NVREG_POWERSTATE_VALID          0x0100
360 #define NVREG_POWERSTATE_MASK           0x0003
361 #define NVREG_POWERSTATE_D0             0x0000
362 #define NVREG_POWERSTATE_D1             0x0001
363 #define NVREG_POWERSTATE_D2             0x0002
364 #define NVREG_POWERSTATE_D3             0x0003
365         NvRegTxCnt = 0x280,
366         NvRegTxZeroReXmt = 0x284,
367         NvRegTxOneReXmt = 0x288,
368         NvRegTxManyReXmt = 0x28c,
369         NvRegTxLateCol = 0x290,
370         NvRegTxUnderflow = 0x294,
371         NvRegTxLossCarrier = 0x298,
372         NvRegTxExcessDef = 0x29c,
373         NvRegTxRetryErr = 0x2a0,
374         NvRegRxFrameErr = 0x2a4,
375         NvRegRxExtraByte = 0x2a8,
376         NvRegRxLateCol = 0x2ac,
377         NvRegRxRunt = 0x2b0,
378         NvRegRxFrameTooLong = 0x2b4,
379         NvRegRxOverflow = 0x2b8,
380         NvRegRxFCSErr = 0x2bc,
381         NvRegRxFrameAlignErr = 0x2c0,
382         NvRegRxLenErr = 0x2c4,
383         NvRegRxUnicast = 0x2c8,
384         NvRegRxMulticast = 0x2cc,
385         NvRegRxBroadcast = 0x2d0,
386         NvRegTxDef = 0x2d4,
387         NvRegTxFrame = 0x2d8,
388         NvRegRxCnt = 0x2dc,
389         NvRegTxPause = 0x2e0,
390         NvRegRxPause = 0x2e4,
391         NvRegRxDropFrame = 0x2e8,
392         NvRegVlanControl = 0x300,
393 #define NVREG_VLANCONTROL_ENABLE        0x2000
394         NvRegMSIXMap0 = 0x3e0,
395         NvRegMSIXMap1 = 0x3e4,
396         NvRegMSIXIrqStatus = 0x3f0,
397
398         NvRegPowerState2 = 0x600,
399 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
400 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
401 };
402
403 /* Big endian: should work, but is untested */
404 struct ring_desc {
405         __le32 buf;
406         __le32 flaglen;
407 };
408
409 struct ring_desc_ex {
410         __le32 bufhigh;
411         __le32 buflow;
412         __le32 txvlan;
413         __le32 flaglen;
414 };
415
416 union ring_type {
417         struct ring_desc* orig;
418         struct ring_desc_ex* ex;
419 };
420
421 #define FLAG_MASK_V1 0xffff0000
422 #define FLAG_MASK_V2 0xffffc000
423 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
424 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
425
426 #define NV_TX_LASTPACKET        (1<<16)
427 #define NV_TX_RETRYERROR        (1<<19)
428 #define NV_TX_FORCED_INTERRUPT  (1<<24)
429 #define NV_TX_DEFERRED          (1<<26)
430 #define NV_TX_CARRIERLOST       (1<<27)
431 #define NV_TX_LATECOLLISION     (1<<28)
432 #define NV_TX_UNDERFLOW         (1<<29)
433 #define NV_TX_ERROR             (1<<30)
434 #define NV_TX_VALID             (1<<31)
435
436 #define NV_TX2_LASTPACKET       (1<<29)
437 #define NV_TX2_RETRYERROR       (1<<18)
438 #define NV_TX2_FORCED_INTERRUPT (1<<30)
439 #define NV_TX2_DEFERRED         (1<<25)
440 #define NV_TX2_CARRIERLOST      (1<<26)
441 #define NV_TX2_LATECOLLISION    (1<<27)
442 #define NV_TX2_UNDERFLOW        (1<<28)
443 /* error and valid are the same for both */
444 #define NV_TX2_ERROR            (1<<30)
445 #define NV_TX2_VALID            (1<<31)
446 #define NV_TX2_TSO              (1<<28)
447 #define NV_TX2_TSO_SHIFT        14
448 #define NV_TX2_TSO_MAX_SHIFT    14
449 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
450 #define NV_TX2_CHECKSUM_L3      (1<<27)
451 #define NV_TX2_CHECKSUM_L4      (1<<26)
452
453 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
454
455 #define NV_RX_DESCRIPTORVALID   (1<<16)
456 #define NV_RX_MISSEDFRAME       (1<<17)
457 #define NV_RX_SUBSTRACT1        (1<<18)
458 #define NV_RX_ERROR1            (1<<23)
459 #define NV_RX_ERROR2            (1<<24)
460 #define NV_RX_ERROR3            (1<<25)
461 #define NV_RX_ERROR4            (1<<26)
462 #define NV_RX_CRCERR            (1<<27)
463 #define NV_RX_OVERFLOW          (1<<28)
464 #define NV_RX_FRAMINGERR        (1<<29)
465 #define NV_RX_ERROR             (1<<30)
466 #define NV_RX_AVAIL             (1<<31)
467
468 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
469 #define NV_RX2_CHECKSUMOK1      (0x10000000)
470 #define NV_RX2_CHECKSUMOK2      (0x14000000)
471 #define NV_RX2_CHECKSUMOK3      (0x18000000)
472 #define NV_RX2_DESCRIPTORVALID  (1<<29)
473 #define NV_RX2_SUBSTRACT1       (1<<25)
474 #define NV_RX2_ERROR1           (1<<18)
475 #define NV_RX2_ERROR2           (1<<19)
476 #define NV_RX2_ERROR3           (1<<20)
477 #define NV_RX2_ERROR4           (1<<21)
478 #define NV_RX2_CRCERR           (1<<22)
479 #define NV_RX2_OVERFLOW         (1<<23)
480 #define NV_RX2_FRAMINGERR       (1<<24)
481 /* error and avail are the same for both */
482 #define NV_RX2_ERROR            (1<<30)
483 #define NV_RX2_AVAIL            (1<<31)
484
485 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
486 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
487
488 /* Miscelaneous hardware related defines: */
489 #define NV_PCI_REGSZ_VER1       0x270
490 #define NV_PCI_REGSZ_VER2       0x604
491
492 /* various timeout delays: all in usec */
493 #define NV_TXRX_RESET_DELAY     4
494 #define NV_TXSTOP_DELAY1        10
495 #define NV_TXSTOP_DELAY1MAX     500000
496 #define NV_TXSTOP_DELAY2        100
497 #define NV_RXSTOP_DELAY1        10
498 #define NV_RXSTOP_DELAY1MAX     500000
499 #define NV_RXSTOP_DELAY2        100
500 #define NV_SETUP5_DELAY         5
501 #define NV_SETUP5_DELAYMAX      50000
502 #define NV_POWERUP_DELAY        5
503 #define NV_POWERUP_DELAYMAX     5000
504 #define NV_MIIBUSY_DELAY        50
505 #define NV_MIIPHY_DELAY 10
506 #define NV_MIIPHY_DELAYMAX      10000
507 #define NV_MAC_RESET_DELAY      64
508
509 #define NV_WAKEUPPATTERNS       5
510 #define NV_WAKEUPMASKENTRIES    4
511
512 /* General driver defaults */
513 #define NV_WATCHDOG_TIMEO       (5*HZ)
514
515 #define RX_RING_DEFAULT         128
516 #define TX_RING_DEFAULT         256
517 #define RX_RING_MIN             128
518 #define TX_RING_MIN             64
519 #define RING_MAX_DESC_VER_1     1024
520 #define RING_MAX_DESC_VER_2_3   16384
521 /*
522  * Difference between the get and put pointers for the tx ring.
523  * This is used to throttle the amount of data outstanding in the
524  * tx ring.
525  */
526 #define TX_LIMIT_DIFFERENCE     1
527
528 /* rx/tx mac addr + type + vlan + align + slack*/
529 #define NV_RX_HEADERS           (64)
530 /* even more slack. */
531 #define NV_RX_ALLOC_PAD         (64)
532
533 /* maximum mtu size */
534 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
535 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
536
537 #define OOM_REFILL      (1+HZ/20)
538 #define POLL_WAIT       (1+HZ/100)
539 #define LINK_TIMEOUT    (3*HZ)
540 #define STATS_INTERVAL  (10*HZ)
541
542 /*
543  * desc_ver values:
544  * The nic supports three different descriptor types:
545  * - DESC_VER_1: Original
546  * - DESC_VER_2: support for jumbo frames.
547  * - DESC_VER_3: 64-bit format.
548  */
549 #define DESC_VER_1      1
550 #define DESC_VER_2      2
551 #define DESC_VER_3      3
552
553 /* PHY defines */
554 #define PHY_OUI_MARVELL 0x5043
555 #define PHY_OUI_CICADA  0x03f1
556 #define PHYID1_OUI_MASK 0x03ff
557 #define PHYID1_OUI_SHFT 6
558 #define PHYID2_OUI_MASK 0xfc00
559 #define PHYID2_OUI_SHFT 10
560 #define PHYID2_MODEL_MASK               0x03f0
561 #define PHY_MODEL_MARVELL_E3016         0x220
562 #define PHY_MARVELL_E3016_INITMASK      0x0300
563 #define PHY_INIT1       0x0f000
564 #define PHY_INIT2       0x0e00
565 #define PHY_INIT3       0x01000
566 #define PHY_INIT4       0x0200
567 #define PHY_INIT5       0x0004
568 #define PHY_INIT6       0x02000
569 #define PHY_GIGABIT     0x0100
570
571 #define PHY_TIMEOUT     0x1
572 #define PHY_ERROR       0x2
573
574 #define PHY_100 0x1
575 #define PHY_1000        0x2
576 #define PHY_HALF        0x100
577
578 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
579 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
580 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
581 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
582 #define NV_PAUSEFRAME_RX_REQ     0x0010
583 #define NV_PAUSEFRAME_TX_REQ     0x0020
584 #define NV_PAUSEFRAME_AUTONEG    0x0040
585
586 /* MSI/MSI-X defines */
587 #define NV_MSI_X_MAX_VECTORS  8
588 #define NV_MSI_X_VECTORS_MASK 0x000f
589 #define NV_MSI_CAPABLE        0x0010
590 #define NV_MSI_X_CAPABLE      0x0020
591 #define NV_MSI_ENABLED        0x0040
592 #define NV_MSI_X_ENABLED      0x0080
593
594 #define NV_MSI_X_VECTOR_ALL   0x0
595 #define NV_MSI_X_VECTOR_RX    0x0
596 #define NV_MSI_X_VECTOR_TX    0x1
597 #define NV_MSI_X_VECTOR_OTHER 0x2
598
599 /* statistics */
600 struct nv_ethtool_str {
601         char name[ETH_GSTRING_LEN];
602 };
603
604 static const struct nv_ethtool_str nv_estats_str[] = {
605         { "tx_bytes" },
606         { "tx_zero_rexmt" },
607         { "tx_one_rexmt" },
608         { "tx_many_rexmt" },
609         { "tx_late_collision" },
610         { "tx_fifo_errors" },
611         { "tx_carrier_errors" },
612         { "tx_excess_deferral" },
613         { "tx_retry_error" },
614         { "tx_deferral" },
615         { "tx_packets" },
616         { "tx_pause" },
617         { "rx_frame_error" },
618         { "rx_extra_byte" },
619         { "rx_late_collision" },
620         { "rx_runt" },
621         { "rx_frame_too_long" },
622         { "rx_over_errors" },
623         { "rx_crc_errors" },
624         { "rx_frame_align_error" },
625         { "rx_length_error" },
626         { "rx_unicast" },
627         { "rx_multicast" },
628         { "rx_broadcast" },
629         { "rx_bytes" },
630         { "rx_pause" },
631         { "rx_drop_frame" },
632         { "rx_packets" },
633         { "rx_errors_total" }
634 };
635
636 struct nv_ethtool_stats {
637         u64 tx_bytes;
638         u64 tx_zero_rexmt;
639         u64 tx_one_rexmt;
640         u64 tx_many_rexmt;
641         u64 tx_late_collision;
642         u64 tx_fifo_errors;
643         u64 tx_carrier_errors;
644         u64 tx_excess_deferral;
645         u64 tx_retry_error;
646         u64 tx_deferral;
647         u64 tx_packets;
648         u64 tx_pause;
649         u64 rx_frame_error;
650         u64 rx_extra_byte;
651         u64 rx_late_collision;
652         u64 rx_runt;
653         u64 rx_frame_too_long;
654         u64 rx_over_errors;
655         u64 rx_crc_errors;
656         u64 rx_frame_align_error;
657         u64 rx_length_error;
658         u64 rx_unicast;
659         u64 rx_multicast;
660         u64 rx_broadcast;
661         u64 rx_bytes;
662         u64 rx_pause;
663         u64 rx_drop_frame;
664         u64 rx_packets;
665         u64 rx_errors_total;
666 };
667
668 /* diagnostics */
669 #define NV_TEST_COUNT_BASE 3
670 #define NV_TEST_COUNT_EXTENDED 4
671
672 static const struct nv_ethtool_str nv_etests_str[] = {
673         { "link      (online/offline)" },
674         { "register  (offline)       " },
675         { "interrupt (offline)       " },
676         { "loopback  (offline)       " }
677 };
678
679 struct register_test {
680         __le32 reg;
681         __le32 mask;
682 };
683
684 static const struct register_test nv_registers_test[] = {
685         { NvRegUnknownSetupReg6, 0x01 },
686         { NvRegMisc1, 0x03c },
687         { NvRegOffloadConfig, 0x03ff },
688         { NvRegMulticastAddrA, 0xffffffff },
689         { NvRegTxWatermark, 0x0ff },
690         { NvRegWakeUpFlags, 0x07777 },
691         { 0,0 }
692 };
693
694 struct nv_skb_map {
695         struct sk_buff *skb;
696         dma_addr_t dma;
697         unsigned int dma_len;
698 };
699
700 /*
701  * SMP locking:
702  * All hardware access under dev->priv->lock, except the performance
703  * critical parts:
704  * - rx is (pseudo-) lockless: it relies on the single-threading provided
705  *      by the arch code for interrupts.
706  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
707  *      needs dev->priv->lock :-(
708  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
709  */
710
711 /* in dev: base, irq */
712 struct fe_priv {
713         spinlock_t lock;
714
715         /* General data:
716          * Locking: spin_lock(&np->lock); */
717         struct net_device_stats stats;
718         struct nv_ethtool_stats estats;
719         int in_shutdown;
720         u32 linkspeed;
721         int duplex;
722         int autoneg;
723         int fixed_mode;
724         int phyaddr;
725         int wolenabled;
726         unsigned int phy_oui;
727         unsigned int phy_model;
728         u16 gigabit;
729         int intr_test;
730         int recover_error;
731
732         /* General data: RO fields */
733         dma_addr_t ring_addr;
734         struct pci_dev *pci_dev;
735         u32 orig_mac[2];
736         u32 irqmask;
737         u32 desc_ver;
738         u32 txrxctl_bits;
739         u32 vlanctl_bits;
740         u32 driver_data;
741         u32 register_size;
742         int rx_csum;
743         u32 mac_in_use;
744
745         void __iomem *base;
746
747         /* rx specific fields.
748          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
749          */
750         union ring_type get_rx, put_rx, first_rx, last_rx;
751         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
752         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
753         struct nv_skb_map *rx_skb;
754
755         union ring_type rx_ring;
756         unsigned int rx_buf_sz;
757         unsigned int pkt_limit;
758         struct timer_list oom_kick;
759         struct timer_list nic_poll;
760         struct timer_list stats_poll;
761         u32 nic_poll_irq;
762         int rx_ring_size;
763
764         /* media detection workaround.
765          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
766          */
767         int need_linktimer;
768         unsigned long link_timeout;
769         /*
770          * tx specific fields.
771          */
772         union ring_type get_tx, put_tx, first_tx, last_tx;
773         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
774         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
775         struct nv_skb_map *tx_skb;
776
777         union ring_type tx_ring;
778         u32 tx_flags;
779         int tx_ring_size;
780         int tx_limit_start;
781         int tx_limit_stop;
782
783         /* vlan fields */
784         struct vlan_group *vlangrp;
785
786         /* msi/msi-x fields */
787         u32 msi_flags;
788         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
789
790         /* flow control */
791         u32 pause_flags;
792 };
793
794 /*
795  * Maximum number of loops until we assume that a bit in the irq mask
796  * is stuck. Overridable with module param.
797  */
798 static int max_interrupt_work = 5;
799
800 /*
801  * Optimization can be either throuput mode or cpu mode
802  *
803  * Throughput Mode: Every tx and rx packet will generate an interrupt.
804  * CPU Mode: Interrupts are controlled by a timer.
805  */
806 enum {
807         NV_OPTIMIZATION_MODE_THROUGHPUT,
808         NV_OPTIMIZATION_MODE_CPU
809 };
810 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
811
812 /*
813  * Poll interval for timer irq
814  *
815  * This interval determines how frequent an interrupt is generated.
816  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
817  * Min = 0, and Max = 65535
818  */
819 static int poll_interval = -1;
820
821 /*
822  * MSI interrupts
823  */
824 enum {
825         NV_MSI_INT_DISABLED,
826         NV_MSI_INT_ENABLED
827 };
828 static int msi = NV_MSI_INT_ENABLED;
829
830 /*
831  * MSIX interrupts
832  */
833 enum {
834         NV_MSIX_INT_DISABLED,
835         NV_MSIX_INT_ENABLED
836 };
837 static int msix = NV_MSIX_INT_ENABLED;
838
839 /*
840  * DMA 64bit
841  */
842 enum {
843         NV_DMA_64BIT_DISABLED,
844         NV_DMA_64BIT_ENABLED
845 };
846 static int dma_64bit = NV_DMA_64BIT_ENABLED;
847
848 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
849 {
850         return netdev_priv(dev);
851 }
852
853 static inline u8 __iomem *get_hwbase(struct net_device *dev)
854 {
855         return ((struct fe_priv *)netdev_priv(dev))->base;
856 }
857
858 static inline void pci_push(u8 __iomem *base)
859 {
860         /* force out pending posted writes */
861         readl(base);
862 }
863
864 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
865 {
866         return le32_to_cpu(prd->flaglen)
867                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
868 }
869
870 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
871 {
872         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
873 }
874
875 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
876                                 int delay, int delaymax, const char *msg)
877 {
878         u8 __iomem *base = get_hwbase(dev);
879
880         pci_push(base);
881         do {
882                 udelay(delay);
883                 delaymax -= delay;
884                 if (delaymax < 0) {
885                         if (msg)
886                                 printk(msg);
887                         return 1;
888                 }
889         } while ((readl(base + offset) & mask) != target);
890         return 0;
891 }
892
893 #define NV_SETUP_RX_RING 0x01
894 #define NV_SETUP_TX_RING 0x02
895
896 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
897 {
898         struct fe_priv *np = get_nvpriv(dev);
899         u8 __iomem *base = get_hwbase(dev);
900
901         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
902                 if (rxtx_flags & NV_SETUP_RX_RING) {
903                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
904                 }
905                 if (rxtx_flags & NV_SETUP_TX_RING) {
906                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
907                 }
908         } else {
909                 if (rxtx_flags & NV_SETUP_RX_RING) {
910                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
911                         writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
912                 }
913                 if (rxtx_flags & NV_SETUP_TX_RING) {
914                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
915                         writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
916                 }
917         }
918 }
919
920 static void free_rings(struct net_device *dev)
921 {
922         struct fe_priv *np = get_nvpriv(dev);
923
924         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
925                 if (np->rx_ring.orig)
926                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
927                                             np->rx_ring.orig, np->ring_addr);
928         } else {
929                 if (np->rx_ring.ex)
930                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
931                                             np->rx_ring.ex, np->ring_addr);
932         }
933         if (np->rx_skb)
934                 kfree(np->rx_skb);
935         if (np->tx_skb)
936                 kfree(np->tx_skb);
937 }
938
939 static int using_multi_irqs(struct net_device *dev)
940 {
941         struct fe_priv *np = get_nvpriv(dev);
942
943         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
944             ((np->msi_flags & NV_MSI_X_ENABLED) &&
945              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
946                 return 0;
947         else
948                 return 1;
949 }
950
951 static void nv_enable_irq(struct net_device *dev)
952 {
953         struct fe_priv *np = get_nvpriv(dev);
954
955         if (!using_multi_irqs(dev)) {
956                 if (np->msi_flags & NV_MSI_X_ENABLED)
957                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
958                 else
959                         enable_irq(dev->irq);
960         } else {
961                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
962                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
963                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
964         }
965 }
966
967 static void nv_disable_irq(struct net_device *dev)
968 {
969         struct fe_priv *np = get_nvpriv(dev);
970
971         if (!using_multi_irqs(dev)) {
972                 if (np->msi_flags & NV_MSI_X_ENABLED)
973                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
974                 else
975                         disable_irq(dev->irq);
976         } else {
977                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
978                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
979                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
980         }
981 }
982
983 /* In MSIX mode, a write to irqmask behaves as XOR */
984 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
985 {
986         u8 __iomem *base = get_hwbase(dev);
987
988         writel(mask, base + NvRegIrqMask);
989 }
990
991 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
992 {
993         struct fe_priv *np = get_nvpriv(dev);
994         u8 __iomem *base = get_hwbase(dev);
995
996         if (np->msi_flags & NV_MSI_X_ENABLED) {
997                 writel(mask, base + NvRegIrqMask);
998         } else {
999                 if (np->msi_flags & NV_MSI_ENABLED)
1000                         writel(0, base + NvRegMSIIrqMask);
1001                 writel(0, base + NvRegIrqMask);
1002         }
1003 }
1004
1005 #define MII_READ        (-1)
1006 /* mii_rw: read/write a register on the PHY.
1007  *
1008  * Caller must guarantee serialization
1009  */
1010 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1011 {
1012         u8 __iomem *base = get_hwbase(dev);
1013         u32 reg;
1014         int retval;
1015
1016         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1017
1018         reg = readl(base + NvRegMIIControl);
1019         if (reg & NVREG_MIICTL_INUSE) {
1020                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1021                 udelay(NV_MIIBUSY_DELAY);
1022         }
1023
1024         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1025         if (value != MII_READ) {
1026                 writel(value, base + NvRegMIIData);
1027                 reg |= NVREG_MIICTL_WRITE;
1028         }
1029         writel(reg, base + NvRegMIIControl);
1030
1031         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1032                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1033                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1034                                 dev->name, miireg, addr);
1035                 retval = -1;
1036         } else if (value != MII_READ) {
1037                 /* it was a write operation - fewer failures are detectable */
1038                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1039                                 dev->name, value, miireg, addr);
1040                 retval = 0;
1041         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1042                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1043                                 dev->name, miireg, addr);
1044                 retval = -1;
1045         } else {
1046                 retval = readl(base + NvRegMIIData);
1047                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1048                                 dev->name, miireg, addr, retval);
1049         }
1050
1051         return retval;
1052 }
1053
1054 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1055 {
1056         struct fe_priv *np = netdev_priv(dev);
1057         u32 miicontrol;
1058         unsigned int tries = 0;
1059
1060         miicontrol = BMCR_RESET | bmcr_setup;
1061         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1062                 return -1;
1063         }
1064
1065         /* wait for 500ms */
1066         msleep(500);
1067
1068         /* must wait till reset is deasserted */
1069         while (miicontrol & BMCR_RESET) {
1070                 msleep(10);
1071                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1072                 /* FIXME: 100 tries seem excessive */
1073                 if (tries++ > 100)
1074                         return -1;
1075         }
1076         return 0;
1077 }
1078
1079 static int phy_init(struct net_device *dev)
1080 {
1081         struct fe_priv *np = get_nvpriv(dev);
1082         u8 __iomem *base = get_hwbase(dev);
1083         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1084
1085         /* phy errata for E3016 phy */
1086         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1087                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1088                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1089                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1090                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1091                         return PHY_ERROR;
1092                 }
1093         }
1094
1095         /* set advertise register */
1096         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1097         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1098         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1099                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1100                 return PHY_ERROR;
1101         }
1102
1103         /* get phy interface type */
1104         phyinterface = readl(base + NvRegPhyInterface);
1105
1106         /* see if gigabit phy */
1107         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1108         if (mii_status & PHY_GIGABIT) {
1109                 np->gigabit = PHY_GIGABIT;
1110                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1111                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1112                 if (phyinterface & PHY_RGMII)
1113                         mii_control_1000 |= ADVERTISE_1000FULL;
1114                 else
1115                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1116
1117                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1118                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1119                         return PHY_ERROR;
1120                 }
1121         }
1122         else
1123                 np->gigabit = 0;
1124
1125         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1126         mii_control |= BMCR_ANENABLE;
1127
1128         /* reset the phy
1129          * (certain phys need bmcr to be setup with reset)
1130          */
1131         if (phy_reset(dev, mii_control)) {
1132                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1133                 return PHY_ERROR;
1134         }
1135
1136         /* phy vendor specific configuration */
1137         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1138                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1139                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1140                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1141                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1142                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1143                         return PHY_ERROR;
1144                 }
1145                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1146                 phy_reserved |= PHY_INIT5;
1147                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1148                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1149                         return PHY_ERROR;
1150                 }
1151         }
1152         if (np->phy_oui == PHY_OUI_CICADA) {
1153                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1154                 phy_reserved |= PHY_INIT6;
1155                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1156                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1157                         return PHY_ERROR;
1158                 }
1159         }
1160         /* some phys clear out pause advertisment on reset, set it back */
1161         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1162
1163         /* restart auto negotiation */
1164         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1165         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1166         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1167                 return PHY_ERROR;
1168         }
1169
1170         return 0;
1171 }
1172
1173 static void nv_start_rx(struct net_device *dev)
1174 {
1175         struct fe_priv *np = netdev_priv(dev);
1176         u8 __iomem *base = get_hwbase(dev);
1177         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1178
1179         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1180         /* Already running? Stop it. */
1181         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1182                 rx_ctrl &= ~NVREG_RCVCTL_START;
1183                 writel(rx_ctrl, base + NvRegReceiverControl);
1184                 pci_push(base);
1185         }
1186         writel(np->linkspeed, base + NvRegLinkSpeed);
1187         pci_push(base);
1188         rx_ctrl |= NVREG_RCVCTL_START;
1189         if (np->mac_in_use)
1190                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1191         writel(rx_ctrl, base + NvRegReceiverControl);
1192         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1193                                 dev->name, np->duplex, np->linkspeed);
1194         pci_push(base);
1195 }
1196
1197 static void nv_stop_rx(struct net_device *dev)
1198 {
1199         struct fe_priv *np = netdev_priv(dev);
1200         u8 __iomem *base = get_hwbase(dev);
1201         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1202
1203         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1204         if (!np->mac_in_use)
1205                 rx_ctrl &= ~NVREG_RCVCTL_START;
1206         else
1207                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1208         writel(rx_ctrl, base + NvRegReceiverControl);
1209         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1210                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1211                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1212
1213         udelay(NV_RXSTOP_DELAY2);
1214         if (!np->mac_in_use)
1215                 writel(0, base + NvRegLinkSpeed);
1216 }
1217
1218 static void nv_start_tx(struct net_device *dev)
1219 {
1220         struct fe_priv *np = netdev_priv(dev);
1221         u8 __iomem *base = get_hwbase(dev);
1222         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1223
1224         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1225         tx_ctrl |= NVREG_XMITCTL_START;
1226         if (np->mac_in_use)
1227                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1228         writel(tx_ctrl, base + NvRegTransmitterControl);
1229         pci_push(base);
1230 }
1231
1232 static void nv_stop_tx(struct net_device *dev)
1233 {
1234         struct fe_priv *np = netdev_priv(dev);
1235         u8 __iomem *base = get_hwbase(dev);
1236         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1237
1238         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1239         if (!np->mac_in_use)
1240                 tx_ctrl &= ~NVREG_XMITCTL_START;
1241         else
1242                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1243         writel(tx_ctrl, base + NvRegTransmitterControl);
1244         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1245                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1246                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1247
1248         udelay(NV_TXSTOP_DELAY2);
1249         if (!np->mac_in_use)
1250                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1251                        base + NvRegTransmitPoll);
1252 }
1253
1254 static void nv_txrx_reset(struct net_device *dev)
1255 {
1256         struct fe_priv *np = netdev_priv(dev);
1257         u8 __iomem *base = get_hwbase(dev);
1258
1259         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1260         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1261         pci_push(base);
1262         udelay(NV_TXRX_RESET_DELAY);
1263         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1264         pci_push(base);
1265 }
1266
1267 static void nv_mac_reset(struct net_device *dev)
1268 {
1269         struct fe_priv *np = netdev_priv(dev);
1270         u8 __iomem *base = get_hwbase(dev);
1271
1272         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1273         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1274         pci_push(base);
1275         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1276         pci_push(base);
1277         udelay(NV_MAC_RESET_DELAY);
1278         writel(0, base + NvRegMacReset);
1279         pci_push(base);
1280         udelay(NV_MAC_RESET_DELAY);
1281         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1282         pci_push(base);
1283 }
1284
1285 /*
1286  * nv_get_stats: dev->get_stats function
1287  * Get latest stats value from the nic.
1288  * Called with read_lock(&dev_base_lock) held for read -
1289  * only synchronized against unregister_netdevice.
1290  */
1291 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1292 {
1293         struct fe_priv *np = netdev_priv(dev);
1294
1295         /* It seems that the nic always generates interrupts and doesn't
1296          * accumulate errors internally. Thus the current values in np->stats
1297          * are already up to date.
1298          */
1299         return &np->stats;
1300 }
1301
1302 /*
1303  * nv_alloc_rx: fill rx ring entries.
1304  * Return 1 if the allocations for the skbs failed and the
1305  * rx engine is without Available descriptors
1306  */
1307 static int nv_alloc_rx(struct net_device *dev)
1308 {
1309         struct fe_priv *np = netdev_priv(dev);
1310         union ring_type less_rx;
1311
1312         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1313                 less_rx.orig = np->get_rx.orig;
1314                 if (less_rx.orig-- == np->first_rx.orig)
1315                         less_rx.orig = np->last_rx.orig;
1316         } else {
1317                 less_rx.ex = np->get_rx.ex;
1318                 if (less_rx.ex-- == np->first_rx.ex)
1319                         less_rx.ex = np->last_rx.ex;
1320         }
1321
1322         while (1) {
1323                 struct sk_buff *skb;
1324
1325                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1326                         if (np->put_rx.orig == less_rx.orig)
1327                                 break;
1328                 } else {
1329                         if (np->put_rx.ex == less_rx.ex)
1330                                 break;
1331                 }
1332
1333                 if (np->put_rx_ctx->skb == NULL) {
1334
1335                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1336                         if (!skb)
1337                                 return 1;
1338
1339                         skb->dev = dev;
1340                         np->put_rx_ctx->skb = skb;
1341                 } else {
1342                         skb = np->put_rx_ctx->skb;
1343                 }
1344                 np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data,
1345                                         skb->end-skb->data, PCI_DMA_FROMDEVICE);
1346                 np->put_rx_ctx->dma_len = skb->end-skb->data;
1347                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1348                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1349                         wmb();
1350                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1351                         if (np->put_rx.orig++ == np->last_rx.orig)
1352                                 np->put_rx.orig = np->first_rx.orig;
1353                 } else {
1354                         np->put_rx.ex->bufhigh = cpu_to_le64(np->put_rx_ctx->dma) >> 32;
1355                         np->put_rx.ex->buflow = cpu_to_le64(np->put_rx_ctx->dma) & 0x0FFFFFFFF;
1356                         wmb();
1357                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1358                         if (np->put_rx.ex++ == np->last_rx.ex)
1359                                 np->put_rx.ex = np->first_rx.ex;
1360                 }
1361                 if (np->put_rx_ctx++ == np->last_rx_ctx)
1362                         np->put_rx_ctx = np->first_rx_ctx;
1363         }
1364         return 0;
1365 }
1366
1367 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1368 #ifdef CONFIG_FORCEDETH_NAPI
1369 static void nv_do_rx_refill(unsigned long data)
1370 {
1371         struct net_device *dev = (struct net_device *) data;
1372
1373         /* Just reschedule NAPI rx processing */
1374         netif_rx_schedule(dev);
1375 }
1376 #else
1377 static void nv_do_rx_refill(unsigned long data)
1378 {
1379         struct net_device *dev = (struct net_device *) data;
1380         struct fe_priv *np = netdev_priv(dev);
1381
1382         if (!using_multi_irqs(dev)) {
1383                 if (np->msi_flags & NV_MSI_X_ENABLED)
1384                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1385                 else
1386                         disable_irq(dev->irq);
1387         } else {
1388                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1389         }
1390         if (nv_alloc_rx(dev)) {
1391                 spin_lock_irq(&np->lock);
1392                 if (!np->in_shutdown)
1393                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1394                 spin_unlock_irq(&np->lock);
1395         }
1396         if (!using_multi_irqs(dev)) {
1397                 if (np->msi_flags & NV_MSI_X_ENABLED)
1398                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1399                 else
1400                         enable_irq(dev->irq);
1401         } else {
1402                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1403         }
1404 }
1405 #endif
1406
1407 static void nv_init_rx(struct net_device *dev)
1408 {
1409         struct fe_priv *np = netdev_priv(dev);
1410         int i;
1411         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1412         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1413                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1414         else
1415                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1416         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1417         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1418
1419         for (i = 0; i < np->rx_ring_size; i++) {
1420                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1421                         np->rx_ring.orig[i].flaglen = 0;
1422                         np->rx_ring.orig[i].buf = 0;
1423                 } else {
1424                         np->rx_ring.ex[i].flaglen = 0;
1425                         np->rx_ring.ex[i].txvlan = 0;
1426                         np->rx_ring.ex[i].bufhigh = 0;
1427                         np->rx_ring.ex[i].buflow = 0;
1428                 }
1429                 np->rx_skb[i].skb = NULL;
1430                 np->rx_skb[i].dma = 0;
1431         }
1432 }
1433
1434 static void nv_init_tx(struct net_device *dev)
1435 {
1436         struct fe_priv *np = netdev_priv(dev);
1437         int i;
1438         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1439         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1440                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1441         else
1442                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1443         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1444         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1445
1446         for (i = 0; i < np->tx_ring_size; i++) {
1447                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1448                         np->tx_ring.orig[i].flaglen = 0;
1449                         np->tx_ring.orig[i].buf = 0;
1450                 } else {
1451                         np->tx_ring.ex[i].flaglen = 0;
1452                         np->tx_ring.ex[i].txvlan = 0;
1453                         np->tx_ring.ex[i].bufhigh = 0;
1454                         np->tx_ring.ex[i].buflow = 0;
1455                 }
1456                 np->tx_skb[i].skb = NULL;
1457                 np->tx_skb[i].dma = 0;
1458         }
1459 }
1460
1461 static int nv_init_ring(struct net_device *dev)
1462 {
1463         nv_init_tx(dev);
1464         nv_init_rx(dev);
1465         return nv_alloc_rx(dev);
1466 }
1467
1468 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1469 {
1470         struct fe_priv *np = netdev_priv(dev);
1471
1472         if (tx_skb->dma) {
1473                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1474                                tx_skb->dma_len,
1475                                PCI_DMA_TODEVICE);
1476                 tx_skb->dma = 0;
1477         }
1478         if (tx_skb->skb) {
1479                 dev_kfree_skb_any(tx_skb->skb);
1480                 tx_skb->skb = NULL;
1481                 return 1;
1482         } else {
1483                 return 0;
1484         }
1485 }
1486
1487 static void nv_drain_tx(struct net_device *dev)
1488 {
1489         struct fe_priv *np = netdev_priv(dev);
1490         unsigned int i;
1491
1492         for (i = 0; i < np->tx_ring_size; i++) {
1493                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1494                         np->tx_ring.orig[i].flaglen = 0;
1495                         np->tx_ring.orig[i].buf = 0;
1496                 } else {
1497                         np->tx_ring.ex[i].flaglen = 0;
1498                         np->tx_ring.ex[i].txvlan = 0;
1499                         np->tx_ring.ex[i].bufhigh = 0;
1500                         np->tx_ring.ex[i].buflow = 0;
1501                 }
1502                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1503                         np->stats.tx_dropped++;
1504         }
1505 }
1506
1507 static void nv_drain_rx(struct net_device *dev)
1508 {
1509         struct fe_priv *np = netdev_priv(dev);
1510         int i;
1511
1512         for (i = 0; i < np->rx_ring_size; i++) {
1513                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1514                         np->rx_ring.orig[i].flaglen = 0;
1515                         np->rx_ring.orig[i].buf = 0;
1516                 } else {
1517                         np->rx_ring.ex[i].flaglen = 0;
1518                         np->rx_ring.ex[i].txvlan = 0;
1519                         np->rx_ring.ex[i].bufhigh = 0;
1520                         np->rx_ring.ex[i].buflow = 0;
1521                 }
1522                 wmb();
1523                 if (np->rx_skb[i].skb) {
1524                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1525                                                 np->rx_skb[i].skb->end-np->rx_skb[i].skb->data,
1526                                                 PCI_DMA_FROMDEVICE);
1527                         dev_kfree_skb(np->rx_skb[i].skb);
1528                         np->rx_skb[i].skb = NULL;
1529                 }
1530         }
1531 }
1532
1533 static void drain_ring(struct net_device *dev)
1534 {
1535         nv_drain_tx(dev);
1536         nv_drain_rx(dev);
1537 }
1538
1539 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1540 {
1541         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1542 }
1543
1544 /*
1545  * nv_start_xmit: dev->hard_start_xmit function
1546  * Called with netif_tx_lock held.
1547  */
1548 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1549 {
1550         struct fe_priv *np = netdev_priv(dev);
1551         u32 tx_flags = 0;
1552         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1553         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1554         unsigned int i;
1555         u32 offset = 0;
1556         u32 bcnt;
1557         u32 size = skb->len-skb->data_len;
1558         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1559         u32 empty_slots;
1560         u32 tx_flags_vlan = 0;
1561         union ring_type put_tx;
1562         union ring_type start_tx;
1563         union ring_type prev_tx;
1564         struct nv_skb_map* prev_tx_ctx;
1565
1566         /* add fragments to entries count */
1567         for (i = 0; i < fragments; i++) {
1568                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1569                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1570         }
1571
1572         empty_slots = nv_get_empty_tx_slots(np);
1573         if ((empty_slots - np->tx_limit_stop) <= entries) {
1574                 spin_lock_irq(&np->lock);
1575                 netif_stop_queue(dev);
1576                 spin_unlock_irq(&np->lock);
1577                 return NETDEV_TX_BUSY;
1578         }
1579
1580         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1581                 start_tx.orig = put_tx.orig = np->put_tx.orig;
1582         else
1583                 start_tx.ex = put_tx.ex = np->put_tx.ex;
1584
1585         /* setup the header buffer */
1586         do {
1587                 prev_tx = put_tx;
1588                 prev_tx_ctx = np->put_tx_ctx;
1589                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1590                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1591                                                 PCI_DMA_TODEVICE);
1592                 np->put_tx_ctx->dma_len = bcnt;
1593                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1594                         put_tx.orig->buf = cpu_to_le32(np->put_tx_ctx->dma);
1595                         put_tx.orig->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1596                 } else {
1597                         put_tx.ex->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1598                         put_tx.ex->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1599                         put_tx.ex->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1600                 }
1601                 tx_flags = np->tx_flags;
1602                 offset += bcnt;
1603                 size -= bcnt;
1604                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1605                         if (put_tx.orig++ == np->last_tx.orig)
1606                                 put_tx.orig = np->first_tx.orig;
1607                 } else {
1608                         if (put_tx.ex++ == np->last_tx.ex)
1609                                 put_tx.ex = np->first_tx.ex;
1610                 }
1611                 if (np->put_tx_ctx++ == np->last_tx_ctx)
1612                         np->put_tx_ctx = np->first_tx_ctx;
1613         } while (size);
1614
1615         /* setup the fragments */
1616         for (i = 0; i < fragments; i++) {
1617                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1618                 u32 size = frag->size;
1619                 offset = 0;
1620
1621                 do {
1622                         prev_tx = put_tx;
1623                         prev_tx_ctx = np->put_tx_ctx;
1624                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1625                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1626                                                            PCI_DMA_TODEVICE);
1627                         np->put_tx_ctx->dma_len = bcnt;
1628
1629                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1630                                 put_tx.orig->buf = cpu_to_le32(np->put_tx_ctx->dma);
1631                                 put_tx.orig->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1632                         } else {
1633                                 put_tx.ex->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1634                                 put_tx.ex->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1635                                 put_tx.ex->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1636                         }
1637                         offset += bcnt;
1638                         size -= bcnt;
1639                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1640                                 if (put_tx.orig++ == np->last_tx.orig)
1641                                         put_tx.orig = np->first_tx.orig;
1642                         } else {
1643                                 if (put_tx.ex++ == np->last_tx.ex)
1644                                         put_tx.ex = np->first_tx.ex;
1645                         }
1646                         if (np->put_tx_ctx++ == np->last_tx_ctx)
1647                                 np->put_tx_ctx = np->first_tx_ctx;
1648                 } while (size);
1649         }
1650
1651         /* set last fragment flag  */
1652         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1653                 prev_tx.orig->flaglen |= cpu_to_le32(tx_flags_extra);
1654         else
1655                 prev_tx.ex->flaglen |= cpu_to_le32(tx_flags_extra);
1656
1657         /* save skb in this slot's context area */
1658         prev_tx_ctx->skb = skb;
1659
1660         if (skb_is_gso(skb))
1661                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1662         else
1663                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1664                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1665
1666         /* vlan tag */
1667         if (np->vlangrp && vlan_tx_tag_present(skb)) {
1668                 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1669         }
1670
1671         spin_lock_irq(&np->lock);
1672
1673         /* set tx flags */
1674         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1675                 start_tx.orig->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1676                 np->put_tx.orig = put_tx.orig;
1677         } else {
1678                 start_tx.ex->txvlan = cpu_to_le32(tx_flags_vlan);
1679                 start_tx.ex->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1680                 np->put_tx.ex = put_tx.ex;
1681         }
1682
1683         spin_unlock_irq(&np->lock);
1684
1685         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
1686                 dev->name, entries, tx_flags_extra);
1687         {
1688                 int j;
1689                 for (j=0; j<64; j++) {
1690                         if ((j%16) == 0)
1691                                 dprintk("\n%03x:", j);
1692                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1693                 }
1694                 dprintk("\n");
1695         }
1696
1697         dev->trans_start = jiffies;
1698         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1699         pci_push(get_hwbase(dev));
1700         return NETDEV_TX_OK;
1701 }
1702
1703 /*
1704  * nv_tx_done: check for completed packets, release the skbs.
1705  *
1706  * Caller must own np->lock.
1707  */
1708 static void nv_tx_done(struct net_device *dev)
1709 {
1710         struct fe_priv *np = netdev_priv(dev);
1711         u32 flags;
1712         struct sk_buff *skb;
1713
1714         while (1) {
1715                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1716                         if (np->get_tx.orig == np->put_tx.orig)
1717                                 break;
1718                         flags = le32_to_cpu(np->get_tx.orig->flaglen);
1719                 } else {
1720                         if (np->get_tx.ex == np->put_tx.ex)
1721                                 break;
1722                         flags = le32_to_cpu(np->get_tx.ex->flaglen);
1723                 }
1724
1725                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
1726                                         dev->name, flags);
1727                 if (flags & NV_TX_VALID)
1728                         break;
1729                 if (np->desc_ver == DESC_VER_1) {
1730                         if (flags & NV_TX_LASTPACKET) {
1731                                 skb = np->get_tx_ctx->skb;
1732                                 if (flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1733                                              NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1734                                         if (flags & NV_TX_UNDERFLOW)
1735                                                 np->stats.tx_fifo_errors++;
1736                                         if (flags & NV_TX_CARRIERLOST)
1737                                                 np->stats.tx_carrier_errors++;
1738                                         np->stats.tx_errors++;
1739                                 } else {
1740                                         np->stats.tx_packets++;
1741                                         np->stats.tx_bytes += skb->len;
1742                                 }
1743                         }
1744                 } else {
1745                         if (flags & NV_TX2_LASTPACKET) {
1746                                 skb = np->get_tx_ctx->skb;
1747                                 if (flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1748                                              NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1749                                         if (flags & NV_TX2_UNDERFLOW)
1750                                                 np->stats.tx_fifo_errors++;
1751                                         if (flags & NV_TX2_CARRIERLOST)
1752                                                 np->stats.tx_carrier_errors++;
1753                                         np->stats.tx_errors++;
1754                                 } else {
1755                                         np->stats.tx_packets++;
1756                                         np->stats.tx_bytes += skb->len;
1757                                 }
1758                         }
1759                 }
1760                 nv_release_txskb(dev, np->get_tx_ctx);
1761                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1762                         if (np->get_tx.orig++ == np->last_tx.orig)
1763                                 np->get_tx.orig = np->first_tx.orig;
1764                 } else {
1765                         if (np->get_tx.ex++ == np->last_tx.ex)
1766                                 np->get_tx.ex = np->first_tx.ex;
1767                 }
1768                 if (np->get_tx_ctx++ == np->last_tx_ctx)
1769                         np->get_tx_ctx = np->first_tx_ctx;
1770         }
1771         if (nv_get_empty_tx_slots(np) > np->tx_limit_start)
1772                 netif_wake_queue(dev);
1773 }
1774
1775 /*
1776  * nv_tx_timeout: dev->tx_timeout function
1777  * Called with netif_tx_lock held.
1778  */
1779 static void nv_tx_timeout(struct net_device *dev)
1780 {
1781         struct fe_priv *np = netdev_priv(dev);
1782         u8 __iomem *base = get_hwbase(dev);
1783         u32 status;
1784
1785         if (np->msi_flags & NV_MSI_X_ENABLED)
1786                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1787         else
1788                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1789
1790         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1791
1792         {
1793                 int i;
1794
1795                 printk(KERN_INFO "%s: Ring at %lx\n",
1796                        dev->name, (unsigned long)np->ring_addr);
1797                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1798                 for (i=0;i<=np->register_size;i+= 32) {
1799                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1800                                         i,
1801                                         readl(base + i + 0), readl(base + i + 4),
1802                                         readl(base + i + 8), readl(base + i + 12),
1803                                         readl(base + i + 16), readl(base + i + 20),
1804                                         readl(base + i + 24), readl(base + i + 28));
1805                 }
1806                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1807                 for (i=0;i<np->tx_ring_size;i+= 4) {
1808                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1809                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1810                                        i,
1811                                        le32_to_cpu(np->tx_ring.orig[i].buf),
1812                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
1813                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
1814                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
1815                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
1816                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
1817                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
1818                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
1819                         } else {
1820                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1821                                        i,
1822                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
1823                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
1824                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
1825                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
1826                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
1827                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
1828                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
1829                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
1830                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
1831                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
1832                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
1833                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
1834                         }
1835                 }
1836         }
1837
1838         spin_lock_irq(&np->lock);
1839
1840         /* 1) stop tx engine */
1841         nv_stop_tx(dev);
1842
1843         /* 2) check that the packets were not sent already: */
1844         nv_tx_done(dev);
1845
1846         /* 3) if there are dead entries: clear everything */
1847         if (np->get_tx_ctx != np->put_tx_ctx) {
1848                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1849                 nv_drain_tx(dev);
1850                 nv_init_tx(dev);
1851                 setup_hw_rings(dev, NV_SETUP_TX_RING);
1852                 netif_wake_queue(dev);
1853         }
1854
1855         /* 4) restart tx engine */
1856         nv_start_tx(dev);
1857         spin_unlock_irq(&np->lock);
1858 }
1859
1860 /*
1861  * Called when the nic notices a mismatch between the actual data len on the
1862  * wire and the len indicated in the 802 header
1863  */
1864 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1865 {
1866         int hdrlen;     /* length of the 802 header */
1867         int protolen;   /* length as stored in the proto field */
1868
1869         /* 1) calculate len according to header */
1870         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
1871                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1872                 hdrlen = VLAN_HLEN;
1873         } else {
1874                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1875                 hdrlen = ETH_HLEN;
1876         }
1877         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1878                                 dev->name, datalen, protolen, hdrlen);
1879         if (protolen > ETH_DATA_LEN)
1880                 return datalen; /* Value in proto field not a len, no checks possible */
1881
1882         protolen += hdrlen;
1883         /* consistency checks: */
1884         if (datalen > ETH_ZLEN) {
1885                 if (datalen >= protolen) {
1886                         /* more data on wire than in 802 header, trim of
1887                          * additional data.
1888                          */
1889                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1890                                         dev->name, protolen);
1891                         return protolen;
1892                 } else {
1893                         /* less data on wire than mentioned in header.
1894                          * Discard the packet.
1895                          */
1896                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1897                                         dev->name);
1898                         return -1;
1899                 }
1900         } else {
1901                 /* short packet. Accept only if 802 values are also short */
1902                 if (protolen > ETH_ZLEN) {
1903                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1904                                         dev->name);
1905                         return -1;
1906                 }
1907                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1908                                 dev->name, datalen);
1909                 return datalen;
1910         }
1911 }
1912
1913 static int nv_rx_process(struct net_device *dev, int limit)
1914 {
1915         struct fe_priv *np = netdev_priv(dev);
1916         u32 flags;
1917         u32 vlanflags = 0;
1918         int count;
1919
1920         for (count = 0; count < limit; ++count) {
1921                 struct sk_buff *skb;
1922                 int len;
1923
1924                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1925                         if (np->get_rx.orig == np->put_rx.orig)
1926                                 break;  /* we scanned the whole ring - do not continue */
1927                         flags = le32_to_cpu(np->get_rx.orig->flaglen);
1928                         len = nv_descr_getlength(np->get_rx.orig, np->desc_ver);
1929                 } else {
1930                         if (np->get_rx.ex == np->put_rx.ex)
1931                                 break;  /* we scanned the whole ring - do not continue */
1932                         flags = le32_to_cpu(np->get_rx.ex->flaglen);
1933                         len = nv_descr_getlength_ex(np->get_rx.ex, np->desc_ver);
1934                         vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
1935                 }
1936
1937                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
1938                                         dev->name, flags);
1939
1940                 if (flags & NV_RX_AVAIL)
1941                         break;  /* still owned by hardware, */
1942
1943                 /*
1944                  * the packet is for us - immediately tear down the pci mapping.
1945                  * TODO: check if a prefetch of the first cacheline improves
1946                  * the performance.
1947                  */
1948                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
1949                                 np->get_rx_ctx->dma_len,
1950                                 PCI_DMA_FROMDEVICE);
1951
1952                 {
1953                         int j;
1954                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
1955                         for (j=0; j<64; j++) {
1956                                 if ((j%16) == 0)
1957                                         dprintk("\n%03x:", j);
1958                                 dprintk(" %02x", ((unsigned char*)np->get_rx_ctx->skb->data)[j]);
1959                         }
1960                         dprintk("\n");
1961                 }
1962                 /* look at what we actually got: */
1963                 if (np->desc_ver == DESC_VER_1) {
1964                         if (!(flags & NV_RX_DESCRIPTORVALID))
1965                                 goto next_pkt;
1966
1967                         if (flags & NV_RX_ERROR) {
1968                                 if (flags & NV_RX_MISSEDFRAME) {
1969                                         np->stats.rx_missed_errors++;
1970                                         np->stats.rx_errors++;
1971                                         goto next_pkt;
1972                                 }
1973                                 if (flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1974                                         np->stats.rx_errors++;
1975                                         goto next_pkt;
1976                                 }
1977                                 if (flags & NV_RX_CRCERR) {
1978                                         np->stats.rx_crc_errors++;
1979                                         np->stats.rx_errors++;
1980                                         goto next_pkt;
1981                                 }
1982                                 if (flags & NV_RX_OVERFLOW) {
1983                                         np->stats.rx_over_errors++;
1984                                         np->stats.rx_errors++;
1985                                         goto next_pkt;
1986                                 }
1987                                 if (flags & NV_RX_ERROR4) {
1988                                         len = nv_getlen(dev, np->get_rx_ctx->skb->data, len);
1989                                         if (len < 0) {
1990                                                 np->stats.rx_errors++;
1991                                                 goto next_pkt;
1992                                         }
1993                                 }
1994                                 /* framing errors are soft errors. */
1995                                 if (flags & NV_RX_FRAMINGERR) {
1996                                         if (flags & NV_RX_SUBSTRACT1) {
1997                                                 len--;
1998                                         }
1999                                 }
2000                         }
2001                 } else {
2002                         if (!(flags & NV_RX2_DESCRIPTORVALID))
2003                                 goto next_pkt;
2004
2005                         if (flags & NV_RX2_ERROR) {
2006                                 if (flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
2007                                         np->stats.rx_errors++;
2008                                         goto next_pkt;
2009                                 }
2010                                 if (flags & NV_RX2_CRCERR) {
2011                                         np->stats.rx_crc_errors++;
2012                                         np->stats.rx_errors++;
2013                                         goto next_pkt;
2014                                 }
2015                                 if (flags & NV_RX2_OVERFLOW) {
2016                                         np->stats.rx_over_errors++;
2017                                         np->stats.rx_errors++;
2018                                         goto next_pkt;
2019                                 }
2020                                 if (flags & NV_RX2_ERROR4) {
2021                                         len = nv_getlen(dev, np->get_rx_ctx->skb->data, len);
2022                                         if (len < 0) {
2023                                                 np->stats.rx_errors++;
2024                                                 goto next_pkt;
2025                                         }
2026                                 }
2027                                 /* framing errors are soft errors */
2028                                 if (flags & NV_RX2_FRAMINGERR) {
2029                                         if (flags & NV_RX2_SUBSTRACT1) {
2030                                                 len--;
2031                                         }
2032                                 }
2033                         }
2034                         if (np->rx_csum) {
2035                                 flags &= NV_RX2_CHECKSUMMASK;
2036                                 if (flags == NV_RX2_CHECKSUMOK1 ||
2037                                     flags == NV_RX2_CHECKSUMOK2 ||
2038                                     flags == NV_RX2_CHECKSUMOK3) {
2039                                         dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
2040                                         np->get_rx_ctx->skb->ip_summed = CHECKSUM_UNNECESSARY;
2041                                 } else {
2042                                         dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
2043                                 }
2044                         }
2045                 }
2046                 /* got a valid packet - forward it to the network core */
2047                 skb = np->get_rx_ctx->skb;
2048                 np->get_rx_ctx->skb = NULL;
2049
2050                 skb_put(skb, len);
2051                 skb->protocol = eth_type_trans(skb, dev);
2052                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2053                                         dev->name, len, skb->protocol);
2054 #ifdef CONFIG_FORCEDETH_NAPI
2055                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
2056                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2057                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2058                 else
2059                         netif_receive_skb(skb);
2060 #else
2061                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
2062                         vlan_hwaccel_rx(skb, np->vlangrp,
2063                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2064                 else
2065                         netif_rx(skb);
2066 #endif
2067                 dev->last_rx = jiffies;
2068                 np->stats.rx_packets++;
2069                 np->stats.rx_bytes += len;
2070 next_pkt:
2071                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2072                         if (np->get_rx.orig++ == np->last_rx.orig)
2073                                 np->get_rx.orig = np->first_rx.orig;
2074                 } else {
2075                         if (np->get_rx.ex++ == np->last_rx.ex)
2076                                 np->get_rx.ex = np->first_rx.ex;
2077                 }
2078                 if (np->get_rx_ctx++ == np->last_rx_ctx)
2079                         np->get_rx_ctx = np->first_rx_ctx;
2080         }
2081
2082         return count;
2083 }
2084
2085 static void set_bufsize(struct net_device *dev)
2086 {
2087         struct fe_priv *np = netdev_priv(dev);
2088
2089         if (dev->mtu <= ETH_DATA_LEN)
2090                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2091         else
2092                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2093 }
2094
2095 /*
2096  * nv_change_mtu: dev->change_mtu function
2097  * Called with dev_base_lock held for read.
2098  */
2099 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2100 {
2101         struct fe_priv *np = netdev_priv(dev);
2102         int old_mtu;
2103
2104         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2105                 return -EINVAL;
2106
2107         old_mtu = dev->mtu;
2108         dev->mtu = new_mtu;
2109
2110         /* return early if the buffer sizes will not change */
2111         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2112                 return 0;
2113         if (old_mtu == new_mtu)
2114                 return 0;
2115
2116         /* synchronized against open : rtnl_lock() held by caller */
2117         if (netif_running(dev)) {
2118                 u8 __iomem *base = get_hwbase(dev);
2119                 /*
2120                  * It seems that the nic preloads valid ring entries into an
2121                  * internal buffer. The procedure for flushing everything is
2122                  * guessed, there is probably a simpler approach.
2123                  * Changing the MTU is a rare event, it shouldn't matter.
2124                  */
2125                 nv_disable_irq(dev);
2126                 netif_tx_lock_bh(dev);
2127                 spin_lock(&np->lock);
2128                 /* stop engines */
2129                 nv_stop_rx(dev);
2130                 nv_stop_tx(dev);
2131                 nv_txrx_reset(dev);
2132                 /* drain rx queue */
2133                 nv_drain_rx(dev);
2134                 nv_drain_tx(dev);
2135                 /* reinit driver view of the rx queue */
2136                 set_bufsize(dev);
2137                 if (nv_init_ring(dev)) {
2138                         if (!np->in_shutdown)
2139                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2140                 }
2141                 /* reinit nic view of the rx queue */
2142                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2143                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2144                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2145                         base + NvRegRingSizes);
2146                 pci_push(base);
2147                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2148                 pci_push(base);
2149
2150                 /* restart rx engine */
2151                 nv_start_rx(dev);
2152                 nv_start_tx(dev);
2153                 spin_unlock(&np->lock);
2154                 netif_tx_unlock_bh(dev);
2155                 nv_enable_irq(dev);
2156         }
2157         return 0;
2158 }
2159
2160 static void nv_copy_mac_to_hw(struct net_device *dev)
2161 {
2162         u8 __iomem *base = get_hwbase(dev);
2163         u32 mac[2];
2164
2165         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2166                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2167         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2168
2169         writel(mac[0], base + NvRegMacAddrA);
2170         writel(mac[1], base + NvRegMacAddrB);
2171 }
2172
2173 /*
2174  * nv_set_mac_address: dev->set_mac_address function
2175  * Called with rtnl_lock() held.
2176  */
2177 static int nv_set_mac_address(struct net_device *dev, void *addr)
2178 {
2179         struct fe_priv *np = netdev_priv(dev);
2180         struct sockaddr *macaddr = (struct sockaddr*)addr;
2181
2182         if (!is_valid_ether_addr(macaddr->sa_data))
2183                 return -EADDRNOTAVAIL;
2184
2185         /* synchronized against open : rtnl_lock() held by caller */
2186         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2187
2188         if (netif_running(dev)) {
2189                 netif_tx_lock_bh(dev);
2190                 spin_lock_irq(&np->lock);
2191
2192                 /* stop rx engine */
2193                 nv_stop_rx(dev);
2194
2195                 /* set mac address */
2196                 nv_copy_mac_to_hw(dev);
2197
2198                 /* restart rx engine */
2199                 nv_start_rx(dev);
2200                 spin_unlock_irq(&np->lock);
2201                 netif_tx_unlock_bh(dev);
2202         } else {
2203                 nv_copy_mac_to_hw(dev);
2204         }
2205         return 0;
2206 }
2207
2208 /*
2209  * nv_set_multicast: dev->set_multicast function
2210  * Called with netif_tx_lock held.
2211  */
2212 static void nv_set_multicast(struct net_device *dev)
2213 {
2214         struct fe_priv *np = netdev_priv(dev);
2215         u8 __iomem *base = get_hwbase(dev);
2216         u32 addr[2];
2217         u32 mask[2];
2218         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2219
2220         memset(addr, 0, sizeof(addr));
2221         memset(mask, 0, sizeof(mask));
2222
2223         if (dev->flags & IFF_PROMISC) {
2224                 pff |= NVREG_PFF_PROMISC;
2225         } else {
2226                 pff |= NVREG_PFF_MYADDR;
2227
2228                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2229                         u32 alwaysOff[2];
2230                         u32 alwaysOn[2];
2231
2232                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2233                         if (dev->flags & IFF_ALLMULTI) {
2234                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2235                         } else {
2236                                 struct dev_mc_list *walk;
2237
2238                                 walk = dev->mc_list;
2239                                 while (walk != NULL) {
2240                                         u32 a, b;
2241                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2242                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2243                                         alwaysOn[0] &= a;
2244                                         alwaysOff[0] &= ~a;
2245                                         alwaysOn[1] &= b;
2246                                         alwaysOff[1] &= ~b;
2247                                         walk = walk->next;
2248                                 }
2249                         }
2250                         addr[0] = alwaysOn[0];
2251                         addr[1] = alwaysOn[1];
2252                         mask[0] = alwaysOn[0] | alwaysOff[0];
2253                         mask[1] = alwaysOn[1] | alwaysOff[1];
2254                 }
2255         }
2256         addr[0] |= NVREG_MCASTADDRA_FORCE;
2257         pff |= NVREG_PFF_ALWAYS;
2258         spin_lock_irq(&np->lock);
2259         nv_stop_rx(dev);
2260         writel(addr[0], base + NvRegMulticastAddrA);
2261         writel(addr[1], base + NvRegMulticastAddrB);
2262         writel(mask[0], base + NvRegMulticastMaskA);
2263         writel(mask[1], base + NvRegMulticastMaskB);
2264         writel(pff, base + NvRegPacketFilterFlags);
2265         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2266                 dev->name);
2267         nv_start_rx(dev);
2268         spin_unlock_irq(&np->lock);
2269 }
2270
2271 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2272 {
2273         struct fe_priv *np = netdev_priv(dev);
2274         u8 __iomem *base = get_hwbase(dev);
2275
2276         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2277
2278         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2279                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2280                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2281                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2282                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2283                 } else {
2284                         writel(pff, base + NvRegPacketFilterFlags);
2285                 }
2286         }
2287         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2288                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2289                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2290                         writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
2291                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2292                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2293                 } else {
2294                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2295                         writel(regmisc, base + NvRegMisc1);
2296                 }
2297         }
2298 }
2299
2300 /**
2301  * nv_update_linkspeed: Setup the MAC according to the link partner
2302  * @dev: Network device to be configured
2303  *
2304  * The function queries the PHY and checks if there is a link partner.
2305  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2306  * set to 10 MBit HD.
2307  *
2308  * The function returns 0 if there is no link partner and 1 if there is
2309  * a good link partner.
2310  */
2311 static int nv_update_linkspeed(struct net_device *dev)
2312 {
2313         struct fe_priv *np = netdev_priv(dev);
2314         u8 __iomem *base = get_hwbase(dev);
2315         int adv = 0;
2316         int lpa = 0;
2317         int adv_lpa, adv_pause, lpa_pause;
2318         int newls = np->linkspeed;
2319         int newdup = np->duplex;
2320         int mii_status;
2321         int retval = 0;
2322         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2323
2324         /* BMSR_LSTATUS is latched, read it twice:
2325          * we want the current value.
2326          */
2327         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2328         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2329
2330         if (!(mii_status & BMSR_LSTATUS)) {
2331                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2332                                 dev->name);
2333                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2334                 newdup = 0;
2335                 retval = 0;
2336                 goto set_speed;
2337         }
2338
2339         if (np->autoneg == 0) {
2340                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2341                                 dev->name, np->fixed_mode);
2342                 if (np->fixed_mode & LPA_100FULL) {
2343                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2344                         newdup = 1;
2345                 } else if (np->fixed_mode & LPA_100HALF) {
2346                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2347                         newdup = 0;
2348                 } else if (np->fixed_mode & LPA_10FULL) {
2349                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2350                         newdup = 1;
2351                 } else {
2352                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2353                         newdup = 0;
2354                 }
2355                 retval = 1;
2356                 goto set_speed;
2357         }
2358         /* check auto negotiation is complete */
2359         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2360                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2361                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2362                 newdup = 0;
2363                 retval = 0;
2364                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2365                 goto set_speed;
2366         }
2367
2368         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2369         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2370         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2371                                 dev->name, adv, lpa);
2372
2373         retval = 1;
2374         if (np->gigabit == PHY_GIGABIT) {
2375                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2376                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2377
2378                 if ((control_1000 & ADVERTISE_1000FULL) &&
2379                         (status_1000 & LPA_1000FULL)) {
2380                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2381                                 dev->name);
2382                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2383                         newdup = 1;
2384                         goto set_speed;
2385                 }
2386         }
2387
2388         /* FIXME: handle parallel detection properly */
2389         adv_lpa = lpa & adv;
2390         if (adv_lpa & LPA_100FULL) {
2391                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2392                 newdup = 1;
2393         } else if (adv_lpa & LPA_100HALF) {
2394                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2395                 newdup = 0;
2396         } else if (adv_lpa & LPA_10FULL) {
2397                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2398                 newdup = 1;
2399         } else if (adv_lpa & LPA_10HALF) {
2400                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2401                 newdup = 0;
2402         } else {
2403                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2404                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2405                 newdup = 0;
2406         }
2407
2408 set_speed:
2409         if (np->duplex == newdup && np->linkspeed == newls)
2410                 return retval;
2411
2412         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2413                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2414
2415         np->duplex = newdup;
2416         np->linkspeed = newls;
2417
2418         if (np->gigabit == PHY_GIGABIT) {
2419                 phyreg = readl(base + NvRegRandomSeed);
2420                 phyreg &= ~(0x3FF00);
2421                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2422                         phyreg |= NVREG_RNDSEED_FORCE3;
2423                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2424                         phyreg |= NVREG_RNDSEED_FORCE2;
2425                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2426                         phyreg |= NVREG_RNDSEED_FORCE;
2427                 writel(phyreg, base + NvRegRandomSeed);
2428         }
2429
2430         phyreg = readl(base + NvRegPhyInterface);
2431         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2432         if (np->duplex == 0)
2433                 phyreg |= PHY_HALF;
2434         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2435                 phyreg |= PHY_100;
2436         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2437                 phyreg |= PHY_1000;
2438         writel(phyreg, base + NvRegPhyInterface);
2439
2440         if (phyreg & PHY_RGMII) {
2441                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2442                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2443                 else
2444                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2445         } else {
2446                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2447         }
2448         writel(txreg, base + NvRegTxDeferral);
2449
2450         if (np->desc_ver == DESC_VER_1) {
2451                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2452         } else {
2453                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2454                         txreg = NVREG_TX_WM_DESC2_3_1000;
2455                 else
2456                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2457         }
2458         writel(txreg, base + NvRegTxWatermark);
2459
2460         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2461                 base + NvRegMisc1);
2462         pci_push(base);
2463         writel(np->linkspeed, base + NvRegLinkSpeed);
2464         pci_push(base);
2465
2466         pause_flags = 0;
2467         /* setup pause frame */
2468         if (np->duplex != 0) {
2469                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2470                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2471                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2472
2473                         switch (adv_pause) {
2474                         case ADVERTISE_PAUSE_CAP:
2475                                 if (lpa_pause & LPA_PAUSE_CAP) {
2476                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2477                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2478                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2479                                 }
2480                                 break;
2481                         case ADVERTISE_PAUSE_ASYM:
2482                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2483                                 {
2484                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2485                                 }
2486                                 break;
2487                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2488                                 if (lpa_pause & LPA_PAUSE_CAP)
2489                                 {
2490                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
2491                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2492                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2493                                 }
2494                                 if (lpa_pause == LPA_PAUSE_ASYM)
2495                                 {
2496                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2497                                 }
2498                                 break;
2499                         }
2500                 } else {
2501                         pause_flags = np->pause_flags;
2502                 }
2503         }
2504         nv_update_pause(dev, pause_flags);
2505
2506         return retval;
2507 }
2508
2509 static void nv_linkchange(struct net_device *dev)
2510 {
2511         if (nv_update_linkspeed(dev)) {
2512                 if (!netif_carrier_ok(dev)) {
2513                         netif_carrier_on(dev);
2514                         printk(KERN_INFO "%s: link up.\n", dev->name);
2515                         nv_start_rx(dev);
2516                 }
2517         } else {
2518                 if (netif_carrier_ok(dev)) {
2519                         netif_carrier_off(dev);
2520                         printk(KERN_INFO "%s: link down.\n", dev->name);
2521                         nv_stop_rx(dev);
2522                 }
2523         }
2524 }
2525
2526 static void nv_link_irq(struct net_device *dev)
2527 {
2528         u8 __iomem *base = get_hwbase(dev);
2529         u32 miistat;
2530
2531         miistat = readl(base + NvRegMIIStatus);
2532         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2533         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2534
2535         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2536                 nv_linkchange(dev);
2537         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2538 }
2539
2540 static irqreturn_t nv_nic_irq(int foo, void *data)
2541 {
2542         struct net_device *dev = (struct net_device *) data;
2543         struct fe_priv *np = netdev_priv(dev);
2544         u8 __iomem *base = get_hwbase(dev);
2545         u32 events;
2546         int i;
2547
2548         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2549
2550         for (i=0; ; i++) {
2551                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2552                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2553                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2554                 } else {
2555                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2556                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2557                 }
2558                 pci_push(base);
2559                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2560                 if (!(events & np->irqmask))
2561                         break;
2562
2563                 spin_lock(&np->lock);
2564                 nv_tx_done(dev);
2565                 spin_unlock(&np->lock);
2566
2567                 if (events & NVREG_IRQ_LINK) {
2568                         spin_lock(&np->lock);
2569                         nv_link_irq(dev);
2570                         spin_unlock(&np->lock);
2571                 }
2572                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2573                         spin_lock(&np->lock);
2574                         nv_linkchange(dev);
2575                         spin_unlock(&np->lock);
2576                         np->link_timeout = jiffies + LINK_TIMEOUT;
2577                 }
2578                 if (events & (NVREG_IRQ_TX_ERR)) {
2579                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2580                                                 dev->name, events);
2581                 }
2582                 if (events & (NVREG_IRQ_UNKNOWN)) {
2583                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2584                                                 dev->name, events);
2585                 }
2586                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
2587                         spin_lock(&np->lock);
2588                         /* disable interrupts on the nic */
2589                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2590                                 writel(0, base + NvRegIrqMask);
2591                         else
2592                                 writel(np->irqmask, base + NvRegIrqMask);
2593                         pci_push(base);
2594
2595                         if (!np->in_shutdown) {
2596                                 np->nic_poll_irq = np->irqmask;
2597                                 np->recover_error = 1;
2598                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2599                         }
2600                         spin_unlock(&np->lock);
2601                         break;
2602                 }
2603 #ifdef CONFIG_FORCEDETH_NAPI
2604                 if (events & NVREG_IRQ_RX_ALL) {
2605                         netif_rx_schedule(dev);
2606
2607                         /* Disable furthur receive irq's */
2608                         spin_lock(&np->lock);
2609                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
2610
2611                         if (np->msi_flags & NV_MSI_X_ENABLED)
2612                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2613                         else
2614                                 writel(np->irqmask, base + NvRegIrqMask);
2615                         spin_unlock(&np->lock);
2616                 }
2617 #else
2618                 nv_rx_process(dev, dev->weight);
2619                 if (nv_alloc_rx(dev)) {
2620                         spin_lock(&np->lock);
2621                         if (!np->in_shutdown)
2622                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2623                         spin_unlock(&np->lock);
2624                 }
2625 #endif
2626                 if (i > max_interrupt_work) {
2627                         spin_lock(&np->lock);
2628                         /* disable interrupts on the nic */
2629                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2630                                 writel(0, base + NvRegIrqMask);
2631                         else
2632                                 writel(np->irqmask, base + NvRegIrqMask);
2633                         pci_push(base);
2634
2635                         if (!np->in_shutdown) {
2636                                 np->nic_poll_irq = np->irqmask;
2637                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2638                         }
2639                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2640                         spin_unlock(&np->lock);
2641                         break;
2642                 }
2643
2644         }
2645         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2646
2647         return IRQ_RETVAL(i);
2648 }
2649
2650 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
2651 {
2652         struct net_device *dev = (struct net_device *) data;
2653         struct fe_priv *np = netdev_priv(dev);
2654         u8 __iomem *base = get_hwbase(dev);
2655         u32 events;
2656         int i;
2657         unsigned long flags;
2658
2659         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
2660
2661         for (i=0; ; i++) {
2662                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2663                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2664                 pci_push(base);
2665                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2666                 if (!(events & np->irqmask))
2667                         break;
2668
2669                 spin_lock_irqsave(&np->lock, flags);
2670                 nv_tx_done(dev);
2671                 spin_unlock_irqrestore(&np->lock, flags);
2672
2673                 if (events & (NVREG_IRQ_TX_ERR)) {
2674                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2675                                                 dev->name, events);
2676                 }
2677                 if (i > max_interrupt_work) {
2678                         spin_lock_irqsave(&np->lock, flags);
2679                         /* disable interrupts on the nic */
2680                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
2681                         pci_push(base);
2682
2683                         if (!np->in_shutdown) {
2684                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
2685                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2686                         }
2687                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
2688                         spin_unlock_irqrestore(&np->lock, flags);
2689                         break;
2690                 }
2691
2692         }
2693         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
2694
2695         return IRQ_RETVAL(i);
2696 }
2697
2698 #ifdef CONFIG_FORCEDETH_NAPI
2699 static int nv_napi_poll(struct net_device *dev, int *budget)
2700 {
2701         int pkts, limit = min(*budget, dev->quota);
2702         struct fe_priv *np = netdev_priv(dev);
2703         u8 __iomem *base = get_hwbase(dev);
2704         unsigned long flags;
2705
2706         pkts = nv_rx_process(dev, limit);
2707
2708         if (nv_alloc_rx(dev)) {
2709                 spin_lock_irqsave(&np->lock, flags);
2710                 if (!np->in_shutdown)
2711                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2712                 spin_unlock_irqrestore(&np->lock, flags);
2713         }
2714
2715         if (pkts < limit) {
2716                 /* all done, no more packets present */
2717                 netif_rx_complete(dev);
2718
2719                 /* re-enable receive interrupts */
2720                 spin_lock_irqsave(&np->lock, flags);
2721
2722                 np->irqmask |= NVREG_IRQ_RX_ALL;
2723                 if (np->msi_flags & NV_MSI_X_ENABLED)
2724                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2725                 else
2726                         writel(np->irqmask, base + NvRegIrqMask);
2727
2728                 spin_unlock_irqrestore(&np->lock, flags);
2729                 return 0;
2730         } else {
2731                 /* used up our quantum, so reschedule */
2732                 dev->quota -= pkts;
2733                 *budget -= pkts;
2734                 return 1;
2735         }
2736 }
2737 #endif
2738
2739 #ifdef CONFIG_FORCEDETH_NAPI
2740 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
2741 {
2742         struct net_device *dev = (struct net_device *) data;
2743         u8 __iomem *base = get_hwbase(dev);
2744         u32 events;
2745
2746         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2747         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2748
2749         if (events) {
2750                 netif_rx_schedule(dev);
2751                 /* disable receive interrupts on the nic */
2752                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2753                 pci_push(base);
2754         }
2755         return IRQ_HANDLED;
2756 }
2757 #else
2758 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
2759 {
2760         struct net_device *dev = (struct net_device *) data;
2761         struct fe_priv *np = netdev_priv(dev);
2762         u8 __iomem *base = get_hwbase(dev);
2763         u32 events;
2764         int i;
2765         unsigned long flags;
2766
2767         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
2768
2769         for (i=0; ; i++) {
2770                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2771                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2772                 pci_push(base);
2773                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
2774                 if (!(events & np->irqmask))
2775                         break;
2776
2777                 nv_rx_process(dev, dev->weight);
2778                 if (nv_alloc_rx(dev)) {
2779                         spin_lock_irqsave(&np->lock, flags);
2780                         if (!np->in_shutdown)
2781                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2782                         spin_unlock_irqrestore(&np->lock, flags);
2783                 }
2784
2785                 if (i > max_interrupt_work) {
2786                         spin_lock_irqsave(&np->lock, flags);
2787                         /* disable interrupts on the nic */
2788                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2789                         pci_push(base);
2790
2791                         if (!np->in_shutdown) {
2792                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
2793                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2794                         }
2795                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
2796                         spin_unlock_irqrestore(&np->lock, flags);
2797                         break;
2798                 }
2799         }
2800         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
2801
2802         return IRQ_RETVAL(i);
2803 }
2804 #endif
2805
2806 static irqreturn_t nv_nic_irq_other(int foo, void *data)
2807 {
2808         struct net_device *dev = (struct net_device *) data;
2809         struct fe_priv *np = netdev_priv(dev);
2810         u8 __iomem *base = get_hwbase(dev);
2811         u32 events;
2812         int i;
2813         unsigned long flags;
2814
2815         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
2816
2817         for (i=0; ; i++) {
2818                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
2819                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
2820                 pci_push(base);
2821                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2822                 if (!(events & np->irqmask))
2823                         break;
2824
2825                 if (events & NVREG_IRQ_LINK) {
2826                         spin_lock_irqsave(&np->lock, flags);
2827                         nv_link_irq(dev);
2828                         spin_unlock_irqrestore(&np->lock, flags);
2829                 }
2830                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2831                         spin_lock_irqsave(&np->lock, flags);
2832                         nv_linkchange(dev);
2833                         spin_unlock_irqrestore(&np->lock, flags);
2834                         np->link_timeout = jiffies + LINK_TIMEOUT;
2835                 }
2836                 if (events & NVREG_IRQ_RECOVER_ERROR) {
2837                         spin_lock_irq(&np->lock);
2838                         /* disable interrupts on the nic */
2839                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2840                         pci_push(base);
2841
2842                         if (!np->in_shutdown) {
2843                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2844                                 np->recover_error = 1;
2845                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2846                         }
2847                         spin_unlock_irq(&np->lock);
2848                         break;
2849                 }
2850                 if (events & (NVREG_IRQ_UNKNOWN)) {
2851                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2852                                                 dev->name, events);
2853                 }
2854                 if (i > max_interrupt_work) {
2855                         spin_lock_irqsave(&np->lock, flags);
2856                         /* disable interrupts on the nic */
2857                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2858                         pci_push(base);
2859
2860                         if (!np->in_shutdown) {
2861                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2862                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2863                         }
2864                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
2865                         spin_unlock_irqrestore(&np->lock, flags);
2866                         break;
2867                 }
2868
2869         }
2870         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
2871
2872         return IRQ_RETVAL(i);
2873 }
2874
2875 static irqreturn_t nv_nic_irq_test(int foo, void *data)
2876 {
2877         struct net_device *dev = (struct net_device *) data;
2878         struct fe_priv *np = netdev_priv(dev);
2879         u8 __iomem *base = get_hwbase(dev);
2880         u32 events;
2881
2882         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
2883
2884         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2885                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2886                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
2887         } else {
2888                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2889                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
2890         }
2891         pci_push(base);
2892         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2893         if (!(events & NVREG_IRQ_TIMER))
2894                 return IRQ_RETVAL(0);
2895
2896         spin_lock(&np->lock);
2897         np->intr_test = 1;
2898         spin_unlock(&np->lock);
2899
2900         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
2901
2902         return IRQ_RETVAL(1);
2903 }
2904
2905 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
2906 {
2907         u8 __iomem *base = get_hwbase(dev);
2908         int i;
2909         u32 msixmap = 0;
2910
2911         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2912          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2913          * the remaining 8 interrupts.
2914          */
2915         for (i = 0; i < 8; i++) {
2916                 if ((irqmask >> i) & 0x1) {
2917                         msixmap |= vector << (i << 2);
2918                 }
2919         }
2920         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
2921
2922         msixmap = 0;
2923         for (i = 0; i < 8; i++) {
2924                 if ((irqmask >> (i + 8)) & 0x1) {
2925                         msixmap |= vector << (i << 2);
2926                 }
2927         }
2928         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
2929 }
2930
2931 static int nv_request_irq(struct net_device *dev, int intr_test)
2932 {
2933         struct fe_priv *np = get_nvpriv(dev);
2934         u8 __iomem *base = get_hwbase(dev);
2935         int ret = 1;
2936         int i;
2937
2938         if (np->msi_flags & NV_MSI_X_CAPABLE) {
2939                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2940                         np->msi_x_entry[i].entry = i;
2941                 }
2942                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
2943                         np->msi_flags |= NV_MSI_X_ENABLED;
2944                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
2945                                 /* Request irq for rx handling */
2946                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
2947                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
2948                                         pci_disable_msix(np->pci_dev);
2949                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2950                                         goto out_err;
2951                                 }
2952                                 /* Request irq for tx handling */
2953                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
2954                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
2955                                         pci_disable_msix(np->pci_dev);
2956                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2957                                         goto out_free_rx;
2958                                 }
2959                                 /* Request irq for link and timer handling */
2960                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
2961                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
2962                                         pci_disable_msix(np->pci_dev);
2963                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2964                                         goto out_free_tx;
2965                                 }
2966                                 /* map interrupts to their respective vector */
2967                                 writel(0, base + NvRegMSIXMap0);
2968                                 writel(0, base + NvRegMSIXMap1);
2969                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
2970                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
2971                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
2972                         } else {
2973                                 /* Request irq for all interrupts */
2974                                 if ((!intr_test &&
2975                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2976                                     (intr_test &&
2977                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2978                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2979                                         pci_disable_msix(np->pci_dev);
2980                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2981                                         goto out_err;
2982                                 }
2983
2984                                 /* map interrupts to vector 0 */
2985                                 writel(0, base + NvRegMSIXMap0);
2986                                 writel(0, base + NvRegMSIXMap1);
2987                         }
2988                 }
2989         }
2990         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
2991                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
2992                         np->msi_flags |= NV_MSI_ENABLED;
2993                         if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2994                             (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2995                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2996                                 pci_disable_msi(np->pci_dev);
2997                                 np->msi_flags &= ~NV_MSI_ENABLED;
2998                                 goto out_err;
2999                         }
3000
3001                         /* map interrupts to vector 0 */
3002                         writel(0, base + NvRegMSIMap0);
3003                         writel(0, base + NvRegMSIMap1);
3004                         /* enable msi vector 0 */
3005                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3006                 }
3007         }
3008         if (ret != 0) {
3009                 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
3010                     (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0))
3011                         goto out_err;
3012
3013         }
3014
3015         return 0;
3016 out_free_tx:
3017         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3018 out_free_rx:
3019         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3020 out_err:
3021         return 1;
3022 }
3023
3024 static void nv_free_irq(struct net_device *dev)
3025 {
3026         struct fe_priv *np = get_nvpriv(dev);
3027         int i;
3028
3029         if (np->msi_flags & NV_MSI_X_ENABLED) {
3030                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3031                         free_irq(np->msi_x_entry[i].vector, dev);
3032                 }
3033                 pci_disable_msix(np->pci_dev);
3034                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3035         } else {
3036                 free_irq(np->pci_dev->irq, dev);
3037                 if (np->msi_flags & NV_MSI_ENABLED) {
3038                         pci_disable_msi(np->pci_dev);
3039                         np->msi_flags &= ~NV_MSI_ENABLED;
3040                 }
3041         }
3042 }
3043
3044 static void nv_do_nic_poll(unsigned long data)
3045 {
3046         struct net_device *dev = (struct net_device *) data;
3047         struct fe_priv *np = netdev_priv(dev);
3048         u8 __iomem *base = get_hwbase(dev);
3049         u32 mask = 0;
3050
3051         /*
3052          * First disable irq(s) and then
3053          * reenable interrupts on the nic, we have to do this before calling
3054          * nv_nic_irq because that may decide to do otherwise
3055          */
3056
3057         if (!using_multi_irqs(dev)) {
3058                 if (np->msi_flags & NV_MSI_X_ENABLED)
3059                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3060                 else
3061                         disable_irq_lockdep(dev->irq);
3062                 mask = np->irqmask;
3063         } else {
3064                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3065                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3066                         mask |= NVREG_IRQ_RX_ALL;
3067                 }
3068                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3069                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3070                         mask |= NVREG_IRQ_TX_ALL;
3071                 }
3072                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3073                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3074                         mask |= NVREG_IRQ_OTHER;
3075                 }
3076         }
3077         np->nic_poll_irq = 0;
3078
3079         if (np->recover_error) {
3080                 np->recover_error = 0;
3081                 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3082                 if (netif_running(dev)) {
3083                         netif_tx_lock_bh(dev);
3084                         spin_lock(&np->lock);
3085                         /* stop engines */
3086                         nv_stop_rx(dev);
3087                         nv_stop_tx(dev);
3088                         nv_txrx_reset(dev);
3089                         /* drain rx queue */
3090                         nv_drain_rx(dev);
3091                         nv_drain_tx(dev);
3092                         /* reinit driver view of the rx queue */
3093                         set_bufsize(dev);
3094                         if (nv_init_ring(dev)) {
3095                                 if (!np->in_shutdown)
3096                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3097                         }
3098                         /* reinit nic view of the rx queue */
3099                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3100                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3101                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3102                                 base + NvRegRingSizes);
3103                         pci_push(base);
3104                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3105                         pci_push(base);
3106
3107                         /* restart rx engine */
3108                         nv_start_rx(dev);
3109                         nv_start_tx(dev);
3110                         spin_unlock(&np->lock);
3111                         netif_tx_unlock_bh(dev);
3112                 }
3113         }
3114
3115         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
3116
3117         writel(mask, base + NvRegIrqMask);
3118         pci_push(base);
3119
3120         if (!using_multi_irqs(dev)) {
3121                 nv_nic_irq(0, dev);
3122                 if (np->msi_flags & NV_MSI_X_ENABLED)
3123                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);