Automatic merge of /spare/repo/netdev-2.6 branch forcedeth
[linux-3.10.git] / drivers / net / forcedeth.c
1 /*
2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3  *
4  * Note: This driver is a cleanroom reimplementation based on reverse
5  *      engineered documentation written by Carl-Daniel Hailfinger
6  *      and Andrew de Quincey. It's neither supported nor endorsed
7  *      by NVIDIA Corp. Use at your own risk.
8  *
9  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10  * trademarks of NVIDIA Corporation in the United States and other
11  * countries.
12  *
13  * Copyright (C) 2003,4 Manfred Spraul
14  * Copyright (C) 2004 Andrew de Quincey (wol support)
15  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
17  * Copyright (c) 2004 NVIDIA Corporation
18  *
19  * This program is free software; you can redistribute it and/or modify
20  * it under the terms of the GNU General Public License as published by
21  * the Free Software Foundation; either version 2 of the License, or
22  * (at your option) any later version.
23  *
24  * This program is distributed in the hope that it will be useful,
25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
27  * GNU General Public License for more details.
28  *
29  * You should have received a copy of the GNU General Public License
30  * along with this program; if not, write to the Free Software
31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
32  *
33  * Changelog:
34  *      0.01: 05 Oct 2003: First release that compiles without warnings.
35  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36  *                         Check all PCI BARs for the register window.
37  *                         udelay added to mii_rw.
38  *      0.03: 06 Oct 2003: Initialize dev->irq.
39  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
42  *                         irq mask updated
43  *      0.07: 14 Oct 2003: Further irq mask updates.
44  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45  *                         added into irq handler, NULL check for drain_ring.
46  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47  *                         requested interrupt sources.
48  *      0.10: 20 Oct 2003: First cleanup for release.
49  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50  *                         MAC Address init fix, set_multicast cleanup.
51  *      0.12: 23 Oct 2003: Cleanups for release.
52  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53  *                         Set link speed correctly. start rx before starting
54  *                         tx (nv_start_rx sets the link speed).
55  *      0.14: 25 Oct 2003: Nic dependant irq mask.
56  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
57  *                         open.
58  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59  *                         increased to 1628 bytes.
60  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
61  *                         the tx length.
62  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64  *                         addresses, really stop rx if already running
65  *                         in nv_start_rx, clean up a bit.
66  *      0.20: 07 Dec 2003: alloc fixes
67  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
69  *                         on close.
70  *      0.23: 26 Jan 2004: various small cleanups
71  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72  *      0.25: 09 Mar 2004: wol support
73  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75  *                         added CK804/MCP04 device IDs, code fixes
76  *                         for registers, link status and other minor fixes.
77  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
79  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80  *                         into nv_close, otherwise reenabling for wol can
81  *                         cause DMA to kfree'd memory.
82  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
83  *                         capabilities.
84  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
85  *
86  * Known bugs:
87  * We suspect that on some hardware no TX done interrupts are generated.
88  * This means recovery from netif_stop_queue only happens if the hw timer
89  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
90  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
91  * If your hardware reliably generates tx done interrupts, then you can remove
92  * DEV_NEED_TIMERIRQ from the driver_data flags.
93  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
94  * superfluous timer interrupts from the nic.
95  */
96 #define FORCEDETH_VERSION               "0.32"
97 #define DRV_NAME                        "forcedeth"
98
99 #include <linux/module.h>
100 #include <linux/types.h>
101 #include <linux/pci.h>
102 #include <linux/interrupt.h>
103 #include <linux/netdevice.h>
104 #include <linux/etherdevice.h>
105 #include <linux/delay.h>
106 #include <linux/spinlock.h>
107 #include <linux/ethtool.h>
108 #include <linux/timer.h>
109 #include <linux/skbuff.h>
110 #include <linux/mii.h>
111 #include <linux/random.h>
112 #include <linux/init.h>
113 #include <linux/if_vlan.h>
114
115 #include <asm/irq.h>
116 #include <asm/io.h>
117 #include <asm/uaccess.h>
118 #include <asm/system.h>
119
120 #if 0
121 #define dprintk                 printk
122 #else
123 #define dprintk(x...)           do { } while (0)
124 #endif
125
126
127 /*
128  * Hardware access:
129  */
130
131 #define DEV_NEED_LASTPACKET1    0x0001  /* set LASTPACKET1 in tx flags */
132 #define DEV_IRQMASK_1           0x0002  /* use NVREG_IRQMASK_WANTED_1 for irq mask */
133 #define DEV_IRQMASK_2           0x0004  /* use NVREG_IRQMASK_WANTED_2 for irq mask */
134 #define DEV_NEED_TIMERIRQ       0x0008  /* set the timer irq flag in the irq mask */
135 #define DEV_NEED_LINKTIMER      0x0010  /* poll link settings. Relies on the timer irq */
136
137 enum {
138         NvRegIrqStatus = 0x000,
139 #define NVREG_IRQSTAT_MIIEVENT  0x040
140 #define NVREG_IRQSTAT_MASK              0x1ff
141         NvRegIrqMask = 0x004,
142 #define NVREG_IRQ_RX_ERROR              0x0001
143 #define NVREG_IRQ_RX                    0x0002
144 #define NVREG_IRQ_RX_NOBUF              0x0004
145 #define NVREG_IRQ_TX_ERR                0x0008
146 #define NVREG_IRQ_TX2                   0x0010
147 #define NVREG_IRQ_TIMER                 0x0020
148 #define NVREG_IRQ_LINK                  0x0040
149 #define NVREG_IRQ_TX1                   0x0100
150 #define NVREG_IRQMASK_WANTED_1          0x005f
151 #define NVREG_IRQMASK_WANTED_2          0x0147
152 #define NVREG_IRQ_UNKNOWN               (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
153
154         NvRegUnknownSetupReg6 = 0x008,
155 #define NVREG_UNKSETUP6_VAL             3
156
157 /*
158  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
159  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
160  */
161         NvRegPollingInterval = 0x00c,
162 #define NVREG_POLL_DEFAULT      970
163         NvRegMisc1 = 0x080,
164 #define NVREG_MISC1_HD          0x02
165 #define NVREG_MISC1_FORCE       0x3b0f3c
166
167         NvRegTransmitterControl = 0x084,
168 #define NVREG_XMITCTL_START     0x01
169         NvRegTransmitterStatus = 0x088,
170 #define NVREG_XMITSTAT_BUSY     0x01
171
172         NvRegPacketFilterFlags = 0x8c,
173 #define NVREG_PFF_ALWAYS        0x7F0008
174 #define NVREG_PFF_PROMISC       0x80
175 #define NVREG_PFF_MYADDR        0x20
176
177         NvRegOffloadConfig = 0x90,
178 #define NVREG_OFFLOAD_HOMEPHY   0x601
179 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
180         NvRegReceiverControl = 0x094,
181 #define NVREG_RCVCTL_START      0x01
182         NvRegReceiverStatus = 0x98,
183 #define NVREG_RCVSTAT_BUSY      0x01
184
185         NvRegRandomSeed = 0x9c,
186 #define NVREG_RNDSEED_MASK      0x00ff
187 #define NVREG_RNDSEED_FORCE     0x7f00
188 #define NVREG_RNDSEED_FORCE2    0x2d00
189 #define NVREG_RNDSEED_FORCE3    0x7400
190
191         NvRegUnknownSetupReg1 = 0xA0,
192 #define NVREG_UNKSETUP1_VAL     0x16070f
193         NvRegUnknownSetupReg2 = 0xA4,
194 #define NVREG_UNKSETUP2_VAL     0x16
195         NvRegMacAddrA = 0xA8,
196         NvRegMacAddrB = 0xAC,
197         NvRegMulticastAddrA = 0xB0,
198 #define NVREG_MCASTADDRA_FORCE  0x01
199         NvRegMulticastAddrB = 0xB4,
200         NvRegMulticastMaskA = 0xB8,
201         NvRegMulticastMaskB = 0xBC,
202
203         NvRegPhyInterface = 0xC0,
204 #define PHY_RGMII               0x10000000
205
206         NvRegTxRingPhysAddr = 0x100,
207         NvRegRxRingPhysAddr = 0x104,
208         NvRegRingSizes = 0x108,
209 #define NVREG_RINGSZ_TXSHIFT 0
210 #define NVREG_RINGSZ_RXSHIFT 16
211         NvRegUnknownTransmitterReg = 0x10c,
212         NvRegLinkSpeed = 0x110,
213 #define NVREG_LINKSPEED_FORCE 0x10000
214 #define NVREG_LINKSPEED_10      1000
215 #define NVREG_LINKSPEED_100     100
216 #define NVREG_LINKSPEED_1000    50
217 #define NVREG_LINKSPEED_MASK    (0xFFF)
218         NvRegUnknownSetupReg5 = 0x130,
219 #define NVREG_UNKSETUP5_BIT31   (1<<31)
220         NvRegUnknownSetupReg3 = 0x13c,
221 #define NVREG_UNKSETUP3_VAL1    0x200010
222         NvRegTxRxControl = 0x144,
223 #define NVREG_TXRXCTL_KICK      0x0001
224 #define NVREG_TXRXCTL_BIT1      0x0002
225 #define NVREG_TXRXCTL_BIT2      0x0004
226 #define NVREG_TXRXCTL_IDLE      0x0008
227 #define NVREG_TXRXCTL_RESET     0x0010
228 #define NVREG_TXRXCTL_RXCHECK   0x0400
229         NvRegMIIStatus = 0x180,
230 #define NVREG_MIISTAT_ERROR             0x0001
231 #define NVREG_MIISTAT_LINKCHANGE        0x0008
232 #define NVREG_MIISTAT_MASK              0x000f
233 #define NVREG_MIISTAT_MASK2             0x000f
234         NvRegUnknownSetupReg4 = 0x184,
235 #define NVREG_UNKSETUP4_VAL     8
236
237         NvRegAdapterControl = 0x188,
238 #define NVREG_ADAPTCTL_START    0x02
239 #define NVREG_ADAPTCTL_LINKUP   0x04
240 #define NVREG_ADAPTCTL_PHYVALID 0x40000
241 #define NVREG_ADAPTCTL_RUNNING  0x100000
242 #define NVREG_ADAPTCTL_PHYSHIFT 24
243         NvRegMIISpeed = 0x18c,
244 #define NVREG_MIISPEED_BIT8     (1<<8)
245 #define NVREG_MIIDELAY  5
246         NvRegMIIControl = 0x190,
247 #define NVREG_MIICTL_INUSE      0x08000
248 #define NVREG_MIICTL_WRITE      0x00400
249 #define NVREG_MIICTL_ADDRSHIFT  5
250         NvRegMIIData = 0x194,
251         NvRegWakeUpFlags = 0x200,
252 #define NVREG_WAKEUPFLAGS_VAL           0x7770
253 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
254 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
255 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
256 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
257 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
258 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
259 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
260 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
261 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
262 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
263
264         NvRegPatternCRC = 0x204,
265         NvRegPatternMask = 0x208,
266         NvRegPowerCap = 0x268,
267 #define NVREG_POWERCAP_D3SUPP   (1<<30)
268 #define NVREG_POWERCAP_D2SUPP   (1<<26)
269 #define NVREG_POWERCAP_D1SUPP   (1<<25)
270         NvRegPowerState = 0x26c,
271 #define NVREG_POWERSTATE_POWEREDUP      0x8000
272 #define NVREG_POWERSTATE_VALID          0x0100
273 #define NVREG_POWERSTATE_MASK           0x0003
274 #define NVREG_POWERSTATE_D0             0x0000
275 #define NVREG_POWERSTATE_D1             0x0001
276 #define NVREG_POWERSTATE_D2             0x0002
277 #define NVREG_POWERSTATE_D3             0x0003
278 };
279
280 /* Big endian: should work, but is untested */
281 struct ring_desc {
282         u32 PacketBuffer;
283         u32 FlagLen;
284 };
285
286 #define FLAG_MASK_V1 0xffff0000
287 #define FLAG_MASK_V2 0xffffc000
288 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
289 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
290
291 #define NV_TX_LASTPACKET        (1<<16)
292 #define NV_TX_RETRYERROR        (1<<19)
293 #define NV_TX_LASTPACKET1       (1<<24)
294 #define NV_TX_DEFERRED          (1<<26)
295 #define NV_TX_CARRIERLOST       (1<<27)
296 #define NV_TX_LATECOLLISION     (1<<28)
297 #define NV_TX_UNDERFLOW         (1<<29)
298 #define NV_TX_ERROR             (1<<30)
299 #define NV_TX_VALID             (1<<31)
300
301 #define NV_TX2_LASTPACKET       (1<<29)
302 #define NV_TX2_RETRYERROR       (1<<18)
303 #define NV_TX2_LASTPACKET1      (1<<23)
304 #define NV_TX2_DEFERRED         (1<<25)
305 #define NV_TX2_CARRIERLOST      (1<<26)
306 #define NV_TX2_LATECOLLISION    (1<<27)
307 #define NV_TX2_UNDERFLOW        (1<<28)
308 /* error and valid are the same for both */
309 #define NV_TX2_ERROR            (1<<30)
310 #define NV_TX2_VALID            (1<<31)
311
312 #define NV_RX_DESCRIPTORVALID   (1<<16)
313 #define NV_RX_MISSEDFRAME       (1<<17)
314 #define NV_RX_SUBSTRACT1        (1<<18)
315 #define NV_RX_ERROR1            (1<<23)
316 #define NV_RX_ERROR2            (1<<24)
317 #define NV_RX_ERROR3            (1<<25)
318 #define NV_RX_ERROR4            (1<<26)
319 #define NV_RX_CRCERR            (1<<27)
320 #define NV_RX_OVERFLOW          (1<<28)
321 #define NV_RX_FRAMINGERR        (1<<29)
322 #define NV_RX_ERROR             (1<<30)
323 #define NV_RX_AVAIL             (1<<31)
324
325 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
326 #define NV_RX2_CHECKSUMOK1      (0x10000000)
327 #define NV_RX2_CHECKSUMOK2      (0x14000000)
328 #define NV_RX2_CHECKSUMOK3      (0x18000000)
329 #define NV_RX2_DESCRIPTORVALID  (1<<29)
330 #define NV_RX2_SUBSTRACT1       (1<<25)
331 #define NV_RX2_ERROR1           (1<<18)
332 #define NV_RX2_ERROR2           (1<<19)
333 #define NV_RX2_ERROR3           (1<<20)
334 #define NV_RX2_ERROR4           (1<<21)
335 #define NV_RX2_CRCERR           (1<<22)
336 #define NV_RX2_OVERFLOW         (1<<23)
337 #define NV_RX2_FRAMINGERR       (1<<24)
338 /* error and avail are the same for both */
339 #define NV_RX2_ERROR            (1<<30)
340 #define NV_RX2_AVAIL            (1<<31)
341
342 /* Miscelaneous hardware related defines: */
343 #define NV_PCI_REGSZ            0x270
344
345 /* various timeout delays: all in usec */
346 #define NV_TXRX_RESET_DELAY     4
347 #define NV_TXSTOP_DELAY1        10
348 #define NV_TXSTOP_DELAY1MAX     500000
349 #define NV_TXSTOP_DELAY2        100
350 #define NV_RXSTOP_DELAY1        10
351 #define NV_RXSTOP_DELAY1MAX     500000
352 #define NV_RXSTOP_DELAY2        100
353 #define NV_SETUP5_DELAY         5
354 #define NV_SETUP5_DELAYMAX      50000
355 #define NV_POWERUP_DELAY        5
356 #define NV_POWERUP_DELAYMAX     5000
357 #define NV_MIIBUSY_DELAY        50
358 #define NV_MIIPHY_DELAY 10
359 #define NV_MIIPHY_DELAYMAX      10000
360
361 #define NV_WAKEUPPATTERNS       5
362 #define NV_WAKEUPMASKENTRIES    4
363
364 /* General driver defaults */
365 #define NV_WATCHDOG_TIMEO       (5*HZ)
366
367 #define RX_RING         128
368 #define TX_RING         64
369 /* 
370  * If your nic mysteriously hangs then try to reduce the limits
371  * to 1/0: It might be required to set NV_TX_LASTPACKET in the
372  * last valid ring entry. But this would be impossible to
373  * implement - probably a disassembly error.
374  */
375 #define TX_LIMIT_STOP   63
376 #define TX_LIMIT_START  62
377
378 /* rx/tx mac addr + type + vlan + align + slack*/
379 #define RX_NIC_BUFSIZE          (ETH_DATA_LEN + 64)
380 /* even more slack */
381 #define RX_ALLOC_BUFSIZE        (ETH_DATA_LEN + 128)
382
383 #define OOM_REFILL      (1+HZ/20)
384 #define POLL_WAIT       (1+HZ/100)
385 #define LINK_TIMEOUT    (3*HZ)
386
387 /* 
388  * desc_ver values:
389  * This field has two purposes:
390  * - Newer nics uses a different ring layout. The layout is selected by
391  *   comparing np->desc_ver with DESC_VER_xy.
392  * - It contains bits that are forced on when writing to NvRegTxRxControl.
393  */
394 #define DESC_VER_1      0x0
395 #define DESC_VER_2      (0x02100|NVREG_TXRXCTL_RXCHECK)
396
397 /* PHY defines */
398 #define PHY_OUI_MARVELL 0x5043
399 #define PHY_OUI_CICADA  0x03f1
400 #define PHYID1_OUI_MASK 0x03ff
401 #define PHYID1_OUI_SHFT 6
402 #define PHYID2_OUI_MASK 0xfc00
403 #define PHYID2_OUI_SHFT 10
404 #define PHY_INIT1       0x0f000
405 #define PHY_INIT2       0x0e00
406 #define PHY_INIT3       0x01000
407 #define PHY_INIT4       0x0200
408 #define PHY_INIT5       0x0004
409 #define PHY_INIT6       0x02000
410 #define PHY_GIGABIT     0x0100
411
412 #define PHY_TIMEOUT     0x1
413 #define PHY_ERROR       0x2
414
415 #define PHY_100 0x1
416 #define PHY_1000        0x2
417 #define PHY_HALF        0x100
418
419 /* FIXME: MII defines that should be added to <linux/mii.h> */
420 #define MII_1000BT_CR   0x09
421 #define MII_1000BT_SR   0x0a
422 #define ADVERTISE_1000FULL      0x0200
423 #define ADVERTISE_1000HALF      0x0100
424 #define LPA_1000FULL    0x0800
425 #define LPA_1000HALF    0x0400
426
427
428 /*
429  * SMP locking:
430  * All hardware access under dev->priv->lock, except the performance
431  * critical parts:
432  * - rx is (pseudo-) lockless: it relies on the single-threading provided
433  *      by the arch code for interrupts.
434  * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
435  *      needs dev->priv->lock :-(
436  * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
437  */
438
439 /* in dev: base, irq */
440 struct fe_priv {
441         spinlock_t lock;
442
443         /* General data:
444          * Locking: spin_lock(&np->lock); */
445         struct net_device_stats stats;
446         int in_shutdown;
447         u32 linkspeed;
448         int duplex;
449         int autoneg;
450         int fixed_mode;
451         int phyaddr;
452         int wolenabled;
453         unsigned int phy_oui;
454         u16 gigabit;
455
456         /* General data: RO fields */
457         dma_addr_t ring_addr;
458         struct pci_dev *pci_dev;
459         u32 orig_mac[2];
460         u32 irqmask;
461         u32 desc_ver;
462
463         void __iomem *base;
464
465         /* rx specific fields.
466          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
467          */
468         struct ring_desc *rx_ring;
469         unsigned int cur_rx, refill_rx;
470         struct sk_buff *rx_skbuff[RX_RING];
471         dma_addr_t rx_dma[RX_RING];
472         unsigned int rx_buf_sz;
473         struct timer_list oom_kick;
474         struct timer_list nic_poll;
475
476         /* media detection workaround.
477          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
478          */
479         int need_linktimer;
480         unsigned long link_timeout;
481         /*
482          * tx specific fields.
483          */
484         struct ring_desc *tx_ring;
485         unsigned int next_tx, nic_tx;
486         struct sk_buff *tx_skbuff[TX_RING];
487         dma_addr_t tx_dma[TX_RING];
488         u32 tx_flags;
489 };
490
491 /*
492  * Maximum number of loops until we assume that a bit in the irq mask
493  * is stuck. Overridable with module param.
494  */
495 static int max_interrupt_work = 5;
496
497 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
498 {
499         return netdev_priv(dev);
500 }
501
502 static inline u8 __iomem *get_hwbase(struct net_device *dev)
503 {
504         return get_nvpriv(dev)->base;
505 }
506
507 static inline void pci_push(u8 __iomem *base)
508 {
509         /* force out pending posted writes */
510         readl(base);
511 }
512
513 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
514 {
515         return le32_to_cpu(prd->FlagLen)
516                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
517 }
518
519 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
520                                 int delay, int delaymax, const char *msg)
521 {
522         u8 __iomem *base = get_hwbase(dev);
523
524         pci_push(base);
525         do {
526                 udelay(delay);
527                 delaymax -= delay;
528                 if (delaymax < 0) {
529                         if (msg)
530                                 printk(msg);
531                         return 1;
532                 }
533         } while ((readl(base + offset) & mask) != target);
534         return 0;
535 }
536
537 #define MII_READ        (-1)
538 /* mii_rw: read/write a register on the PHY.
539  *
540  * Caller must guarantee serialization
541  */
542 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
543 {
544         u8 __iomem *base = get_hwbase(dev);
545         u32 reg;
546         int retval;
547
548         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
549
550         reg = readl(base + NvRegMIIControl);
551         if (reg & NVREG_MIICTL_INUSE) {
552                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
553                 udelay(NV_MIIBUSY_DELAY);
554         }
555
556         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
557         if (value != MII_READ) {
558                 writel(value, base + NvRegMIIData);
559                 reg |= NVREG_MIICTL_WRITE;
560         }
561         writel(reg, base + NvRegMIIControl);
562
563         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
564                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
565                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
566                                 dev->name, miireg, addr);
567                 retval = -1;
568         } else if (value != MII_READ) {
569                 /* it was a write operation - fewer failures are detectable */
570                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
571                                 dev->name, value, miireg, addr);
572                 retval = 0;
573         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
574                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
575                                 dev->name, miireg, addr);
576                 retval = -1;
577         } else {
578                 retval = readl(base + NvRegMIIData);
579                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
580                                 dev->name, miireg, addr, retval);
581         }
582
583         return retval;
584 }
585
586 static int phy_reset(struct net_device *dev)
587 {
588         struct fe_priv *np = get_nvpriv(dev);
589         u32 miicontrol;
590         unsigned int tries = 0;
591
592         miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
593         miicontrol |= BMCR_RESET;
594         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
595                 return -1;
596         }
597
598         /* wait for 500ms */
599         msleep(500);
600
601         /* must wait till reset is deasserted */
602         while (miicontrol & BMCR_RESET) {
603                 msleep(10);
604                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
605                 /* FIXME: 100 tries seem excessive */
606                 if (tries++ > 100)
607                         return -1;
608         }
609         return 0;
610 }
611
612 static int phy_init(struct net_device *dev)
613 {
614         struct fe_priv *np = get_nvpriv(dev);
615         u8 __iomem *base = get_hwbase(dev);
616         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
617
618         /* set advertise register */
619         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
620         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
621         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
622                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
623                 return PHY_ERROR;
624         }
625
626         /* get phy interface type */
627         phyinterface = readl(base + NvRegPhyInterface);
628
629         /* see if gigabit phy */
630         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
631         if (mii_status & PHY_GIGABIT) {
632                 np->gigabit = PHY_GIGABIT;
633                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
634                 mii_control_1000 &= ~ADVERTISE_1000HALF;
635                 if (phyinterface & PHY_RGMII)
636                         mii_control_1000 |= ADVERTISE_1000FULL;
637                 else
638                         mii_control_1000 &= ~ADVERTISE_1000FULL;
639
640                 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
641                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
642                         return PHY_ERROR;
643                 }
644         }
645         else
646                 np->gigabit = 0;
647
648         /* reset the phy */
649         if (phy_reset(dev)) {
650                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
651                 return PHY_ERROR;
652         }
653
654         /* phy vendor specific configuration */
655         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
656                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
657                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
658                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
659                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
660                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
661                         return PHY_ERROR;
662                 }
663                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
664                 phy_reserved |= PHY_INIT5;
665                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
666                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
667                         return PHY_ERROR;
668                 }
669         }
670         if (np->phy_oui == PHY_OUI_CICADA) {
671                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
672                 phy_reserved |= PHY_INIT6;
673                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
674                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
675                         return PHY_ERROR;
676                 }
677         }
678
679         /* restart auto negotiation */
680         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
681         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
682         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
683                 return PHY_ERROR;
684         }
685
686         return 0;
687 }
688
689 static void nv_start_rx(struct net_device *dev)
690 {
691         struct fe_priv *np = get_nvpriv(dev);
692         u8 __iomem *base = get_hwbase(dev);
693
694         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
695         /* Already running? Stop it. */
696         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
697                 writel(0, base + NvRegReceiverControl);
698                 pci_push(base);
699         }
700         writel(np->linkspeed, base + NvRegLinkSpeed);
701         pci_push(base);
702         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
703         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
704                                 dev->name, np->duplex, np->linkspeed);
705         pci_push(base);
706 }
707
708 static void nv_stop_rx(struct net_device *dev)
709 {
710         u8 __iomem *base = get_hwbase(dev);
711
712         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
713         writel(0, base + NvRegReceiverControl);
714         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
715                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
716                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
717
718         udelay(NV_RXSTOP_DELAY2);
719         writel(0, base + NvRegLinkSpeed);
720 }
721
722 static void nv_start_tx(struct net_device *dev)
723 {
724         u8 __iomem *base = get_hwbase(dev);
725
726         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
727         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
728         pci_push(base);
729 }
730
731 static void nv_stop_tx(struct net_device *dev)
732 {
733         u8 __iomem *base = get_hwbase(dev);
734
735         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
736         writel(0, base + NvRegTransmitterControl);
737         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
738                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
739                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
740
741         udelay(NV_TXSTOP_DELAY2);
742         writel(0, base + NvRegUnknownTransmitterReg);
743 }
744
745 static void nv_txrx_reset(struct net_device *dev)
746 {
747         struct fe_priv *np = get_nvpriv(dev);
748         u8 __iomem *base = get_hwbase(dev);
749
750         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
751         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->desc_ver, base + NvRegTxRxControl);
752         pci_push(base);
753         udelay(NV_TXRX_RESET_DELAY);
754         writel(NVREG_TXRXCTL_BIT2 | np->desc_ver, base + NvRegTxRxControl);
755         pci_push(base);
756 }
757
758 /*
759  * nv_get_stats: dev->get_stats function
760  * Get latest stats value from the nic.
761  * Called with read_lock(&dev_base_lock) held for read -
762  * only synchronized against unregister_netdevice.
763  */
764 static struct net_device_stats *nv_get_stats(struct net_device *dev)
765 {
766         struct fe_priv *np = get_nvpriv(dev);
767
768         /* It seems that the nic always generates interrupts and doesn't
769          * accumulate errors internally. Thus the current values in np->stats
770          * are already up to date.
771          */
772         return &np->stats;
773 }
774
775 /*
776  * nv_alloc_rx: fill rx ring entries.
777  * Return 1 if the allocations for the skbs failed and the
778  * rx engine is without Available descriptors
779  */
780 static int nv_alloc_rx(struct net_device *dev)
781 {
782         struct fe_priv *np = get_nvpriv(dev);
783         unsigned int refill_rx = np->refill_rx;
784         int nr;
785
786         while (np->cur_rx != refill_rx) {
787                 struct sk_buff *skb;
788
789                 nr = refill_rx % RX_RING;
790                 if (np->rx_skbuff[nr] == NULL) {
791
792                         skb = dev_alloc_skb(RX_ALLOC_BUFSIZE);
793                         if (!skb)
794                                 break;
795
796                         skb->dev = dev;
797                         np->rx_skbuff[nr] = skb;
798                 } else {
799                         skb = np->rx_skbuff[nr];
800                 }
801                 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
802                                                 PCI_DMA_FROMDEVICE);
803                 np->rx_ring[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
804                 wmb();
805                 np->rx_ring[nr].FlagLen = cpu_to_le32(RX_NIC_BUFSIZE | NV_RX_AVAIL);
806                 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
807                                         dev->name, refill_rx);
808                 refill_rx++;
809         }
810         np->refill_rx = refill_rx;
811         if (np->cur_rx - refill_rx == RX_RING)
812                 return 1;
813         return 0;
814 }
815
816 static void nv_do_rx_refill(unsigned long data)
817 {
818         struct net_device *dev = (struct net_device *) data;
819         struct fe_priv *np = get_nvpriv(dev);
820
821         disable_irq(dev->irq);
822         if (nv_alloc_rx(dev)) {
823                 spin_lock(&np->lock);
824                 if (!np->in_shutdown)
825                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
826                 spin_unlock(&np->lock);
827         }
828         enable_irq(dev->irq);
829 }
830
831 static int nv_init_ring(struct net_device *dev)
832 {
833         struct fe_priv *np = get_nvpriv(dev);
834         int i;
835
836         np->next_tx = np->nic_tx = 0;
837         for (i = 0; i < TX_RING; i++)
838                 np->tx_ring[i].FlagLen = 0;
839
840         np->cur_rx = RX_RING;
841         np->refill_rx = 0;
842         for (i = 0; i < RX_RING; i++)
843                 np->rx_ring[i].FlagLen = 0;
844         return nv_alloc_rx(dev);
845 }
846
847 static void nv_drain_tx(struct net_device *dev)
848 {
849         struct fe_priv *np = get_nvpriv(dev);
850         int i;
851         for (i = 0; i < TX_RING; i++) {
852                 np->tx_ring[i].FlagLen = 0;
853                 if (np->tx_skbuff[i]) {
854                         pci_unmap_single(np->pci_dev, np->tx_dma[i],
855                                                 np->tx_skbuff[i]->len,
856                                                 PCI_DMA_TODEVICE);
857                         dev_kfree_skb(np->tx_skbuff[i]);
858                         np->tx_skbuff[i] = NULL;
859                         np->stats.tx_dropped++;
860                 }
861         }
862 }
863
864 static void nv_drain_rx(struct net_device *dev)
865 {
866         struct fe_priv *np = get_nvpriv(dev);
867         int i;
868         for (i = 0; i < RX_RING; i++) {
869                 np->rx_ring[i].FlagLen = 0;
870                 wmb();
871                 if (np->rx_skbuff[i]) {
872                         pci_unmap_single(np->pci_dev, np->rx_dma[i],
873                                                 np->rx_skbuff[i]->len,
874                                                 PCI_DMA_FROMDEVICE);
875                         dev_kfree_skb(np->rx_skbuff[i]);
876                         np->rx_skbuff[i] = NULL;
877                 }
878         }
879 }
880
881 static void drain_ring(struct net_device *dev)
882 {
883         nv_drain_tx(dev);
884         nv_drain_rx(dev);
885 }
886
887 /*
888  * nv_start_xmit: dev->hard_start_xmit function
889  * Called with dev->xmit_lock held.
890  */
891 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
892 {
893         struct fe_priv *np = get_nvpriv(dev);
894         int nr = np->next_tx % TX_RING;
895
896         np->tx_skbuff[nr] = skb;
897         np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data,skb->len,
898                                         PCI_DMA_TODEVICE);
899
900         np->tx_ring[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
901
902         spin_lock_irq(&np->lock);
903         wmb();
904         np->tx_ring[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags );
905         dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission.\n",
906                                 dev->name, np->next_tx);
907         {
908                 int j;
909                 for (j=0; j<64; j++) {
910                         if ((j%16) == 0)
911                                 dprintk("\n%03x:", j);
912                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
913                 }
914                 dprintk("\n");
915         }
916
917         np->next_tx++;
918
919         dev->trans_start = jiffies;
920         if (np->next_tx - np->nic_tx >= TX_LIMIT_STOP)
921                 netif_stop_queue(dev);
922         spin_unlock_irq(&np->lock);
923         writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl);
924         pci_push(get_hwbase(dev));
925         return 0;
926 }
927
928 /*
929  * nv_tx_done: check for completed packets, release the skbs.
930  *
931  * Caller must own np->lock.
932  */
933 static void nv_tx_done(struct net_device *dev)
934 {
935         struct fe_priv *np = get_nvpriv(dev);
936         u32 Flags;
937         int i;
938
939         while (np->nic_tx != np->next_tx) {
940                 i = np->nic_tx % TX_RING;
941
942                 Flags = le32_to_cpu(np->tx_ring[i].FlagLen);
943
944                 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
945                                         dev->name, np->nic_tx, Flags);
946                 if (Flags & NV_TX_VALID)
947                         break;
948                 if (np->desc_ver == DESC_VER_1) {
949                         if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
950                                                         NV_TX_UNDERFLOW|NV_TX_ERROR)) {
951                                 if (Flags & NV_TX_UNDERFLOW)
952                                         np->stats.tx_fifo_errors++;
953                                 if (Flags & NV_TX_CARRIERLOST)
954                                         np->stats.tx_carrier_errors++;
955                                 np->stats.tx_errors++;
956                         } else {
957                                 np->stats.tx_packets++;
958                                 np->stats.tx_bytes += np->tx_skbuff[i]->len;
959                         }
960                 } else {
961                         if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
962                                                         NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
963                                 if (Flags & NV_TX2_UNDERFLOW)
964                                         np->stats.tx_fifo_errors++;
965                                 if (Flags & NV_TX2_CARRIERLOST)
966                                         np->stats.tx_carrier_errors++;
967                                 np->stats.tx_errors++;
968                         } else {
969                                 np->stats.tx_packets++;
970                                 np->stats.tx_bytes += np->tx_skbuff[i]->len;
971                         }
972                 }
973                 pci_unmap_single(np->pci_dev, np->tx_dma[i],
974                                         np->tx_skbuff[i]->len,
975                                         PCI_DMA_TODEVICE);
976                 dev_kfree_skb_irq(np->tx_skbuff[i]);
977                 np->tx_skbuff[i] = NULL;
978                 np->nic_tx++;
979         }
980         if (np->next_tx - np->nic_tx < TX_LIMIT_START)
981                 netif_wake_queue(dev);
982 }
983
984 /*
985  * nv_tx_timeout: dev->tx_timeout function
986  * Called with dev->xmit_lock held.
987  */
988 static void nv_tx_timeout(struct net_device *dev)
989 {
990         struct fe_priv *np = get_nvpriv(dev);
991         u8 __iomem *base = get_hwbase(dev);
992
993         dprintk(KERN_DEBUG "%s: Got tx_timeout. irq: %08x\n", dev->name,
994                         readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
995
996         spin_lock_irq(&np->lock);
997
998         /* 1) stop tx engine */
999         nv_stop_tx(dev);
1000
1001         /* 2) check that the packets were not sent already: */
1002         nv_tx_done(dev);
1003
1004         /* 3) if there are dead entries: clear everything */
1005         if (np->next_tx != np->nic_tx) {
1006                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1007                 nv_drain_tx(dev);
1008                 np->next_tx = np->nic_tx = 0;
1009                 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1010                 netif_wake_queue(dev);
1011         }
1012
1013         /* 4) restart tx engine */
1014         nv_start_tx(dev);
1015         spin_unlock_irq(&np->lock);
1016 }
1017
1018 /*
1019  * Called when the nic notices a mismatch between the actual data len on the
1020  * wire and the len indicated in the 802 header
1021  */
1022 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1023 {
1024         int hdrlen;     /* length of the 802 header */
1025         int protolen;   /* length as stored in the proto field */
1026
1027         /* 1) calculate len according to header */
1028         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1029                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1030                 hdrlen = VLAN_HLEN;
1031         } else {
1032                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1033                 hdrlen = ETH_HLEN;
1034         }
1035         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1036                                 dev->name, datalen, protolen, hdrlen);
1037         if (protolen > ETH_DATA_LEN)
1038                 return datalen; /* Value in proto field not a len, no checks possible */
1039
1040         protolen += hdrlen;
1041         /* consistency checks: */
1042         if (datalen > ETH_ZLEN) {
1043                 if (datalen >= protolen) {
1044                         /* more data on wire than in 802 header, trim of
1045                          * additional data.
1046                          */
1047                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1048                                         dev->name, protolen);
1049                         return protolen;
1050                 } else {
1051                         /* less data on wire than mentioned in header.
1052                          * Discard the packet.
1053                          */
1054                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1055                                         dev->name);
1056                         return -1;
1057                 }
1058         } else {
1059                 /* short packet. Accept only if 802 values are also short */
1060                 if (protolen > ETH_ZLEN) {
1061                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1062                                         dev->name);
1063                         return -1;
1064                 }
1065                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1066                                 dev->name, datalen);
1067                 return datalen;
1068         }
1069 }
1070
1071 static void nv_rx_process(struct net_device *dev)
1072 {
1073         struct fe_priv *np = get_nvpriv(dev);
1074         u32 Flags;
1075
1076         for (;;) {
1077                 struct sk_buff *skb;
1078                 int len;
1079                 int i;
1080                 if (np->cur_rx - np->refill_rx >= RX_RING)
1081                         break;  /* we scanned the whole ring - do not continue */
1082
1083                 i = np->cur_rx % RX_RING;
1084                 Flags = le32_to_cpu(np->rx_ring[i].FlagLen);
1085                 len = nv_descr_getlength(&np->rx_ring[i], np->desc_ver);
1086
1087                 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1088                                         dev->name, np->cur_rx, Flags);
1089
1090                 if (Flags & NV_RX_AVAIL)
1091                         break;  /* still owned by hardware, */
1092
1093                 /*
1094                  * the packet is for us - immediately tear down the pci mapping.
1095                  * TODO: check if a prefetch of the first cacheline improves
1096                  * the performance.
1097                  */
1098                 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1099                                 np->rx_skbuff[i]->len,
1100                                 PCI_DMA_FROMDEVICE);
1101
1102                 {
1103                         int j;
1104                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1105                         for (j=0; j<64; j++) {
1106                                 if ((j%16) == 0)
1107                                         dprintk("\n%03x:", j);
1108                                 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1109                         }
1110                         dprintk("\n");
1111                 }
1112                 /* look at what we actually got: */
1113                 if (np->desc_ver == DESC_VER_1) {
1114                         if (!(Flags & NV_RX_DESCRIPTORVALID))
1115                                 goto next_pkt;
1116
1117                         if (Flags & NV_RX_MISSEDFRAME) {
1118                                 np->stats.rx_missed_errors++;
1119                                 np->stats.rx_errors++;
1120                                 goto next_pkt;
1121                         }
1122                         if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1123                                 np->stats.rx_errors++;
1124                                 goto next_pkt;
1125                         }
1126                         if (Flags & NV_RX_CRCERR) {
1127                                 np->stats.rx_crc_errors++;
1128                                 np->stats.rx_errors++;
1129                                 goto next_pkt;
1130                         }
1131                         if (Flags & NV_RX_OVERFLOW) {
1132                                 np->stats.rx_over_errors++;
1133                                 np->stats.rx_errors++;
1134                                 goto next_pkt;
1135                         }
1136                         if (Flags & NV_RX_ERROR4) {
1137                                 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1138                                 if (len < 0) {
1139                                         np->stats.rx_errors++;
1140                                         goto next_pkt;
1141                                 }
1142                         }
1143                         /* framing errors are soft errors. */
1144                         if (Flags & NV_RX_FRAMINGERR) {
1145                                 if (Flags & NV_RX_SUBSTRACT1) {
1146                                         len--;
1147                                 }
1148                         }
1149                 } else {
1150                         if (!(Flags & NV_RX2_DESCRIPTORVALID))
1151                                 goto next_pkt;
1152
1153                         if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1154                                 np->stats.rx_errors++;
1155                                 goto next_pkt;
1156                         }
1157                         if (Flags & NV_RX2_CRCERR) {
1158                                 np->stats.rx_crc_errors++;
1159                                 np->stats.rx_errors++;
1160                                 goto next_pkt;
1161                         }
1162                         if (Flags & NV_RX2_OVERFLOW) {
1163                                 np->stats.rx_over_errors++;
1164                                 np->stats.rx_errors++;
1165                                 goto next_pkt;
1166                         }
1167                         if (Flags & NV_RX2_ERROR4) {
1168                                 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1169                                 if (len < 0) {
1170                                         np->stats.rx_errors++;
1171                                         goto next_pkt;
1172                                 }
1173                         }
1174                         /* framing errors are soft errors */
1175                         if (Flags & NV_RX2_FRAMINGERR) {
1176                                 if (Flags & NV_RX2_SUBSTRACT1) {
1177                                         len--;
1178                                 }
1179                         }
1180                         Flags &= NV_RX2_CHECKSUMMASK;
1181                         if (Flags == NV_RX2_CHECKSUMOK1 ||
1182                                         Flags == NV_RX2_CHECKSUMOK2 ||
1183                                         Flags == NV_RX2_CHECKSUMOK3) {
1184                                 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1185                                 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1186                         } else {
1187                                 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1188                         }
1189                 }
1190                 /* got a valid packet - forward it to the network core */
1191                 skb = np->rx_skbuff[i];
1192                 np->rx_skbuff[i] = NULL;
1193
1194                 skb_put(skb, len);
1195                 skb->protocol = eth_type_trans(skb, dev);
1196                 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1197                                         dev->name, np->cur_rx, len, skb->protocol);
1198                 netif_rx(skb);
1199                 dev->last_rx = jiffies;
1200                 np->stats.rx_packets++;
1201                 np->stats.rx_bytes += len;
1202 next_pkt:
1203                 np->cur_rx++;
1204         }
1205 }
1206
1207 /*
1208  * nv_change_mtu: dev->change_mtu function
1209  * Called with dev_base_lock held for read.
1210  */
1211 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1212 {
1213         if (new_mtu > ETH_DATA_LEN)
1214                 return -EINVAL;
1215         dev->mtu = new_mtu;
1216         return 0;
1217 }
1218
1219 /*
1220  * nv_set_multicast: dev->set_multicast function
1221  * Called with dev->xmit_lock held.
1222  */
1223 static void nv_set_multicast(struct net_device *dev)
1224 {
1225         struct fe_priv *np = get_nvpriv(dev);
1226         u8 __iomem *base = get_hwbase(dev);
1227         u32 addr[2];
1228         u32 mask[2];
1229         u32 pff;
1230
1231         memset(addr, 0, sizeof(addr));
1232         memset(mask, 0, sizeof(mask));
1233
1234         if (dev->flags & IFF_PROMISC) {
1235                 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1236                 pff = NVREG_PFF_PROMISC;
1237         } else {
1238                 pff = NVREG_PFF_MYADDR;
1239
1240                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1241                         u32 alwaysOff[2];
1242                         u32 alwaysOn[2];
1243
1244                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1245                         if (dev->flags & IFF_ALLMULTI) {
1246                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1247                         } else {
1248                                 struct dev_mc_list *walk;
1249
1250                                 walk = dev->mc_list;
1251                                 while (walk != NULL) {
1252                                         u32 a, b;
1253                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1254                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1255                                         alwaysOn[0] &= a;
1256                                         alwaysOff[0] &= ~a;
1257                                         alwaysOn[1] &= b;
1258                                         alwaysOff[1] &= ~b;
1259                                         walk = walk->next;
1260                                 }
1261                         }
1262                         addr[0] = alwaysOn[0];
1263                         addr[1] = alwaysOn[1];
1264                         mask[0] = alwaysOn[0] | alwaysOff[0];
1265                         mask[1] = alwaysOn[1] | alwaysOff[1];
1266                 }
1267         }
1268         addr[0] |= NVREG_MCASTADDRA_FORCE;
1269         pff |= NVREG_PFF_ALWAYS;
1270         spin_lock_irq(&np->lock);
1271         nv_stop_rx(dev);
1272         writel(addr[0], base + NvRegMulticastAddrA);
1273         writel(addr[1], base + NvRegMulticastAddrB);
1274         writel(mask[0], base + NvRegMulticastMaskA);
1275         writel(mask[1], base + NvRegMulticastMaskB);
1276         writel(pff, base + NvRegPacketFilterFlags);
1277         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1278                 dev->name);
1279         nv_start_rx(dev);
1280         spin_unlock_irq(&np->lock);
1281 }
1282
1283 static int nv_update_linkspeed(struct net_device *dev)
1284 {
1285         struct fe_priv *np = get_nvpriv(dev);
1286         u8 __iomem *base = get_hwbase(dev);
1287         int adv, lpa;
1288         int newls = np->linkspeed;
1289         int newdup = np->duplex;
1290         int mii_status;
1291         int retval = 0;
1292         u32 control_1000, status_1000, phyreg;
1293
1294         /* BMSR_LSTATUS is latched, read it twice:
1295          * we want the current value.
1296          */
1297         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1298         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1299
1300         if (!(mii_status & BMSR_LSTATUS)) {
1301                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1302                                 dev->name);
1303                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1304                 newdup = 0;
1305                 retval = 0;
1306                 goto set_speed;
1307         }
1308
1309         if (np->autoneg == 0) {
1310                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1311                                 dev->name, np->fixed_mode);
1312                 if (np->fixed_mode & LPA_100FULL) {
1313                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1314                         newdup = 1;
1315                 } else if (np->fixed_mode & LPA_100HALF) {
1316                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1317                         newdup = 0;
1318                 } else if (np->fixed_mode & LPA_10FULL) {
1319                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1320                         newdup = 1;
1321                 } else {
1322                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1323                         newdup = 0;
1324                 }
1325                 retval = 1;
1326                 goto set_speed;
1327         }
1328         /* check auto negotiation is complete */
1329         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1330                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1331                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1332                 newdup = 0;
1333                 retval = 0;
1334                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1335                 goto set_speed;
1336         }
1337
1338         retval = 1;
1339         if (np->gigabit == PHY_GIGABIT) {
1340                 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1341                 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1342
1343                 if ((control_1000 & ADVERTISE_1000FULL) &&
1344                         (status_1000 & LPA_1000FULL)) {
1345                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1346                                 dev->name);
1347                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1348                         newdup = 1;
1349                         goto set_speed;
1350                 }
1351         }
1352
1353         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1354         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1355         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1356                                 dev->name, adv, lpa);
1357
1358         /* FIXME: handle parallel detection properly */
1359         lpa = lpa & adv;
1360         if (lpa & LPA_100FULL) {
1361                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1362                 newdup = 1;
1363         } else if (lpa & LPA_100HALF) {
1364                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1365                 newdup = 0;
1366         } else if (lpa & LPA_10FULL) {
1367                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1368                 newdup = 1;
1369         } else if (lpa & LPA_10HALF) {
1370                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1371                 newdup = 0;
1372         } else {
1373                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1374                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1375                 newdup = 0;
1376         }
1377
1378 set_speed:
1379         if (np->duplex == newdup && np->linkspeed == newls)
1380                 return retval;
1381
1382         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1383                         dev->name, np->linkspeed, np->duplex, newls, newdup);
1384
1385         np->duplex = newdup;
1386         np->linkspeed = newls;
1387
1388         if (np->gigabit == PHY_GIGABIT) {
1389                 phyreg = readl(base + NvRegRandomSeed);
1390                 phyreg &= ~(0x3FF00);
1391                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1392                         phyreg |= NVREG_RNDSEED_FORCE3;
1393                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1394                         phyreg |= NVREG_RNDSEED_FORCE2;
1395                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1396                         phyreg |= NVREG_RNDSEED_FORCE;
1397                 writel(phyreg, base + NvRegRandomSeed);
1398         }
1399
1400         phyreg = readl(base + NvRegPhyInterface);
1401         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1402         if (np->duplex == 0)
1403                 phyreg |= PHY_HALF;
1404         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
1405                 phyreg |= PHY_100;
1406         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
1407                 phyreg |= PHY_1000;
1408         writel(phyreg, base + NvRegPhyInterface);
1409
1410         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1411                 base + NvRegMisc1);
1412         pci_push(base);
1413         writel(np->linkspeed, base + NvRegLinkSpeed);
1414         pci_push(base);
1415
1416         return retval;
1417 }
1418
1419 static void nv_linkchange(struct net_device *dev)
1420 {
1421         if (nv_update_linkspeed(dev)) {
1422                 if (netif_carrier_ok(dev)) {
1423                         nv_stop_rx(dev);
1424                 } else {
1425                         netif_carrier_on(dev);
1426                         printk(KERN_INFO "%s: link up.\n", dev->name);
1427                 }
1428                 nv_start_rx(dev);
1429         } else {
1430                 if (netif_carrier_ok(dev)) {
1431                         netif_carrier_off(dev);
1432                         printk(KERN_INFO "%s: link down.\n", dev->name);
1433                         nv_stop_rx(dev);
1434                 }
1435         }
1436 }
1437
1438 static void nv_link_irq(struct net_device *dev)
1439 {
1440         u8 __iomem *base = get_hwbase(dev);
1441         u32 miistat;
1442
1443         miistat = readl(base + NvRegMIIStatus);
1444         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1445         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
1446
1447         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
1448                 nv_linkchange(dev);
1449         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1450 }
1451
1452 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1453 {
1454         struct net_device *dev = (struct net_device *) data;
1455         struct fe_priv *np = get_nvpriv(dev);
1456         u8 __iomem *base = get_hwbase(dev);
1457         u32 events;
1458         int i;
1459
1460         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1461
1462         for (i=0; ; i++) {
1463                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1464                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1465                 pci_push(base);
1466                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1467                 if (!(events & np->irqmask))
1468                         break;
1469
1470                 if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX2|NVREG_IRQ_TX_ERR)) {
1471                         spin_lock(&np->lock);
1472                         nv_tx_done(dev);
1473                         spin_unlock(&np->lock);
1474                 }
1475
1476                 if (events & (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF)) {
1477                         nv_rx_process(dev);
1478                         if (nv_alloc_rx(dev)) {
1479                                 spin_lock(&np->lock);
1480                                 if (!np->in_shutdown)
1481                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1482                                 spin_unlock(&np->lock);
1483                         }
1484                 }
1485
1486                 if (events & NVREG_IRQ_LINK) {
1487                         spin_lock(&np->lock);
1488                         nv_link_irq(dev);
1489                         spin_unlock(&np->lock);
1490                 }
1491                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
1492                         spin_lock(&np->lock);
1493                         nv_linkchange(dev);
1494                         spin_unlock(&np->lock);
1495                         np->link_timeout = jiffies + LINK_TIMEOUT;
1496                 }
1497                 if (events & (NVREG_IRQ_TX_ERR)) {
1498                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1499                                                 dev->name, events);
1500                 }
1501                 if (events & (NVREG_IRQ_UNKNOWN)) {
1502                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1503                                                 dev->name, events);
1504                 }
1505                 if (i > max_interrupt_work) {
1506                         spin_lock(&np->lock);
1507                         /* disable interrupts on the nic */
1508                         writel(0, base + NvRegIrqMask);
1509                         pci_push(base);
1510
1511                         if (!np->in_shutdown)
1512                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1513                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1514                         spin_unlock(&np->lock);
1515                         break;
1516                 }
1517
1518         }
1519         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1520
1521         return IRQ_RETVAL(i);
1522 }
1523
1524 static void nv_do_nic_poll(unsigned long data)
1525 {
1526         struct net_device *dev = (struct net_device *) data;
1527         struct fe_priv *np = get_nvpriv(dev);
1528         u8 __iomem *base = get_hwbase(dev);
1529
1530         disable_irq(dev->irq);
1531         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1532         /*
1533          * reenable interrupts on the nic, we have to do this before calling
1534          * nv_nic_irq because that may decide to do otherwise
1535          */
1536         writel(np->irqmask, base + NvRegIrqMask);
1537         pci_push(base);
1538         nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1539         enable_irq(dev->irq);
1540 }
1541
1542 #ifdef CONFIG_NET_POLL_CONTROLLER
1543 static void nv_poll_controller(struct net_device *dev)
1544 {
1545         nv_do_nic_poll((unsigned long) dev);
1546 }
1547 #endif
1548
1549 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1550 {
1551         struct fe_priv *np = get_nvpriv(dev);
1552         strcpy(info->driver, "forcedeth");
1553         strcpy(info->version, FORCEDETH_VERSION);
1554         strcpy(info->bus_info, pci_name(np->pci_dev));
1555 }
1556
1557 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1558 {
1559         struct fe_priv *np = get_nvpriv(dev);
1560         wolinfo->supported = WAKE_MAGIC;
1561
1562         spin_lock_irq(&np->lock);
1563         if (np->wolenabled)
1564                 wolinfo->wolopts = WAKE_MAGIC;
1565         spin_unlock_irq(&np->lock);
1566 }
1567
1568 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1569 {
1570         struct fe_priv *np = get_nvpriv(dev);
1571         u8 __iomem *base = get_hwbase(dev);
1572
1573         spin_lock_irq(&np->lock);
1574         if (wolinfo->wolopts == 0) {
1575                 writel(0, base + NvRegWakeUpFlags);
1576                 np->wolenabled = 0;
1577         }
1578         if (wolinfo->wolopts & WAKE_MAGIC) {
1579                 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
1580                 np->wolenabled = 1;
1581         }
1582         spin_unlock_irq(&np->lock);
1583         return 0;
1584 }
1585
1586 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1587 {
1588         struct fe_priv *np = netdev_priv(dev);
1589         int adv;
1590
1591         spin_lock_irq(&np->lock);
1592         ecmd->port = PORT_MII;
1593         if (!netif_running(dev)) {
1594                 /* We do not track link speed / duplex setting if the
1595                  * interface is disabled. Force a link check */
1596                 nv_update_linkspeed(dev);
1597         }
1598         switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
1599                 case NVREG_LINKSPEED_10:
1600                         ecmd->speed = SPEED_10;
1601                         break;
1602                 case NVREG_LINKSPEED_100:
1603                         ecmd->speed = SPEED_100;
1604                         break;
1605                 case NVREG_LINKSPEED_1000:
1606                         ecmd->speed = SPEED_1000;
1607                         break;
1608         }
1609         ecmd->duplex = DUPLEX_HALF;
1610         if (np->duplex)
1611                 ecmd->duplex = DUPLEX_FULL;
1612
1613         ecmd->autoneg = np->autoneg;
1614
1615         ecmd->advertising = ADVERTISED_MII;
1616         if (np->autoneg) {
1617                 ecmd->advertising |= ADVERTISED_Autoneg;
1618                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1619         } else {
1620                 adv = np->fixed_mode;
1621         }
1622         if (adv & ADVERTISE_10HALF)
1623                 ecmd->advertising |= ADVERTISED_10baseT_Half;
1624         if (adv & ADVERTISE_10FULL)
1625                 ecmd->advertising |= ADVERTISED_10baseT_Full;
1626         if (adv & ADVERTISE_100HALF)
1627                 ecmd->advertising |= ADVERTISED_100baseT_Half;
1628         if (adv & ADVERTISE_100FULL)
1629                 ecmd->advertising |= ADVERTISED_100baseT_Full;
1630         if (np->autoneg && np->gigabit == PHY_GIGABIT) {
1631                 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1632                 if (adv & ADVERTISE_1000FULL)
1633                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
1634         }
1635
1636         ecmd->supported = (SUPPORTED_Autoneg |
1637                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
1638                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1639                 SUPPORTED_MII);
1640         if (np->gigabit == PHY_GIGABIT)
1641                 ecmd->supported |= SUPPORTED_1000baseT_Full;
1642
1643         ecmd->phy_address = np->phyaddr;
1644         ecmd->transceiver = XCVR_EXTERNAL;
1645
1646         /* ignore maxtxpkt, maxrxpkt for now */
1647         spin_unlock_irq(&np->lock);
1648         return 0;
1649 }
1650
1651 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1652 {
1653         struct fe_priv *np = netdev_priv(dev);
1654
1655         if (ecmd->port != PORT_MII)
1656                 return -EINVAL;
1657         if (ecmd->transceiver != XCVR_EXTERNAL)
1658                 return -EINVAL;
1659         if (ecmd->phy_address != np->phyaddr) {
1660                 /* TODO: support switching between multiple phys. Should be
1661                  * trivial, but not enabled due to lack of test hardware. */
1662                 return -EINVAL;
1663         }
1664         if (ecmd->autoneg == AUTONEG_ENABLE) {
1665                 u32 mask;
1666
1667                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1668                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
1669                 if (np->gigabit == PHY_GIGABIT)
1670                         mask |= ADVERTISED_1000baseT_Full;
1671
1672                 if ((ecmd->advertising & mask) == 0)
1673                         return -EINVAL;
1674
1675         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
1676                 /* Note: autonegotiation disable, speed 1000 intentionally
1677                  * forbidden - noone should need that. */
1678
1679                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
1680                         return -EINVAL;
1681                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
1682                         return -EINVAL;
1683         } else {
1684                 return -EINVAL;
1685         }
1686
1687         spin_lock_irq(&np->lock);
1688         if (ecmd->autoneg == AUTONEG_ENABLE) {
1689                 int adv, bmcr;
1690
1691                 np->autoneg = 1;
1692
1693                 /* advertise only what has been requested */
1694                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1695                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1696                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
1697                         adv |= ADVERTISE_10HALF;
1698                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
1699                         adv |= ADVERTISE_10FULL;
1700                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
1701                         adv |= ADVERTISE_100HALF;
1702                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
1703                         adv |= ADVERTISE_100FULL;
1704                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
1705
1706                 if (np->gigabit == PHY_GIGABIT) {
1707                         adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1708                         adv &= ~ADVERTISE_1000FULL;
1709                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
1710                                 adv |= ADVERTISE_1000FULL;
1711                         mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
1712                 }
1713
1714                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1715                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1716                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
1717
1718         } else {
1719                 int adv, bmcr;
1720
1721                 np->autoneg = 0;
1722
1723                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1724                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1725                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
1726                         adv |= ADVERTISE_10HALF;
1727                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
1728                         adv |= ADVERTISE_10FULL;
1729                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
1730                         adv |= ADVERTISE_100HALF;
1731                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
1732                         adv |= ADVERTISE_100FULL;
1733                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
1734                 np->fixed_mode = adv;
1735
1736                 if (np->gigabit == PHY_GIGABIT) {
1737                         adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1738                         adv &= ~ADVERTISE_1000FULL;
1739                         mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
1740                 }
1741
1742                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1743                 bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX);
1744                 if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL))
1745                         bmcr |= BMCR_FULLDPLX;
1746                 if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL))
1747                         bmcr |= BMCR_SPEED100;
1748                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
1749
1750                 if (netif_running(dev)) {
1751                         /* Wait a bit and then reconfigure the nic. */
1752                         udelay(10);
1753                         nv_linkchange(dev);
1754                 }
1755         }
1756         spin_unlock_irq(&np->lock);
1757
1758         return 0;
1759 }
1760
1761 static struct ethtool_ops ops = {
1762         .get_drvinfo = nv_get_drvinfo,
1763         .get_link = ethtool_op_get_link,
1764         .get_wol = nv_get_wol,
1765         .set_wol = nv_set_wol,
1766         .get_settings = nv_get_settings,
1767         .set_settings = nv_set_settings,
1768 };
1769
1770 static int nv_open(struct net_device *dev)
1771 {
1772         struct fe_priv *np = get_nvpriv(dev);
1773         u8 __iomem *base = get_hwbase(dev);
1774         int ret, oom, i;
1775
1776         dprintk(KERN_DEBUG "nv_open: begin\n");
1777
1778         /* 1) erase previous misconfiguration */
1779         /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
1780         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1781         writel(0, base + NvRegMulticastAddrB);
1782         writel(0, base + NvRegMulticastMaskA);
1783         writel(0, base + NvRegMulticastMaskB);
1784         writel(0, base + NvRegPacketFilterFlags);
1785
1786         writel(0, base + NvRegTransmitterControl);
1787         writel(0, base + NvRegReceiverControl);
1788
1789         writel(0, base + NvRegAdapterControl);
1790
1791         /* 2) initialize descriptor rings */
1792         oom = nv_init_ring(dev);
1793
1794         writel(0, base + NvRegLinkSpeed);
1795         writel(0, base + NvRegUnknownTransmitterReg);
1796         nv_txrx_reset(dev);
1797         writel(0, base + NvRegUnknownSetupReg6);
1798
1799         np->in_shutdown = 0;
1800
1801         /* 3) set mac address */
1802         {
1803                 u32 mac[2];
1804
1805                 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1806                                 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1807                 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1808
1809                 writel(mac[0], base + NvRegMacAddrA);
1810                 writel(mac[1], base + NvRegMacAddrB);
1811         }
1812
1813         /* 4) give hw rings */
1814         writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1815         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1816         writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1817                 base + NvRegRingSizes);
1818
1819         /* 5) continue setup */
1820         writel(np->linkspeed, base + NvRegLinkSpeed);
1821         writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
1822         writel(np->desc_ver, base + NvRegTxRxControl);
1823         pci_push(base);
1824         writel(NVREG_TXRXCTL_BIT1|np->desc_ver, base + NvRegTxRxControl);
1825         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
1826                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
1827                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
1828
1829         writel(0, base + NvRegUnknownSetupReg4);
1830         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1831         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1832
1833         /* 6) continue setup */
1834         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
1835         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
1836         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
1837         writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig);
1838
1839         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
1840         get_random_bytes(&i, sizeof(i));
1841         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
1842         writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
1843         writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
1844         writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
1845         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
1846         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
1847                         base + NvRegAdapterControl);
1848         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
1849         writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
1850         writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
1851
1852         i = readl(base + NvRegPowerState);
1853         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
1854                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
1855
1856         pci_push(base);
1857         udelay(10);
1858         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
1859
1860         writel(0, base + NvRegIrqMask);
1861         pci_push(base);
1862         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1863         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1864         pci_push(base);
1865
1866         ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
1867         if (ret)
1868                 goto out_drain;
1869
1870         /* ask for interrupts */
1871         writel(np->irqmask, base + NvRegIrqMask);
1872
1873         spin_lock_irq(&np->lock);
1874         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1875         writel(0, base + NvRegMulticastAddrB);
1876         writel(0, base + NvRegMulticastMaskA);
1877         writel(0, base + NvRegMulticastMaskB);
1878         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
1879         /* One manual link speed update: Interrupts are enabled, future link
1880          * speed changes cause interrupts and are handled by nv_link_irq().
1881          */
1882         {
1883                 u32 miistat;
1884                 miistat = readl(base + NvRegMIIStatus);
1885                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1886                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
1887         }
1888         ret = nv_update_linkspeed(dev);
1889         nv_start_rx(dev);
1890         nv_start_tx(dev);
1891         netif_start_queue(dev);
1892         if (ret) {
1893                 netif_carrier_on(dev);
1894         } else {
1895                 printk("%s: no link during initialization.\n", dev->name);
1896                 netif_carrier_off(dev);
1897         }
1898         if (oom)
1899                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1900         spin_unlock_irq(&np->lock);
1901
1902         return 0;
1903 out_drain:
1904         drain_ring(dev);
1905         return ret;
1906 }
1907
1908 static int nv_close(struct net_device *dev)
1909 {
1910         struct fe_priv *np = get_nvpriv(dev);
1911         u8 __iomem *base;
1912
1913         spin_lock_irq(&np->lock);
1914         np->in_shutdown = 1;
1915         spin_unlock_irq(&np->lock);
1916         synchronize_irq(dev->irq);
1917
1918         del_timer_sync(&np->oom_kick);
1919         del_timer_sync(&np->nic_poll);
1920
1921         netif_stop_queue(dev);
1922         spin_lock_irq(&np->lock);
1923         nv_stop_tx(dev);
1924         nv_stop_rx(dev);
1925         nv_txrx_reset(dev);
1926
1927         /* disable interrupts on the nic or we will lock up */
1928         base = get_hwbase(dev);
1929         writel(0, base + NvRegIrqMask);
1930         pci_push(base);
1931         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
1932
1933         spin_unlock_irq(&np->lock);
1934
1935         free_irq(dev->irq, dev);
1936
1937         drain_ring(dev);
1938
1939         if (np->wolenabled)
1940                 nv_start_rx(dev);
1941
1942         /* FIXME: power down nic */
1943
1944         return 0;
1945 }
1946
1947 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
1948 {
1949         struct net_device *dev;
1950         struct fe_priv *np;
1951         unsigned long addr;
1952         u8 __iomem *base;
1953         int err, i;
1954
1955         dev = alloc_etherdev(sizeof(struct fe_priv));
1956         err = -ENOMEM;
1957         if (!dev)
1958                 goto out;
1959
1960         np = get_nvpriv(dev);
1961         np->pci_dev = pci_dev;
1962         spin_lock_init(&np->lock);
1963         SET_MODULE_OWNER(dev);
1964         SET_NETDEV_DEV(dev, &pci_dev->dev);
1965
1966         init_timer(&np->oom_kick);
1967         np->oom_kick.data = (unsigned long) dev;
1968         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
1969         init_timer(&np->nic_poll);
1970         np->nic_poll.data = (unsigned long) dev;
1971         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
1972
1973         err = pci_enable_device(pci_dev);
1974         if (err) {
1975                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
1976                                 err, pci_name(pci_dev));
1977                 goto out_free;
1978         }
1979
1980         pci_set_master(pci_dev);
1981
1982         err = pci_request_regions(pci_dev, DRV_NAME);
1983         if (err < 0)
1984                 goto out_disable;
1985
1986         err = -EINVAL;
1987         addr = 0;
1988         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1989                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
1990                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
1991                                 pci_resource_len(pci_dev, i),
1992                                 pci_resource_flags(pci_dev, i));
1993                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
1994                                 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
1995                         addr = pci_resource_start(pci_dev, i);
1996                         break;
1997                 }
1998         }
1999         if (i == DEVICE_COUNT_RESOURCE) {
2000                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
2001                                         pci_name(pci_dev));
2002                 goto out_relreg;
2003         }
2004
2005         /* handle different descriptor versions */
2006         if (pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_1 ||
2007                 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_2 ||
2008                 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_3)
2009                 np->desc_ver = DESC_VER_1;
2010         else
2011                 np->desc_ver = DESC_VER_2;
2012
2013         err = -ENOMEM;
2014         np->base = ioremap(addr, NV_PCI_REGSZ);
2015         if (!np->base)
2016                 goto out_relreg;
2017         dev->base_addr = (unsigned long)np->base;
2018         dev->irq = pci_dev->irq;
2019         np->rx_ring = pci_alloc_consistent(pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2020                                                 &np->ring_addr);
2021         if (!np->rx_ring)
2022                 goto out_unmap;
2023         np->tx_ring = &np->rx_ring[RX_RING];
2024
2025         dev->open = nv_open;
2026         dev->stop = nv_close;
2027         dev->hard_start_xmit = nv_start_xmit;
2028         dev->get_stats = nv_get_stats;
2029         dev->change_mtu = nv_change_mtu;
2030         dev->set_multicast_list = nv_set_multicast;
2031 #ifdef CONFIG_NET_POLL_CONTROLLER
2032         dev->poll_controller = nv_poll_controller;
2033 #endif
2034         SET_ETHTOOL_OPS(dev, &ops);
2035         dev->tx_timeout = nv_tx_timeout;
2036         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
2037
2038         pci_set_drvdata(pci_dev, dev);
2039
2040         /* read the mac address */
2041         base = get_hwbase(dev);
2042         np->orig_mac[0] = readl(base + NvRegMacAddrA);
2043         np->orig_mac[1] = readl(base + NvRegMacAddrB);
2044
2045         dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
2046         dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
2047         dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
2048         dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
2049         dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
2050         dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
2051
2052         if (!is_valid_ether_addr(dev->dev_addr)) {
2053                 /*
2054                  * Bad mac address. At least one bios sets the mac address
2055                  * to 01:23:45:67:89:ab
2056                  */
2057                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
2058                         pci_name(pci_dev),
2059                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2060                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2061                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
2062                 dev->dev_addr[0] = 0x00;
2063                 dev->dev_addr[1] = 0x00;
2064                 dev->dev_addr[2] = 0x6c;
2065                 get_random_bytes(&dev->dev_addr[3], 3);
2066         }
2067
2068         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
2069                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2070                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2071
2072         /* disable WOL */
2073         writel(0, base + NvRegWakeUpFlags);
2074         np->wolenabled = 0;
2075
2076         if (np->desc_ver == DESC_VER_1) {
2077                 np->tx_flags = NV_TX_LASTPACKET|NV_TX_VALID;
2078                 if (id->driver_data & DEV_NEED_LASTPACKET1)
2079                         np->tx_flags |= NV_TX_LASTPACKET1;
2080         } else {
2081                 np->tx_flags = NV_TX2_LASTPACKET|NV_TX2_VALID;
2082                 if (id->driver_data & DEV_NEED_LASTPACKET1)
2083                         np->tx_flags |= NV_TX2_LASTPACKET1;
2084         }
2085         if (id->driver_data & DEV_IRQMASK_1)
2086                 np->irqmask = NVREG_IRQMASK_WANTED_1;
2087         if (id->driver_data & DEV_IRQMASK_2)
2088                 np->irqmask = NVREG_IRQMASK_WANTED_2;
2089         if (id->driver_data & DEV_NEED_TIMERIRQ)
2090                 np->irqmask |= NVREG_IRQ_TIMER;
2091         if (id->driver_data & DEV_NEED_LINKTIMER) {
2092                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
2093                 np->need_linktimer = 1;
2094                 np->link_timeout = jiffies + LINK_TIMEOUT;
2095         } else {
2096                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
2097                 np->need_linktimer = 0;
2098         }
2099
2100         /* find a suitable phy */
2101         for (i = 1; i < 32; i++) {
2102                 int id1, id2;
2103
2104                 spin_lock_irq(&np->lock);
2105                 id1 = mii_rw(dev, i, MII_PHYSID1, MII_READ);
2106                 spin_unlock_irq(&np->lock);
2107                 if (id1 < 0 || id1 == 0xffff)
2108                         continue;
2109                 spin_lock_irq(&np->lock);
2110                 id2 = mii_rw(dev, i, MII_PHYSID2, MII_READ);
2111                 spin_unlock_irq(&np->lock);
2112                 if (id2 < 0 || id2 == 0xffff)
2113                         continue;
2114
2115                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
2116                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
2117                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
2118                                 pci_name(pci_dev), id1, id2, i);
2119                 np->phyaddr = i;
2120                 np->phy_oui = id1 | id2;
2121                 break;
2122         }
2123         if (i == 32) {
2124                 /* PHY in isolate mode? No phy attached and user wants to
2125                  * test loopback? Very odd, but can be correct.
2126                  */
2127                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
2128                                 pci_name(pci_dev));
2129         }
2130
2131         if (i != 32) {
2132                 /* reset it */
2133                 phy_init(dev);
2134         }
2135
2136         /* set default link speed settings */
2137         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2138         np->duplex = 0;
2139         np->autoneg = 1;
2140
2141         err = register_netdev(dev);
2142         if (err) {
2143                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
2144                 goto out_freering;
2145         }
2146         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
2147                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
2148                         pci_name(pci_dev));
2149
2150         return 0;
2151
2152 out_freering:
2153         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2154                                 np->rx_ring, np->ring_addr);
2155         pci_set_drvdata(pci_dev, NULL);
2156 out_unmap:
2157         iounmap(get_hwbase(dev));
2158 out_relreg:
2159         pci_release_regions(pci_dev);
2160 out_disable:
2161         pci_disable_device(pci_dev);
2162 out_free:
2163         free_netdev(dev);
2164 out:
2165         return err;
2166 }
2167
2168 static void __devexit nv_remove(struct pci_dev *pci_dev)
2169 {
2170         struct net_device *dev = pci_get_drvdata(pci_dev);
2171         struct fe_priv *np = get_nvpriv(dev);
2172         u8 __iomem *base = get_hwbase(dev);
2173
2174         unregister_netdev(dev);
2175
2176         /* special op: write back the misordered MAC address - otherwise
2177          * the next nv_probe would see a wrong address.
2178          */
2179         writel(np->orig_mac[0], base + NvRegMacAddrA);
2180         writel(np->orig_mac[1], base + NvRegMacAddrB);
2181
2182         /* free all structures */
2183         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring, np->ring_addr);
2184         iounmap(get_hwbase(dev));
2185         pci_release_regions(pci_dev);
2186         pci_disable_device(pci_dev);
2187         free_netdev(dev);
2188         pci_set_drvdata(pci_dev, NULL);
2189 }
2190
2191 static struct pci_device_id pci_tbl[] = {
2192         {       /* nForce Ethernet Controller */
2193                 .vendor = PCI_VENDOR_ID_NVIDIA,
2194                 .device = PCI_DEVICE_ID_NVIDIA_NVENET_1,
2195                 .subvendor = PCI_ANY_ID,
2196                 .subdevice = PCI_ANY_ID,
2197                 .driver_data = DEV_IRQMASK_1|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2198         },
2199         {       /* nForce2 Ethernet Controller */
2200                 .vendor = PCI_VENDOR_ID_NVIDIA,
2201                 .device = PCI_DEVICE_ID_NVIDIA_NVENET_2,
2202                 .subvendor = PCI_ANY_ID,
2203                 .subdevice = PCI_ANY_ID,
2204                 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2205         },
2206         {       /* nForce3 Ethernet Controller */
2207                 .vendor = PCI_VENDOR_ID_NVIDIA,
2208                 .device = PCI_DEVICE_ID_NVIDIA_NVENET_3,
2209                 .subvendor = PCI_ANY_ID,
2210                 .subdevice = PCI_ANY_ID,
2211                 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2212         },
2213         {       /* nForce3 Ethernet Controller */
2214                 .vendor = PCI_VENDOR_ID_NVIDIA,
2215                 .device = PCI_DEVICE_ID_NVIDIA_NVENET_4,
2216                 .subvendor = PCI_ANY_ID,
2217                 .subdevice = PCI_ANY_ID,
2218                 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
2219         },
2220         {       /* nForce3 Ethernet Controller */
2221                 .vendor = PCI_VENDOR_ID_NVIDIA,
2222                 .device = PCI_DEVICE_ID_NVIDIA_NVENET_5,
2223                 .subvendor = PCI_ANY_ID,
2224                 .subdevice = PCI_ANY_ID,
2225                 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
2226         },
2227         {       /* nForce3 Ethernet Controller */
2228                 .vendor = PCI_VENDOR_ID_NVIDIA,
2229                 .device = PCI_DEVICE_ID_NVIDIA_NVENET_6,
2230                 .subvendor = PCI_ANY_ID,
2231                 .subdevice = PCI_ANY_ID,
2232                 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
2233         },
2234         {       /* nForce3 Ethernet Controller */
2235                 .vendor = PCI_VENDOR_ID_NVIDIA,
2236                 .device = PCI_DEVICE_ID_NVIDIA_NVENET_7,
2237                 .subvendor = PCI_ANY_ID,
2238                 .subdevice = PCI_ANY_ID,
2239                 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
2240         },
2241         {       /* CK804 Ethernet Controller */
2242                 .vendor = PCI_VENDOR_ID_NVIDIA,
2243                 .device = PCI_DEVICE_ID_NVIDIA_NVENET_8,
2244                 .subvendor = PCI_ANY_ID,
2245                 .subdevice = PCI_ANY_ID,
2246                 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
2247         },
2248         {       /* CK804 Ethernet Controller */
2249                 .vendor = PCI_VENDOR_ID_NVIDIA,
2250                 .device = PCI_DEVICE_ID_NVIDIA_NVENET_9,
2251                 .subvendor = PCI_ANY_ID,
2252                 .subdevice = PCI_ANY_ID,
2253                 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
2254         },
2255         {       /* MCP04 Ethernet Controller */
2256                 .vendor = PCI_VENDOR_ID_NVIDIA,
2257                 .device = PCI_DEVICE_ID_NVIDIA_NVENET_10,
2258                 .subvendor = PCI_ANY_ID,
2259                 .subdevice = PCI_ANY_ID,
2260                 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
2261         },
2262         {       /* MCP04 Ethernet Controller */
2263                 .vendor = PCI_VENDOR_ID_NVIDIA,
2264                 .device = PCI_DEVICE_ID_NVIDIA_NVENET_11,
2265                 .subvendor = PCI_ANY_ID,
2266                 .subdevice = PCI_ANY_ID,
2267                 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
2268         },
2269         {0,},
2270 };
2271
2272 static struct pci_driver driver = {
2273         .name = "forcedeth",
2274         .id_table = pci_tbl,
2275         .probe = nv_probe,
2276         .remove = __devexit_p(nv_remove),
2277 };
2278
2279
2280 static int __init init_nic(void)
2281 {
2282         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
2283         return pci_module_init(&driver);
2284 }
2285
2286 static void __exit exit_nic(void)
2287 {
2288         pci_unregister_driver(&driver);
2289 }
2290
2291 module_param(max_interrupt_work, int, 0);
2292 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2293
2294 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2295 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2296 MODULE_LICENSE("GPL");
2297
2298 MODULE_DEVICE_TABLE(pci, pci_tbl);
2299
2300 module_init(init_nic);
2301 module_exit(exit_nic);