drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Known bugs:
  33  * We suspect that on some hardware no TX done interrupts are generated.
  34  * This means recovery from netif_stop_queue only happens if the hw timer
  35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  37  * If your hardware reliably generates tx done interrupts, then you can remove
  38  * DEV_NEED_TIMERIRQ from the driver_data flags.
  39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  40  * superfluous timer interrupts from the nic.
  41  */
  42 #define FORCEDETH_VERSION               "0.64"
  43 #define DRV_NAME                        "forcedeth"
  44
  45 #include <linux/module.h>
  46 #include <linux/types.h>
  47 #include <linux/pci.h>
  48 #include <linux/interrupt.h>
  49 #include <linux/netdevice.h>
  50 #include <linux/etherdevice.h>
  51 #include <linux/delay.h>
  52 #include <linux/sched.h>
  53 #include <linux/spinlock.h>
  54 #include <linux/ethtool.h>
  55 #include <linux/timer.h>
  56 #include <linux/skbuff.h>
  57 #include <linux/mii.h>
  58 #include <linux/random.h>
  59 #include <linux/init.h>
  60 #include <linux/if_vlan.h>
  61 #include <linux/dma-mapping.h>
  62
  63 #include <asm/irq.h>
  64 #include <asm/io.h>
  65 #include <asm/uaccess.h>
  66 #include <asm/system.h>
  67
  68 #if 0
  69 #define dprintk                 printk
  70 #else
  71 #define dprintk(x...)           do { } while (0)
  72 #endif
  73
  74 #define TX_WORK_PER_LOOP  64
  75 #define RX_WORK_PER_LOOP  64
  76
  77 /*
  78  * Hardware access:
  79  */
  80
  81 #define DEV_NEED_TIMERIRQ          0x0000001  /* set the timer irq flag in the irq mask */
  82 #define DEV_NEED_LINKTIMER         0x0000002  /* poll link settings. Relies on the timer irq */
  83 #define DEV_HAS_LARGEDESC          0x0000004  /* device supports jumbo frames and needs packet format 2 */
  84 #define DEV_HAS_HIGH_DMA           0x0000008  /* device supports 64bit dma */
  85 #define DEV_HAS_CHECKSUM           0x0000010  /* device supports tx and rx checksum offloads */
  86 #define DEV_HAS_VLAN               0x0000020  /* device supports vlan tagging and striping */
  87 #define DEV_HAS_MSI                0x0000040  /* device supports MSI */
  88 #define DEV_HAS_MSI_X              0x0000080  /* device supports MSI-X */
  89 #define DEV_HAS_POWER_CNTRL        0x0000100  /* device supports power savings */
  90 #define DEV_HAS_STATISTICS_V1      0x0000200  /* device supports hw statistics version 1 */
  91 #define DEV_HAS_STATISTICS_V2      0x0000600  /* device supports hw statistics version 2 */
  92 #define DEV_HAS_STATISTICS_V3      0x0000e00  /* device supports hw statistics version 3 */
  93 #define DEV_HAS_TEST_EXTENDED      0x0001000  /* device supports extended diagnostic test */
  94 #define DEV_HAS_MGMT_UNIT          0x0002000  /* device supports management unit */
  95 #define DEV_HAS_CORRECT_MACADDR    0x0004000  /* device supports correct mac address order */
  96 #define DEV_HAS_COLLISION_FIX      0x0008000  /* device supports tx collision fix */
  97 #define DEV_HAS_PAUSEFRAME_TX_V1   0x0010000  /* device supports tx pause frames version 1 */
  98 #define DEV_HAS_PAUSEFRAME_TX_V2   0x0020000  /* device supports tx pause frames version 2 */
  99 #define DEV_HAS_PAUSEFRAME_TX_V3   0x0040000  /* device supports tx pause frames version 3 */
 100 #define DEV_NEED_TX_LIMIT          0x0080000  /* device needs to limit tx */
 101 #define DEV_NEED_TX_LIMIT2         0x0180000  /* device needs to limit tx, expect for some revs */
 102 #define DEV_HAS_GEAR_MODE          0x0200000  /* device supports gear mode */
 103 #define DEV_NEED_PHY_INIT_FIX      0x0400000  /* device needs specific phy workaround */
 104 #define DEV_NEED_LOW_POWER_FIX     0x0800000  /* device needs special power up workaround */
 105 #define DEV_NEED_MSI_FIX           0x1000000  /* device needs msi workaround */
 106
 107 enum {
 108         NvRegIrqStatus = 0x000,
 109 #define NVREG_IRQSTAT_MIIEVENT  0x040
 110 #define NVREG_IRQSTAT_MASK              0x83ff
 111         NvRegIrqMask = 0x004,
 112 #define NVREG_IRQ_RX_ERROR              0x0001
 113 #define NVREG_IRQ_RX                    0x0002
 114 #define NVREG_IRQ_RX_NOBUF              0x0004
 115 #define NVREG_IRQ_TX_ERR                0x0008
 116 #define NVREG_IRQ_TX_OK                 0x0010
 117 #define NVREG_IRQ_TIMER                 0x0020
 118 #define NVREG_IRQ_LINK                  0x0040
 119 #define NVREG_IRQ_RX_FORCED             0x0080
 120 #define NVREG_IRQ_TX_FORCED             0x0100
 121 #define NVREG_IRQ_RECOVER_ERROR         0x8200
 122 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 123 #define NVREG_IRQMASK_CPU               0x0060
 124 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 125 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 126 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 127
 128         NvRegUnknownSetupReg6 = 0x008,
 129 #define NVREG_UNKSETUP6_VAL             3
 130
 131 /*
 132  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 133  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 134  */
 135         NvRegPollingInterval = 0x00c,
 136 #define NVREG_POLL_DEFAULT_THROUGHPUT   65535 /* backup tx cleanup if loop max reached */
 137 #define NVREG_POLL_DEFAULT_CPU  13
 138         NvRegMSIMap0 = 0x020,
 139         NvRegMSIMap1 = 0x024,
 140         NvRegMSIIrqMask = 0x030,
 141 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 142         NvRegMisc1 = 0x080,
 143 #define NVREG_MISC1_PAUSE_TX    0x01
 144 #define NVREG_MISC1_HD          0x02
 145 #define NVREG_MISC1_FORCE       0x3b0f3c
 146
 147         NvRegMacReset = 0x34,
 148 #define NVREG_MAC_RESET_ASSERT  0x0F3
 149         NvRegTransmitterControl = 0x084,
 150 #define NVREG_XMITCTL_START     0x01
 151 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 152 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 153 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 154 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 155 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 156 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 157 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 158 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 159 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 160 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 161 #define NVREG_XMITCTL_DATA_START        0x00100000
 162 #define NVREG_XMITCTL_DATA_READY        0x00010000
 163 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
 164         NvRegTransmitterStatus = 0x088,
 165 #define NVREG_XMITSTAT_BUSY     0x01
 166
 167         NvRegPacketFilterFlags = 0x8c,
 168 #define NVREG_PFF_PAUSE_RX      0x08
 169 #define NVREG_PFF_ALWAYS        0x7F0000
 170 #define NVREG_PFF_PROMISC       0x80
 171 #define NVREG_PFF_MYADDR        0x20
 172 #define NVREG_PFF_LOOPBACK      0x10
 173
 174         NvRegOffloadConfig = 0x90,
 175 #define NVREG_OFFLOAD_HOMEPHY   0x601
 176 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 177         NvRegReceiverControl = 0x094,
 178 #define NVREG_RCVCTL_START      0x01
 179 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 180         NvRegReceiverStatus = 0x98,
 181 #define NVREG_RCVSTAT_BUSY      0x01
 182
 183         NvRegSlotTime = 0x9c,
 184 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
 185 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
 186 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
 187 #define NVREG_SLOTTIME_HALF             0x0000ff00
 188 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
 189 #define NVREG_SLOTTIME_MASK             0x000000ff
 190
 191         NvRegTxDeferral = 0xA0,
 192 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
 193 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
 194 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
 195 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
 196 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
 197 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
 198         NvRegRxDeferral = 0xA4,
 199 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 200         NvRegMacAddrA = 0xA8,
 201         NvRegMacAddrB = 0xAC,
 202         NvRegMulticastAddrA = 0xB0,
 203 #define NVREG_MCASTADDRA_FORCE  0x01
 204         NvRegMulticastAddrB = 0xB4,
 205         NvRegMulticastMaskA = 0xB8,
 206 #define NVREG_MCASTMASKA_NONE           0xffffffff
 207         NvRegMulticastMaskB = 0xBC,
 208 #define NVREG_MCASTMASKB_NONE           0xffff
 209
 210         NvRegPhyInterface = 0xC0,
 211 #define PHY_RGMII               0x10000000
 212         NvRegBackOffControl = 0xC4,
 213 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
 214 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
 215 #define NVREG_BKOFFCTRL_SELECT                  24
 216 #define NVREG_BKOFFCTRL_GEAR                    12
 217
 218         NvRegTxRingPhysAddr = 0x100,
 219         NvRegRxRingPhysAddr = 0x104,
 220         NvRegRingSizes = 0x108,
 221 #define NVREG_RINGSZ_TXSHIFT 0
 222 #define NVREG_RINGSZ_RXSHIFT 16
 223         NvRegTransmitPoll = 0x10c,
 224 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 225         NvRegLinkSpeed = 0x110,
 226 #define NVREG_LINKSPEED_FORCE 0x10000
 227 #define NVREG_LINKSPEED_10      1000
 228 #define NVREG_LINKSPEED_100     100
 229 #define NVREG_LINKSPEED_1000    50
 230 #define NVREG_LINKSPEED_MASK    (0xFFF)
 231         NvRegUnknownSetupReg5 = 0x130,
 232 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 233         NvRegTxWatermark = 0x13c,
 234 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 235 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 236 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 237         NvRegTxRxControl = 0x144,
 238 #define NVREG_TXRXCTL_KICK      0x0001
 239 #define NVREG_TXRXCTL_BIT1      0x0002
 240 #define NVREG_TXRXCTL_BIT2      0x0004
 241 #define NVREG_TXRXCTL_IDLE      0x0008
 242 #define NVREG_TXRXCTL_RESET     0x0010
 243 #define NVREG_TXRXCTL_RXCHECK   0x0400
 244 #define NVREG_TXRXCTL_DESC_1    0
 245 #define NVREG_TXRXCTL_DESC_2    0x002100
 246 #define NVREG_TXRXCTL_DESC_3    0xc02200
 247 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 248 #define NVREG_TXRXCTL_VLANINS   0x00080
 249         NvRegTxRingPhysAddrHigh = 0x148,
 250         NvRegRxRingPhysAddrHigh = 0x14C,
 251         NvRegTxPauseFrame = 0x170,
 252 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
 253 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
 254 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
 255 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
 256         NvRegTxPauseFrameLimit = 0x174,
 257 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
 258         NvRegMIIStatus = 0x180,
 259 #define NVREG_MIISTAT_ERROR             0x0001
 260 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 261 #define NVREG_MIISTAT_MASK_RW           0x0007
 262 #define NVREG_MIISTAT_MASK_ALL          0x000f
 263         NvRegMIIMask = 0x184,
 264 #define NVREG_MII_LINKCHANGE            0x0008
 265
 266         NvRegAdapterControl = 0x188,
 267 #define NVREG_ADAPTCTL_START    0x02
 268 #define NVREG_ADAPTCTL_LINKUP   0x04
 269 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 270 #define NVREG_ADAPTCTL_RUNNING  0x100000
 271 #define NVREG_ADAPTCTL_PHYSHIFT 24
 272         NvRegMIISpeed = 0x18c,
 273 #define NVREG_MIISPEED_BIT8     (1<<8)
 274 #define NVREG_MIIDELAY  5
 275         NvRegMIIControl = 0x190,
 276 #define NVREG_MIICTL_INUSE      0x08000
 277 #define NVREG_MIICTL_WRITE      0x00400
 278 #define NVREG_MIICTL_ADDRSHIFT  5
 279         NvRegMIIData = 0x194,
 280         NvRegTxUnicast = 0x1a0,
 281         NvRegTxMulticast = 0x1a4,
 282         NvRegTxBroadcast = 0x1a8,
 283         NvRegWakeUpFlags = 0x200,
 284 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 285 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 286 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 287 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 288 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 289 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 290 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 291 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 292 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 293 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 294 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 295
 296         NvRegMgmtUnitGetVersion = 0x204,
 297 #define NVREG_MGMTUNITGETVERSION        0x01
 298         NvRegMgmtUnitVersion = 0x208,
 299 #define NVREG_MGMTUNITVERSION           0x08
 300         NvRegPowerCap = 0x268,
 301 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 302 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 303 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 304         NvRegPowerState = 0x26c,
 305 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 306 #define NVREG_POWERSTATE_VALID          0x0100
 307 #define NVREG_POWERSTATE_MASK           0x0003
 308 #define NVREG_POWERSTATE_D0             0x0000
 309 #define NVREG_POWERSTATE_D1             0x0001
 310 #define NVREG_POWERSTATE_D2             0x0002
 311 #define NVREG_POWERSTATE_D3             0x0003
 312         NvRegMgmtUnitControl = 0x278,
 313 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
 314         NvRegTxCnt = 0x280,
 315         NvRegTxZeroReXmt = 0x284,
 316         NvRegTxOneReXmt = 0x288,
 317         NvRegTxManyReXmt = 0x28c,
 318         NvRegTxLateCol = 0x290,
 319         NvRegTxUnderflow = 0x294,
 320         NvRegTxLossCarrier = 0x298,
 321         NvRegTxExcessDef = 0x29c,
 322         NvRegTxRetryErr = 0x2a0,
 323         NvRegRxFrameErr = 0x2a4,
 324         NvRegRxExtraByte = 0x2a8,
 325         NvRegRxLateCol = 0x2ac,
 326         NvRegRxRunt = 0x2b0,
 327         NvRegRxFrameTooLong = 0x2b4,
 328         NvRegRxOverflow = 0x2b8,
 329         NvRegRxFCSErr = 0x2bc,
 330         NvRegRxFrameAlignErr = 0x2c0,
 331         NvRegRxLenErr = 0x2c4,
 332         NvRegRxUnicast = 0x2c8,
 333         NvRegRxMulticast = 0x2cc,
 334         NvRegRxBroadcast = 0x2d0,
 335         NvRegTxDef = 0x2d4,
 336         NvRegTxFrame = 0x2d8,
 337         NvRegRxCnt = 0x2dc,
 338         NvRegTxPause = 0x2e0,
 339         NvRegRxPause = 0x2e4,
 340         NvRegRxDropFrame = 0x2e8,
 341         NvRegVlanControl = 0x300,
 342 #define NVREG_VLANCONTROL_ENABLE        0x2000
 343         NvRegMSIXMap0 = 0x3e0,
 344         NvRegMSIXMap1 = 0x3e4,
 345         NvRegMSIXIrqStatus = 0x3f0,
 346
 347         NvRegPowerState2 = 0x600,
 348 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
 349 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 350 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
 351 #define NVREG_POWERSTATE2_GATE_CLOCKS           0x0F00
 352 };
 353
 354 /* Big endian: should work, but is untested */
 355 struct ring_desc {
 356         __le32 buf;
 357         __le32 flaglen;
 358 };
 359
 360 struct ring_desc_ex {
 361         __le32 bufhigh;
 362         __le32 buflow;
 363         __le32 txvlan;
 364         __le32 flaglen;
 365 };
 366
 367 union ring_type {
 368         struct ring_desc* orig;
 369         struct ring_desc_ex* ex;
 370 };
 371
 372 #define FLAG_MASK_V1 0xffff0000
 373 #define FLAG_MASK_V2 0xffffc000
 374 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 375 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 376
 377 #define NV_TX_LASTPACKET        (1<<16)
 378 #define NV_TX_RETRYERROR        (1<<19)
 379 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
 380 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 381 #define NV_TX_DEFERRED          (1<<26)
 382 #define NV_TX_CARRIERLOST       (1<<27)
 383 #define NV_TX_LATECOLLISION     (1<<28)
 384 #define NV_TX_UNDERFLOW         (1<<29)
 385 #define NV_TX_ERROR             (1<<30)
 386 #define NV_TX_VALID             (1<<31)
 387
 388 #define NV_TX2_LASTPACKET       (1<<29)
 389 #define NV_TX2_RETRYERROR       (1<<18)
 390 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
 391 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 392 #define NV_TX2_DEFERRED         (1<<25)
 393 #define NV_TX2_CARRIERLOST      (1<<26)
 394 #define NV_TX2_LATECOLLISION    (1<<27)
 395 #define NV_TX2_UNDERFLOW        (1<<28)
 396 /* error and valid are the same for both */
 397 #define NV_TX2_ERROR            (1<<30)
 398 #define NV_TX2_VALID            (1<<31)
 399 #define NV_TX2_TSO              (1<<28)
 400 #define NV_TX2_TSO_SHIFT        14
 401 #define NV_TX2_TSO_MAX_SHIFT    14
 402 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 403 #define NV_TX2_CHECKSUM_L3      (1<<27)
 404 #define NV_TX2_CHECKSUM_L4      (1<<26)
 405
 406 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 407
 408 #define NV_RX_DESCRIPTORVALID   (1<<16)
 409 #define NV_RX_MISSEDFRAME       (1<<17)
 410 #define NV_RX_SUBSTRACT1        (1<<18)
 411 #define NV_RX_ERROR1            (1<<23)
 412 #define NV_RX_ERROR2            (1<<24)
 413 #define NV_RX_ERROR3            (1<<25)
 414 #define NV_RX_ERROR4            (1<<26)
 415 #define NV_RX_CRCERR            (1<<27)
 416 #define NV_RX_OVERFLOW          (1<<28)
 417 #define NV_RX_FRAMINGERR        (1<<29)
 418 #define NV_RX_ERROR             (1<<30)
 419 #define NV_RX_AVAIL             (1<<31)
 420 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
 421
 422 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 423 #define NV_RX2_CHECKSUM_IP      (0x10000000)
 424 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
 425 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
 426 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 427 #define NV_RX2_SUBSTRACT1       (1<<25)
 428 #define NV_RX2_ERROR1           (1<<18)
 429 #define NV_RX2_ERROR2           (1<<19)
 430 #define NV_RX2_ERROR3           (1<<20)
 431 #define NV_RX2_ERROR4           (1<<21)
 432 #define NV_RX2_CRCERR           (1<<22)
 433 #define NV_RX2_OVERFLOW         (1<<23)
 434 #define NV_RX2_FRAMINGERR       (1<<24)
 435 /* error and avail are the same for both */
 436 #define NV_RX2_ERROR            (1<<30)
 437 #define NV_RX2_AVAIL            (1<<31)
 438 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
 439
 440 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 441 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 442
 443 /* Miscelaneous hardware related defines: */
 444 #define NV_PCI_REGSZ_VER1       0x270
 445 #define NV_PCI_REGSZ_VER2       0x2d4
 446 #define NV_PCI_REGSZ_VER3       0x604
 447 #define NV_PCI_REGSZ_MAX        0x604
 448
 449 /* various timeout delays: all in usec */
 450 #define NV_TXRX_RESET_DELAY     4
 451 #define NV_TXSTOP_DELAY1        10
 452 #define NV_TXSTOP_DELAY1MAX     500000
 453 #define NV_TXSTOP_DELAY2        100
 454 #define NV_RXSTOP_DELAY1        10
 455 #define NV_RXSTOP_DELAY1MAX     500000
 456 #define NV_RXSTOP_DELAY2        100
 457 #define NV_SETUP5_DELAY         5
 458 #define NV_SETUP5_DELAYMAX      50000
 459 #define NV_POWERUP_DELAY        5
 460 #define NV_POWERUP_DELAYMAX     5000
 461 #define NV_MIIBUSY_DELAY        50
 462 #define NV_MIIPHY_DELAY 10
 463 #define NV_MIIPHY_DELAYMAX      10000
 464 #define NV_MAC_RESET_DELAY      64
 465
 466 #define NV_WAKEUPPATTERNS       5
 467 #define NV_WAKEUPMASKENTRIES    4
 468
 469 /* General driver defaults */
 470 #define NV_WATCHDOG_TIMEO       (5*HZ)
 471
 472 #define RX_RING_DEFAULT         512
 473 #define TX_RING_DEFAULT         256
 474 #define RX_RING_MIN             128
 475 #define TX_RING_MIN             64
 476 #define RING_MAX_DESC_VER_1     1024
 477 #define RING_MAX_DESC_VER_2_3   16384
 478
 479 /* rx/tx mac addr + type + vlan + align + slack*/
 480 #define NV_RX_HEADERS           (64)
 481 /* even more slack. */
 482 #define NV_RX_ALLOC_PAD         (64)
 483
 484 /* maximum mtu size */
 485 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 486 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 487
 488 #define OOM_REFILL      (1+HZ/20)
 489 #define POLL_WAIT       (1+HZ/100)
 490 #define LINK_TIMEOUT    (3*HZ)
 491 #define STATS_INTERVAL  (10*HZ)
 492
 493 /*
 494  * desc_ver values:
 495  * The nic supports three different descriptor types:
 496  * - DESC_VER_1: Original
 497  * - DESC_VER_2: support for jumbo frames.
 498  * - DESC_VER_3: 64-bit format.
 499  */
 500 #define DESC_VER_1      1
 501 #define DESC_VER_2      2
 502 #define DESC_VER_3      3
 503
 504 /* PHY defines */
 505 #define PHY_OUI_MARVELL         0x5043
 506 #define PHY_OUI_CICADA          0x03f1
 507 #define PHY_OUI_VITESSE         0x01c1
 508 #define PHY_OUI_REALTEK         0x0732
 509 #define PHY_OUI_REALTEK2        0x0020
 510 #define PHYID1_OUI_MASK 0x03ff
 511 #define PHYID1_OUI_SHFT 6
 512 #define PHYID2_OUI_MASK 0xfc00
 513 #define PHYID2_OUI_SHFT 10
 514 #define PHYID2_MODEL_MASK               0x03f0
 515 #define PHY_MODEL_REALTEK_8211          0x0110
 516 #define PHY_REV_MASK                    0x0001
 517 #define PHY_REV_REALTEK_8211B           0x0000
 518 #define PHY_REV_REALTEK_8211C           0x0001
 519 #define PHY_MODEL_REALTEK_8201          0x0200
 520 #define PHY_MODEL_MARVELL_E3016         0x0220
 521 #define PHY_MARVELL_E3016_INITMASK      0x0300
 522 #define PHY_CICADA_INIT1        0x0f000
 523 #define PHY_CICADA_INIT2        0x0e00
 524 #define PHY_CICADA_INIT3        0x01000
 525 #define PHY_CICADA_INIT4        0x0200
 526 #define PHY_CICADA_INIT5        0x0004
 527 #define PHY_CICADA_INIT6        0x02000
 528 #define PHY_VITESSE_INIT_REG1   0x1f
 529 #define PHY_VITESSE_INIT_REG2   0x10
 530 #define PHY_VITESSE_INIT_REG3   0x11
 531 #define PHY_VITESSE_INIT_REG4   0x12
 532 #define PHY_VITESSE_INIT_MSK1   0xc
 533 #define PHY_VITESSE_INIT_MSK2   0x0180
 534 #define PHY_VITESSE_INIT1       0x52b5
 535 #define PHY_VITESSE_INIT2       0xaf8a
 536 #define PHY_VITESSE_INIT3       0x8
 537 #define PHY_VITESSE_INIT4       0x8f8a
 538 #define PHY_VITESSE_INIT5       0xaf86
 539 #define PHY_VITESSE_INIT6       0x8f86
 540 #define PHY_VITESSE_INIT7       0xaf82
 541 #define PHY_VITESSE_INIT8       0x0100
 542 #define PHY_VITESSE_INIT9       0x8f82
 543 #define PHY_VITESSE_INIT10      0x0
 544 #define PHY_REALTEK_INIT_REG1   0x1f
 545 #define PHY_REALTEK_INIT_REG2   0x19
 546 #define PHY_REALTEK_INIT_REG3   0x13
 547 #define PHY_REALTEK_INIT_REG4   0x14
 548 #define PHY_REALTEK_INIT_REG5   0x18
 549 #define PHY_REALTEK_INIT_REG6   0x11
 550 #define PHY_REALTEK_INIT_REG7   0x01
 551 #define PHY_REALTEK_INIT1       0x0000
 552 #define PHY_REALTEK_INIT2       0x8e00
 553 #define PHY_REALTEK_INIT3       0x0001
 554 #define PHY_REALTEK_INIT4       0xad17
 555 #define PHY_REALTEK_INIT5       0xfb54
 556 #define PHY_REALTEK_INIT6       0xf5c7
 557 #define PHY_REALTEK_INIT7       0x1000
 558 #define PHY_REALTEK_INIT8       0x0003
 559 #define PHY_REALTEK_INIT9       0x0008
 560 #define PHY_REALTEK_INIT10      0x0005
 561 #define PHY_REALTEK_INIT11      0x0200
 562 #define PHY_REALTEK_INIT_MSK1   0x0003
 563
 564 #define PHY_GIGABIT     0x0100
 565
 566 #define PHY_TIMEOUT     0x1
 567 #define PHY_ERROR       0x2
 568
 569 #define PHY_100 0x1
 570 #define PHY_1000        0x2
 571 #define PHY_HALF        0x100
 572
 573 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 574 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 575 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 576 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 577 #define NV_PAUSEFRAME_RX_REQ     0x0010
 578 #define NV_PAUSEFRAME_TX_REQ     0x0020
 579 #define NV_PAUSEFRAME_AUTONEG    0x0040
 580
 581 /* MSI/MSI-X defines */
 582 #define NV_MSI_X_MAX_VECTORS  8
 583 #define NV_MSI_X_VECTORS_MASK 0x000f
 584 #define NV_MSI_CAPABLE        0x0010
 585 #define NV_MSI_X_CAPABLE      0x0020
 586 #define NV_MSI_ENABLED        0x0040
 587 #define NV_MSI_X_ENABLED      0x0080
 588
 589 #define NV_MSI_X_VECTOR_ALL   0x0
 590 #define NV_MSI_X_VECTOR_RX    0x0
 591 #define NV_MSI_X_VECTOR_TX    0x1
 592 #define NV_MSI_X_VECTOR_OTHER 0x2
 593
 594 #define NV_MSI_PRIV_OFFSET 0x68
 595 #define NV_MSI_PRIV_VALUE  0xffffffff
 596
 597 #define NV_RESTART_TX         0x1
 598 #define NV_RESTART_RX         0x2
 599
 600 #define NV_TX_LIMIT_COUNT     16
 601
 602 #define NV_DYNAMIC_THRESHOLD        4
 603 #define NV_DYNAMIC_MAX_QUIET_COUNT  2048
 604
 605 /* statistics */
 606 struct nv_ethtool_str {
 607         char name[ETH_GSTRING_LEN];
 608 };
 609
 610 static const struct nv_ethtool_str nv_estats_str[] = {
 611         { "tx_bytes" },
 612         { "tx_zero_rexmt" },
 613         { "tx_one_rexmt" },
 614         { "tx_many_rexmt" },
 615         { "tx_late_collision" },
 616         { "tx_fifo_errors" },
 617         { "tx_carrier_errors" },
 618         { "tx_excess_deferral" },
 619         { "tx_retry_error" },
 620         { "rx_frame_error" },
 621         { "rx_extra_byte" },
 622         { "rx_late_collision" },
 623         { "rx_runt" },
 624         { "rx_frame_too_long" },
 625         { "rx_over_errors" },
 626         { "rx_crc_errors" },
 627         { "rx_frame_align_error" },
 628         { "rx_length_error" },
 629         { "rx_unicast" },
 630         { "rx_multicast" },
 631         { "rx_broadcast" },
 632         { "rx_packets" },
 633         { "rx_errors_total" },
 634         { "tx_errors_total" },
 635
 636         /* version 2 stats */
 637         { "tx_deferral" },
 638         { "tx_packets" },
 639         { "rx_bytes" },
 640         { "tx_pause" },
 641         { "rx_pause" },
 642         { "rx_drop_frame" },
 643
 644         /* version 3 stats */
 645         { "tx_unicast" },
 646         { "tx_multicast" },
 647         { "tx_broadcast" }
 648 };
 649
 650 struct nv_ethtool_stats {
 651         u64 tx_bytes;
 652         u64 tx_zero_rexmt;
 653         u64 tx_one_rexmt;
 654         u64 tx_many_rexmt;
 655         u64 tx_late_collision;
 656         u64 tx_fifo_errors;
 657         u64 tx_carrier_errors;
 658         u64 tx_excess_deferral;
 659         u64 tx_retry_error;
 660         u64 rx_frame_error;
 661         u64 rx_extra_byte;
 662         u64 rx_late_collision;
 663         u64 rx_runt;
 664         u64 rx_frame_too_long;
 665         u64 rx_over_errors;
 666         u64 rx_crc_errors;
 667         u64 rx_frame_align_error;
 668         u64 rx_length_error;
 669         u64 rx_unicast;
 670         u64 rx_multicast;
 671         u64 rx_broadcast;
 672         u64 rx_packets;
 673         u64 rx_errors_total;
 674         u64 tx_errors_total;
 675
 676         /* version 2 stats */
 677         u64 tx_deferral;
 678         u64 tx_packets;
 679         u64 rx_bytes;
 680         u64 tx_pause;
 681         u64 rx_pause;
 682         u64 rx_drop_frame;
 683
 684         /* version 3 stats */
 685         u64 tx_unicast;
 686         u64 tx_multicast;
 687         u64 tx_broadcast;
 688 };
 689
 690 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 691 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
 692 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 693
 694 /* diagnostics */
 695 #define NV_TEST_COUNT_BASE 3
 696 #define NV_TEST_COUNT_EXTENDED 4
 697
 698 static const struct nv_ethtool_str nv_etests_str[] = {
 699         { "link      (online/offline)" },
 700         { "register  (offline)       " },
 701         { "interrupt (offline)       " },
 702         { "loopback  (offline)       " }
 703 };
 704
 705 struct register_test {
 706         __u32 reg;
 707         __u32 mask;
 708 };
 709
 710 static const struct register_test nv_registers_test[] = {
 711         { NvRegUnknownSetupReg6, 0x01 },
 712         { NvRegMisc1, 0x03c },
 713         { NvRegOffloadConfig, 0x03ff },
 714         { NvRegMulticastAddrA, 0xffffffff },
 715         { NvRegTxWatermark, 0x0ff },
 716         { NvRegWakeUpFlags, 0x07777 },
 717         { 0,0 }
 718 };
 719
 720 struct nv_skb_map {
 721         struct sk_buff *skb;
 722         dma_addr_t dma;
 723         unsigned int dma_len:31;
 724         unsigned int dma_single:1;
 725         struct ring_desc_ex *first_tx_desc;
 726         struct nv_skb_map *next_tx_ctx;
 727 };
 728
 729 /*
 730  * SMP locking:
 731  * All hardware access under netdev_priv(dev)->lock, except the performance
 732  * critical parts:
 733  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 734  *      by the arch code for interrupts.
 735  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 736  *      needs netdev_priv(dev)->lock :-(
 737  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 738  */
 739
 740 /* in dev: base, irq */
 741 struct fe_priv {
 742         spinlock_t lock;
 743
 744         struct net_device *dev;
 745         struct napi_struct napi;
 746
 747         /* General data:
 748          * Locking: spin_lock(&np->lock); */
 749         struct nv_ethtool_stats estats;
 750         int in_shutdown;
 751         u32 linkspeed;
 752         int duplex;
 753         int autoneg;
 754         int fixed_mode;
 755         int phyaddr;
 756         int wolenabled;
 757         unsigned int phy_oui;
 758         unsigned int phy_model;
 759         unsigned int phy_rev;
 760         u16 gigabit;
 761         int intr_test;
 762         int recover_error;
 763         int quiet_count;
 764
 765         /* General data: RO fields */
 766         dma_addr_t ring_addr;
 767         struct pci_dev *pci_dev;
 768         u32 orig_mac[2];
 769         u32 events;
 770         u32 irqmask;
 771         u32 desc_ver;
 772         u32 txrxctl_bits;
 773         u32 vlanctl_bits;
 774         u32 driver_data;
 775         u32 device_id;
 776         u32 register_size;
 777         int rx_csum;
 778         u32 mac_in_use;
 779         int mgmt_version;
 780         int mgmt_sema;
 781
 782         void __iomem *base;
 783
 784         /* rx specific fields.
 785          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 786          */
 787         union ring_type get_rx, put_rx, first_rx, last_rx;
 788         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 789         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 790         struct nv_skb_map *rx_skb;
 791
 792         union ring_type rx_ring;
 793         unsigned int rx_buf_sz;
 794         unsigned int pkt_limit;
 795         struct timer_list oom_kick;
 796         struct timer_list nic_poll;
 797         struct timer_list stats_poll;
 798         u32 nic_poll_irq;
 799         int rx_ring_size;
 800
 801         /* media detection workaround.
 802          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 803          */
 804         int need_linktimer;
 805         unsigned long link_timeout;
 806         /*
 807          * tx specific fields.
 808          */
 809         union ring_type get_tx, put_tx, first_tx, last_tx;
 810         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 811         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 812         struct nv_skb_map *tx_skb;
 813
 814         union ring_type tx_ring;
 815         u32 tx_flags;
 816         int tx_ring_size;
 817         int tx_limit;
 818         u32 tx_pkts_in_progress;
 819         struct nv_skb_map *tx_change_owner;
 820         struct nv_skb_map *tx_end_flip;
 821         int tx_stop;
 822
 823         /* vlan fields */
 824         struct vlan_group *vlangrp;
 825
 826         /* msi/msi-x fields */
 827         u32 msi_flags;
 828         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 829
 830         /* flow control */
 831         u32 pause_flags;
 832
 833         /* power saved state */
 834         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
 835
 836         /* for different msi-x irq type */
 837         char name_rx[IFNAMSIZ + 3];       /* -rx    */
 838         char name_tx[IFNAMSIZ + 3];       /* -tx    */
 839         char name_other[IFNAMSIZ + 6];    /* -other */
 840 };
 841
 842 /*
 843  * Maximum number of loops until we assume that a bit in the irq mask
 844  * is stuck. Overridable with module param.
 845  */
 846 static int max_interrupt_work = 4;
 847
 848 /*
 849  * Optimization can be either throuput mode or cpu mode
 850  *
 851  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 852  * CPU Mode: Interrupts are controlled by a timer.
 853  */
 854 enum {
 855         NV_OPTIMIZATION_MODE_THROUGHPUT,
 856         NV_OPTIMIZATION_MODE_CPU,
 857         NV_OPTIMIZATION_MODE_DYNAMIC
 858 };
 859 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
 860
 861 /*
 862  * Poll interval for timer irq
 863  *
 864  * This interval determines how frequent an interrupt is generated.
 865  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 866  * Min = 0, and Max = 65535
 867  */
 868 static int poll_interval = -1;
 869
 870 /*
 871  * MSI interrupts
 872  */
 873 enum {
 874         NV_MSI_INT_DISABLED,
 875         NV_MSI_INT_ENABLED
 876 };
 877 static int msi = NV_MSI_INT_ENABLED;
 878
 879 /*
 880  * MSIX interrupts
 881  */
 882 enum {
 883         NV_MSIX_INT_DISABLED,
 884         NV_MSIX_INT_ENABLED
 885 };
 886 static int msix = NV_MSIX_INT_ENABLED;
 887
 888 /*
 889  * DMA 64bit
 890  */
 891 enum {
 892         NV_DMA_64BIT_DISABLED,
 893         NV_DMA_64BIT_ENABLED
 894 };
 895 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 896
 897 /*
 898  * Crossover Detection
 899  * Realtek 8201 phy + some OEM boards do not work properly.
 900  */
 901 enum {
 902         NV_CROSSOVER_DETECTION_DISABLED,
 903         NV_CROSSOVER_DETECTION_ENABLED
 904 };
 905 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
 906
 907 /*
 908  * Power down phy when interface is down (persists through reboot;
 909  * older Linux and other OSes may not power it up again)
 910  */
 911 static int phy_power_down = 0;
 912
 913 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 914 {
 915         return netdev_priv(dev);
 916 }
 917
 918 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 919 {
 920         return ((struct fe_priv *)netdev_priv(dev))->base;
 921 }
 922
 923 static inline void pci_push(u8 __iomem *base)
 924 {
 925         /* force out pending posted writes */
 926         readl(base);
 927 }
 928
 929 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 930 {
 931         return le32_to_cpu(prd->flaglen)
 932                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 933 }
 934
 935 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 936 {
 937         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 938 }
 939
 940 static bool nv_optimized(struct fe_priv *np)
 941 {
 942         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 943                 return false;
 944         return true;
 945 }
 946
 947 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 948                                 int delay, int delaymax, const char *msg)
 949 {
 950         u8 __iomem *base = get_hwbase(dev);
 951
 952         pci_push(base);
 953         do {
 954                 udelay(delay);
 955                 delaymax -= delay;
 956                 if (delaymax < 0) {
 957                         if (msg)
 958                                 printk("%s", msg);
 959                         return 1;
 960                 }
 961         } while ((readl(base + offset) & mask) != target);
 962         return 0;
 963 }
 964
 965 #define NV_SETUP_RX_RING 0x01
 966 #define NV_SETUP_TX_RING 0x02
 967
 968 static inline u32 dma_low(dma_addr_t addr)
 969 {
 970         return addr;
 971 }
 972
 973 static inline u32 dma_high(dma_addr_t addr)
 974 {
 975         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
 976 }
 977
 978 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 979 {
 980         struct fe_priv *np = get_nvpriv(dev);
 981         u8 __iomem *base = get_hwbase(dev);
 982
 983         if (!nv_optimized(np)) {
 984                 if (rxtx_flags & NV_SETUP_RX_RING) {
 985                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 986                 }
 987                 if (rxtx_flags & NV_SETUP_TX_RING) {
 988                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 989                 }
 990         } else {
 991                 if (rxtx_flags & NV_SETUP_RX_RING) {
 992                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 993                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
 994                 }
 995                 if (rxtx_flags & NV_SETUP_TX_RING) {
 996                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 997                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
 998                 }
 999         }
1000 }
1001
1002 static void free_rings(struct net_device *dev)
1003 {
1004         struct fe_priv *np = get_nvpriv(dev);
1005
1006         if (!nv_optimized(np)) {
1007                 if (np->rx_ring.orig)
1008                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1009                                             np->rx_ring.orig, np->ring_addr);
1010         } else {
1011                 if (np->rx_ring.ex)
1012                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1013                                             np->rx_ring.ex, np->ring_addr);
1014         }
1015         if (np->rx_skb)
1016                 kfree(np->rx_skb);
1017         if (np->tx_skb)
1018                 kfree(np->tx_skb);
1019 }
1020
1021 static int using_multi_irqs(struct net_device *dev)
1022 {
1023         struct fe_priv *np = get_nvpriv(dev);
1024
1025         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1026             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1027              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1028                 return 0;
1029         else
1030                 return 1;
1031 }
1032
1033 static void nv_txrx_gate(struct net_device *dev, bool gate)
1034 {
1035         struct fe_priv *np = get_nvpriv(dev);
1036         u8 __iomem *base = get_hwbase(dev);
1037         u32 powerstate;
1038
1039         if (!np->mac_in_use &&
1040             (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1041                 powerstate = readl(base + NvRegPowerState2);
1042                 if (gate)
1043                         powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1044                 else
1045                         powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1046                 writel(powerstate, base + NvRegPowerState2);
1047         }
1048 }
1049
1050 static void nv_enable_irq(struct net_device *dev)
1051 {
1052         struct fe_priv *np = get_nvpriv(dev);
1053
1054         if (!using_multi_irqs(dev)) {
1055                 if (np->msi_flags & NV_MSI_X_ENABLED)
1056                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1057                 else
1058                         enable_irq(np->pci_dev->irq);
1059         } else {
1060                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1061                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1062                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1063         }
1064 }
1065
1066 static void nv_disable_irq(struct net_device *dev)
1067 {
1068         struct fe_priv *np = get_nvpriv(dev);
1069
1070         if (!using_multi_irqs(dev)) {
1071                 if (np->msi_flags & NV_MSI_X_ENABLED)
1072                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1073                 else
1074                         disable_irq(np->pci_dev->irq);
1075         } else {
1076                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1077                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1078                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1079         }
1080 }
1081
1082 /* In MSIX mode, a write to irqmask behaves as XOR */
1083 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1084 {
1085         u8 __iomem *base = get_hwbase(dev);
1086
1087         writel(mask, base + NvRegIrqMask);
1088 }
1089
1090 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1091 {
1092         struct fe_priv *np = get_nvpriv(dev);
1093         u8 __iomem *base = get_hwbase(dev);
1094
1095         if (np->msi_flags & NV_MSI_X_ENABLED) {
1096                 writel(mask, base + NvRegIrqMask);
1097         } else {
1098                 if (np->msi_flags & NV_MSI_ENABLED)
1099                         writel(0, base + NvRegMSIIrqMask);
1100                 writel(0, base + NvRegIrqMask);
1101         }
1102 }
1103
1104 static void nv_napi_enable(struct net_device *dev)
1105 {
1106 #ifdef CONFIG_FORCEDETH_NAPI
1107         struct fe_priv *np = get_nvpriv(dev);
1108
1109         napi_enable(&np->napi);
1110 #endif
1111 }
1112
1113 static void nv_napi_disable(struct net_device *dev)
1114 {
1115 #ifdef CONFIG_FORCEDETH_NAPI
1116         struct fe_priv *np = get_nvpriv(dev);
1117
1118         napi_disable(&np->napi);
1119 #endif
1120 }
1121
1122 #define MII_READ        (-1)
1123 /* mii_rw: read/write a register on the PHY.
1124  *
1125  * Caller must guarantee serialization
1126  */
1127 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1128 {
1129         u8 __iomem *base = get_hwbase(dev);
1130         u32 reg;
1131         int retval;
1132
1133         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1134
1135         reg = readl(base + NvRegMIIControl);
1136         if (reg & NVREG_MIICTL_INUSE) {
1137                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1138                 udelay(NV_MIIBUSY_DELAY);
1139         }
1140
1141         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1142         if (value != MII_READ) {
1143                 writel(value, base + NvRegMIIData);
1144                 reg |= NVREG_MIICTL_WRITE;
1145         }
1146         writel(reg, base + NvRegMIIControl);
1147
1148         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1149                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1150                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1151                                 dev->name, miireg, addr);
1152                 retval = -1;
1153         } else if (value != MII_READ) {
1154                 /* it was a write operation - fewer failures are detectable */
1155                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1156                                 dev->name, value, miireg, addr);
1157                 retval = 0;
1158         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1159                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1160                                 dev->name, miireg, addr);
1161                 retval = -1;
1162         } else {
1163                 retval = readl(base + NvRegMIIData);
1164                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1165                                 dev->name, miireg, addr, retval);
1166         }
1167
1168         return retval;
1169 }
1170
1171 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1172 {
1173         struct fe_priv *np = netdev_priv(dev);
1174         u32 miicontrol;
1175         unsigned int tries = 0;
1176
1177         miicontrol = BMCR_RESET | bmcr_setup;
1178         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1179                 return -1;
1180         }
1181
1182         /* wait for 500ms */
1183         msleep(500);
1184
1185         /* must wait till reset is deasserted */
1186         while (miicontrol & BMCR_RESET) {
1187                 msleep(10);
1188                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1189                 /* FIXME: 100 tries seem excessive */
1190                 if (tries++ > 100)
1191                         return -1;
1192         }
1193         return 0;
1194 }
1195
1196 static int phy_init(struct net_device *dev)
1197 {
1198         struct fe_priv *np = get_nvpriv(dev);
1199         u8 __iomem *base = get_hwbase(dev);
1200         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1201
1202         /* phy errata for E3016 phy */
1203         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1204                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1205                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1206                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1207                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1208                         return PHY_ERROR;
1209                 }
1210         }
1211         if (np->phy_oui == PHY_OUI_REALTEK) {
1212                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1213                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1214                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1215                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1216                                 return PHY_ERROR;
1217                         }
1218                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1219                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1220                                 return PHY_ERROR;
1221                         }
1222                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1223                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1224                                 return PHY_ERROR;
1225                         }
1226                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1227                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1228                                 return PHY_ERROR;
1229                         }
1230                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1231                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1232                                 return PHY_ERROR;
1233                         }
1234                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1235                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1236                                 return PHY_ERROR;
1237                         }
1238                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1239                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1240                                 return PHY_ERROR;
1241                         }
1242                 }
1243                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1244                     np->phy_rev == PHY_REV_REALTEK_8211C) {
1245                         u32 powerstate = readl(base + NvRegPowerState2);
1246
1247                         /* need to perform hw phy reset */
1248                         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1249                         writel(powerstate, base + NvRegPowerState2);
1250                         msleep(25);
1251
1252                         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1253                         writel(powerstate, base + NvRegPowerState2);
1254                         msleep(25);
1255
1256                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1257                         reg |= PHY_REALTEK_INIT9;
1258                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1259                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1260                                 return PHY_ERROR;
1261                         }
1262                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1263                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1264                                 return PHY_ERROR;
1265                         }
1266                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1267                         if (!(reg & PHY_REALTEK_INIT11)) {
1268                                 reg |= PHY_REALTEK_INIT11;
1269                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1270                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1271                                         return PHY_ERROR;
1272                                 }
1273                         }
1274                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1275                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1276                                 return PHY_ERROR;
1277                         }
1278                 }
1279                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1280                         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1281                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1282                                 phy_reserved |= PHY_REALTEK_INIT7;
1283                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1284                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1285                                         return PHY_ERROR;
1286                                 }
1287                         }
1288                 }
1289         }
1290
1291         /* set advertise register */
1292         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1293         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1294         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1295                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1296                 return PHY_ERROR;
1297         }
1298
1299         /* get phy interface type */
1300         phyinterface = readl(base + NvRegPhyInterface);
1301
1302         /* see if gigabit phy */
1303         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1304         if (mii_status & PHY_GIGABIT) {
1305                 np->gigabit = PHY_GIGABIT;
1306                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1307                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1308                 if (phyinterface & PHY_RGMII)
1309                         mii_control_1000 |= ADVERTISE_1000FULL;
1310                 else
1311                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1312
1313                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1314                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1315                         return PHY_ERROR;
1316                 }
1317         }
1318         else
1319                 np->gigabit = 0;
1320
1321         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1322         mii_control |= BMCR_ANENABLE;
1323
1324         if (np->phy_oui == PHY_OUI_REALTEK &&
1325             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1326             np->phy_rev == PHY_REV_REALTEK_8211C) {
1327                 /* start autoneg since we already performed hw reset above */
1328                 mii_control |= BMCR_ANRESTART;
1329                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1330                         printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1331                         return PHY_ERROR;
1332                 }
1333         } else {
1334                 /* reset the phy
1335                  * (certain phys need bmcr to be setup with reset)
1336                  */
1337                 if (phy_reset(dev, mii_control)) {
1338                         printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1339                         return PHY_ERROR;
1340                 }
1341         }
1342
1343         /* phy vendor specific configuration */
1344         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1345                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1346                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1347                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1348                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1349                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1350                         return PHY_ERROR;
1351                 }
1352                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1353                 phy_reserved |= PHY_CICADA_INIT5;
1354                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1355                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1356                         return PHY_ERROR;
1357                 }
1358         }
1359         if (np->phy_oui == PHY_OUI_CICADA) {
1360                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1361                 phy_reserved |= PHY_CICADA_INIT6;
1362                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1363                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1364                         return PHY_ERROR;
1365                 }
1366         }
1367         if (np->phy_oui == PHY_OUI_VITESSE) {
1368                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1369                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1370                         return PHY_ERROR;
1371                 }
1372                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1373                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1374                         return PHY_ERROR;
1375                 }
1376                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1377                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1378                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1379                         return PHY_ERROR;
1380                 }
1381                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1382                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1383                 phy_reserved |= PHY_VITESSE_INIT3;
1384                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1385                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1386                         return PHY_ERROR;
1387                 }
1388                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1389                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1390                         return PHY_ERROR;
1391                 }
1392                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1393                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1394                         return PHY_ERROR;
1395                 }
1396                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1397                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1398                 phy_reserved |= PHY_VITESSE_INIT3;
1399                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1400                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1401                         return PHY_ERROR;
1402                 }
1403                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1404                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1405                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1406                         return PHY_ERROR;
1407                 }
1408                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1409                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1410                         return PHY_ERROR;
1411                 }
1412                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1413                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1414                         return PHY_ERROR;
1415                 }
1416                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1417                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1418                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1419                         return PHY_ERROR;
1420                 }
1421                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1422                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1423                 phy_reserved |= PHY_VITESSE_INIT8;
1424                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1425                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1426                         return PHY_ERROR;
1427                 }
1428                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1429                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1430                         return PHY_ERROR;
1431                 }
1432                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1433                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1434                         return PHY_ERROR;
1435                 }
1436         }
1437         if (np->phy_oui == PHY_OUI_REALTEK) {
1438                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1439                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1440                         /* reset could have cleared these out, set them back */
1441                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1442                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1443                                 return PHY_ERROR;
1444                         }
1445                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1446                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1447                                 return PHY_ERROR;
1448                         }
1449                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1450                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1451                                 return PHY_ERROR;
1452                         }
1453                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1454                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1455                                 return PHY_ERROR;
1456                         }
1457                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1458                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1459                                 return PHY_ERROR;
1460                         }
1461                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1462                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1463                                 return PHY_ERROR;
1464                         }
1465                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1466                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1467                                 return PHY_ERROR;
1468                         }
1469                 }
1470                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1471                         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1472                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1473                                 phy_reserved |= PHY_REALTEK_INIT7;
1474                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1475                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1476                                         return PHY_ERROR;
1477                                 }
1478                         }
1479                         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1480                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1481                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1482                                         return PHY_ERROR;
1483                                 }
1484                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1485                                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1486                                 phy_reserved |= PHY_REALTEK_INIT3;
1487                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1488                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1489                                         return PHY_ERROR;
1490                                 }
1491                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1492                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1493                                         return PHY_ERROR;
1494                                 }
1495                         }
1496                 }
1497         }
1498
1499         /* some phys clear out pause advertisment on reset, set it back */
1500         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1501
1502         /* restart auto negotiation, power down phy */
1503         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1504         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1505         if (phy_power_down) {
1506                 mii_control |= BMCR_PDOWN;
1507         }
1508         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1509                 return PHY_ERROR;
1510         }
1511
1512         return 0;
1513 }
1514
1515 static void nv_start_rx(struct net_device *dev)
1516 {
1517         struct fe_priv *np = netdev_priv(dev);
1518         u8 __iomem *base = get_hwbase(dev);
1519         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1520
1521         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1522         /* Already running? Stop it. */
1523         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1524                 rx_ctrl &= ~NVREG_RCVCTL_START;
1525                 writel(rx_ctrl, base + NvRegReceiverControl);
1526                 pci_push(base);
1527         }
1528         writel(np->linkspeed, base + NvRegLinkSpeed);
1529         pci_push(base);
1530         rx_ctrl |= NVREG_RCVCTL_START;
1531         if (np->mac_in_use)
1532                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1533         writel(rx_ctrl, base + NvRegReceiverControl);
1534         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1535                                 dev->name, np->duplex, np->linkspeed);
1536         pci_push(base);
1537 }
1538
1539 static void nv_stop_rx(struct net_device *dev)
1540 {
1541         struct fe_priv *np = netdev_priv(dev);
1542         u8 __iomem *base = get_hwbase(dev);
1543         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1544
1545         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1546         if (!np->mac_in_use)
1547                 rx_ctrl &= ~NVREG_RCVCTL_START;
1548         else
1549                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1550         writel(rx_ctrl, base + NvRegReceiverControl);
1551         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1552                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1553                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1554
1555         udelay(NV_RXSTOP_DELAY2);
1556         if (!np->mac_in_use)
1557                 writel(0, base + NvRegLinkSpeed);
1558 }
1559
1560 static void nv_start_tx(struct net_device *dev)
1561 {
1562         struct fe_priv *np = netdev_priv(dev);
1563         u8 __iomem *base = get_hwbase(dev);
1564         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1565
1566         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1567         tx_ctrl |= NVREG_XMITCTL_START;
1568         if (np->mac_in_use)
1569                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1570         writel(tx_ctrl, base + NvRegTransmitterControl);
1571         pci_push(base);
1572 }
1573
1574 static void nv_stop_tx(struct net_device *dev)
1575 {
1576         struct fe_priv *np = netdev_priv(dev);
1577         u8 __iomem *base = get_hwbase(dev);
1578         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1579
1580         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1581         if (!np->mac_in_use)
1582                 tx_ctrl &= ~NVREG_XMITCTL_START;
1583         else
1584                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1585         writel(tx_ctrl, base + NvRegTransmitterControl);
1586         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1587                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1588                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1589
1590         udelay(NV_TXSTOP_DELAY2);
1591         if (!np->mac_in_use)
1592                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1593                        base + NvRegTransmitPoll);
1594 }
1595
1596 static void nv_start_rxtx(struct net_device *dev)
1597 {
1598         nv_start_rx(dev);
1599         nv_start_tx(dev);
1600 }
1601
1602 static void nv_stop_rxtx(struct net_device *dev)
1603 {
1604         nv_stop_rx(dev);
1605         nv_stop_tx(dev);
1606 }
1607
1608 static void nv_txrx_reset(struct net_device *dev)
1609 {
1610         struct fe_priv *np = netdev_priv(dev);
1611         u8 __iomem *base = get_hwbase(dev);
1612
1613         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1614         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1615         pci_push(base);
1616         udelay(NV_TXRX_RESET_DELAY);
1617         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1618         pci_push(base);
1619 }
1620
1621 static void nv_mac_reset(struct net_device *dev)
1622 {
1623         struct fe_priv *np = netdev_priv(dev);
1624         u8 __iomem *base = get_hwbase(dev);
1625         u32 temp1, temp2, temp3;
1626
1627         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1628
1629         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1630         pci_push(base);
1631
1632         /* save registers since they will be cleared on reset */
1633         temp1 = readl(base + NvRegMacAddrA);
1634         temp2 = readl(base + NvRegMacAddrB);
1635         temp3 = readl(base + NvRegTransmitPoll);
1636
1637         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1638         pci_push(base);
1639         udelay(NV_MAC_RESET_DELAY);
1640         writel(0, base + NvRegMacReset);
1641         pci_push(base);
1642         udelay(NV_MAC_RESET_DELAY);
1643
1644         /* restore saved registers */
1645         writel(temp1, base + NvRegMacAddrA);
1646         writel(temp2, base + NvRegMacAddrB);
1647         writel(temp3, base + NvRegTransmitPoll);
1648
1649         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1650         pci_push(base);
1651 }
1652
1653 static void nv_get_hw_stats(struct net_device *dev)
1654 {
1655         struct fe_priv *np = netdev_priv(dev);
1656         u8 __iomem *base = get_hwbase(dev);
1657
1658         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1659         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1660         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1661         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1662         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1663         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1664         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1665         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1666         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1667         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1668         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1669         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1670         np->estats.rx_runt += readl(base + NvRegRxRunt);
1671         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1672         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1673         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1674         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1675         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1676         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1677         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1678         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1679         np->estats.rx_packets =
1680                 np->estats.rx_unicast +
1681                 np->estats.rx_multicast +
1682                 np->estats.rx_broadcast;
1683         np->estats.rx_errors_total =
1684                 np->estats.rx_crc_errors +
1685                 np->estats.rx_over_errors +
1686                 np->estats.rx_frame_error +
1687                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1688                 np->estats.rx_late_collision +
1689                 np->estats.rx_runt +
1690                 np->estats.rx_frame_too_long;
1691         np->estats.tx_errors_total =
1692                 np->estats.tx_late_collision +
1693                 np->estats.tx_fifo_errors +
1694                 np->estats.tx_carrier_errors +
1695                 np->estats.tx_excess_deferral +
1696                 np->estats.tx_retry_error;
1697
1698         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1699                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1700                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1701                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1702                 np->estats.tx_pause += readl(base + NvRegTxPause);
1703                 np->estats.rx_pause += readl(base + NvRegRxPause);
1704                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1705         }
1706
1707         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1708                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1709                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1710                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1711         }
1712 }
1713
1714 /*
1715  * nv_get_stats: dev->get_stats function
1716  * Get latest stats value from the nic.
1717  * Called with read_lock(&dev_base_lock) held for read -
1718  * only synchronized against unregister_netdevice.
1719  */
1720 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1721 {
1722         struct fe_priv *np = netdev_priv(dev);
1723
1724         /* If the nic supports hw counters then retrieve latest values */
1725         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1726                 nv_get_hw_stats(dev);
1727
1728                 /* copy to net_device stats */
1729                 dev->stats.tx_bytes = np->estats.tx_bytes;
1730                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1731                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1732                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1733                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1734                 dev->stats.rx_errors = np->estats.rx_errors_total;
1735                 dev->stats.tx_errors = np->estats.tx_errors_total;
1736         }
1737
1738         return &dev->stats;
1739 }
1740
1741 /*
1742  * nv_alloc_rx: fill rx ring entries.
1743  * Return 1 if the allocations for the skbs failed and the
1744  * rx engine is without Available descriptors
1745  */
1746 static int nv_alloc_rx(struct net_device *dev)
1747 {
1748         struct fe_priv *np = netdev_priv(dev);
1749         struct ring_desc* less_rx;
1750
1751         less_rx = np->get_rx.orig;
1752         if (less_rx-- == np->first_rx.orig)
1753                 less_rx = np->last_rx.orig;
1754
1755         while (np->put_rx.orig != less_rx) {
1756                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1757                 if (skb) {
1758                         np->put_rx_ctx->skb = skb;
1759                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1760                                                              skb->data,
1761                                                              skb_tailroom(skb),
1762                                                              PCI_DMA_FROMDEVICE);
1763                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1764                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1765                         wmb();
1766                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1767                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1768                                 np->put_rx.orig = np->first_rx.orig;
1769                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1770                                 np->put_rx_ctx = np->first_rx_ctx;
1771                 } else {
1772                         return 1;
1773                 }
1774         }
1775         return 0;
1776 }
1777
1778 static int nv_alloc_rx_optimized(struct net_device *dev)
1779 {
1780         struct fe_priv *np = netdev_priv(dev);
1781         struct ring_desc_ex* less_rx;
1782
1783         less_rx = np->get_rx.ex;
1784         if (less_rx-- == np->first_rx.ex)
1785                 less_rx = np->last_rx.ex;
1786
1787         while (np->put_rx.ex != less_rx) {
1788                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1789                 if (skb) {
1790                         np->put_rx_ctx->skb = skb;
1791                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1792                                                              skb->data,
1793                                                              skb_tailroom(skb),
1794                                                              PCI_DMA_FROMDEVICE);
1795                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1796                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1797                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1798                         wmb();
1799                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1800                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1801                                 np->put_rx.ex = np->first_rx.ex;
1802                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1803                                 np->put_rx_ctx = np->first_rx_ctx;
1804                 } else {
1805                         return 1;
1806                 }
1807         }
1808         return 0;
1809 }
1810
1811 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1812 #ifdef CONFIG_FORCEDETH_NAPI
1813 static void nv_do_rx_refill(unsigned long data)
1814 {
1815         struct net_device *dev = (struct net_device *) data;
1816         struct fe_priv *np = netdev_priv(dev);
1817
1818         /* Just reschedule NAPI rx processing */
1819         napi_schedule(&np->napi);
1820 }
1821 #else
1822 static void nv_do_rx_refill(unsigned long data)
1823 {
1824         struct net_device *dev = (struct net_device *) data;
1825         struct fe_priv *np = netdev_priv(dev);
1826         int retcode;
1827
1828         if (!using_multi_irqs(dev)) {
1829                 if (np->msi_flags & NV_MSI_X_ENABLED)
1830                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1831                 else
1832                         disable_irq(np->pci_dev->irq);
1833         } else {
1834                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1835         }
1836         if (!nv_optimized(np))
1837                 retcode = nv_alloc_rx(dev);
1838         else
1839                 retcode = nv_alloc_rx_optimized(dev);
1840         if (retcode) {
1841                 spin_lock_irq(&np->lock);
1842                 if (!np->in_shutdown)
1843                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1844                 spin_unlock_irq(&np->lock);
1845         }
1846         if (!using_multi_irqs(dev)) {
1847                 if (np->msi_flags & NV_MSI_X_ENABLED)
1848                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1849                 else
1850                         enable_irq(np->pci_dev->irq);
1851         } else {
1852                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1853         }
1854 }
1855 #endif
1856
1857 static void nv_init_rx(struct net_device *dev)
1858 {
1859         struct fe_priv *np = netdev_priv(dev);
1860         int i;
1861
1862         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1863
1864         if (!nv_optimized(np))
1865                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1866         else
1867                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1868         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1869         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1870
1871         for (i = 0; i < np->rx_ring_size; i++) {
1872                 if (!nv_optimized(np)) {
1873                         np->rx_ring.orig[i].flaglen = 0;
1874                         np->rx_ring.orig[i].buf = 0;
1875                 } else {
1876                         np->rx_ring.ex[i].flaglen = 0;
1877                         np->rx_ring.ex[i].txvlan = 0;
1878                         np->rx_ring.ex[i].bufhigh = 0;
1879                         np->rx_ring.ex[i].buflow = 0;
1880                 }
1881                 np->rx_skb[i].skb = NULL;
1882                 np->rx_skb[i].dma = 0;
1883         }
1884 }
1885
1886 static void nv_init_tx(struct net_device *dev)
1887 {
1888         struct fe_priv *np = netdev_priv(dev);
1889         int i;
1890
1891         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1892
1893         if (!nv_optimized(np))
1894                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1895         else
1896                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1897         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1898         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1899         np->tx_pkts_in_progress = 0;
1900         np->tx_change_owner = NULL;
1901         np->tx_end_flip = NULL;
1902         np->tx_stop = 0;
1903
1904         for (i = 0; i < np->tx_ring_size; i++) {
1905                 if (!nv_optimized(np)) {
1906                         np->tx_ring.orig[i].flaglen = 0;
1907                         np->tx_ring.orig[i].buf = 0;
1908                 } else {
1909                         np->tx_ring.ex[i].flaglen = 0;
1910                         np->tx_ring.ex[i].txvlan = 0;
1911                         np->tx_ring.ex[i].bufhigh = 0;
1912                         np->tx_ring.ex[i].buflow = 0;
1913                 }
1914                 np->tx_skb[i].skb = NULL;
1915                 np->tx_skb[i].dma = 0;
1916                 np->tx_skb[i].dma_len = 0;
1917                 np->tx_skb[i].dma_single = 0;
1918                 np->tx_skb[i].first_tx_desc = NULL;
1919                 np->tx_skb[i].next_tx_ctx = NULL;
1920         }
1921 }
1922
1923 static int nv_init_ring(struct net_device *dev)
1924 {
1925         struct fe_priv *np = netdev_priv(dev);
1926
1927         nv_init_tx(dev);
1928         nv_init_rx(dev);
1929
1930         if (!nv_optimized(np))
1931                 return nv_alloc_rx(dev);
1932         else
1933                 return nv_alloc_rx_optimized(dev);
1934 }
1935
1936 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1937 {
1938         if (tx_skb->dma) {
1939                 if (tx_skb->dma_single)
1940                         pci_unmap_single(np->pci_dev, tx_skb->dma,
1941                                          tx_skb->dma_len,
1942                                          PCI_DMA_TODEVICE);
1943                 else
1944                         pci_unmap_page(np->pci_dev, tx_skb->dma,
1945                                        tx_skb->dma_len,
1946                                        PCI_DMA_TODEVICE);
1947                 tx_skb->dma = 0;
1948         }
1949 }
1950
1951 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1952 {
1953         nv_unmap_txskb(np, tx_skb);
1954         if (tx_skb->skb) {
1955                 dev_kfree_skb_any(tx_skb->skb);
1956                 tx_skb->skb = NULL;
1957                 return 1;
1958         }
1959         return 0;
1960 }
1961
1962 static void nv_drain_tx(struct net_device *dev)
1963 {
1964         struct fe_priv *np = netdev_priv(dev);
1965         unsigned int i;
1966
1967         for (i = 0; i < np->tx_ring_size; i++) {
1968                 if (!nv_optimized(np)) {
1969                         np->tx_ring.orig[i].flaglen = 0;
1970                         np->tx_ring.orig[i].buf = 0;
1971                 } else {
1972                         np->tx_ring.ex[i].flaglen = 0;
1973                         np->tx_ring.ex[i].txvlan = 0;
1974                         np->tx_ring.ex[i].bufhigh = 0;
1975                         np->tx_ring.ex[i].buflow = 0;
1976                 }
1977                 if (nv_release_txskb(np, &np->tx_skb[i]))
1978                         dev->stats.tx_dropped++;
1979                 np->tx_skb[i].dma = 0;
1980                 np->tx_skb[i].dma_len = 0;
1981                 np->tx_skb[i].dma_single = 0;
1982                 np->tx_skb[i].first_tx_desc = NULL;
1983                 np->tx_skb[i].next_tx_ctx = NULL;
1984         }
1985         np->tx_pkts_in_progress = 0;
1986         np->tx_change_owner = NULL;
1987         np->tx_end_flip = NULL;
1988 }
1989
1990 static void nv_drain_rx(struct net_device *dev)
1991 {
1992         struct fe_priv *np = netdev_priv(dev);
1993         int i;
1994
1995         for (i = 0; i < np->rx_ring_size; i++) {
1996                 if (!nv_optimized(np)) {
1997                         np->rx_ring.orig[i].flaglen = 0;
1998                         np->rx_ring.orig[i].buf = 0;
1999                 } else {
2000                         np->rx_ring.ex[i].flaglen = 0;
2001                         np->rx_ring.ex[i].txvlan = 0;
2002                         np->rx_ring.ex[i].bufhigh = 0;
2003                         np->rx_ring.ex[i].buflow = 0;
2004                 }
2005                 wmb();
2006                 if (np->rx_skb[i].skb) {
2007                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
2008                                          (skb_end_pointer(np->rx_skb[i].skb) -
2009                                           np->rx_skb[i].skb->data),
2010                                          PCI_DMA_FROMDEVICE);
2011                         dev_kfree_skb(np->rx_skb[i].skb);
2012                         np->rx_skb[i].skb = NULL;
2013                 }
2014         }
2015 }
2016
2017 static void nv_drain_rxtx(struct net_device *dev)
2018 {
2019         nv_drain_tx(dev);
2020         nv_drain_rx(dev);
2021 }
2022
2023 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2024 {
2025         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2026 }
2027
2028 static void nv_legacybackoff_reseed(struct net_device *dev)
2029 {
2030         u8 __iomem *base = get_hwbase(dev);
2031         u32 reg;
2032         u32 low;
2033         int tx_status = 0;
2034
2035         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2036         get_random_bytes(&low, sizeof(low));
2037         reg |= low & NVREG_SLOTTIME_MASK;
2038
2039         /* Need to stop tx before change takes effect.
2040          * Caller has already gained np->lock.
2041          */
2042         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2043         if (tx_status)
2044                 nv_stop_tx(dev);
2045         nv_stop_rx(dev);
2046         writel(reg, base + NvRegSlotTime);
2047         if (tx_status)
2048                 nv_start_tx(dev);
2049         nv_start_rx(dev);
2050 }
2051
2052 /* Gear Backoff Seeds */
2053 #define BACKOFF_SEEDSET_ROWS    8
2054 #define BACKOFF_SEEDSET_LFSRS   15
2055
2056 /* Known Good seed sets */
2057 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2058     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2059     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2060     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2061     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2062     {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2063     {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2064     {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2065     {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2066
2067 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2068     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2069     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2070     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2071     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2072     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2073     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2074     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2075     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2076
2077 static void nv_gear_backoff_reseed(struct net_device *dev)
2078 {
2079         u8 __iomem *base = get_hwbase(dev);
2080         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2081         u32 temp, seedset, combinedSeed;
2082         int i;
2083
2084         /* Setup seed for free running LFSR */
2085         /* We are going to read the time stamp counter 3 times
2086            and swizzle bits around to increase randomness */
2087         get_random_bytes(&miniseed1, sizeof(miniseed1));
2088         miniseed1 &= 0x0fff;
2089         if (miniseed1 == 0)
2090                 miniseed1 = 0xabc;
2091
2092         get_random_bytes(&miniseed2, sizeof(miniseed2));
2093         miniseed2 &= 0x0fff;
2094         if (miniseed2 == 0)
2095                 miniseed2 = 0xabc;
2096         miniseed2_reversed =
2097                 ((miniseed2 & 0xF00) >> 8) |
2098                  (miniseed2 & 0x0F0) |
2099                  ((miniseed2 & 0x00F) << 8);
2100
2101         get_random_bytes(&miniseed3, sizeof(miniseed3));
2102         miniseed3 &= 0x0fff;
2103         if (miniseed3 == 0)
2104                 miniseed3 = 0xabc;
2105         miniseed3_reversed =
2106                 ((miniseed3 & 0xF00) >> 8) |
2107                  (miniseed3 & 0x0F0) |
2108                  ((miniseed3 & 0x00F) << 8);
2109
2110         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2111                        (miniseed2 ^ miniseed3_reversed);
2112
2113         /* Seeds can not be zero */
2114         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2115                 combinedSeed |= 0x08;
2116         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2117                 combinedSeed |= 0x8000;
2118
2119         /* No need to disable tx here */
2120         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2121         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2122         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2123         writel(temp,base + NvRegBackOffControl);
2124
2125         /* Setup seeds for all gear LFSRs. */
2126         get_random_bytes(&seedset, sizeof(seedset));
2127         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2128         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
2129         {
2130                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2131                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2132                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2133                 writel(temp, base + NvRegBackOffControl);
2134         }
2135 }
2136
2137 /*
2138  * nv_start_xmit: dev->hard_start_xmit function
2139  * Called with netif_tx_lock held.
2140  */
2141 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2142 {
2143         struct fe_priv *np = netdev_priv(dev);
2144         u32 tx_flags = 0;
2145         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2146         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2147         unsigned int i;
2148         u32 offset = 0;
2149         u32 bcnt;
2150         u32 size = skb->len-skb->data_len;
2151         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2152         u32 empty_slots;
2153         struct ring_desc* put_tx;
2154         struct ring_desc* start_tx;
2155         struct ring_desc* prev_tx;
2156         struct nv_skb_map* prev_tx_ctx;
2157         unsigned long flags;
2158
2159         /* add fragments to entries count */
2160         for (i = 0; i < fragments; i++) {
2161                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2162                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2163         }
2164
2165         spin_lock_irqsave(&np->lock, flags);
2166         empty_slots = nv_get_empty_tx_slots(np);
2167         if (unlikely(empty_slots <= entries)) {
2168                 netif_stop_queue(dev);
2169                 np->tx_stop = 1;
2170                 spin_unlock_irqrestore(&np->lock, flags);
2171                 return NETDEV_TX_BUSY;
2172         }
2173         spin_unlock_irqrestore(&np->lock, flags);
2174
2175         start_tx = put_tx = np->put_tx.orig;
2176
2177         /* setup the header buffer */
2178         do {
2179                 prev_tx = put_tx;
2180                 prev_tx_ctx = np->put_tx_ctx;
2181                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2182                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2183                                                 PCI_DMA_TODEVICE);
2184                 np->put_tx_ctx->dma_len = bcnt;
2185                 np->put_tx_ctx->dma_single = 1;
2186                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2187                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2188
2189                 tx_flags = np->tx_flags;
2190                 offset += bcnt;
2191                 size -= bcnt;
2192                 if (unlikely(put_tx++ == np->last_tx.orig))
2193                         put_tx = np->first_tx.orig;
2194                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2195                         np->put_tx_ctx = np->first_tx_ctx;
2196         } while (size);
2197
2198         /* setup the fragments */
2199         for (i = 0; i < fragments; i++) {
2200                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2201                 u32 size = frag->size;
2202                 offset = 0;
2203
2204                 do {
2205                         prev_tx = put_tx;
2206                         prev_tx_ctx = np->put_tx_ctx;
2207                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2208                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2209                                                            PCI_DMA_TODEVICE);
2210                         np->put_tx_ctx->dma_len = bcnt;
2211                         np->put_tx_ctx->dma_single = 0;
2212                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2213                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2214
2215                         offset += bcnt;
2216                         size -= bcnt;
2217                         if (unlikely(put_tx++ == np->last_tx.orig))
2218                                 put_tx = np->first_tx.orig;
2219                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2220                                 np->put_tx_ctx = np->first_tx_ctx;
2221                 } while (size);
2222         }
2223
2224         /* set last fragment flag  */
2225         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2226
2227         /* save skb in this slot's context area */
2228         prev_tx_ctx->skb = skb;
2229
2230         if (skb_is_gso(skb))
2231                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2232         else
2233                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2234                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2235
2236         spin_lock_irqsave(&np->lock, flags);
2237
2238         /* set tx flags */
2239         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2240         np->put_tx.orig = put_tx;
2241
2242         spin_unlock_irqrestore(&np->lock, flags);
2243
2244         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2245                 dev->name, entries, tx_flags_extra);
2246         {
2247                 int j;
2248                 for (j=0; j<64; j++) {
2249                         if ((j%16) == 0)
2250                                 dprintk("\n%03x:", j);
2251                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2252                 }
2253                 dprintk("\n");
2254         }
2255
2256         dev->trans_start = jiffies;
2257         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2258         return NETDEV_TX_OK;
2259 }
2260
2261 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2262                                            struct net_device *dev)
2263 {
2264         struct fe_priv *np = netdev_priv(dev);
2265         u32 tx_flags = 0;
2266         u32 tx_flags_extra;
2267         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2268         unsigned int i;
2269         u32 offset = 0;
2270         u32 bcnt;
2271         u32 size = skb->len-skb->data_len;
2272         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2273         u32 empty_slots;
2274         struct ring_desc_ex* put_tx;
2275         struct ring_desc_ex* start_tx;
2276         struct ring_desc_ex* prev_tx;
2277         struct nv_skb_map* prev_tx_ctx;
2278         struct nv_skb_map* start_tx_ctx;
2279         unsigned long flags;
2280
2281         /* add fragments to entries count */
2282         for (i = 0; i < fragments; i++) {
2283                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2284                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2285         }
2286
2287         spin_lock_irqsave(&np->lock, flags);
2288         empty_slots = nv_get_empty_tx_slots(np);
2289         if (unlikely(empty_slots <= entries)) {
2290                 netif_stop_queue(dev);
2291                 np->tx_stop = 1;
2292                 spin_unlock_irqrestore(&np->lock, flags);
2293                 return NETDEV_TX_BUSY;
2294         }
2295         spin_unlock_irqrestore(&np->lock, flags);
2296
2297         start_tx = put_tx = np->put_tx.ex;
2298         start_tx_ctx = np->put_tx_ctx;
2299
2300         /* setup the header buffer */
2301         do {
2302                 prev_tx = put_tx;
2303                 prev_tx_ctx = np->put_tx_ctx;
2304                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2305                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2306                                                 PCI_DMA_TODEVICE);
2307                 np->put_tx_ctx->dma_len = bcnt;
2308                 np->put_tx_ctx->dma_single = 1;
2309                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2310                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2311                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2312
2313                 tx_flags = NV_TX2_VALID;
2314                 offset += bcnt;
2315                 size -= bcnt;
2316                 if (unlikely(put_tx++ == np->last_tx.ex))
2317                         put_tx = np->first_tx.ex;
2318                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2319                         np->put_tx_ctx = np->first_tx_ctx;
2320         } while (size);
2321
2322         /* setup the fragments */
2323         for (i = 0; i < fragments; i++) {
2324                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2325                 u32 size = frag->size;
2326                 offset = 0;
2327
2328                 do {
2329                         prev_tx = put_tx;
2330                         prev_tx_ctx = np->put_tx_ctx;
2331                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2332                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2333                                                            PCI_DMA_TODEVICE);
2334                         np->put_tx_ctx->dma_len = bcnt;
2335                         np->put_tx_ctx->dma_single = 0;
2336                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2337                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2338                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2339
2340                         offset += bcnt;
2341                         size -= bcnt;
2342                         if (unlikely(put_tx++ == np->last_tx.ex))
2343                                 put_tx = np->first_tx.ex;
2344                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2345                                 np->put_tx_ctx = np->first_tx_ctx;
2346                 } while (size);
2347         }
2348
2349         /* set last fragment flag  */
2350         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2351
2352         /* save skb in this slot's context area */
2353         prev_tx_ctx->skb = skb;
2354
2355         if (skb_is_gso(skb))
2356                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2357         else
2358                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2359                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2360
2361         /* vlan tag */
2362         if (likely(!np->vlangrp)) {
2363                 start_tx->txvlan = 0;
2364         } else {
2365                 if (vlan_tx_tag_present(skb))
2366                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2367                 else
2368                         start_tx->txvlan = 0;
2369         }
2370
2371         spin_lock_irqsave(&np->lock, flags);
2372
2373         if (np->tx_limit) {
2374                 /* Limit the number of outstanding tx. Setup all fragments, but
2375                  * do not set the VALID bit on the first descriptor. Save a pointer
2376                  * to that descriptor and also for next skb_map element.
2377                  */
2378
2379                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2380                         if (!np->tx_change_owner)
2381                                 np->tx_change_owner = start_tx_ctx;
2382
2383                         /* remove VALID bit */
2384                         tx_flags &= ~NV_TX2_VALID;
2385                         start_tx_ctx->first_tx_desc = start_tx;
2386                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2387                         np->tx_end_flip = np->put_tx_ctx;
2388                 } else {
2389                         np->tx_pkts_in_progress++;
2390                 }
2391         }
2392
2393         /* set tx flags */
2394         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2395         np->put_tx.ex = put_tx;
2396
2397         spin_unlock_irqrestore(&np->lock, flags);
2398
2399         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2400                 dev->name, entries, tx_flags_extra);
2401         {
2402                 int j;
2403                 for (j=0; j<64; j++) {
2404                         if ((j%16) == 0)
2405                                 dprintk("\n%03x:", j);
2406                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2407                 }
2408                 dprintk("\n");
2409         }
2410
2411         dev->trans_start = jiffies;
2412         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2413         return NETDEV_TX_OK;
2414 }
2415
2416 static inline void nv_tx_flip_ownership(struct net_device *dev)
2417 {
2418         struct fe_priv *np = netdev_priv(dev);
2419
2420         np->tx_pkts_in_progress--;
2421         if (np->tx_change_owner) {
2422                 np->tx_change_owner->first_tx_desc->flaglen |=
2423                         cpu_to_le32(NV_TX2_VALID);
2424                 np->tx_pkts_in_progress++;
2425
2426                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2427                 if (np->tx_change_owner == np->tx_end_flip)
2428                         np->tx_change_owner = NULL;
2429
2430                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2431         }
2432 }
2433
2434 /*
2435  * nv_tx_done: check for completed packets, release the skbs.
2436  *
2437  * Caller must own np->lock.
2438  */
2439 static int nv_tx_done(struct net_device *dev, int limit)
2440 {
2441         struct fe_priv *np = netdev_priv(dev);
2442         u32 flags;
2443         int tx_work = 0;
2444         struct ring_desc* orig_get_tx = np->get_tx.orig;
2445
2446         while ((np->get_tx.orig != np->put_tx.orig) &&
2447                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2448                (tx_work < limit)) {
2449
2450                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2451                                         dev->name, flags);
2452
2453                 nv_unmap_txskb(np, np->get_tx_ctx);
2454
2455                 if (np->desc_ver == DESC_VER_1) {
2456                         if (flags & NV_TX_LASTPACKET) {
2457                                 if (flags & NV_TX_ERROR) {
2458                                         if (flags & NV_TX_UNDERFLOW)
2459                                                 dev->stats.tx_fifo_errors++;
2460                                         if (flags & NV_TX_CARRIERLOST)
2461                                                 dev->stats.tx_carrier_errors++;
2462                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2463                                                 nv_legacybackoff_reseed(dev);
2464                                         dev->stats.tx_errors++;
2465                                 } else {
2466                                         dev->stats.tx_packets++;
2467                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2468                                 }
2469                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2470                                 np->get_tx_ctx->skb = NULL;
2471                                 tx_work++;
2472                         }
2473                 } else {
2474                         if (flags & NV_TX2_LASTPACKET) {
2475                                 if (flags & NV_TX2_ERROR) {
2476                                         if (flags & NV_TX2_UNDERFLOW)
2477                                                 dev->stats.tx_fifo_errors++;
2478                                         if (flags & NV_TX2_CARRIERLOST)
2479                                                 dev->stats.tx_carrier_errors++;
2480                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2481                                                 nv_legacybackoff_reseed(dev);
2482                                         dev->stats.tx_errors++;
2483                                 } else {
2484                                         dev->stats.tx_packets++;
2485                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2486                                 }
2487                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2488                                 np->get_tx_ctx->skb = NULL;
2489                                 tx_work++;
2490                         }
2491                 }
2492                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2493                         np->get_tx.orig = np->first_tx.orig;
2494                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2495                         np->get_tx_ctx = np->first_tx_ctx;
2496         }
2497         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2498                 np->tx_stop = 0;
2499                 netif_wake_queue(dev);
2500         }
2501         return tx_work;
2502 }
2503
2504 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2505 {
2506         struct fe_priv *np = netdev_priv(dev);
2507         u32 flags;
2508         int tx_work = 0;
2509         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2510
2511         while ((np->get_tx.ex != np->put_tx.ex) &&
2512                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2513                (tx_work < limit)) {
2514
2515                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2516                                         dev->name, flags);
2517
2518                 nv_unmap_txskb(np, np->get_tx_ctx);
2519
2520                 if (flags & NV_TX2_LASTPACKET) {
2521                         if (!(flags & NV_TX2_ERROR))
2522                                 dev->stats.tx_packets++;
2523                         else {
2524                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2525                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2526                                                 nv_gear_backoff_reseed(dev);
2527                                         else
2528                                                 nv_legacybackoff_reseed(dev);
2529                                 }
2530                         }
2531
2532                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2533                         np->get_tx_ctx->skb = NULL;
2534                         tx_work++;
2535
2536                         if (np->tx_limit) {
2537                                 nv_tx_flip_ownership(dev);
2538                         }
2539                 }
2540                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2541                         np->get_tx.ex = np->first_tx.ex;
2542                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2543                         np->get_tx_ctx = np->first_tx_ctx;
2544         }
2545         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2546                 np->tx_stop = 0;
2547                 netif_wake_queue(dev);
2548         }
2549         return tx_work;
2550 }
2551
2552 /*
2553  * nv_tx_timeout: dev->tx_timeout function
2554  * Called with netif_tx_lock held.
2555  */
2556 static void nv_tx_timeout(struct net_device *dev)
2557 {
2558         struct fe_priv *np = netdev_priv(dev);
2559         u8 __iomem *base = get_hwbase(dev);
2560         u32 status;
2561         union ring_type put_tx;
2562         int saved_tx_limit;
2563
2564         if (np->msi_flags & NV_MSI_X_ENABLED)
2565                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2566         else
2567                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2568
2569         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2570
2571         {
2572                 int i;
2573
2574                 printk(KERN_INFO "%s: Ring at %lx\n",
2575                        dev->name, (unsigned long)np->ring_addr);
2576                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2577                 for (i=0;i<=np->register_size;i+= 32) {
2578                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2579                                         i,
2580                                         readl(base + i + 0), readl(base + i + 4),
2581                                         readl(base + i + 8), readl(base + i + 12),
2582                                         readl(base + i + 16), readl(base + i + 20),
2583                                         readl(base + i + 24), readl(base + i + 28));
2584                 }
2585                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2586                 for (i=0;i<np->tx_ring_size;i+= 4) {
2587                         if (!nv_optimized(np)) {
2588                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2589                                        i,
2590                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2591                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2592                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2593                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2594                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2595                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2596                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2597                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2598                         } else {
2599                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2600                                        i,
2601                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2602                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2603                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2604                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2605                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2606                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2607                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2608                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2609                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2610                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2611                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2612                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2613                         }
2614                 }
2615         }
2616
2617         spin_lock_irq(&np->lock);
2618
2619         /* 1) stop tx engine */
2620         nv_stop_tx(dev);
2621
2622         /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2623         saved_tx_limit = np->tx_limit;
2624         np->tx_limit = 0; /* prevent giving HW any limited pkts */
2625         np->tx_stop = 0;  /* prevent waking tx queue */
2626         if (!nv_optimized(np))
2627                 nv_tx_done(dev, np->tx_ring_size);
2628         else
2629                 nv_tx_done_optimized(dev, np->tx_ring_size);
2630
2631         /* save current HW postion */
2632         if (np->tx_change_owner)
2633                 put_tx.ex = np->tx_change_owner->first_tx_desc;
2634         else
2635                 put_tx = np->put_tx;
2636
2637         /* 3) clear all tx state */
2638         nv_drain_tx(dev);
2639         nv_init_tx(dev);
2640
2641         /* 4) restore state to current HW position */
2642         np->get_tx = np->put_tx = put_tx;
2643         np->tx_limit = saved_tx_limit;
2644
2645         /* 5) restart tx engine */
2646         nv_start_tx(dev);
2647         netif_wake_queue(dev);
2648         spin_unlock_irq(&np->lock);
2649 }
2650
2651 /*
2652  * Called when the nic notices a mismatch between the actual data len on the
2653  * wire and the len indicated in the 802 header
2654  */
2655 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2656 {
2657         int hdrlen;     /* length of the 802 header */
2658         int protolen;   /* length as stored in the proto field */
2659
2660         /* 1) calculate len according to header */
2661         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2662                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2663                 hdrlen = VLAN_HLEN;
2664         } else {
2665                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2666                 hdrlen = ETH_HLEN;
2667         }
2668         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2669                                 dev->name, datalen, protolen, hdrlen);
2670         if (protolen > ETH_DATA_LEN)
2671                 return datalen; /* Value in proto field not a len, no checks possible */
2672
2673         protolen += hdrlen;
2674         /* consistency checks: */
2675         if (datalen > ETH_ZLEN) {
2676                 if (datalen >= protolen) {
2677                         /* more data on wire than in 802 header, trim of
2678                          * additional data.
2679                          */
2680                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2681                                         dev->name, protolen);
2682                         return protolen;
2683                 } else {
2684                         /* less data on wire than mentioned in header.
2685                          * Discard the packet.
2686                          */
2687                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2688                                         dev->name);
2689                         return -1;
2690                 }
2691         } else {
2692                 /* short packet. Accept only if 802 values are also short */
2693                 if (protolen > ETH_ZLEN) {
2694                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2695                                         dev->name);
2696                         return -1;
2697                 }
2698                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2699                                 dev->name, datalen);
2700                 return datalen;
2701         }
2702 }
2703
2704 static int nv_rx_process(struct net_device *dev, int limit)
2705 {
2706         struct fe_priv *np = netdev_priv(dev);
2707         u32 flags;
2708         int rx_work = 0;
2709         struct sk_buff *skb;
2710         int len;
2711
2712         while((np->get_rx.orig != np->put_rx.orig) &&
2713               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2714                 (rx_work < limit)) {
2715
2716                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2717                                         dev->name, flags);
2718
2719                 /*
2720                  * the packet is for us - immediately tear down the pci mapping.
2721                  * TODO: check if a prefetch of the first cacheline improves
2722                  * the performance.
2723                  */
2724                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2725                                 np->get_rx_ctx->dma_len,
2726                                 PCI_DMA_FROMDEVICE);
2727                 skb = np->get_rx_ctx->skb;
2728                 np->get_rx_ctx->skb = NULL;
2729
2730                 {
2731                         int j;
2732                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2733                         for (j=0; j<64; j++) {
2734                                 if ((j%16) == 0)
2735                                         dprintk("\n%03x:", j);
2736                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2737                         }
2738                         dprintk("\n");
2739                 }
2740                 /* look at what we actually got: */
2741                 if (np->desc_ver == DESC_VER_1) {
2742                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2743                                 len = flags & LEN_MASK_V1;
2744                                 if (unlikely(flags & NV_RX_ERROR)) {
2745                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2746                                                 len = nv_getlen(dev, skb->data, len);
2747                                                 if (len < 0) {
2748                                                         dev->stats.rx_errors++;
2749                                                         dev_kfree_skb(skb);
2750                                                         goto next_pkt;
2751                                                 }
2752                                         }
2753                                         /* framing errors are soft errors */
2754                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2755                                                 if (flags & NV_RX_SUBSTRACT1) {
2756                                                         len--;
2757                                                 }
2758                                         }
2759                                         /* the rest are hard errors */
2760                                         else {
2761                                                 if (flags & NV_RX_MISSEDFRAME)
2762                                                         dev->stats.rx_missed_errors++;
2763                                                 if (flags & NV_RX_CRCERR)
2764                                                         dev->stats.rx_crc_errors++;
2765                                                 if (flags & NV_RX_OVERFLOW)
2766                                                         dev->stats.rx_over_errors++;
2767                                                 dev->stats.rx_errors++;
2768                                                 dev_kfree_skb(skb);
2769                                                 goto next_pkt;
2770                                         }
2771                                 }
2772                         } else {
2773                                 dev_kfree_skb(skb);
2774                                 goto next_pkt;
2775                         }
2776                 } else {
2777                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2778                                 len = flags & LEN_MASK_V2;
2779                                 if (unlikely(flags & NV_RX2_ERROR)) {
2780                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2781                                                 len = nv_getlen(dev, skb->data, len);
2782                                                 if (len < 0) {
2783                                                         dev->stats.rx_errors++;
2784                                                         dev_kfree_skb(skb);
2785                                                         goto next_pkt;
2786                                                 }
2787                                         }
2788                                         /* framing errors are soft errors */
2789                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2790                                                 if (flags & NV_RX2_SUBSTRACT1) {
2791                                                         len--;
2792                                                 }
2793                                         }
2794                                         /* the rest are hard errors */
2795                                         else {
2796                                                 if (flags & NV_RX2_CRCERR)
2797                                                         dev->stats.rx_crc_errors++;
2798                                                 if (flags & NV_RX2_OVERFLOW)
2799                                                         dev->stats.rx_over_errors++;
2800                                                 dev->stats.rx_errors++;
2801                                                 dev_kfree_skb(skb);
2802                                                 goto next_pkt;
2803                                         }
2804                                 }
2805                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2806                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2807                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2808                         } else {
2809                                 dev_kfree_skb(skb);
2810                                 goto next_pkt;
2811                         }
2812                 }
2813                 /* got a valid packet - forward it to the network core */
2814                 skb_put(skb, len);
2815                 skb->protocol = eth_type_trans(skb, dev);
2816                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2817                                         dev->name, len, skb->protocol);
2818 #ifdef CONFIG_FORCEDETH_NAPI
2819                 netif_receive_skb(skb);
2820 #else
2821                 netif_rx(skb);
2822 #endif
2823                 dev->stats.rx_packets++;
2824                 dev->stats.rx_bytes += len;
2825 next_pkt:
2826                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2827                         np->get_rx.orig = np->first_rx.orig;
2828                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2829                         np->get_rx_ctx = np->first_rx_ctx;
2830
2831                 rx_work++;
2832         }
2833
2834         return rx_work;
2835 }
2836
2837 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2838 {
2839         struct fe_priv *np = netdev_priv(dev);
2840         u32 flags;
2841         u32 vlanflags = 0;
2842         int rx_work = 0;
2843         struct sk_buff *skb;
2844         int len;
2845
2846         while((np->get_rx.ex != np->put_rx.ex) &&
2847               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2848               (rx_work < limit)) {
2849
2850                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2851                                         dev->name, flags);
2852
2853                 /*
2854                  * the packet is for us - immediately tear down the pci mapping.
2855                  * TODO: check if a prefetch of the first cacheline improves
2856                  * the performance.
2857                  */
2858                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2859                                 np->get_rx_ctx->dma_len,
2860                                 PCI_DMA_FROMDEVICE);
2861                 skb = np->get_rx_ctx->skb;
2862                 np->get_rx_ctx->skb = NULL;
2863
2864                 {
2865                         int j;
2866                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2867                         for (j=0; j<64; j++) {
2868                                 if ((j%16) == 0)
2869                                         dprintk("\n%03x:", j);
2870                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2871                         }
2872                         dprintk("\n");
2873                 }
2874                 /* look at what we actually got: */
2875                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2876                         len = flags & LEN_MASK_V2;
2877                         if (unlikely(flags & NV_RX2_ERROR)) {
2878                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2879                                         len = nv_getlen(dev, skb->data, len);
2880                                         if (len < 0) {
2881                                                 dev_kfree_skb(skb);
2882                                                 goto next_pkt;
2883                                         }
2884                                 }
2885                                 /* framing errors are soft errors */
2886                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2887                                         if (flags & NV_RX2_SUBSTRACT1) {
2888                                                 len--;
2889                                         }
2890                                 }
2891                                 /* the rest are hard errors */
2892                                 else {
2893                                         dev_kfree_skb(skb);
2894                                         goto next_pkt;
2895                                 }
2896                         }
2897
2898                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2899                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2900                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2901
2902                         /* got a valid packet - forward it to the network core */
2903                         skb_put(skb, len);
2904                         skb->protocol = eth_type_trans(skb, dev);
2905                         prefetch(skb->data);
2906
2907                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2908                                 dev->name, len, skb->protocol);
2909
2910                         if (likely(!np->vlangrp)) {
2911 #ifdef CONFIG_FORCEDETH_NAPI
2912                                 netif_receive_skb(skb);
2913 #else
2914                                 netif_rx(skb);
2915 #endif
2916                         } else {
2917                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2918                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2919 #ifdef CONFIG_FORCEDETH_NAPI
2920                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2921                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2922 #else
2923                                         vlan_hwaccel_rx(skb, np->vlangrp,
2924                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2925 #endif
2926                                 } else {
2927 #ifdef CONFIG_FORCEDETH_NAPI
2928                                         netif_receive_skb(skb);
2929 #else
2930                                         netif_rx(skb);
2931 #endif
2932                                 }
2933                         }
2934
2935                         dev->stats.rx_packets++;
2936                         dev->stats.rx_bytes += len;
2937                 } else {
2938                         dev_kfree_skb(skb);
2939                 }
2940 next_pkt:
2941                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2942                         np->get_rx.ex = np->first_rx.ex;
2943                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2944                         np->get_rx_ctx = np->first_rx_ctx;
2945
2946                 rx_work++;
2947         }
2948
2949         return rx_work;
2950 }
2951
2952 static void set_bufsize(struct net_device *dev)
2953 {
2954         struct fe_priv *np = netdev_priv(dev);
2955
2956         if (dev->mtu <= ETH_DATA_LEN)
2957                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2958         else
2959                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2960 }
2961
2962 /*
2963  * nv_change_mtu: dev->change_mtu function
2964  * Called with dev_base_lock held for read.
2965  */
2966 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2967 {
2968         struct fe_priv *np = netdev_priv(dev);
2969         int old_mtu;
2970
2971         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2972                 return -EINVAL;
2973
2974         old_mtu = dev->mtu;
2975         dev->mtu = new_mtu;
2976
2977         /* return early if the buffer sizes will not change */
2978         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2979                 return 0;
2980         if (old_mtu == new_mtu)
2981                 return 0;
2982
2983         /* synchronized against open : rtnl_lock() held by caller */
2984         if (netif_running(dev)) {
2985                 u8 __iomem *base = get_hwbase(dev);
2986                 /*
2987                  * It seems that the nic preloads valid ring entries into an
2988                  * internal buffer. The procedure for flushing everything is
2989                  * guessed, there is probably a simpler approach.
2990                  * Changing the MTU is a rare event, it shouldn't matter.
2991                  */
2992                 nv_disable_irq(dev);
2993                 nv_napi_disable(dev);
2994                 netif_tx_lock_bh(dev);
2995                 netif_addr_lock(dev);
2996                 spin_lock(&np->lock);
2997                 /* stop engines */
2998                 nv_stop_rxtx(dev);
2999                 nv_txrx_reset(dev);
3000                 /* drain rx queue */
3001                 nv_drain_rxtx(dev);
3002                 /* reinit driver view of the rx queue */
3003                 set_bufsize(dev);
3004                 if (nv_init_ring(dev)) {
3005                         if (!np->in_shutdown)
3006                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3007                 }
3008                 /* reinit nic view of the rx queue */
3009                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3010                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3011                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3012                         base + NvRegRingSizes);
3013                 pci_push(base);
3014                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3015                 pci_push(base);
3016
3017                 /* restart rx engine */
3018                 nv_start_rxtx(dev);
3019                 spin_unlock(&np->lock);
3020                 netif_addr_unlock(dev);
3021                 netif_tx_unlock_bh(dev);
3022                 nv_napi_enable(dev);
3023                 nv_enable_irq(dev);
3024         }
3025         return 0;
3026 }
3027
3028 static void nv_copy_mac_to_hw(struct net_device *dev)
3029 {
3030         u8 __iomem *base = get_hwbase(dev);
3031         u32 mac[2];
3032
3033         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
3034                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
3035         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
3036
3037         writel(mac[0], base + NvRegMacAddrA);
3038         writel(mac[1], base + NvRegMacAddrB);
3039 }
3040
3041 /*
3042  * nv_set_mac_address: dev->set_mac_address function
3043  * Called with rtnl_lock() held.
3044  */
3045 static int nv_set_mac_address(struct net_device *dev, void *addr)
3046 {
3047         struct fe_priv *np = netdev_priv(dev);
3048         struct sockaddr *macaddr = (struct sockaddr*)addr;
3049
3050         if (!is_valid_ether_addr(macaddr->sa_data))
3051                 return -EADDRNOTAVAIL;
3052
3053         /* synchronized against open : rtnl_lock() held by caller */
3054         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3055
3056         if (netif_running(dev)) {
3057                 netif_tx_lock_bh(dev);
3058                 netif_addr_lock(dev);
3059                 spin_lock_irq(&np->lock);
3060
3061                 /* stop rx engine */
3062                 nv_stop_rx(dev);
3063
3064                 /* set mac address */
3065                 nv_copy_mac_to_hw(dev);
3066
3067                 /* restart rx engine */
3068                 nv_start_rx(dev);
3069                 spin_unlock_irq(&np->lock);
3070                 netif_addr_unlock(dev);
3071                 netif_tx_unlock_bh(dev);
3072         } else {
3073                 nv_copy_mac_to_hw(dev);
3074         }
3075         return 0;
3076 }
3077
3078 /*
3079  * nv_set_multicast: dev->set_multicast function
3080  * Called with netif_tx_lock held.
3081  */
3082 static void nv_set_multicast(struct net_device *dev)
3083 {
3084         struct fe_priv *np = netdev_priv(dev);
3085         u8 __iomem *base = get_hwbase(dev);
3086         u32 addr[2];
3087         u32 mask[2];
3088         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3089
3090         memset(addr, 0, sizeof(addr));
3091         memset(mask, 0, sizeof(mask));
3092
3093         if (dev->flags & IFF_PROMISC) {
3094                 pff |= NVREG_PFF_PROMISC;
3095         } else {
3096                 pff |= NVREG_PFF_MYADDR;
3097
3098                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
3099                         u32 alwaysOff[2];
3100                         u32 alwaysOn[2];
3101
3102                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3103                         if (dev->flags & IFF_ALLMULTI) {
3104                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3105                         } else {
3106                                 struct dev_mc_list *walk;
3107
3108                                 walk = dev->mc_list;
3109                                 while (walk != NULL) {
3110                                         u32 a, b;
3111                                         a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
3112                                         b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
3113                                         alwaysOn[0] &= a;
3114                                         alwaysOff[0] &= ~a;
3115                                         alwaysOn[1] &= b;
3116                                         alwaysOff[1] &= ~b;
3117                                         walk = walk->next;
3118                                 }
3119                         }
3120                         addr[0] = alwaysOn[0];
3121                         addr[1] = alwaysOn[1];
3122                         mask[0] = alwaysOn[0] | alwaysOff[0];
3123                         mask[1] = alwaysOn[1] | alwaysOff[1];
3124                 } else {
3125                         mask[0] = NVREG_MCASTMASKA_NONE;
3126                         mask[1] = NVREG_MCASTMASKB_NONE;
3127                 }
3128         }
3129         addr[0] |= NVREG_MCASTADDRA_FORCE;
3130         pff |= NVREG_PFF_ALWAYS;
3131         spin_lock_irq(&np->lock);
3132         nv_stop_rx(dev);
3133         writel(addr[0], base + NvRegMulticastAddrA);
3134         writel(addr[1], base + NvRegMulticastAddrB);
3135         writel(mask[0], base + NvRegMulticastMaskA);
3136         writel(mask[1], base + NvRegMulticastMaskB);
3137         writel(pff, base + NvRegPacketFilterFlags);
3138         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3139                 dev->name);
3140         nv_start_rx(dev);
3141         spin_unlock_irq(&np->lock);
3142 }
3143
3144 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3145 {
3146         struct fe_priv *np = netdev_priv(dev);
3147         u8 __iomem *base = get_hwbase(dev);
3148
3149         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3150
3151         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3152                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3153                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3154                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3155                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3156                 } else {
3157                         writel(pff, base + NvRegPacketFilterFlags);
3158                 }
3159         }
3160         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3161                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3162                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3163                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3164                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3165                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3166                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3167                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3168                                 /* limit the number of tx pause frames to a default of 8 */
3169                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3170                         }
3171                         writel(pause_enable,  base + NvRegTxPauseFrame);
3172                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3173                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3174                 } else {
3175                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3176                         writel(regmisc, base + NvRegMisc1);
3177                 }
3178         }
3179 }
3180
3181 /**
3182  * nv_update_linkspeed: Setup the MAC according to the link partner
3183  * @dev: Network device to be configured
3184  *
3185  * The function queries the PHY and checks if there is a link partner.
3186  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3187  * set to 10 MBit HD.
3188  *
3189  * The function returns 0 if there is no link partner and 1 if there is
3190  * a good link partner.
3191  */
3192 static int nv_update_linkspeed(struct net_device *dev)
3193 {
3194         struct fe_priv *np = netdev_priv(dev);
3195         u8 __iomem *base = get_hwbase(dev);
3196         int adv = 0;
3197         int lpa = 0;
3198         int adv_lpa, adv_pause, lpa_pause;
3199         int newls = np->linkspeed;
3200         int newdup = np->duplex;
3201         int mii_status;
3202         int retval = 0;
3203         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3204         u32 txrxFlags = 0;
3205         u32 phy_exp;
3206
3207         /* BMSR_LSTATUS is latched, read it twice:
3208          * we want the current value.
3209          */
3210         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3211         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3212
3213         if (!(mii_status & BMSR_LSTATUS)) {
3214                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3215                                 dev->name);
3216                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3217                 newdup = 0;
3218                 retval = 0;
3219                 goto set_speed;
3220         }
3221
3222         if (np->autoneg == 0) {
3223                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3224                                 dev->name, np->fixed_mode);
3225                 if (np->fixed_mode & LPA_100FULL) {
3226                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3227                         newdup = 1;
3228                 } else if (np->fixed_mode & LPA_100HALF) {
3229                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3230                         newdup = 0;
3231                 } else if (np->fixed_mode & LPA_10FULL) {
3232                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3233                         newdup = 1;
3234                 } else {
3235                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3236                         newdup = 0;
3237                 }
3238                 retval = 1;
3239                 goto set_speed;
3240         }
3241         /* check auto negotiation is complete */
3242         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3243                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3244                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3245                 newdup = 0;
3246                 retval = 0;
3247                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3248                 goto set_speed;
3249         }
3250
3251         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3252         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3253         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3254                                 dev->name, adv, lpa);
3255
3256         retval = 1;
3257         if (np->gigabit == PHY_GIGABIT) {
3258                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3259                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3260
3261                 if ((control_1000 & ADVERTISE_1000FULL) &&
3262                         (status_1000 & LPA_1000FULL)) {
3263                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3264                                 dev->name);
3265                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3266                         newdup = 1;
3267                         goto set_speed;
3268                 }
3269         }
3270
3271         /* FIXME: handle parallel detection properly */
3272         adv_lpa = lpa & adv;
3273         if (adv_lpa & LPA_100FULL) {
3274                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3275                 newdup = 1;
3276         } else if (adv_lpa & LPA_100HALF) {
3277                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3278                 newdup = 0;
3279         } else if (adv_lpa & LPA_10FULL) {
3280                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3281                 newdup = 1;
3282         } else if (adv_lpa & LPA_10HALF) {
3283                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3284                 newdup = 0;
3285         } else {
3286                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3287                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3288                 newdup = 0;
3289         }
3290
3291 set_speed:
3292         if (np->duplex == newdup && np->linkspeed == newls)
3293                 return retval;
3294
3295         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3296                         dev->name, np->linkspeed, np->duplex, newls, newdup);
3297
3298         np->duplex = newdup;
3299         np->linkspeed = newls;
3300
3301         /* The transmitter and receiver must be restarted for safe update */
3302         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3303                 txrxFlags |= NV_RESTART_TX;
3304                 nv_stop_tx(dev);
3305         }
3306         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3307                 txrxFlags |= NV_RESTART_RX;
3308                 nv_stop_rx(dev);
3309         }
3310
3311         if (np->gigabit == PHY_GIGABIT) {
3312                 phyreg = readl(base + NvRegSlotTime);
3313                 phyreg &= ~(0x3FF00);
3314                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3315                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3316                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3317                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3318                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3319                 writel(phyreg, base + NvRegSlotTime);
3320         }
3321
3322         phyreg = readl(base + NvRegPhyInterface);
3323         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3324         if (np->duplex == 0)
3325                 phyreg |= PHY_HALF;
3326         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3327                 phyreg |= PHY_100;
3328         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3329                 phyreg |= PHY_1000;
3330         writel(phyreg, base + NvRegPhyInterface);
3331
3332         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3333         if (phyreg & PHY_RGMII) {
3334                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3335                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3336                 } else {
3337                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3338                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3339                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3340                                 else
3341                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3342                         } else {
3343                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3344                         }
3345                 }
3346         } else {
3347                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3348                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3349                 else
3350                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3351         }
3352         writel(txreg, base + NvRegTxDeferral);
3353
3354         if (np->desc_ver == DESC_VER_1) {
3355                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3356         } else {
3357                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3358                         txreg = NVREG_TX_WM_DESC2_3_1000;
3359                 else
3360                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3361         }
3362         writel(txreg, base + NvRegTxWatermark);
3363
3364         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3365                 base + NvRegMisc1);
3366         pci_push(base);
3367         writel(np->linkspeed, base + NvRegLinkSpeed);
3368         pci_push(base);
3369
3370         pause_flags = 0;
3371         /* setup pause frame */
3372         if (np->duplex != 0) {
3373                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3374                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3375                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3376
3377                         switch (adv_pause) {
3378                         case ADVERTISE_PAUSE_CAP:
3379                                 if (lpa_pause & LPA_PAUSE_CAP) {
3380                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3381                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3382                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3383                                 }
3384                                 break;
3385                         case ADVERTISE_PAUSE_ASYM:
3386                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3387                                 {
3388                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3389                                 }
3390                                 break;
3391                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3392                                 if (lpa_pause & LPA_PAUSE_CAP)
3393                                 {
3394                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3395                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3396                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3397                                 }
3398                                 if (lpa_pause == LPA_PAUSE_ASYM)
3399                                 {
3400                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3401                                 }
3402                                 break;
3403                         }
3404                 } else {
3405                         pause_flags = np->pause_flags;
3406                 }
3407         }
3408         nv_update_pause(dev, pause_flags);
3409
3410         if (txrxFlags & NV_RESTART_TX)
3411                 nv_start_tx(dev);
3412         if (txrxFlags & NV_RESTART_RX)
3413                 nv_start_rx(dev);
3414
3415         return retval;
3416 }
3417
3418 static void nv_linkchange(struct net_device *dev)
3419 {
3420         if (nv_update_linkspeed(dev)) {
3421                 if (!netif_carrier_ok(dev)) {
3422                         netif_carrier_on(dev);
3423                         printk(KERN_INFO "%s: link up.\n", dev->name);
3424                         nv_txrx_gate(dev, false);
3425                         nv_start_rx(dev);
3426                 }
3427         } else {
3428                 if (netif_carrier_ok(dev)) {
3429                         netif_carrier_off(dev);
3430                         printk(KERN_INFO "%s: link down.\n", dev->name);
3431                         nv_txrx_gate(dev, true);
3432                         nv_stop_rx(dev);
3433                 }
3434         }
3435 }
3436
3437 static void nv_link_irq(struct net_device *dev)
3438 {
3439         u8 __iomem *base = get_hwbase(dev);
3440         u32 miistat;
3441
3442         miistat = readl(base + NvRegMIIStatus);
3443         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3444         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3445
3446         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3447                 nv_linkchange(dev);
3448         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3449 }
3450
3451 static void nv_msi_workaround(struct fe_priv *np)
3452 {
3453
3454         /* Need to toggle the msi irq mask within the ethernet device,
3455          * otherwise, future interrupts will not be detected.
3456          */
3457         if (np->msi_flags & NV_MSI_ENABLED) {
3458                 u8 __iomem *base = np->base;
3459
3460                 writel(0, base + NvRegMSIIrqMask);
3461                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3462         }
3463 }
3464
3465 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3466 {
3467         struct fe_priv *np = netdev_priv(dev);
3468
3469         if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3470                 if (total_work > NV_DYNAMIC_THRESHOLD) {
3471                         /* transition to poll based interrupts */
3472                         np->quiet_count = 0;
3473                         if (np->irqmask != NVREG_IRQMASK_CPU) {
3474                                 np->irqmask = NVREG_IRQMASK_CPU;
3475                                 return 1;
3476                         }
3477                 } else {
3478                         if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3479                                 np->quiet_count++;
3480                         } else {
3481                                 /* reached a period of low activity, switch
3482                                    to per tx/rx packet interrupts */
3483                                 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3484                                         np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3485                                         return 1;
3486                                 }
3487                         }
3488                 }
3489         }
3490         return 0;
3491 }
3492
3493 static irqreturn_t nv_nic_irq(int foo, void *data)
3494 {
3495         struct net_device *dev = (struct net_device *) data;
3496         struct fe_priv *np = netdev_priv(dev);
3497         u8 __iomem *base = get_hwbase(dev);
3498 #ifndef CONFIG_FORCEDETH_NAPI
3499         int total_work = 0;
3500         int loop_count = 0;
3501 #endif
3502
3503         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3504
3505         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3506                 np->events = readl(base + NvRegIrqStatus);
3507                 writel(np->events, base + NvRegIrqStatus);
3508         } else {
3509                 np->events = readl(base + NvRegMSIXIrqStatus);
3510                 writel(np->events, base + NvRegMSIXIrqStatus);
3511         }
3512         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3513         if (!(np->events & np->irqmask))
3514                 return IRQ_NONE;
3515
3516         nv_msi_workaround(np);
3517
3518 #ifdef CONFIG_FORCEDETH_NAPI
3519         if (napi_schedule_prep(&np->napi)) {
3520                 /*
3521                  * Disable further irq's (msix not enabled with napi)
3522                  */
3523                 writel(0, base + NvRegIrqMask);
3524                 __napi_schedule(&np->napi);
3525         }
3526
3527 #else
3528         do
3529         {
3530                 int work = 0;
3531                 if ((work = nv_rx_process(dev, RX_WORK_PER_LOOP))) {
3532                         if (unlikely(nv_alloc_rx(dev))) {
3533                                 spin_lock(&np->lock);
3534                                 if (!np->in_shutdown)
3535                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3536                                 spin_unlock(&np->lock);
3537                         }
3538                 }
3539
3540                 spin_lock(&np->lock);
3541                 work += nv_tx_done(dev, TX_WORK_PER_LOOP);
3542                 spin_unlock(&np->lock);
3543
3544                 if (!work)
3545                         break;
3546
3547                 total_work += work;
3548
3549                 loop_count++;
3550         }
3551         while (loop_count < max_interrupt_work);
3552
3553         if (nv_change_interrupt_mode(dev, total_work)) {
3554                 /* setup new irq mask */
3555                 writel(np->irqmask, base + NvRegIrqMask);
3556         }
3557
3558         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3559                 spin_lock(&np->lock);
3560                 nv_link_irq(dev);
3561                 spin_unlock(&np->lock);
3562         }
3563         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3564                 spin_lock(&np->lock);
3565                 nv_linkchange(dev);
3566                 spin_unlock(&np->lock);
3567                 np->link_timeout = jiffies + LINK_TIMEOUT;
3568         }
3569         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3570                 spin_lock(&np->lock);
3571                 /* disable interrupts on the nic */
3572                 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3573                         writel(0, base + NvRegIrqMask);
3574                 else
3575                         writel(np->irqmask, base + NvRegIrqMask);
3576                 pci_push(base);
3577
3578                 if (!np->in_shutdown) {
3579                         np->nic_poll_irq = np->irqmask;
3580                         np->recover_error = 1;
3581                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3582                 }
3583                 spin_unlock(&np->lock);
3584         }
3585 #endif
3586         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3587
3588         return IRQ_HANDLED;
3589 }
3590
3591 /**
3592  * All _optimized functions are used to help increase performance
3593  * (reduce CPU and increase throughput). They use descripter version 3,
3594  * compiler directives, and reduce memory accesses.
3595  */
3596 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3597 {
3598         struct net_device *dev = (struct net_device *) data;
3599         struct fe_priv *np = netdev_priv(dev);
3600         u8 __iomem *base = get_hwbase(dev);
3601 #ifndef CONFIG_FORCEDETH_NAPI
3602         int total_work = 0;
3603         int loop_count = 0;
3604 #endif
3605
3606         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3607
3608         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3609                 np->events = readl(base + NvRegIrqStatus);
3610                 writel(np->events, base + NvRegIrqStatus);
3611         } else {
3612                 np->events = readl(base + NvRegMSIXIrqStatus);
3613                 writel(np->events, base + NvRegMSIXIrqStatus);
3614         }
3615         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3616         if (!(np->events & np->irqmask))
3617                 return IRQ_NONE;
3618
3619         nv_msi_workaround(np);
3620
3621 #ifdef CONFIG_FORCEDETH_NAPI
3622         if (napi_schedule_prep(&np->napi)) {
3623                 /*
3624                  * Disable further irq's (msix not enabled with napi)
3625                  */
3626                 writel(0, base + NvRegIrqMask);
3627                 __napi_schedule(&np->napi);
3628         }
3629 #else
3630         do
3631         {
3632                 int work = 0;
3633                 if ((work = nv_rx_process_optimized(dev, RX_WORK_PER_LOOP))) {
3634                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3635                                 spin_lock(&np->lock);
3636                                 if (!np->in_shutdown)
3637                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3638                                 spin_unlock(&np->lock);
3639                         }
3640                 }
3641
3642                 spin_lock(&np->lock);
3643                 work += nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3644                 spin_unlock(&np->lock);
3645
3646                 if (!work)
3647                         break;
3648
3649                 total_work += work;
3650
3651                 loop_count++;
3652         }
3653         while (loop_count < max_interrupt_work);
3654
3655         if (nv_change_interrupt_mode(dev, total_work)) {
3656                 /* setup new irq mask */
3657                 writel(np->irqmask, base + NvRegIrqMask);
3658         }
3659
3660         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3661                 spin_lock(&np->lock);
3662                 nv_link_irq(dev);
3663                 spin_unlock(&np->lock);
3664         }
3665         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3666                 spin_lock(&np->lock);
3667                 nv_linkchange(dev);
3668                 spin_unlock(&np->lock);
3669                 np->link_timeout = jiffies + LINK_TIMEOUT;
3670         }
3671         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3672                 spin_lock(&np->lock);
3673                 /* disable interrupts on the nic */
3674                 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3675                         writel(0, base + NvRegIrqMask);
3676                 else
3677                         writel(np->irqmask, base + NvRegIrqMask);
3678                 pci_push(base);
3679
3680                 if (!np->in_shutdown) {
3681                         np->nic_poll_irq = np->irqmask;
3682                         np->recover_error = 1;
3683                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3684                 }
3685                 spin_unlock(&np->lock);
3686         }
3687
3688 #endif
3689         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3690
3691         return IRQ_HANDLED;
3692 }
3693
3694 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3695 {
3696         struct net_device *dev = (struct net_device *) data;
3697         struct fe_priv *np = netdev_priv(dev);
3698         u8 __iomem *base = get_hwbase(dev);
3699         u32 events;
3700         int i;
3701         unsigned long flags;
3702
3703         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3704
3705         for (i=0; ; i++) {
3706                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3707                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3708                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3709                 if (!(events & np->irqmask))
3710                         break;
3711
3712                 spin_lock_irqsave(&np->lock, flags);
3713                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3714                 spin_unlock_irqrestore(&np->lock, flags);
3715
3716                 if (unlikely(i > max_interrupt_work)) {
3717                         spin_lock_irqsave(&np->lock, flags);
3718                         /* disable interrupts on the nic */
3719                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3720                         pci_push(base);
3721
3722                         if (!np->in_shutdown) {
3723                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3724                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3725                         }
3726                         spin_unlock_irqrestore(&np->lock, flags);
3727                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3728                         break;
3729                 }
3730
3731         }
3732         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3733
3734         return IRQ_RETVAL(i);
3735 }
3736
3737 #ifdef CONFIG_FORCEDETH_NAPI
3738 static int nv_napi_poll(struct napi_struct *napi, int budget)
3739 {
3740         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3741         struct net_device *dev = np->dev;
3742         u8 __iomem *base = get_hwbase(dev);
3743         unsigned long flags;
3744         int retcode;
3745         int tx_work, rx_work;
3746
3747         if (!nv_optimized(np)) {
3748                 spin_lock_irqsave(&np->lock, flags);
3749                 tx_work = nv_tx_done(dev, np->tx_ring_size);
3750                 spin_unlock_irqrestore(&np->lock, flags);
3751
3752                 rx_work = nv_rx_process(dev, budget);
3753                 retcode = nv_alloc_rx(dev);
3754         } else {
3755                 spin_lock_irqsave(&np->lock, flags);
3756                 tx_work = nv_tx_done_optimized(dev, np->tx_ring_size);
3757                 spin_unlock_irqrestore(&np->lock, flags);
3758
3759                 rx_work = nv_rx_process_optimized(dev, budget);
3760                 retcode = nv_alloc_rx_optimized(dev);
3761         }
3762
3763         if (retcode) {
3764                 spin_lock_irqsave(&np->lock, flags);
3765                 if (!np->in_shutdown)
3766                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3767                 spin_unlock_irqrestore(&np->lock, flags);
3768         }
3769
3770         nv_change_interrupt_mode(dev, tx_work + rx_work);
3771
3772         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3773                 spin_lock_irqsave(&np->lock, flags);
3774                 nv_link_irq(dev);
3775                 spin_unlock_irqrestore(&np->lock, flags);
3776         }
3777         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3778                 spin_lock_irqsave(&np->lock, flags);
3779                 nv_linkchange(dev);
3780                 spin_unlock_irqrestore(&np->lock, flags);
3781                 np->link_timeout = jiffies + LINK_TIMEOUT;
3782         }
3783         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3784                 spin_lock_irqsave(&np->lock, flags);
3785                 if (!np->in_shutdown) {
3786                         np->nic_poll_irq = np->irqmask;
3787                         np->recover_error = 1;
3788                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3789                 }
3790                 spin_unlock_irqrestore(&np->lock, flags);
3791                 napi_complete(napi);
3792                 return rx_work;
3793         }
3794
3795         if (rx_work < budget) {
3796                 /* re-enable interrupts
3797                    (msix not enabled in napi) */
3798                 napi_complete(napi);
3799
3800                 writel(np->irqmask, base + NvRegIrqMask);
3801         }
3802         return rx_work;
3803 }
3804 #endif
3805
3806 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3807 {
3808         struct net_device *dev = (struct net_device *) data;
3809         struct fe_priv *np = netdev_priv(dev);
3810         u8 __iomem *base = get_hwbase(dev);
3811         u32 events;
3812         int i;
3813         unsigned long flags;
3814
3815         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3816
3817         for (i=0; ; i++) {
3818                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3819                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3820                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3821                 if (!(events & np->irqmask))
3822                         break;
3823
3824                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3825                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3826                                 spin_lock_irqsave(&np->lock, flags);
3827                                 if (!np->in_shutdown)
3828                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3829                                 spin_unlock_irqrestore(&np->lock, flags);
3830                         }
3831                 }
3832
3833                 if (unlikely(i > max_interrupt_work)) {
3834                         spin_lock_irqsave(&np->lock, flags);
3835                         /* disable interrupts on the nic */
3836                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3837                         pci_push(base);
3838
3839                         if (!np->in_shutdown) {
3840                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3841                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3842                         }
3843                         spin_unlock_irqrestore(&np->lock, flags);
3844                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3845                         break;
3846                 }
3847         }
3848         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3849
3850         return IRQ_RETVAL(i);
3851 }
3852
3853 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3854 {
3855         struct net_device *dev = (struct net_device *) data;
3856         struct fe_priv *np = netdev_priv(dev);
3857         u8 __iomem *base = get_hwbase(dev);
3858         u32 events;
3859         int i;
3860         unsigned long flags;
3861
3862         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3863
3864         for (i=0; ; i++) {
3865                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3866                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3867                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3868                 if (!(events & np->irqmask))
3869                         break;
3870
3871                 /* check tx in case we reached max loop limit in tx isr */
3872                 spin_lock_irqsave(&np->lock, flags);
3873                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3874                 spin_unlock_irqrestore(&np->lock, flags);
3875
3876                 if (events & NVREG_IRQ_LINK) {
3877                         spin_lock_irqsave(&np->lock, flags);
3878                         nv_link_irq(dev);
3879                         spin_unlock_irqrestore(&np->lock, flags);
3880                 }
3881                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3882                         spin_lock_irqsave(&np->lock, flags);
3883                         nv_linkchange(dev);
3884                         spin_unlock_irqrestore(&np->lock, flags);
3885                         np->link_timeout = jiffies + LINK_TIMEOUT;
3886                 }
3887                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3888                         spin_lock_irq(&np->lock);
3889                         /* disable interrupts on the nic */
3890                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3891                         pci_push(base);
3892
3893                         if (!np->in_shutdown) {
3894                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3895                                 np->recover_error = 1;
3896                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3897                         }
3898                         spin_unlock_irq(&np->lock);
3899                         break;
3900                 }
3901                 if (unlikely(i > max_interrupt_work)) {
3902                         spin_lock_irqsave(&np->lock, flags);
3903                         /* disable interrupts on the nic */
3904                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3905                         pci_push(base);
3906
3907                         if (!np->in_shutdown) {
3908                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3909                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3910                         }
3911                         spin_unlock_irqrestore(&np->lock, flags);
3912                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3913                         break;
3914                 }
3915
3916         }
3917         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3918
3919         return IRQ_RETVAL(i);
3920 }
3921
3922 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3923 {
3924         struct net_device *dev = (struct net_device *) data;
3925         struct fe_priv *np = netdev_priv(dev);
3926         u8 __iomem *base = get_hwbase(dev);
3927         u32 events;
3928
3929         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3930
3931         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3932                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3933                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3934         } else {
3935                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3936                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3937         }
3938         pci_push(base);
3939         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3940         if (!(events & NVREG_IRQ_TIMER))
3941                 return IRQ_RETVAL(0);
3942
3943         nv_msi_workaround(np);
3944
3945         spin_lock(&np->lock);
3946         np->intr_test = 1;
3947         spin_unlock(&np->lock);
3948
3949         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3950
3951         return IRQ_RETVAL(1);
3952 }
3953
3954 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3955 {
3956         u8 __iomem *base = get_hwbase(dev);
3957         int i;
3958         u32 msixmap = 0;
3959
3960         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3961          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3962          * the remaining 8 interrupts.
3963          */
3964         for (i = 0; i < 8; i++) {
3965                 if ((irqmask >> i) & 0x1) {
3966                         msixmap |= vector << (i << 2);
3967                 }
3968         }
3969         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3970
3971         msixmap = 0;
3972         for (i = 0; i < 8; i++) {
3973                 if ((irqmask >> (i + 8)) & 0x1) {
3974                         msixmap |= vector << (i << 2);
3975                 }
3976         }
3977         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3978 }
3979
3980 static int nv_request_irq(struct net_device *dev, int intr_test)
3981 {
3982         struct fe_priv *np = get_nvpriv(dev);
3983         u8 __iomem *base = get_hwbase(dev);
3984         int ret = 1;
3985         int i;
3986         irqreturn_t (*handler)(int foo, void *data);
3987
3988         if (intr_test) {
3989                 handler = nv_nic_irq_test;
3990         } else {
3991                 if (nv_optimized(np))
3992                         handler = nv_nic_irq_optimized;
3993                 else
3994                         handler = nv_nic_irq;
3995         }
3996
3997         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3998                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3999                         np->msi_x_entry[i].entry = i;
4000                 }
4001                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
4002                         np->msi_flags |= NV_MSI_X_ENABLED;
4003                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
4004                                 /* Request irq for rx handling */
4005                                 sprintf(np->name_rx, "%s-rx", dev->name);
4006                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
4007                                                 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
4008                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
4009                                         pci_disable_msix(np->pci_dev);
4010                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4011                                         goto out_err;
4012                                 }
4013                                 /* Request irq for tx handling */
4014                                 sprintf(np->name_tx, "%s-tx", dev->name);
4015                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
4016                                                 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
4017                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
4018                                         pci_disable_msix(np->pci_dev);
4019                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4020                                         goto out_free_rx;
4021                                 }
4022                                 /* Request irq for link and timer handling */
4023                                 sprintf(np->name_other, "%s-other", dev->name);
4024                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
4025                                                 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
4026                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
4027                                         pci_disable_msix(np->pci_dev);
4028                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4029                                         goto out_free_tx;
4030                                 }
4031                                 /* map interrupts to their respective vector */
4032                                 writel(0, base + NvRegMSIXMap0);
4033                                 writel(0, base + NvRegMSIXMap1);
4034                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
4035                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
4036                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
4037                         } else {
4038                                 /* Request irq for all interrupts */
4039                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
4040                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
4041                                         pci_disable_msix(np->pci_dev);
4042                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4043                                         goto out_err;
4044                                 }
4045
4046                                 /* map interrupts to vector 0 */
4047                                 writel(0, base + NvRegMSIXMap0);
4048                                 writel(0, base + NvRegMSIXMap1);
4049                         }
4050                 }
4051         }
4052         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
4053                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
4054                         np->msi_flags |= NV_MSI_ENABLED;
4055                         dev->irq = np->pci_dev->irq;
4056                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
4057                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
4058                                 pci_disable_msi(np->pci_dev);
4059                                 np->msi_flags &= ~NV_MSI_ENABLED;
4060                                 dev->irq = np->pci_dev->irq;
4061                                 goto out_err;
4062                         }
4063
4064                         /* map interrupts to vector 0 */
4065                         writel(0, base + NvRegMSIMap0);
4066                         writel(0, base + NvRegMSIMap1);
4067                         /* enable msi vector 0 */
4068                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
4069                 }
4070         }
4071         if (ret != 0) {
4072                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
4073                         goto out_err;
4074
4075         }
4076
4077         return 0;
4078 out_free_tx:
4079         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
4080 out_free_rx:
4081         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
4082 out_err:
4083         return 1;
4084 }
4085
4086 static void nv_free_irq(struct net_device *dev)
4087 {
4088         struct fe_priv *np = get_nvpriv(dev);
4089         int i;
4090
4091         if (np->msi_flags & NV_MSI_X_ENABLED) {
4092                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
4093                         free_irq(np->msi_x_entry[i].vector, dev);
4094                 }
4095                 pci_disable_msix(np->pci_dev);
4096                 np->msi_flags &= ~NV_MSI_X_ENABLED;
4097         } else {
4098                 free_irq(np->pci_dev->irq, dev);
4099                 if (np->msi_flags & NV_MSI_ENABLED) {
4100                         pci_disable_msi(np->pci_dev);
4101                         np->msi_flags &= ~NV_MSI_ENABLED;
4102                 }
4103         }
4104 }
4105
4106 static void nv_do_nic_poll(unsigned long data)
4107 {
4108         struct net_device *dev = (struct net_device *) data;
4109         struct fe_priv *np = netdev_priv(dev);
4110         u8 __iomem *base = get_hwbase(dev);
4111         u32 mask = 0;
4112
4113         /*
4114          * First disable irq(s) and then
4115          * reenable interrupts on the nic, we have to do this before calling
4116          * nv_nic_irq because that may decide to do otherwise
4117          */
4118
4119         if (!using_multi_irqs(dev)) {
4120                 if (np->msi_flags & NV_MSI_X_ENABLED)
4121                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4122                 else
4123                         disable_irq_lockdep(np->pci_dev->irq);
4124                 mask = np->irqmask;
4125         } else {
4126                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4127                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4128                         mask |= NVREG_IRQ_RX_ALL;
4129                 }
4130                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4131                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4132                         mask |= NVREG_IRQ_TX_ALL;
4133                 }
4134                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4135                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4136                         mask |= NVREG_IRQ_OTHER;
4137                 }
4138         }
4139         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4140
4141         if (np->recover_error) {
4142                 np->recover_error = 0;
4143                 printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name);
4144                 if (netif_running(dev)) {
4145                         netif_tx_lock_bh(dev);
4146                         netif_addr_lock(dev);
4147                         spin_lock(&np->lock);
4148                         /* stop engines */
4149                         nv_stop_rxtx(dev);
4150                         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4151                                 nv_mac_reset(dev);
4152                         nv_txrx_reset(dev);
4153                         /* drain rx queue */
4154                         nv_drain_rxtx(dev);
4155                         /* reinit driver view of the rx queue */
4156                         set_bufsize(dev);
4157                         if (nv_init_ring(dev)) {
4158                                 if (!np->in_shutdown)
4159                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4160                         }
4161                         /* reinit nic view of the rx queue */
4162                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4163                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4164                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4165                                 base + NvRegRingSizes);
4166                         pci_push(base);
4167                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4168                         pci_push(base);
4169                         /* clear interrupts */
4170                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4171                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4172                         else
4173                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4174
4175                         /* restart rx engine */
4176                         nv_start_rxtx(dev);
4177                         spin_unlock(&np->lock);
4178                         netif_addr_unlock(dev);
4179                         netif_tx_unlock_bh(dev);
4180                 }
4181         }
4182
4183         writel(mask, base + NvRegIrqMask);
4184         pci_push(base);
4185
4186         if (!using_multi_irqs(dev)) {
4187                 np->nic_poll_irq = 0;
4188                 if (nv_optimized(np))
4189                         nv_nic_irq_optimized(0, dev);
4190                 else
4191                         nv_nic_irq(0, dev);
4192                 if (np->msi_flags & NV_MSI_X_ENABLED)
4193                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4194                 else
4195                         enable_irq_lockdep(np->pci_dev->irq);
4196         } else {
4197                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4198                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4199                         nv_nic_irq_rx(0, dev);
4200                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4201                 }
4202                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4203                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4204                         nv_nic_irq_tx(0, dev);
4205                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4206                 }
4207                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4208                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4209                         nv_nic_irq_other(0, dev);
4210                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4211                 }
4212         }
4213
4214 }
4215
4216 #ifdef CONFIG_NET_POLL_CONTROLLER
4217 static void nv_poll_controller(struct net_device *dev)
4218 {
4219         nv_do_nic_poll((unsigned long) dev);
4220 }
4221 #endif
4222
4223 static void nv_do_stats_poll(unsigned long data)
4224 {
4225         struct net_device *dev = (struct net_device *) data;
4226         struct fe_priv *np = netdev_priv(dev);
4227
4228         nv_get_hw_stats(dev);
4229
4230         if (!np->in_shutdown)
4231                 mod_timer(&np->stats_poll,
4232                         round_jiffies(jiffies + STATS_INTERVAL));
4233 }
4234
4235 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4236 {
4237         struct fe_priv *np = netdev_priv(dev);
4238         strcpy(info->driver, DRV_NAME);
4239         strcpy(info->version, FORCEDETH_VERSION);
4240         strcpy(info->bus_info, pci_name(np->pci_dev));
4241 }
4242
4243 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4244 {
4245         struct fe_priv *np = netdev_priv(dev);
4246         wolinfo->supported = WAKE_MAGIC;
4247
4248         spin_lock_irq(&np->lock);
4249         if (np->wolenabled)
4250                 wolinfo->wolopts = WAKE_MAGIC;
4251         spin_unlock_irq(&np->lock);
4252 }
4253
4254 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4255 {
4256         struct fe_priv *np = netdev_priv(dev);
4257         u8 __iomem *base = get_hwbase(dev);
4258         u32 flags = 0;
4259
4260         if (wolinfo->wolopts == 0) {
4261                 np->wolenabled = 0;
4262         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4263                 np->wolenabled = 1;
4264                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4265         }
4266         if (netif_running(dev)) {
4267                 spin_lock_irq(&np->lock);
4268                 writel(flags, base + NvRegWakeUpFlags);
4269                 spin_unlock_irq(&np->lock);
4270         }
4271         return 0;
4272 }
4273
4274 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4275 {
4276         struct fe_priv *np = netdev_priv(dev);
4277         int adv;
4278
4279         spin_lock_irq(&np->lock);
4280         ecmd->port = PORT_MII;
4281         if (!netif_running(dev)) {
4282                 /* We do not track link speed / duplex setting if the
4283                  * interface is disabled. Force a link check */
4284                 if (nv_update_linkspeed(dev)) {
4285                         if (!netif_carrier_ok(dev))
4286                                 netif_carrier_on(dev);
4287                 } else {
4288                         if (netif_carrier_ok(dev))
4289                                 netif_carrier_off(dev);
4290                 }
4291         }
4292
4293         if (netif_carrier_ok(dev)) {
4294                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4295                 case NVREG_LINKSPEED_10:
4296                         ecmd->speed = SPEED_10;
4297                         break;
4298                 case NVREG_LINKSPEED_100:
4299                         ecmd->speed = SPEED_100;
4300                         break;
4301                 case NVREG_LINKSPEED_1000:
4302                         ecmd->speed = SPEED_1000;
4303                         break;
4304                 }
4305                 ecmd->duplex = DUPLEX_HALF;
4306                 if (np->duplex)
4307                         ecmd->duplex = DUPLEX_FULL;
4308         } else {
4309                 ecmd->speed = -1;
4310                 ecmd->duplex = -1;
4311         }
4312
4313         ecmd->autoneg = np->autoneg;
4314
4315         ecmd->advertising = ADVERTISED_MII;
4316         if (np->autoneg) {
4317                 ecmd->advertising |= ADVERTISED_Autoneg;
4318                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4319                 if (adv & ADVERTISE_10HALF)
4320                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4321                 if (adv & ADVERTISE_10FULL)
4322                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4323                 if (adv & ADVERTISE_100HALF)
4324                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4325                 if (adv & ADVERTISE_100FULL)
4326                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4327                 if (np->gigabit == PHY_GIGABIT) {
4328                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4329                         if (adv & ADVERTISE_1000FULL)
4330                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4331                 }
4332         }
4333         ecmd->supported = (SUPPORTED_Autoneg |
4334                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4335                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4336                 SUPPORTED_MII);
4337         if (np->gigabit == PHY_GIGABIT)
4338                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4339
4340         ecmd->phy_address = np->phyaddr;
4341         ecmd->transceiver = XCVR_EXTERNAL;
4342
4343         /* ignore maxtxpkt, maxrxpkt for now */
4344         spin_unlock_irq(&np->lock);
4345         return 0;
4346 }
4347
4348 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4349 {
4350         struct fe_priv *np = netdev_priv(dev);
4351
4352         if (ecmd->port != PORT_MII)
4353                 return -EINVAL;
4354         if (ecmd->transceiver != XCVR_EXTERNAL)
4355                 return -EINVAL;
4356         if (ecmd->phy_address != np->phyaddr) {
4357                 /* TODO: support switching between multiple phys. Should be
4358                  * trivial, but not enabled due to lack of test hardware. */
4359                 return -EINVAL;
4360         }
4361         if (ecmd->autoneg == AUTONEG_ENABLE) {
4362                 u32 mask;
4363
4364                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4365                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4366                 if (np->gigabit == PHY_GIGABIT)
4367                         mask |= ADVERTISED_1000baseT_Full;
4368
4369                 if ((ecmd->advertising & mask) == 0)
4370                         return -EINVAL;
4371
4372         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4373                 /* Note: autonegotiation disable, speed 1000 intentionally
4374                  * forbidden - noone should need that. */
4375
4376                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4377                         return -EINVAL;
4378                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4379                         return -EINVAL;
4380         } else {
4381                 return -EINVAL;
4382         }
4383
4384         netif_carrier_off(dev);
4385         if (netif_running(dev)) {
4386                 unsigned long flags;
4387
4388                 nv_disable_irq(dev);
4389                 netif_tx_lock_bh(dev);
4390                 netif_addr_lock(dev);
4391                 /* with plain spinlock lockdep complains */
4392                 spin_lock_irqsave(&np->lock, flags);
4393                 /* stop engines */
4394                 /* FIXME:
4395                  * this can take some time, and interrupts are disabled
4396                  * due to spin_lock_irqsave, but let's hope no daemon
4397                  * is going to change the settings very often...
4398                  * Worst case:
4399                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4400                  * + some minor delays, which is up to a second approximately
4401                  */
4402                 nv_stop_rxtx(dev);
4403                 spin_unlock_irqrestore(&np->lock, flags);
4404                 netif_addr_unlock(dev);
4405                 netif_tx_unlock_bh(dev);
4406         }
4407
4408         if (ecmd->autoneg == AUTONEG_ENABLE) {
4409                 int adv, bmcr;
4410
4411                 np->autoneg = 1;
4412
4413                 /* advertise only what has been requested */
4414                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4415                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4416                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4417                         adv |= ADVERTISE_10HALF;
4418                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4419                         adv |= ADVERTISE_10FULL;
4420                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4421                         adv |= ADVERTISE_100HALF;
4422                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4423                         adv |= ADVERTISE_100FULL;
4424                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
4425                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4426                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4427                         adv |=  ADVERTISE_PAUSE_ASYM;
4428                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4429
4430                 if (np->gigabit == PHY_GIGABIT) {
4431                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4432                         adv &= ~ADVERTISE_1000FULL;
4433                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4434                                 adv |= ADVERTISE_1000FULL;
4435                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4436                 }
4437
4438                 if (netif_running(dev))
4439                         printk(KERN_INFO "%s: link down.\n", dev->name);
4440                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4441                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4442                         bmcr |= BMCR_ANENABLE;
4443                         /* reset the phy in order for settings to stick,
4444                          * and cause autoneg to start */
4445                         if (phy_reset(dev, bmcr)) {
4446                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4447                                 return -EINVAL;
4448                         }
4449                 } else {
4450                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4451                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4452                 }
4453         } else {
4454                 int adv, bmcr;
4455
4456                 np->autoneg = 0;
4457
4458                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4459                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4460                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4461                         adv |= ADVERTISE_10HALF;
4462                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4463                         adv |= ADVERTISE_10FULL;
4464                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4465                         adv |= ADVERTISE_100HALF;
4466                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4467                         adv |= ADVERTISE_100FULL;
4468                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4469                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4470                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4471                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4472                 }
4473                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4474                         adv |=  ADVERTISE_PAUSE_ASYM;
4475                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4476                 }
4477                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4478                 np->fixed_mode = adv;
4479
4480                 if (np->gigabit == PHY_GIGABIT) {
4481                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4482                         adv &= ~ADVERTISE_1000FULL;
4483                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4484                 }
4485
4486                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4487                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4488                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4489                         bmcr |= BMCR_FULLDPLX;
4490                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4491                         bmcr |= BMCR_SPEED100;
4492                 if (np->phy_oui == PHY_OUI_MARVELL) {
4493                         /* reset the phy in order for forced mode settings to stick */
4494                         if (phy_reset(dev, bmcr)) {
4495                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4496                                 return -EINVAL;
4497                         }
4498                 } else {
4499                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4500                         if (netif_running(dev)) {
4501                                 /* Wait a bit and then reconfigure the nic. */
4502                                 udelay(10);
4503                                 nv_linkchange(dev);
4504                         }
4505                 }
4506         }
4507
4508         if (netif_running(dev)) {
4509                 nv_start_rxtx(dev);
4510                 nv_enable_irq(dev);
4511         }
4512
4513         return 0;
4514 }
4515
4516 #define FORCEDETH_REGS_VER      1
4517
4518 static int nv_get_regs_len(struct net_device *dev)
4519 {
4520         struct fe_priv *np = netdev_priv(dev);
4521         return np->register_size;
4522 }
4523
4524 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4525 {
4526         struct fe_priv *np = netdev_priv(dev);
4527         u8 __iomem *base = get_hwbase(dev);
4528         u32 *rbuf = buf;
4529         int i;
4530
4531         regs->version = FORCEDETH_REGS_VER;
4532         spin_lock_irq(&np->lock);
4533         for (i = 0;i <= np->register_size/sizeof(u32); i++)
4534                 rbuf[i] = readl(base + i*sizeof(u32));
4535         spin_unlock_irq(&np->lock);
4536 }
4537
4538 static int nv_nway_reset(struct net_device *dev)
4539 {
4540         struct fe_priv *np = netdev_priv(dev);
4541         int ret;
4542
4543         if (np->autoneg) {
4544                 int bmcr;
4545
4546                 netif_carrier_off(dev);
4547                 if (netif_running(dev)) {
4548                         nv_disable_irq(dev);
4549                         netif_tx_lock_bh(dev);
4550                         netif_addr_lock(dev);
4551                         spin_lock(&np->lock);
4552                         /* stop engines */
4553                         nv_stop_rxtx(dev);
4554                         spin_unlock(&np->lock);
4555                         netif_addr_unlock(dev);
4556                         netif_tx_unlock_bh(dev);
4557                         printk(KERN_INFO "%s: link down.\n", dev->name);
4558                 }
4559
4560                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4561                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4562                         bmcr |= BMCR_ANENABLE;
4563                         /* reset the phy in order for settings to stick*/
4564                         if (phy_reset(dev, bmcr)) {
4565                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4566                                 return -EINVAL;
4567                         }
4568                 } else {
4569                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4570                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4571                 }
4572
4573                 if (netif_running(dev)) {
4574                         nv_start_rxtx(dev);
4575                         nv_enable_irq(dev);
4576                 }
4577                 ret = 0;
4578         } else {
4579                 ret = -EINVAL;
4580         }
4581
4582         return ret;
4583 }
4584
4585 static int nv_set_tso(struct net_device *dev, u32 value)
4586 {
4587         struct fe_priv *np = netdev_priv(dev);
4588
4589         if ((np->driver_data & DEV_HAS_CHECKSUM))
4590                 return ethtool_op_set_tso(dev, value);
4591         else
4592                 return -EOPNOTSUPP;
4593 }
4594
4595 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4596 {
4597         struct fe_priv *np = netdev_priv(dev);
4598
4599         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4600         ring->rx_mini_max_pending = 0;
4601         ring->rx_jumbo_max_pending = 0;
4602         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4603
4604         ring->rx_pending = np->rx_ring_size;
4605         ring->rx_mini_pending = 0;
4606         ring->rx_jumbo_pending = 0;
4607         ring->tx_pending = np->tx_ring_size;
4608 }
4609
4610 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4611 {
4612         struct fe_priv *np = netdev_priv(dev);
4613         u8 __iomem *base = get_hwbase(dev);
4614         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4615         dma_addr_t ring_addr;
4616
4617         if (ring->rx_pending < RX_RING_MIN ||
4618             ring->tx_pending < TX_RING_MIN ||
4619             ring->rx_mini_pending != 0 ||
4620             ring->rx_jumbo_pending != 0 ||
4621             (np->desc_ver == DESC_VER_1 &&
4622              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4623               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4624             (np->desc_ver != DESC_VER_1 &&
4625              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4626               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4627                 return -EINVAL;
4628         }
4629
4630         /* allocate new rings */
4631         if (!nv_optimized(np)) {
4632                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4633                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4634                                             &ring_addr);
4635         } else {
4636                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4637                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4638                                             &ring_addr);
4639         }
4640         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4641         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4642         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4643                 /* fall back to old rings */
4644                 if (!nv_optimized(np)) {
4645                         if (rxtx_ring)
4646                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4647                                                     rxtx_ring, ring_addr);
4648                 } else {
4649                         if (rxtx_ring)
4650                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4651                                                     rxtx_ring, ring_addr);
4652                 }
4653                 if (rx_skbuff)
4654                         kfree(rx_skbuff);
4655                 if (tx_skbuff)
4656                         kfree(tx_skbuff);
4657                 goto exit;
4658         }
4659
4660         if (netif_running(dev)) {
4661                 nv_disable_irq(dev);
4662                 nv_napi_disable(dev);
4663                 netif_tx_lock_bh(dev);
4664                 netif_addr_lock(dev);
4665                 spin_lock(&np->lock);
4666                 /* stop engines */
4667                 nv_stop_rxtx(dev);
4668                 nv_txrx_reset(dev);
4669                 /* drain queues */
4670                 nv_drain_rxtx(dev);
4671                 /* delete queues */
4672                 free_rings(dev);
4673         }
4674
4675         /* set new values */
4676         np->rx_ring_size = ring->rx_pending;
4677         np->tx_ring_size = ring->tx_pending;
4678
4679         if (!nv_optimized(np)) {
4680                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4681                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4682         } else {
4683                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4684                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4685         }
4686         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4687         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4688         np->ring_addr = ring_addr;
4689
4690         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4691         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4692
4693         if (netif_running(dev)) {
4694                 /* reinit driver view of the queues */
4695                 set_bufsize(dev);
4696                 if (nv_init_ring(dev)) {
4697                         if (!np->in_shutdown)
4698                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4699                 }
4700
4701                 /* reinit nic view of the queues */
4702                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4703                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4704                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4705                         base + NvRegRingSizes);
4706                 pci_push(base);
4707                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4708                 pci_push(base);
4709
4710                 /* restart engines */
4711                 nv_start_rxtx(dev);
4712                 spin_unlock(&np->lock);
4713                 netif_addr_unlock(dev);
4714                 netif_tx_unlock_bh(dev);
4715                 nv_napi_enable(dev);
4716                 nv_enable_irq(dev);
4717         }
4718         return 0;
4719 exit:
4720         return -ENOMEM;
4721 }
4722
4723 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4724 {
4725         struct fe_priv *np = netdev_priv(dev);
4726
4727         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4728         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4729         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4730 }
4731
4732 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4733 {
4734         struct fe_priv *np = netdev_priv(dev);
4735         int adv, bmcr;
4736
4737         if ((!np->autoneg && np->duplex == 0) ||
4738             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4739                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4740                        dev->name);
4741                 return -EINVAL;
4742         }
4743         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4744                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4745                 return -EINVAL;
4746         }
4747
4748         netif_carrier_off(dev);
4749         if (netif_running(dev)) {
4750                 nv_disable_irq(dev);
4751                 netif_tx_lock_bh(dev);
4752                 netif_addr_lock(dev);
4753                 spin_lock(&np->lock);
4754                 /* stop engines */
4755                 nv_stop_rxtx(dev);
4756                 spin_unlock(&np->lock);
4757                 netif_addr_unlock(dev);
4758                 netif_tx_unlock_bh(dev);
4759         }
4760
4761         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4762         if (pause->rx_pause)
4763                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4764         if (pause->tx_pause)
4765                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4766
4767         if (np->autoneg && pause->autoneg) {
4768                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4769
4770                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4771                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4772                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4773                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4774                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4775                         adv |=  ADVERTISE_PAUSE_ASYM;
4776                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4777
4778                 if (netif_running(dev))
4779                         printk(KERN_INFO "%s: link down.\n", dev->name);
4780                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4781                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4782                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4783         } else {
4784                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4785                 if (pause->rx_pause)
4786                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4787                 if (pause->tx_pause)
4788                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4789
4790                 if (!netif_running(dev))
4791                         nv_update_linkspeed(dev);
4792                 else
4793                         nv_update_pause(dev, np->pause_flags);
4794         }
4795
4796         if (netif_running(dev)) {
4797                 nv_start_rxtx(dev);
4798                 nv_enable_irq(dev);
4799         }
4800         return 0;
4801 }
4802
4803 static u32 nv_get_rx_csum(struct net_device *dev)
4804 {
4805         struct fe_priv *np = netdev_priv(dev);
4806         return (np->rx_csum) != 0;
4807 }
4808
4809 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4810 {
4811         struct fe_priv *np = netdev_priv(dev);
4812         u8 __iomem *base = get_hwbase(dev);
4813         int retcode = 0;
4814
4815         if (np->driver_data & DEV_HAS_CHECKSUM) {
4816                 if (data) {
4817                         np->rx_csum = 1;
4818                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4819                 } else {
4820                         np->rx_csum = 0;
4821                         /* vlan is dependent on rx checksum offload */
4822                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4823                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4824                 }
4825                 if (netif_running(dev)) {
4826                         spin_lock_irq(&np->lock);
4827                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4828                         spin_unlock_irq(&np->lock);
4829                 }
4830         } else {
4831                 return -EINVAL;
4832         }
4833
4834         return retcode;
4835 }
4836
4837 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4838 {
4839         struct fe_priv *np = netdev_priv(dev);
4840
4841         if (np->driver_data & DEV_HAS_CHECKSUM)
4842                 return ethtool_op_set_tx_csum(dev, data);
4843         else
4844                 return -EOPNOTSUPP;
4845 }
4846
4847 static int nv_set_sg(struct net_device *dev, u32 data)
4848 {
4849         struct fe_priv *np = netdev_priv(dev);
4850
4851         if (np->driver_data & DEV_HAS_CHECKSUM)
4852                 return ethtool_op_set_sg(dev, data);
4853         else
4854                 return -EOPNOTSUPP;
4855 }
4856
4857 static int nv_get_sset_count(struct net_device *dev, int sset)
4858 {
4859         struct fe_priv *np = netdev_priv(dev);
4860
4861         switch (sset) {
4862         case ETH_SS_TEST:
4863                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4864                         return NV_TEST_COUNT_EXTENDED;
4865                 else
4866                         return NV_TEST_COUNT_BASE;
4867         case ETH_SS_STATS:
4868                 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4869                         return NV_DEV_STATISTICS_V3_COUNT;
4870                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4871                         return NV_DEV_STATISTICS_V2_COUNT;
4872                 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4873                         return NV_DEV_STATISTICS_V1_COUNT;
4874                 else
4875                         return 0;
4876         default:
4877                 return -EOPNOTSUPP;
4878         }
4879 }
4880
4881 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4882 {
4883         struct fe_priv *np = netdev_priv(dev);
4884
4885         /* update stats */
4886         nv_do_stats_poll((unsigned long)dev);
4887
4888         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4889 }
4890
4891 static int nv_link_test(struct net_device *dev)
4892 {
4893         struct fe_priv *np = netdev_priv(dev);
4894         int mii_status;
4895
4896         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4897         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4898
4899         /* check phy link status */
4900         if (!(mii_status & BMSR_LSTATUS))
4901                 return 0;
4902         else
4903                 return 1;
4904 }
4905
4906 static int nv_register_test(struct net_device *dev)
4907 {
4908         u8 __iomem *base = get_hwbase(dev);
4909         int i = 0;
4910         u32 orig_read, new_read;
4911
4912         do {
4913                 orig_read = readl(base + nv_registers_test[i].reg);
4914
4915                 /* xor with mask to toggle bits */
4916                 orig_read ^= nv_registers_test[i].mask;
4917
4918                 writel(orig_read, base + nv_registers_test[i].reg);
4919
4920                 new_read = readl(base + nv_registers_test[i].reg);
4921
4922                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4923                         return 0;
4924
4925                 /* restore original value */
4926                 orig_read ^= nv_registers_test[i].mask;
4927                 writel(orig_read, base + nv_registers_test[i].reg);
4928
4929         } while (nv_registers_test[++i].reg != 0);
4930
4931         return 1;
4932 }
4933
4934 static int nv_interrupt_test(struct net_device *dev)
4935 {
4936         struct fe_priv *np = netdev_priv(dev);
4937         u8 __iomem *base = get_hwbase(dev);
4938         int ret = 1;
4939         int testcnt;
4940         u32 save_msi_flags, save_poll_interval = 0;
4941
4942         if (netif_running(dev)) {
4943                 /* free current irq */
4944                 nv_free_irq(dev);
4945                 save_poll_interval = readl(base+NvRegPollingInterval);
4946         }
4947
4948         /* flag to test interrupt handler */
4949         np->intr_test = 0;
4950
4951         /* setup test irq */
4952         save_msi_flags = np->msi_flags;
4953         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4954         np->msi_flags |= 0x001; /* setup 1 vector */
4955         if (nv_request_irq(dev, 1))
4956                 return 0;
4957
4958         /* setup timer interrupt */
4959         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4960         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4961
4962         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4963
4964         /* wait for at least one interrupt */
4965         msleep(100);
4966
4967         spin_lock_irq(&np->lock);
4968
4969         /* flag should be set within ISR */
4970         testcnt = np->intr_test;
4971         if (!testcnt)
4972                 ret = 2;
4973
4974         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4975         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4976                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4977         else
4978                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4979
4980         spin_unlock_irq(&np->lock);
4981
4982         nv_free_irq(dev);
4983
4984         np->msi_flags = save_msi_flags;
4985
4986         if (netif_running(dev)) {
4987                 writel(save_poll_interval, base + NvRegPollingInterval);
4988                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4989                 /* restore original irq */
4990                 if (nv_request_irq(dev, 0))
4991                         return 0;
4992         }
4993
4994         return ret;
4995 }
4996
4997 static int nv_loopback_test(struct net_device *dev)
4998 {
4999         struct fe_priv *np = netdev_priv(dev);
5000         u8 __iomem *base = get_hwbase(dev);
5001         struct sk_buff *tx_skb, *rx_skb;
5002         dma_addr_t test_dma_addr;
5003         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
5004         u32 flags;
5005         int len, i, pkt_len;
5006         u8 *pkt_data;
5007         u32 filter_flags = 0;
5008         u32 misc1_flags = 0;
5009         int ret = 1;
5010
5011         if (netif_running(dev)) {
5012                 nv_disable_irq(dev);
5013                 filter_flags = readl(base + NvRegPacketFilterFlags);
5014                 misc1_flags = readl(base + NvRegMisc1);
5015         } else {
5016                 nv_txrx_reset(dev);
5017         }
5018
5019         /* reinit driver view of the rx queue */
5020         set_bufsize(dev);
5021         nv_init_ring(dev);
5022
5023         /* setup hardware for loopback */
5024         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
5025         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
5026
5027         /* reinit nic view of the rx queue */
5028         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5029         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5030         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5031                 base + NvRegRingSizes);
5032         pci_push(base);
5033
5034         /* restart rx engine */
5035         nv_start_rxtx(dev);
5036
5037         /* setup packet for tx */
5038         pkt_len = ETH_DATA_LEN;
5039         tx_skb = dev_alloc_skb(pkt_len);
5040         if (!tx_skb) {
5041                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
5042                          " of %s\n", dev->name);
5043                 ret = 0;
5044                 goto out;
5045         }
5046         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
5047                                        skb_tailroom(tx_skb),
5048                                        PCI_DMA_FROMDEVICE);
5049         pkt_data = skb_put(tx_skb, pkt_len);
5050         for (i = 0; i < pkt_len; i++)
5051                 pkt_data[i] = (u8)(i & 0xff);
5052
5053         if (!nv_optimized(np)) {
5054                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
5055                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5056         } else {
5057                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
5058                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
5059                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5060         }
5061         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5062         pci_push(get_hwbase(dev));
5063
5064         msleep(500);
5065
5066         /* check for rx of the packet */
5067         if (!nv_optimized(np)) {
5068                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
5069                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5070
5071         } else {
5072                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
5073                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5074         }
5075
5076         if (flags & NV_RX_AVAIL) {
5077                 ret = 0;
5078         } else if (np->desc_ver == DESC_VER_1) {
5079                 if (flags & NV_RX_ERROR)
5080                         ret = 0;
5081         } else {
5082                 if (flags & NV_RX2_ERROR) {
5083                         ret = 0;
5084                 }
5085         }
5086
5087         if (ret) {
5088                 if (len != pkt_len) {
5089                         ret = 0;
5090                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
5091                                 dev->name, len, pkt_len);
5092                 } else {
5093                         rx_skb = np->rx_skb[0].skb;
5094                         for (i = 0; i < pkt_len; i++) {
5095                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5096                                         ret = 0;
5097                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
5098                                                 dev->name, i);
5099                                         break;
5100                                 }
5101                         }
5102                 }
5103         } else {
5104                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
5105         }
5106
5107         pci_unmap_single(np->pci_dev, test_dma_addr,
5108                        (skb_end_pointer(tx_skb) - tx_skb->data),
5109                        PCI_DMA_TODEVICE);
5110         dev_kfree_skb_any(tx_skb);
5111  out:
5112         /* stop engines */
5113         nv_stop_rxtx(dev);
5114         nv_txrx_reset(dev);
5115         /* drain rx queue */
5116         nv_drain_rxtx(dev);
5117
5118         if (netif_running(dev)) {
5119                 writel(misc1_flags, base + NvRegMisc1);
5120                 writel(filter_flags, base + NvRegPacketFilterFlags);
5121                 nv_enable_irq(dev);
5122         }
5123
5124         return ret;
5125 }
5126
5127 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5128 {
5129         struct fe_priv *np = netdev_priv(dev);
5130         u8 __iomem *base = get_hwbase(dev);
5131         int result;
5132         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
5133
5134         if (!nv_link_test(dev)) {
5135                 test->flags |= ETH_TEST_FL_FAILED;
5136                 buffer[0] = 1;
5137         }
5138
5139         if (test->flags & ETH_TEST_FL_OFFLINE) {
5140                 if (netif_running(dev)) {
5141                         netif_stop_queue(dev);
5142                         nv_napi_disable(dev);
5143                         netif_tx_lock_bh(dev);
5144                         netif_addr_lock(dev);
5145                         spin_lock_irq(&np->lock);
5146                         nv_disable_hw_interrupts(dev, np->irqmask);
5147                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
5148                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5149                         } else {
5150                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5151                         }
5152                         /* stop engines */
5153                         nv_stop_rxtx(dev);
5154                         nv_txrx_reset(dev);
5155                         /* drain rx queue */
5156                         nv_drain_rxtx(dev);
5157                         spin_unlock_irq(&np->lock);
5158                         netif_addr_unlock(dev);
5159                         netif_tx_unlock_bh(dev);
5160                 }
5161
5162                 if (!nv_register_test(dev)) {
5163                         test->flags |= ETH_TEST_FL_FAILED;
5164                         buffer[1] = 1;
5165                 }
5166
5167                 result = nv_interrupt_test(dev);
5168                 if (result != 1) {
5169                         test->flags |= ETH_TEST_FL_FAILED;
5170                         buffer[2] = 1;
5171                 }
5172                 if (result == 0) {
5173                         /* bail out */
5174                         return;
5175                 }
5176
5177                 if (!nv_loopback_test(dev)) {
5178                         test->flags |= ETH_TEST_FL_FAILED;
5179                         buffer[3] = 1;
5180                 }
5181
5182                 if (netif_running(dev)) {
5183                         /* reinit driver view of the rx queue */
5184                         set_bufsize(dev);
5185                         if (nv_init_ring(dev)) {
5186                                 if (!np->in_shutdown)
5187                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5188                         }
5189                         /* reinit nic view of the rx queue */
5190                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5191                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5192                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5193                                 base + NvRegRingSizes);
5194                         pci_push(base);
5195                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5196                         pci_push(base);
5197                         /* restart rx engine */
5198                         nv_start_rxtx(dev);
5199                         netif_start_queue(dev);
5200                         nv_napi_enable(dev);
5201                         nv_enable_hw_interrupts(dev, np->irqmask);
5202                 }
5203         }
5204 }
5205
5206 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5207 {
5208         switch (stringset) {
5209         case ETH_SS_STATS:
5210                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5211                 break;
5212         case ETH_SS_TEST:
5213                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5214                 break;
5215         }
5216 }
5217
5218 static const struct ethtool_ops ops = {
5219         .get_drvinfo = nv_get_drvinfo,
5220         .get_link = ethtool_op_get_link,
5221         .get_wol = nv_get_wol,
5222         .set_wol = nv_set_wol,
5223         .get_settings = nv_get_settings,
5224         .set_settings = nv_set_settings,
5225         .get_regs_len = nv_get_regs_len,
5226         .get_regs = nv_get_regs,
5227         .nway_reset = nv_nway_reset,
5228         .set_tso = nv_set_tso,
5229         .get_ringparam = nv_get_ringparam,
5230         .set_ringparam = nv_set_ringparam,
5231         .get_pauseparam = nv_get_pauseparam,
5232         .set_pauseparam = nv_set_pauseparam,
5233         .get_rx_csum = nv_get_rx_csum,
5234         .set_rx_csum = nv_set_rx_csum,
5235         .set_tx_csum = nv_set_tx_csum,
5236         .set_sg = nv_set_sg,
5237         .get_strings = nv_get_strings,
5238         .get_ethtool_stats = nv_get_ethtool_stats,
5239         .get_sset_count = nv_get_sset_count,
5240         .self_test = nv_self_test,
5241 };
5242
5243 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5244 {
5245         struct fe_priv *np = get_nvpriv(dev);
5246
5247         spin_lock_irq(&np->lock);
5248
5249         /* save vlan group */
5250         np->vlangrp = grp;
5251
5252         if (grp) {
5253                 /* enable vlan on MAC */
5254                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5255         } else {
5256                 /* disable vlan on MAC */
5257                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5258                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5259         }
5260
5261         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5262
5263         spin_unlock_irq(&np->lock);
5264 }
5265
5266 /* The mgmt unit and driver use a semaphore to access the phy during init */
5267 static int nv_mgmt_acquire_sema(struct net_device *dev)
5268 {
5269         struct fe_priv *np = netdev_priv(dev);
5270         u8 __iomem *base = get_hwbase(dev);
5271         int i;
5272         u32 tx_ctrl, mgmt_sema;
5273
5274         for (i = 0; i < 10; i++) {
5275                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5276                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5277                         break;
5278                 msleep(500);
5279         }
5280
5281         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5282                 return 0;
5283
5284         for (i = 0; i < 2; i++) {
5285                 tx_ctrl = readl(base + NvRegTransmitterControl);
5286                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5287                 writel(tx_ctrl, base + NvRegTransmitterControl);
5288
5289                 /* verify that semaphore was acquired */
5290                 tx_ctrl = readl(base + NvRegTransmitterControl);
5291                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5292                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5293                         np->mgmt_sema = 1;
5294                         return 1;
5295                 }
5296                 else
5297                         udelay(50);
5298         }
5299
5300         return 0;
5301 }
5302
5303 static void nv_mgmt_release_sema(struct net_device *dev)
5304 {
5305         struct fe_priv *np = netdev_priv(dev);
5306         u8 __iomem *base = get_hwbase(dev);
5307         u32 tx_ctrl;
5308
5309         if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5310                 if (np->mgmt_sema) {
5311                         tx_ctrl = readl(base + NvRegTransmitterControl);
5312                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5313                         writel(tx_ctrl, base + NvRegTransmitterControl);
5314                 }
5315         }
5316 }
5317
5318
5319 static int nv_mgmt_get_version(struct net_device *dev)
5320 {
5321         struct fe_priv *np = netdev_priv(dev);
5322         u8 __iomem *base = get_hwbase(dev);
5323         u32 data_ready = readl(base + NvRegTransmitterControl);
5324         u32 data_ready2 = 0;
5325         unsigned long start;
5326         int ready = 0;
5327
5328         writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5329         writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5330         start = jiffies;
5331         while (time_before(jiffies, start + 5*HZ)) {
5332                 data_ready2 = readl(base + NvRegTransmitterControl);
5333                 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5334                         ready = 1;
5335                         break;
5336                 }
5337                 schedule_timeout_uninterruptible(1);
5338         }
5339
5340         if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5341                 return 0;
5342
5343         np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5344
5345         return 1;
5346 }
5347
5348 static int nv_open(struct net_device *dev)
5349 {
5350         struct fe_priv *np = netdev_priv(dev);
5351         u8 __iomem *base = get_hwbase(dev);
5352         int ret = 1;
5353         int oom, i;
5354         u32 low;
5355
5356         dprintk(KERN_DEBUG "nv_open: begin\n");
5357
5358         /* power up phy */
5359         mii_rw(dev, np->phyaddr, MII_BMCR,
5360                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5361
5362         nv_txrx_gate(dev, false);
5363         /* erase previous misconfiguration */
5364         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5365                 nv_mac_reset(dev);
5366         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5367         writel(0, base + NvRegMulticastAddrB);
5368         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5369         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5370         writel(0, base + NvRegPacketFilterFlags);
5371
5372         writel(0, base + NvRegTransmitterControl);
5373         writel(0, base + NvRegReceiverControl);
5374
5375         writel(0, base + NvRegAdapterControl);
5376
5377         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5378                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5379
5380         /* initialize descriptor rings */
5381         set_bufsize(dev);
5382         oom = nv_init_ring(dev);
5383
5384         writel(0, base + NvRegLinkSpeed);
5385         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5386         nv_txrx_reset(dev);
5387         writel(0, base + NvRegUnknownSetupReg6);
5388
5389         np->in_shutdown = 0;
5390
5391         /* give hw rings */
5392         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5393         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5394                 base + NvRegRingSizes);
5395
5396         writel(np->linkspeed, base + NvRegLinkSpeed);
5397         if (np->desc_ver == DESC_VER_1)
5398                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5399         else
5400                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5401         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5402         writel(np->vlanctl_bits, base + NvRegVlanControl);
5403         pci_push(base);
5404         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5405         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5406                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5407                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5408
5409         writel(0, base + NvRegMIIMask);
5410         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5411         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5412
5413         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5414         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5415         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5416         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5417
5418         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5419
5420         get_random_bytes(&low, sizeof(low));
5421         low &= NVREG_SLOTTIME_MASK;
5422         if (np->desc_ver == DESC_VER_1) {
5423                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5424         } else {
5425                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5426                         /* setup legacy backoff */
5427                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5428                 } else {
5429                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5430                         nv_gear_backoff_reseed(dev);
5431                 }
5432         }
5433         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5434         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5435         if (poll_interval == -1) {
5436                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5437                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5438                 else
5439                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5440         }
5441         else
5442                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5443         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5444         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5445                         base + NvRegAdapterControl);
5446         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5447         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5448         if (np->wolenabled)
5449                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5450
5451         i = readl(base + NvRegPowerState);
5452         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5453                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5454
5455         pci_push(base);
5456         udelay(10);
5457         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5458
5459         nv_disable_hw_interrupts(dev, np->irqmask);
5460         pci_push(base);
5461         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5462         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5463         pci_push(base);
5464
5465         if (nv_request_irq(dev, 0)) {
5466                 goto out_drain;
5467         }
5468
5469         /* ask for interrupts */
5470         nv_enable_hw_interrupts(dev, np->irqmask);
5471
5472         spin_lock_irq(&np->lock);
5473         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5474         writel(0, base + NvRegMulticastAddrB);
5475         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5476         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5477         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5478         /* One manual link speed update: Interrupts are enabled, future link
5479          * speed changes cause interrupts and are handled by nv_link_irq().
5480          */
5481         {
5482                 u32 miistat;
5483                 miistat = readl(base + NvRegMIIStatus);
5484                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5485                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5486         }
5487         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5488          * to init hw */
5489         np->linkspeed = 0;
5490         ret = nv_update_linkspeed(dev);
5491         nv_start_rxtx(dev);
5492         netif_start_queue(dev);
5493         nv_napi_enable(dev);
5494
5495         if (ret) {
5496                 netif_carrier_on(dev);
5497         } else {
5498                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5499                 netif_carrier_off(dev);
5500         }
5501         if (oom)
5502                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5503
5504         /* start statistics timer */
5505         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5506                 mod_timer(&np->stats_poll,
5507                         round_jiffies(jiffies + STATS_INTERVAL));
5508
5509         spin_unlock_irq(&np->lock);
5510
5511         return 0;
5512 out_drain:
5513         nv_drain_rxtx(dev);
5514         return ret;
5515 }
5516
5517 static int nv_close(struct net_device *dev)
5518 {
5519         struct fe_priv *np = netdev_priv(dev);
5520         u8 __iomem *base;
5521
5522         spin_lock_irq(&np->lock);
5523         np->in_shutdown = 1;
5524         spin_unlock_irq(&np->lock);
5525         nv_napi_disable(dev);
5526         synchronize_irq(np->pci_dev->irq);
5527
5528         del_timer_sync(&np->oom_kick);
5529         del_timer_sync(&np->nic_poll);
5530         del_timer_sync(&np->stats_poll);
5531
5532         netif_stop_queue(dev);
5533         spin_lock_irq(&np->lock);
5534         nv_stop_rxtx(dev);
5535         nv_txrx_reset(dev);
5536
5537         /* disable interrupts on the nic or we will lock up */
5538         base = get_hwbase(dev);
5539         nv_disable_hw_interrupts(dev, np->irqmask);
5540         pci_push(base);
5541         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5542
5543         spin_unlock_irq(&np->lock);
5544
5545         nv_free_irq(dev);
5546
5547         nv_drain_rxtx(dev);
5548
5549         if (np->wolenabled || !phy_power_down) {
5550                 nv_txrx_gate(dev, false);
5551                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5552                 nv_start_rx(dev);
5553         } else {
5554                 /* power down phy */
5555                 mii_rw(dev, np->phyaddr, MII_BMCR,
5556                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5557                 nv_txrx_gate(dev, true);
5558         }
5559
5560         /* FIXME: power down nic */
5561
5562         return 0;
5563 }
5564
5565 static const struct net_device_ops nv_netdev_ops = {
5566         .ndo_open               = nv_open,
5567         .ndo_stop               = nv_close,
5568         .ndo_get_stats          = nv_get_stats,
5569         .ndo_start_xmit         = nv_start_xmit,
5570         .ndo_tx_timeout         = nv_tx_timeout,
5571         .ndo_change_mtu         = nv_change_mtu,
5572         .ndo_validate_addr      = eth_validate_addr,
5573         .ndo_set_mac_address    = nv_set_mac_address,
5574         .ndo_set_multicast_list = nv_set_multicast,
5575         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5576 #ifdef CONFIG_NET_POLL_CONTROLLER
5577         .ndo_poll_controller    = nv_poll_controller,
5578 #endif
5579 };
5580
5581 static const struct net_device_ops nv_netdev_ops_optimized = {
5582         .ndo_open               = nv_open,
5583         .ndo_stop               = nv_close,
5584         .ndo_get_stats          = nv_get_stats,
5585         .ndo_start_xmit         = nv_start_xmit_optimized,
5586         .ndo_tx_timeout         = nv_tx_timeout,
5587         .ndo_change_mtu         = nv_change_mtu,
5588         .ndo_validate_addr      = eth_validate_addr,
5589         .ndo_set_mac_address    = nv_set_mac_address,
5590         .ndo_set_multicast_list = nv_set_multicast,
5591         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5592 #ifdef CONFIG_NET_POLL_CONTROLLER
5593         .ndo_poll_controller    = nv_poll_controller,
5594 #endif
5595 };
5596
5597 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5598 {
5599         struct net_device *dev;
5600         struct fe_priv *np;
5601         unsigned long addr;
5602         u8 __iomem *base;
5603         int err, i;
5604         u32 powerstate, txreg;
5605         u32 phystate_orig = 0, phystate;
5606         int phyinitialized = 0;
5607         static int printed_version;
5608
5609         if (!printed_version++)
5610                 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5611                        " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5612
5613         dev = alloc_etherdev(sizeof(struct fe_priv));
5614         err = -ENOMEM;
5615         if (!dev)
5616                 goto out;
5617
5618         np = netdev_priv(dev);
5619         np->dev = dev;
5620         np->pci_dev = pci_dev;
5621         spin_lock_init(&np->lock);
5622         SET_NETDEV_DEV(dev, &pci_dev->dev);
5623
5624         init_timer(&np->oom_kick);
5625         np->oom_kick.data = (unsigned long) dev;
5626         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
5627         init_timer(&np->nic_poll);
5628         np->nic_poll.data = (unsigned long) dev;
5629         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
5630         init_timer(&np->stats_poll);
5631         np->stats_poll.data = (unsigned long) dev;
5632         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
5633
5634         err = pci_enable_device(pci_dev);
5635         if (err)
5636                 goto out_free;
5637
5638         pci_set_master(pci_dev);
5639
5640         err = pci_request_regions(pci_dev, DRV_NAME);
5641         if (err < 0)
5642                 goto out_disable;
5643
5644         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5645                 np->register_size = NV_PCI_REGSZ_VER3;
5646         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5647                 np->register_size = NV_PCI_REGSZ_VER2;
5648         else
5649                 np->register_size = NV_PCI_REGSZ_VER1;
5650
5651         err = -EINVAL;
5652         addr = 0;
5653         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5654                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5655                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5656                                 pci_resource_len(pci_dev, i),
5657                                 pci_resource_flags(pci_dev, i));
5658                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5659                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5660                         addr = pci_resource_start(pci_dev, i);
5661                         break;
5662                 }
5663         }
5664         if (i == DEVICE_COUNT_RESOURCE) {
5665                 dev_printk(KERN_INFO, &pci_dev->dev,
5666                            "Couldn't find register window\n");
5667                 goto out_relreg;
5668         }
5669
5670         /* copy of driver data */
5671         np->driver_data = id->driver_data;
5672         /* copy of device id */
5673         np->device_id = id->device;
5674
5675         /* handle different descriptor versions */
5676         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5677                 /* packet format 3: supports 40-bit addressing */
5678                 np->desc_ver = DESC_VER_3;
5679                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5680                 if (dma_64bit) {
5681                         if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5682                                 dev_printk(KERN_INFO, &pci_dev->dev,
5683                                         "64-bit DMA failed, using 32-bit addressing\n");
5684                         else
5685                                 dev->features |= NETIF_F_HIGHDMA;
5686                         if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5687                                 dev_printk(KERN_INFO, &pci_dev->dev,
5688                                         "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5689                         }
5690                 }
5691         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5692                 /* packet format 2: supports jumbo frames */
5693                 np->desc_ver = DESC_VER_2;
5694                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5695         } else {
5696                 /* original packet format */
5697                 np->desc_ver = DESC_VER_1;
5698                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5699         }
5700
5701         np->pkt_limit = NV_PKTLIMIT_1;
5702         if (id->driver_data & DEV_HAS_LARGEDESC)
5703                 np->pkt_limit = NV_PKTLIMIT_2;
5704
5705         if (id->driver_data & DEV_HAS_CHECKSUM) {
5706                 np->rx_csum = 1;
5707                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5708                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
5709                 dev->features |= NETIF_F_TSO;
5710         }
5711
5712         np->vlanctl_bits = 0;
5713         if (id->driver_data & DEV_HAS_VLAN) {
5714                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5715                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5716         }
5717
5718         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5719         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5720             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5721             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5722                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5723         }
5724
5725
5726         err = -ENOMEM;
5727         np->base = ioremap(addr, np->register_size);
5728         if (!np->base)
5729                 goto out_relreg;
5730         dev->base_addr = (unsigned long)np->base;
5731
5732         dev->irq = pci_dev->irq;
5733
5734         np->rx_ring_size = RX_RING_DEFAULT;
5735         np->tx_ring_size = TX_RING_DEFAULT;
5736
5737         if (!nv_optimized(np)) {
5738                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5739                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5740                                         &np->ring_addr);
5741                 if (!np->rx_ring.orig)
5742                         goto out_unmap;
5743                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5744         } else {
5745                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5746                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5747                                         &np->ring_addr);
5748                 if (!np->rx_ring.ex)
5749                         goto out_unmap;
5750                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5751         }
5752         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5753         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5754         if (!np->rx_skb || !np->tx_skb)
5755                 goto out_freering;
5756
5757         if (!nv_optimized(np))
5758                 dev->netdev_ops = &nv_netdev_ops;
5759         else
5760                 dev->netdev_ops = &nv_netdev_ops_optimized;
5761
5762 #ifdef CONFIG_FORCEDETH_NAPI
5763         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5764 #endif
5765         SET_ETHTOOL_OPS(dev, &ops);
5766         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5767
5768         pci_set_drvdata(pci_dev, dev);
5769
5770         /* read the mac address */
5771         base = get_hwbase(dev);
5772         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5773         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5774
5775         /* check the workaround bit for correct mac address order */
5776         txreg = readl(base + NvRegTransmitPoll);
5777         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5778                 /* mac address is already in correct order */
5779                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5780                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5781                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5782                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5783                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5784                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5785         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5786                 /* mac address is already in correct order */
5787                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5788                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5789                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5790                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5791                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5792                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5793                 /*
5794                  * Set orig mac address back to the reversed version.
5795                  * This flag will be cleared during low power transition.
5796                  * Therefore, we should always put back the reversed address.
5797                  */
5798                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5799                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5800                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5801         } else {
5802                 /* need to reverse mac address to correct order */
5803                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5804                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5805                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5806                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5807                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5808                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5809                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5810                 printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
5811         }
5812         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5813
5814         if (!is_valid_ether_addr(dev->perm_addr)) {
5815                 /*
5816                  * Bad mac address. At least one bios sets the mac address
5817                  * to 01:23:45:67:89:ab
5818                  */
5819                 dev_printk(KERN_ERR, &pci_dev->dev,
5820                         "Invalid Mac address detected: %pM\n",
5821                         dev->dev_addr);
5822                 dev_printk(KERN_ERR, &pci_dev->dev,
5823                         "Please complain to your hardware vendor. Switching to a random MAC.\n");
5824                 random_ether_addr(dev->dev_addr);
5825         }
5826
5827         dprintk(KERN_DEBUG "%s: MAC Address %pM\n",
5828                 pci_name(pci_dev), dev->dev_addr);
5829
5830         /* set mac address */
5831         nv_copy_mac_to_hw(dev);
5832
5833         /* Workaround current PCI init glitch:  wakeup bits aren't
5834          * being set from PCI PM capability.
5835          */
5836         device_init_wakeup(&pci_dev->dev, 1);
5837
5838         /* disable WOL */
5839         writel(0, base + NvRegWakeUpFlags);
5840         np->wolenabled = 0;
5841
5842         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5843
5844                 /* take phy and nic out of low power mode */
5845                 powerstate = readl(base + NvRegPowerState2);
5846                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5847                 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5848                     pci_dev->revision >= 0xA3)
5849                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5850                 writel(powerstate, base + NvRegPowerState2);
5851         }
5852
5853         if (np->desc_ver == DESC_VER_1) {
5854                 np->tx_flags = NV_TX_VALID;
5855         } else {
5856                 np->tx_flags = NV_TX2_VALID;
5857         }
5858
5859         np->msi_flags = 0;
5860         if ((id->driver_data & DEV_HAS_MSI) && msi) {
5861                 np->msi_flags |= NV_MSI_CAPABLE;
5862         }
5863         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5864                 /* msix has had reported issues when modifying irqmask
5865                    as in the case of napi, therefore, disable for now
5866                 */
5867 #ifndef CONFIG_FORCEDETH_NAPI
5868                 np->msi_flags |= NV_MSI_X_CAPABLE;
5869 #endif
5870         }
5871
5872         if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5873                 np->irqmask = NVREG_IRQMASK_CPU;
5874                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5875                         np->msi_flags |= 0x0001;
5876         } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5877                    !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5878                 /* start off in throughput mode */
5879                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5880                 /* remove support for msix mode */
5881                 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5882         } else {
5883                 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5884                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5885                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5886                         np->msi_flags |= 0x0003;
5887         }
5888
5889         if (id->driver_data & DEV_NEED_TIMERIRQ)
5890                 np->irqmask |= NVREG_IRQ_TIMER;
5891         if (id->driver_data & DEV_NEED_LINKTIMER) {
5892                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5893                 np->need_linktimer = 1;
5894                 np->link_timeout = jiffies + LINK_TIMEOUT;
5895         } else {
5896                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5897                 np->need_linktimer = 0;
5898         }
5899
5900         /* Limit the number of tx's outstanding for hw bug */
5901         if (id->driver_data & DEV_NEED_TX_LIMIT) {
5902                 np->tx_limit = 1;
5903                 if ((id->driver_data & DEV_NEED_TX_LIMIT2) &&
5904                     pci_dev->revision >= 0xA2)
5905                         np->tx_limit = 0;
5906         }
5907
5908         /* clear phy state and temporarily halt phy interrupts */
5909         writel(0, base + NvRegMIIMask);
5910         phystate = readl(base + NvRegAdapterControl);
5911         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5912                 phystate_orig = 1;
5913                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5914                 writel(phystate, base + NvRegAdapterControl);
5915         }
5916         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5917
5918         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5919                 /* management unit running on the mac? */
5920                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5921                     (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5922                     nv_mgmt_acquire_sema(dev) &&
5923                     nv_mgmt_get_version(dev)) {
5924                         np->mac_in_use = 1;
5925                         if (np->mgmt_version > 0) {
5926                                 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5927                         }
5928                         dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n",
5929                                 pci_name(pci_dev), np->mac_in_use);
5930                         /* management unit setup the phy already? */
5931                         if (np->mac_in_use &&
5932                             ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5933                              NVREG_XMITCTL_SYNC_PHY_INIT)) {
5934                                 /* phy is inited by mgmt unit */
5935                                 phyinitialized = 1;
5936                                 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n",
5937                                         pci_name(pci_dev));
5938                         } else {
5939                                 /* we need to init the phy */
5940                         }
5941                 }
5942         }
5943
5944         /* find a suitable phy */
5945         for (i = 1; i <= 32; i++) {
5946                 int id1, id2;
5947                 int phyaddr = i & 0x1F;
5948
5949                 spin_lock_irq(&np->lock);
5950                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5951                 spin_unlock_irq(&np->lock);
5952                 if (id1 < 0 || id1 == 0xffff)
5953                         continue;
5954                 spin_lock_irq(&np->lock);
5955                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5956                 spin_unlock_irq(&np->lock);
5957                 if (id2 < 0 || id2 == 0xffff)
5958                         continue;
5959
5960                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5961                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5962                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5963                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5964                         pci_name(pci_dev), id1, id2, phyaddr);
5965                 np->phyaddr = phyaddr;
5966                 np->phy_oui = id1 | id2;
5967
5968                 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5969                 if (np->phy_oui == PHY_OUI_REALTEK2)
5970                         np->phy_oui = PHY_OUI_REALTEK;
5971                 /* Setup phy revision for Realtek */
5972                 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5973                         np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5974
5975                 break;
5976         }
5977         if (i == 33) {
5978                 dev_printk(KERN_INFO, &pci_dev->dev,
5979                         "open: Could not find a valid PHY.\n");
5980                 goto out_error;
5981         }
5982
5983         if (!phyinitialized) {
5984                 /* reset it */
5985                 phy_init(dev);
5986         } else {
5987                 /* see if it is a gigabit phy */
5988                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5989                 if (mii_status & PHY_GIGABIT) {
5990                         np->gigabit = PHY_GIGABIT;
5991                 }
5992         }
5993
5994         /* set default link speed settings */
5995         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5996         np->duplex = 0;
5997         np->autoneg = 1;
5998
5999         err = register_netdev(dev);
6000         if (err) {
6001                 dev_printk(KERN_INFO, &pci_dev->dev,
6002                            "unable to register netdev: %d\n", err);
6003                 goto out_error;
6004         }
6005
6006         dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
6007                    "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
6008                    dev->name,
6009                    np->phy_oui,
6010                    np->phyaddr,
6011                    dev->dev_addr[0],
6012                    dev->dev_addr[1],
6013                    dev->dev_addr[2],
6014                    dev->dev_addr[3],
6015                    dev->dev_addr[4],
6016                    dev->dev_addr[5]);
6017
6018         dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
6019                    dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
6020                    dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
6021                         "csum " : "",
6022                    dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
6023                         "vlan " : "",
6024                    id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
6025                    id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
6026                    id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
6027                    np->gigabit == PHY_GIGABIT ? "gbit " : "",
6028                    np->need_linktimer ? "lnktim " : "",
6029                    np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
6030                    np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
6031                    np->desc_ver);
6032
6033         return 0;
6034
6035 out_error:
6036         if (phystate_orig)
6037                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
6038         pci_set_drvdata(pci_dev, NULL);
6039 out_freering:
6040         free_rings(dev);
6041 out_unmap:
6042         iounmap(get_hwbase(dev));
6043 out_relreg:
6044         pci_release_regions(pci_dev);
6045 out_disable:
6046         pci_disable_device(pci_dev);
6047 out_free:
6048         free_netdev(dev);
6049 out:
6050         return err;
6051 }
6052
6053 static void nv_restore_phy(struct net_device *dev)
6054 {
6055         struct fe_priv *np = netdev_priv(dev);
6056         u16 phy_reserved, mii_control;
6057
6058         if (np->phy_oui == PHY_OUI_REALTEK &&
6059             np->phy_model == PHY_MODEL_REALTEK_8201 &&
6060             phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
6061                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
6062                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
6063                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
6064                 phy_reserved |= PHY_REALTEK_INIT8;
6065                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
6066                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
6067
6068                 /* restart auto negotiation */
6069                 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
6070                 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
6071                 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
6072         }
6073 }
6074
6075 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
6076 {
6077         struct net_device *dev = pci_get_drvdata(pci_dev);
6078         struct fe_priv *np = netdev_priv(dev);
6079         u8 __iomem *base = get_hwbase(dev);
6080
6081         /* special op: write back the misordered MAC address - otherwise
6082          * the next nv_probe would see a wrong address.
6083          */
6084         writel(np->orig_mac[0], base + NvRegMacAddrA);
6085         writel(np->orig_mac[1], base + NvRegMacAddrB);
6086         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
6087                base + NvRegTransmitPoll);
6088 }
6089
6090 static void __devexit nv_remove(struct pci_dev *pci_dev)
6091 {
6092         struct net_device *dev = pci_get_drvdata(pci_dev);
6093
6094         unregister_netdev(dev);
6095
6096         nv_restore_mac_addr(pci_dev);
6097
6098         /* restore any phy related changes */
6099         nv_restore_phy(dev);
6100
6101         nv_mgmt_release_sema(dev);
6102
6103         /* free all structures */
6104         free_rings(dev);
6105         iounmap(get_hwbase(dev));
6106         pci_release_regions(pci_dev);
6107         pci_disable_device(pci_dev);
6108         free_netdev(dev);
6109         pci_set_drvdata(pci_dev, NULL);
6110 }
6111
6112 #ifdef CONFIG_PM
6113 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
6114 {
6115         struct net_device *dev = pci_get_drvdata(pdev);
6116         struct fe_priv *np = netdev_priv(dev);
6117         u8 __iomem *base = get_hwbase(dev);
6118         int i;
6119
6120         if (netif_running(dev)) {
6121                 // Gross.
6122                 nv_close(dev);
6123         }
6124         netif_device_detach(dev);
6125
6126         /* save non-pci configuration space */
6127         for (i = 0;i <= np->register_size/sizeof(u32); i++)
6128                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6129
6130         pci_save_state(pdev);
6131         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
6132         pci_disable_device(pdev);
6133         pci_set_power_state(pdev, pci_choose_state(pdev, state));
6134         return 0;
6135 }
6136
6137 static int nv_resume(struct pci_dev *pdev)
6138 {
6139         struct net_device *dev = pci_get_drvdata(pdev);
6140         struct fe_priv *np = netdev_priv(dev);
6141         u8 __iomem *base = get_hwbase(dev);
6142         int i, rc = 0;
6143
6144         pci_set_power_state(pdev, PCI_D0);
6145         pci_restore_state(pdev);
6146         /* ack any pending wake events, disable PME */
6147         pci_enable_wake(pdev, PCI_D0, 0);
6148
6149         /* restore non-pci configuration space */
6150         for (i = 0;i <= np->register_size/sizeof(u32); i++)
6151                 writel(np->saved_config_space[i], base+i*sizeof(u32));
6152
6153         if (np->driver_data & DEV_NEED_MSI_FIX)
6154                 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6155
6156         /* restore phy state, including autoneg */
6157         phy_init(dev);
6158
6159         netif_device_attach(dev);
6160         if (netif_running(dev)) {
6161                 rc = nv_open(dev);
6162                 nv_set_multicast(dev);
6163         }
6164         return rc;
6165 }
6166
6167 static void nv_shutdown(struct pci_dev *pdev)
6168 {
6169         struct net_device *dev = pci_get_drvdata(pdev);
6170         struct fe_priv *np = netdev_priv(dev);
6171
6172         if (netif_running(dev))
6173                 nv_close(dev);
6174
6175         /*
6176          * Restore the MAC so a kernel started by kexec won't get confused.
6177          * If we really go for poweroff, we must not restore the MAC,
6178          * otherwise the MAC for WOL will be reversed at least on some boards.
6179          */
6180         if (system_state != SYSTEM_POWER_OFF) {
6181                 nv_restore_mac_addr(pdev);
6182         }
6183
6184         pci_disable_device(pdev);
6185         /*
6186          * Apparently it is not possible to reinitialise from D3 hot,
6187          * only put the device into D3 if we really go for poweroff.
6188          */
6189         if (system_state == SYSTEM_POWER_OFF) {
6190                 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
6191                         pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
6192                 pci_set_power_state(pdev, PCI_D3hot);
6193         }
6194 }
6195 #else
6196 #define nv_suspend NULL
6197 #define nv_shutdown NULL
6198 #define nv_resume NULL
6199 #endif /* CONFIG_PM */
6200
6201 static struct pci_device_id pci_tbl[] = {
6202         {       /* nForce Ethernet Controller */
6203                 PCI_DEVICE(0x10DE, 0x01C3),
6204                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6205         },
6206         {       /* nForce2 Ethernet Controller */
6207                 PCI_DEVICE(0x10DE, 0x0066),
6208                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6209         },
6210         {       /* nForce3 Ethernet Controller */
6211                 PCI_DEVICE(0x10DE, 0x00D6),
6212                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6213         },
6214         {       /* nForce3 Ethernet Controller */
6215                 PCI_DEVICE(0x10DE, 0x0086),
6216                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6217         },
6218         {       /* nForce3 Ethernet Controller */
6219                 PCI_DEVICE(0x10DE, 0x008C),
6220                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6221         },
6222         {       /* nForce3 Ethernet Controller */
6223                 PCI_DEVICE(0x10DE, 0x00E6),
6224                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6225         },
6226         {       /* nForce3 Ethernet Controller */
6227                 PCI_DEVICE(0x10DE, 0x00DF),
6228                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6229         },
6230         {       /* CK804 Ethernet Controller */
6231                 PCI_DEVICE(0x10DE, 0x0056),
6232                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6233         },
6234         {       /* CK804 Ethernet Controller */
6235                 PCI_DEVICE(0x10DE, 0x0057),
6236                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6237         },
6238         {       /* MCP04 Ethernet Controller */
6239                 PCI_DEVICE(0x10DE, 0x0037),
6240                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6241         },
6242         {       /* MCP04 Ethernet Controller */
6243                 PCI_DEVICE(0x10DE, 0x0038),
6244                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6245         },
6246         {       /* MCP51 Ethernet Controller */
6247                 PCI_DEVICE(0x10DE, 0x0268),
6248                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6249         },
6250         {       /* MCP51 Ethernet Controller */
6251                 PCI_DEVICE(0x10DE, 0x0269),
6252                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6253         },
6254         {       /* MCP55 Ethernet Controller */
6255                 PCI_DEVICE(0x10DE, 0x0372),
6256                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6257         },
6258         {       /* MCP55 Ethernet Controller */
6259                 PCI_DEVICE(0x10DE, 0x0373),
6260                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6261         },
6262         {       /* MCP61 Ethernet Controller */
6263                 PCI_DEVICE(0x10DE, 0x03E5),
6264                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6265         },
6266         {       /* MCP61 Ethernet Controller */
6267                 PCI_DEVICE(0x10DE, 0x03E6),
6268                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6269         },
6270         {       /* MCP61 Ethernet Controller */
6271                 PCI_DEVICE(0x10DE, 0x03EE),
6272                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6273         },
6274         {       /* MCP61 Ethernet Controller */
6275                 PCI_DEVICE(0x10DE, 0x03EF),
6276                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6277         },
6278         {       /* MCP65 Ethernet Controller */
6279                 PCI_DEVICE(0x10DE, 0x0450),
6280                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6281         },
6282         {       /* MCP65 Ethernet Controller */
6283                 PCI_DEVICE(0x10DE, 0x0451),
6284                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6285         },
6286         {       /* MCP65 Ethernet Controller */
6287                 PCI_DEVICE(0x10DE, 0x0452),
6288                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6289         },
6290         {       /* MCP65 Ethernet Controller */
6291                 PCI_DEVICE(0x10DE, 0x0453),
6292                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6293         },
6294         {       /* MCP67 Ethernet Controller */
6295                 PCI_DEVICE(0x10DE, 0x054C),
6296                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6297         },
6298         {       /* MCP67 Ethernet Controller */
6299                 PCI_DEVICE(0x10DE, 0x054D),
6300                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6301         },
6302         {       /* MCP67 Ethernet Controller */
6303                 PCI_DEVICE(0x10DE, 0x054E),
6304                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6305         },
6306         {       /* MCP67 Ethernet Controller */
6307                 PCI_DEVICE(0x10DE, 0x054F),
6308                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6309         },
6310         {       /* MCP73 Ethernet Controller */
6311                 PCI_DEVICE(0x10DE, 0x07DC),
6312                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6313         },
6314         {       /* MCP73 Ethernet Controller */
6315                 PCI_DEVICE(0x10DE, 0x07DD),
6316                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6317         },
6318         {       /* MCP73 Ethernet Controller */
6319                 PCI_DEVICE(0x10DE, 0x07DE),
6320                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6321         },
6322         {       /* MCP73 Ethernet Controller */
6323                 PCI_DEVICE(0x10DE, 0x07DF),
6324                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6325         },
6326         {       /* MCP77 Ethernet Controller */
6327                 PCI_DEVICE(0x10DE, 0x0760),
6328                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6329         },
6330         {       /* MCP77 Ethernet Controller */
6331                 PCI_DEVICE(0x10DE, 0x0761),
6332                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6333         },
6334         {       /* MCP77 Ethernet Controller */
6335                 PCI_DEVICE(0x10DE, 0x0762),
6336                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6337         },
6338         {       /* MCP77 Ethernet Controller */
6339                 PCI_DEVICE(0x10DE, 0x0763),
6340                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6341         },
6342         {       /* MCP79 Ethernet Controller */
6343                 PCI_DEVICE(0x10DE, 0x0AB0),
6344                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6345         },
6346         {       /* MCP79 Ethernet Controller */
6347                 PCI_DEVICE(0x10DE, 0x0AB1),
6348                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6349         },
6350         {       /* MCP79 Ethernet Controller */
6351                 PCI_DEVICE(0x10DE, 0x0AB2),
6352                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6353         },
6354         {       /* MCP79 Ethernet Controller */
6355                 PCI_DEVICE(0x10DE, 0x0AB3),
6356                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6357         },
6358         {       /* MCP89 Ethernet Controller */
6359                 PCI_DEVICE(0x10DE, 0x0D7D),
6360                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6361         },
6362         {0,},
6363 };
6364
6365 static struct pci_driver driver = {
6366         .name           = DRV_NAME,
6367         .id_table       = pci_tbl,
6368         .probe          = nv_probe,
6369         .remove         = __devexit_p(nv_remove),
6370         .suspend        = nv_suspend,
6371         .resume         = nv_resume,
6372         .shutdown       = nv_shutdown,
6373 };
6374
6375 static int __init init_nic(void)
6376 {
6377         return pci_register_driver(&driver);
6378 }
6379
6380 static void __exit exit_nic(void)
6381 {
6382         pci_unregister_driver(&driver);
6383 }
6384
6385 module_param(max_interrupt_work, int, 0);
6386 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6387 module_param(optimization_mode, int, 0);
6388 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6389 module_param(poll_interval, int, 0);
6390 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6391 module_param(msi, int, 0);
6392 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6393 module_param(msix, int, 0);
6394 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6395 module_param(dma_64bit, int, 0);
6396 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6397 module_param(phy_cross, int, 0);
6398 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6399 module_param(phy_power_down, int, 0);
6400 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6401
6402 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6403 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6404 MODULE_LICENSE("GPL");
6405
6406 MODULE_DEVICE_TABLE(pci, pci_tbl);
6407
6408 module_init(init_nic);
6409 module_exit(exit_nic);