forcedeth: tx data path optimization
[linux-3.10.git] / drivers / net / forcedeth.c
1 /*
2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3  *
4  * Note: This driver is a cleanroom reimplementation based on reverse
5  *      engineered documentation written by Carl-Daniel Hailfinger
6  *      and Andrew de Quincey.
7  *
8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9  * trademarks of NVIDIA Corporation in the United States and other
10  * countries.
11  *
12  * Copyright (C) 2003,4,5 Manfred Spraul
13  * Copyright (C) 2004 Andrew de Quincey (wol support)
14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
16  * Copyright (c) 2004,5,6 NVIDIA Corporation
17  *
18  * This program is free software; you can redistribute it and/or modify
19  * it under the terms of the GNU General Public License as published by
20  * the Free Software Foundation; either version 2 of the License, or
21  * (at your option) any later version.
22  *
23  * This program is distributed in the hope that it will be useful,
24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26  * GNU General Public License for more details.
27  *
28  * You should have received a copy of the GNU General Public License
29  * along with this program; if not, write to the Free Software
30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
31  *
32  * Changelog:
33  *      0.01: 05 Oct 2003: First release that compiles without warnings.
34  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
35  *                         Check all PCI BARs for the register window.
36  *                         udelay added to mii_rw.
37  *      0.03: 06 Oct 2003: Initialize dev->irq.
38  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
39  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
40  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
41  *                         irq mask updated
42  *      0.07: 14 Oct 2003: Further irq mask updates.
43  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
44  *                         added into irq handler, NULL check for drain_ring.
45  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
46  *                         requested interrupt sources.
47  *      0.10: 20 Oct 2003: First cleanup for release.
48  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
49  *                         MAC Address init fix, set_multicast cleanup.
50  *      0.12: 23 Oct 2003: Cleanups for release.
51  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
52  *                         Set link speed correctly. start rx before starting
53  *                         tx (nv_start_rx sets the link speed).
54  *      0.14: 25 Oct 2003: Nic dependant irq mask.
55  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
56  *                         open.
57  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
58  *                         increased to 1628 bytes.
59  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
60  *                         the tx length.
61  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
62  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
63  *                         addresses, really stop rx if already running
64  *                         in nv_start_rx, clean up a bit.
65  *      0.20: 07 Dec 2003: alloc fixes
66  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
67  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
68  *                         on close.
69  *      0.23: 26 Jan 2004: various small cleanups
70  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
71  *      0.25: 09 Mar 2004: wol support
72  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
73  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
74  *                         added CK804/MCP04 device IDs, code fixes
75  *                         for registers, link status and other minor fixes.
76  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
77  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
78  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
79  *                         into nv_close, otherwise reenabling for wol can
80  *                         cause DMA to kfree'd memory.
81  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
82  *                         capabilities.
83  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
84  *      0.33: 16 May 2005: Support for MCP51 added.
85  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
86  *      0.35: 26 Jun 2005: Support for MCP55 added.
87  *      0.36: 28 Jun 2005: Add jumbo frame support.
88  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
89  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
90  *                         per-packet flags.
91  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
92  *      0.40: 19 Jul 2005: Add support for mac address change.
93  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
94  *                         of nv_remove
95  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
96  *                         in the second (and later) nv_open call
97  *      0.43: 10 Aug 2005: Add support for tx checksum.
98  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
99  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
100  *      0.46: 20 Oct 2005: Add irq optimization modes.
101  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
102  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
103  *      0.49: 10 Dec 2005: Fix tso for large buffers.
104  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
105  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
106  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
107  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
108  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
109  *      0.55: 22 Mar 2006: Add flow control (pause frame).
110  *      0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
111  *      0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
112  *      0.58: 30 Oct 2006: Added support for sideband management unit.
113  *      0.59: 30 Oct 2006: Added support for recoverable error.
114  *
115  * Known bugs:
116  * We suspect that on some hardware no TX done interrupts are generated.
117  * This means recovery from netif_stop_queue only happens if the hw timer
118  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
119  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
120  * If your hardware reliably generates tx done interrupts, then you can remove
121  * DEV_NEED_TIMERIRQ from the driver_data flags.
122  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
123  * superfluous timer interrupts from the nic.
124  */
125 #ifdef CONFIG_FORCEDETH_NAPI
126 #define DRIVERNAPI "-NAPI"
127 #else
128 #define DRIVERNAPI
129 #endif
130 #define FORCEDETH_VERSION               "0.59"
131 #define DRV_NAME                        "forcedeth"
132
133 #include <linux/module.h>
134 #include <linux/types.h>
135 #include <linux/pci.h>
136 #include <linux/interrupt.h>
137 #include <linux/netdevice.h>
138 #include <linux/etherdevice.h>
139 #include <linux/delay.h>
140 #include <linux/spinlock.h>
141 #include <linux/ethtool.h>
142 #include <linux/timer.h>
143 #include <linux/skbuff.h>
144 #include <linux/mii.h>
145 #include <linux/random.h>
146 #include <linux/init.h>
147 #include <linux/if_vlan.h>
148 #include <linux/dma-mapping.h>
149
150 #include <asm/irq.h>
151 #include <asm/io.h>
152 #include <asm/uaccess.h>
153 #include <asm/system.h>
154
155 #if 0
156 #define dprintk                 printk
157 #else
158 #define dprintk(x...)           do { } while (0)
159 #endif
160
161
162 /*
163  * Hardware access:
164  */
165
166 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
167 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
168 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
169 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
170 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
171 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
172 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
173 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
174 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
175 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
176 #define DEV_HAS_STATISTICS      0x0400  /* device supports hw statistics */
177 #define DEV_HAS_TEST_EXTENDED   0x0800  /* device supports extended diagnostic test */
178 #define DEV_HAS_MGMT_UNIT       0x1000  /* device supports management unit */
179
180 enum {
181         NvRegIrqStatus = 0x000,
182 #define NVREG_IRQSTAT_MIIEVENT  0x040
183 #define NVREG_IRQSTAT_MASK              0x81ff
184         NvRegIrqMask = 0x004,
185 #define NVREG_IRQ_RX_ERROR              0x0001
186 #define NVREG_IRQ_RX                    0x0002
187 #define NVREG_IRQ_RX_NOBUF              0x0004
188 #define NVREG_IRQ_TX_ERR                0x0008
189 #define NVREG_IRQ_TX_OK                 0x0010
190 #define NVREG_IRQ_TIMER                 0x0020
191 #define NVREG_IRQ_LINK                  0x0040
192 #define NVREG_IRQ_RX_FORCED             0x0080
193 #define NVREG_IRQ_TX_FORCED             0x0100
194 #define NVREG_IRQ_RECOVER_ERROR         0x8000
195 #define NVREG_IRQMASK_THROUGHPUT        0x00df
196 #define NVREG_IRQMASK_CPU               0x0040
197 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
198 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
199 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
200
201 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
202                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
203                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
204
205         NvRegUnknownSetupReg6 = 0x008,
206 #define NVREG_UNKSETUP6_VAL             3
207
208 /*
209  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
210  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
211  */
212         NvRegPollingInterval = 0x00c,
213 #define NVREG_POLL_DEFAULT_THROUGHPUT   970
214 #define NVREG_POLL_DEFAULT_CPU  13
215         NvRegMSIMap0 = 0x020,
216         NvRegMSIMap1 = 0x024,
217         NvRegMSIIrqMask = 0x030,
218 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
219         NvRegMisc1 = 0x080,
220 #define NVREG_MISC1_PAUSE_TX    0x01
221 #define NVREG_MISC1_HD          0x02
222 #define NVREG_MISC1_FORCE       0x3b0f3c
223
224         NvRegMacReset = 0x3c,
225 #define NVREG_MAC_RESET_ASSERT  0x0F3
226         NvRegTransmitterControl = 0x084,
227 #define NVREG_XMITCTL_START     0x01
228 #define NVREG_XMITCTL_MGMT_ST   0x40000000
229 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
230 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
231 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
232 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
233 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
234 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
235 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
236 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
237 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
238         NvRegTransmitterStatus = 0x088,
239 #define NVREG_XMITSTAT_BUSY     0x01
240
241         NvRegPacketFilterFlags = 0x8c,
242 #define NVREG_PFF_PAUSE_RX      0x08
243 #define NVREG_PFF_ALWAYS        0x7F0000
244 #define NVREG_PFF_PROMISC       0x80
245 #define NVREG_PFF_MYADDR        0x20
246 #define NVREG_PFF_LOOPBACK      0x10
247
248         NvRegOffloadConfig = 0x90,
249 #define NVREG_OFFLOAD_HOMEPHY   0x601
250 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
251         NvRegReceiverControl = 0x094,
252 #define NVREG_RCVCTL_START      0x01
253 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
254         NvRegReceiverStatus = 0x98,
255 #define NVREG_RCVSTAT_BUSY      0x01
256
257         NvRegRandomSeed = 0x9c,
258 #define NVREG_RNDSEED_MASK      0x00ff
259 #define NVREG_RNDSEED_FORCE     0x7f00
260 #define NVREG_RNDSEED_FORCE2    0x2d00
261 #define NVREG_RNDSEED_FORCE3    0x7400
262
263         NvRegTxDeferral = 0xA0,
264 #define NVREG_TX_DEFERRAL_DEFAULT       0x15050f
265 #define NVREG_TX_DEFERRAL_RGMII_10_100  0x16070f
266 #define NVREG_TX_DEFERRAL_RGMII_1000    0x14050f
267         NvRegRxDeferral = 0xA4,
268 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
269         NvRegMacAddrA = 0xA8,
270         NvRegMacAddrB = 0xAC,
271         NvRegMulticastAddrA = 0xB0,
272 #define NVREG_MCASTADDRA_FORCE  0x01
273         NvRegMulticastAddrB = 0xB4,
274         NvRegMulticastMaskA = 0xB8,
275         NvRegMulticastMaskB = 0xBC,
276
277         NvRegPhyInterface = 0xC0,
278 #define PHY_RGMII               0x10000000
279
280         NvRegTxRingPhysAddr = 0x100,
281         NvRegRxRingPhysAddr = 0x104,
282         NvRegRingSizes = 0x108,
283 #define NVREG_RINGSZ_TXSHIFT 0
284 #define NVREG_RINGSZ_RXSHIFT 16
285         NvRegTransmitPoll = 0x10c,
286 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
287         NvRegLinkSpeed = 0x110,
288 #define NVREG_LINKSPEED_FORCE 0x10000
289 #define NVREG_LINKSPEED_10      1000
290 #define NVREG_LINKSPEED_100     100
291 #define NVREG_LINKSPEED_1000    50
292 #define NVREG_LINKSPEED_MASK    (0xFFF)
293         NvRegUnknownSetupReg5 = 0x130,
294 #define NVREG_UNKSETUP5_BIT31   (1<<31)
295         NvRegTxWatermark = 0x13c,
296 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
297 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
298 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
299         NvRegTxRxControl = 0x144,
300 #define NVREG_TXRXCTL_KICK      0x0001
301 #define NVREG_TXRXCTL_BIT1      0x0002
302 #define NVREG_TXRXCTL_BIT2      0x0004
303 #define NVREG_TXRXCTL_IDLE      0x0008
304 #define NVREG_TXRXCTL_RESET     0x0010
305 #define NVREG_TXRXCTL_RXCHECK   0x0400
306 #define NVREG_TXRXCTL_DESC_1    0
307 #define NVREG_TXRXCTL_DESC_2    0x002100
308 #define NVREG_TXRXCTL_DESC_3    0xc02200
309 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
310 #define NVREG_TXRXCTL_VLANINS   0x00080
311         NvRegTxRingPhysAddrHigh = 0x148,
312         NvRegRxRingPhysAddrHigh = 0x14C,
313         NvRegTxPauseFrame = 0x170,
314 #define NVREG_TX_PAUSEFRAME_DISABLE     0x1ff0080
315 #define NVREG_TX_PAUSEFRAME_ENABLE      0x0c00030
316         NvRegMIIStatus = 0x180,
317 #define NVREG_MIISTAT_ERROR             0x0001
318 #define NVREG_MIISTAT_LINKCHANGE        0x0008
319 #define NVREG_MIISTAT_MASK              0x000f
320 #define NVREG_MIISTAT_MASK2             0x000f
321         NvRegMIIMask = 0x184,
322 #define NVREG_MII_LINKCHANGE            0x0008
323
324         NvRegAdapterControl = 0x188,
325 #define NVREG_ADAPTCTL_START    0x02
326 #define NVREG_ADAPTCTL_LINKUP   0x04
327 #define NVREG_ADAPTCTL_PHYVALID 0x40000
328 #define NVREG_ADAPTCTL_RUNNING  0x100000
329 #define NVREG_ADAPTCTL_PHYSHIFT 24
330         NvRegMIISpeed = 0x18c,
331 #define NVREG_MIISPEED_BIT8     (1<<8)
332 #define NVREG_MIIDELAY  5
333         NvRegMIIControl = 0x190,
334 #define NVREG_MIICTL_INUSE      0x08000
335 #define NVREG_MIICTL_WRITE      0x00400
336 #define NVREG_MIICTL_ADDRSHIFT  5
337         NvRegMIIData = 0x194,
338         NvRegWakeUpFlags = 0x200,
339 #define NVREG_WAKEUPFLAGS_VAL           0x7770
340 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
341 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
342 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
343 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
344 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
345 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
346 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
347 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
348 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
349 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
350
351         NvRegPatternCRC = 0x204,
352         NvRegPatternMask = 0x208,
353         NvRegPowerCap = 0x268,
354 #define NVREG_POWERCAP_D3SUPP   (1<<30)
355 #define NVREG_POWERCAP_D2SUPP   (1<<26)
356 #define NVREG_POWERCAP_D1SUPP   (1<<25)
357         NvRegPowerState = 0x26c,
358 #define NVREG_POWERSTATE_POWEREDUP      0x8000
359 #define NVREG_POWERSTATE_VALID          0x0100
360 #define NVREG_POWERSTATE_MASK           0x0003
361 #define NVREG_POWERSTATE_D0             0x0000
362 #define NVREG_POWERSTATE_D1             0x0001
363 #define NVREG_POWERSTATE_D2             0x0002
364 #define NVREG_POWERSTATE_D3             0x0003
365         NvRegTxCnt = 0x280,
366         NvRegTxZeroReXmt = 0x284,
367         NvRegTxOneReXmt = 0x288,
368         NvRegTxManyReXmt = 0x28c,
369         NvRegTxLateCol = 0x290,
370         NvRegTxUnderflow = 0x294,
371         NvRegTxLossCarrier = 0x298,
372         NvRegTxExcessDef = 0x29c,
373         NvRegTxRetryErr = 0x2a0,
374         NvRegRxFrameErr = 0x2a4,
375         NvRegRxExtraByte = 0x2a8,
376         NvRegRxLateCol = 0x2ac,
377         NvRegRxRunt = 0x2b0,
378         NvRegRxFrameTooLong = 0x2b4,
379         NvRegRxOverflow = 0x2b8,
380         NvRegRxFCSErr = 0x2bc,
381         NvRegRxFrameAlignErr = 0x2c0,
382         NvRegRxLenErr = 0x2c4,
383         NvRegRxUnicast = 0x2c8,
384         NvRegRxMulticast = 0x2cc,
385         NvRegRxBroadcast = 0x2d0,
386         NvRegTxDef = 0x2d4,
387         NvRegTxFrame = 0x2d8,
388         NvRegRxCnt = 0x2dc,
389         NvRegTxPause = 0x2e0,
390         NvRegRxPause = 0x2e4,
391         NvRegRxDropFrame = 0x2e8,
392         NvRegVlanControl = 0x300,
393 #define NVREG_VLANCONTROL_ENABLE        0x2000
394         NvRegMSIXMap0 = 0x3e0,
395         NvRegMSIXMap1 = 0x3e4,
396         NvRegMSIXIrqStatus = 0x3f0,
397
398         NvRegPowerState2 = 0x600,
399 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
400 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
401 };
402
403 /* Big endian: should work, but is untested */
404 struct ring_desc {
405         __le32 buf;
406         __le32 flaglen;
407 };
408
409 struct ring_desc_ex {
410         __le32 bufhigh;
411         __le32 buflow;
412         __le32 txvlan;
413         __le32 flaglen;
414 };
415
416 union ring_type {
417         struct ring_desc* orig;
418         struct ring_desc_ex* ex;
419 };
420
421 #define FLAG_MASK_V1 0xffff0000
422 #define FLAG_MASK_V2 0xffffc000
423 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
424 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
425
426 #define NV_TX_LASTPACKET        (1<<16)
427 #define NV_TX_RETRYERROR        (1<<19)
428 #define NV_TX_FORCED_INTERRUPT  (1<<24)
429 #define NV_TX_DEFERRED          (1<<26)
430 #define NV_TX_CARRIERLOST       (1<<27)
431 #define NV_TX_LATECOLLISION     (1<<28)
432 #define NV_TX_UNDERFLOW         (1<<29)
433 #define NV_TX_ERROR             (1<<30)
434 #define NV_TX_VALID             (1<<31)
435
436 #define NV_TX2_LASTPACKET       (1<<29)
437 #define NV_TX2_RETRYERROR       (1<<18)
438 #define NV_TX2_FORCED_INTERRUPT (1<<30)
439 #define NV_TX2_DEFERRED         (1<<25)
440 #define NV_TX2_CARRIERLOST      (1<<26)
441 #define NV_TX2_LATECOLLISION    (1<<27)
442 #define NV_TX2_UNDERFLOW        (1<<28)
443 /* error and valid are the same for both */
444 #define NV_TX2_ERROR            (1<<30)
445 #define NV_TX2_VALID            (1<<31)
446 #define NV_TX2_TSO              (1<<28)
447 #define NV_TX2_TSO_SHIFT        14
448 #define NV_TX2_TSO_MAX_SHIFT    14
449 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
450 #define NV_TX2_CHECKSUM_L3      (1<<27)
451 #define NV_TX2_CHECKSUM_L4      (1<<26)
452
453 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
454
455 #define NV_RX_DESCRIPTORVALID   (1<<16)
456 #define NV_RX_MISSEDFRAME       (1<<17)
457 #define NV_RX_SUBSTRACT1        (1<<18)
458 #define NV_RX_ERROR1            (1<<23)
459 #define NV_RX_ERROR2            (1<<24)
460 #define NV_RX_ERROR3            (1<<25)
461 #define NV_RX_ERROR4            (1<<26)
462 #define NV_RX_CRCERR            (1<<27)
463 #define NV_RX_OVERFLOW          (1<<28)
464 #define NV_RX_FRAMINGERR        (1<<29)
465 #define NV_RX_ERROR             (1<<30)
466 #define NV_RX_AVAIL             (1<<31)
467
468 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
469 #define NV_RX2_CHECKSUMOK1      (0x10000000)
470 #define NV_RX2_CHECKSUMOK2      (0x14000000)
471 #define NV_RX2_CHECKSUMOK3      (0x18000000)
472 #define NV_RX2_DESCRIPTORVALID  (1<<29)
473 #define NV_RX2_SUBSTRACT1       (1<<25)
474 #define NV_RX2_ERROR1           (1<<18)
475 #define NV_RX2_ERROR2           (1<<19)
476 #define NV_RX2_ERROR3           (1<<20)
477 #define NV_RX2_ERROR4           (1<<21)
478 #define NV_RX2_CRCERR           (1<<22)
479 #define NV_RX2_OVERFLOW         (1<<23)
480 #define NV_RX2_FRAMINGERR       (1<<24)
481 /* error and avail are the same for both */
482 #define NV_RX2_ERROR            (1<<30)
483 #define NV_RX2_AVAIL            (1<<31)
484
485 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
486 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
487
488 /* Miscelaneous hardware related defines: */
489 #define NV_PCI_REGSZ_VER1       0x270
490 #define NV_PCI_REGSZ_VER2       0x604
491
492 /* various timeout delays: all in usec */
493 #define NV_TXRX_RESET_DELAY     4
494 #define NV_TXSTOP_DELAY1        10
495 #define NV_TXSTOP_DELAY1MAX     500000
496 #define NV_TXSTOP_DELAY2        100
497 #define NV_RXSTOP_DELAY1        10
498 #define NV_RXSTOP_DELAY1MAX     500000
499 #define NV_RXSTOP_DELAY2        100
500 #define NV_SETUP5_DELAY         5
501 #define NV_SETUP5_DELAYMAX      50000
502 #define NV_POWERUP_DELAY        5
503 #define NV_POWERUP_DELAYMAX     5000
504 #define NV_MIIBUSY_DELAY        50
505 #define NV_MIIPHY_DELAY 10
506 #define NV_MIIPHY_DELAYMAX      10000
507 #define NV_MAC_RESET_DELAY      64
508
509 #define NV_WAKEUPPATTERNS       5
510 #define NV_WAKEUPMASKENTRIES    4
511
512 /* General driver defaults */
513 #define NV_WATCHDOG_TIMEO       (5*HZ)
514
515 #define RX_RING_DEFAULT         128
516 #define TX_RING_DEFAULT         256
517 #define RX_RING_MIN             128
518 #define TX_RING_MIN             64
519 #define RING_MAX_DESC_VER_1     1024
520 #define RING_MAX_DESC_VER_2_3   16384
521
522 /* rx/tx mac addr + type + vlan + align + slack*/
523 #define NV_RX_HEADERS           (64)
524 /* even more slack. */
525 #define NV_RX_ALLOC_PAD         (64)
526
527 /* maximum mtu size */
528 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
529 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
530
531 #define OOM_REFILL      (1+HZ/20)
532 #define POLL_WAIT       (1+HZ/100)
533 #define LINK_TIMEOUT    (3*HZ)
534 #define STATS_INTERVAL  (10*HZ)
535
536 /*
537  * desc_ver values:
538  * The nic supports three different descriptor types:
539  * - DESC_VER_1: Original
540  * - DESC_VER_2: support for jumbo frames.
541  * - DESC_VER_3: 64-bit format.
542  */
543 #define DESC_VER_1      1
544 #define DESC_VER_2      2
545 #define DESC_VER_3      3
546
547 /* PHY defines */
548 #define PHY_OUI_MARVELL 0x5043
549 #define PHY_OUI_CICADA  0x03f1
550 #define PHYID1_OUI_MASK 0x03ff
551 #define PHYID1_OUI_SHFT 6
552 #define PHYID2_OUI_MASK 0xfc00
553 #define PHYID2_OUI_SHFT 10
554 #define PHYID2_MODEL_MASK               0x03f0
555 #define PHY_MODEL_MARVELL_E3016         0x220
556 #define PHY_MARVELL_E3016_INITMASK      0x0300
557 #define PHY_INIT1       0x0f000
558 #define PHY_INIT2       0x0e00
559 #define PHY_INIT3       0x01000
560 #define PHY_INIT4       0x0200
561 #define PHY_INIT5       0x0004
562 #define PHY_INIT6       0x02000
563 #define PHY_GIGABIT     0x0100
564
565 #define PHY_TIMEOUT     0x1
566 #define PHY_ERROR       0x2
567
568 #define PHY_100 0x1
569 #define PHY_1000        0x2
570 #define PHY_HALF        0x100
571
572 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
573 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
574 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
575 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
576 #define NV_PAUSEFRAME_RX_REQ     0x0010
577 #define NV_PAUSEFRAME_TX_REQ     0x0020
578 #define NV_PAUSEFRAME_AUTONEG    0x0040
579
580 /* MSI/MSI-X defines */
581 #define NV_MSI_X_MAX_VECTORS  8
582 #define NV_MSI_X_VECTORS_MASK 0x000f
583 #define NV_MSI_CAPABLE        0x0010
584 #define NV_MSI_X_CAPABLE      0x0020
585 #define NV_MSI_ENABLED        0x0040
586 #define NV_MSI_X_ENABLED      0x0080
587
588 #define NV_MSI_X_VECTOR_ALL   0x0
589 #define NV_MSI_X_VECTOR_RX    0x0
590 #define NV_MSI_X_VECTOR_TX    0x1
591 #define NV_MSI_X_VECTOR_OTHER 0x2
592
593 /* statistics */
594 struct nv_ethtool_str {
595         char name[ETH_GSTRING_LEN];
596 };
597
598 static const struct nv_ethtool_str nv_estats_str[] = {
599         { "tx_bytes" },
600         { "tx_zero_rexmt" },
601         { "tx_one_rexmt" },
602         { "tx_many_rexmt" },
603         { "tx_late_collision" },
604         { "tx_fifo_errors" },
605         { "tx_carrier_errors" },
606         { "tx_excess_deferral" },
607         { "tx_retry_error" },
608         { "tx_deferral" },
609         { "tx_packets" },
610         { "tx_pause" },
611         { "rx_frame_error" },
612         { "rx_extra_byte" },
613         { "rx_late_collision" },
614         { "rx_runt" },
615         { "rx_frame_too_long" },
616         { "rx_over_errors" },
617         { "rx_crc_errors" },
618         { "rx_frame_align_error" },
619         { "rx_length_error" },
620         { "rx_unicast" },
621         { "rx_multicast" },
622         { "rx_broadcast" },
623         { "rx_bytes" },
624         { "rx_pause" },
625         { "rx_drop_frame" },
626         { "rx_packets" },
627         { "rx_errors_total" }
628 };
629
630 struct nv_ethtool_stats {
631         u64 tx_bytes;
632         u64 tx_zero_rexmt;
633         u64 tx_one_rexmt;
634         u64 tx_many_rexmt;
635         u64 tx_late_collision;
636         u64 tx_fifo_errors;
637         u64 tx_carrier_errors;
638         u64 tx_excess_deferral;
639         u64 tx_retry_error;
640         u64 tx_deferral;
641         u64 tx_packets;
642         u64 tx_pause;
643         u64 rx_frame_error;
644         u64 rx_extra_byte;
645         u64 rx_late_collision;
646         u64 rx_runt;
647         u64 rx_frame_too_long;
648         u64 rx_over_errors;
649         u64 rx_crc_errors;
650         u64 rx_frame_align_error;
651         u64 rx_length_error;
652         u64 rx_unicast;
653         u64 rx_multicast;
654         u64 rx_broadcast;
655         u64 rx_bytes;
656         u64 rx_pause;
657         u64 rx_drop_frame;
658         u64 rx_packets;
659         u64 rx_errors_total;
660 };
661
662 /* diagnostics */
663 #define NV_TEST_COUNT_BASE 3
664 #define NV_TEST_COUNT_EXTENDED 4
665
666 static const struct nv_ethtool_str nv_etests_str[] = {
667         { "link      (online/offline)" },
668         { "register  (offline)       " },
669         { "interrupt (offline)       " },
670         { "loopback  (offline)       " }
671 };
672
673 struct register_test {
674         __le32 reg;
675         __le32 mask;
676 };
677
678 static const struct register_test nv_registers_test[] = {
679         { NvRegUnknownSetupReg6, 0x01 },
680         { NvRegMisc1, 0x03c },
681         { NvRegOffloadConfig, 0x03ff },
682         { NvRegMulticastAddrA, 0xffffffff },
683         { NvRegTxWatermark, 0x0ff },
684         { NvRegWakeUpFlags, 0x07777 },
685         { 0,0 }
686 };
687
688 struct nv_skb_map {
689         struct sk_buff *skb;
690         dma_addr_t dma;
691         unsigned int dma_len;
692 };
693
694 /*
695  * SMP locking:
696  * All hardware access under dev->priv->lock, except the performance
697  * critical parts:
698  * - rx is (pseudo-) lockless: it relies on the single-threading provided
699  *      by the arch code for interrupts.
700  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
701  *      needs dev->priv->lock :-(
702  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
703  */
704
705 /* in dev: base, irq */
706 struct fe_priv {
707         spinlock_t lock;
708
709         /* General data:
710          * Locking: spin_lock(&np->lock); */
711         struct net_device_stats stats;
712         struct nv_ethtool_stats estats;
713         int in_shutdown;
714         u32 linkspeed;
715         int duplex;
716         int autoneg;
717         int fixed_mode;
718         int phyaddr;
719         int wolenabled;
720         unsigned int phy_oui;
721         unsigned int phy_model;
722         u16 gigabit;
723         int intr_test;
724         int recover_error;
725
726         /* General data: RO fields */
727         dma_addr_t ring_addr;
728         struct pci_dev *pci_dev;
729         u32 orig_mac[2];
730         u32 irqmask;
731         u32 desc_ver;
732         u32 txrxctl_bits;
733         u32 vlanctl_bits;
734         u32 driver_data;
735         u32 register_size;
736         int rx_csum;
737         u32 mac_in_use;
738
739         void __iomem *base;
740
741         /* rx specific fields.
742          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
743          */
744         union ring_type get_rx, put_rx, first_rx, last_rx;
745         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
746         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
747         struct nv_skb_map *rx_skb;
748
749         union ring_type rx_ring;
750         unsigned int rx_buf_sz;
751         unsigned int pkt_limit;
752         struct timer_list oom_kick;
753         struct timer_list nic_poll;
754         struct timer_list stats_poll;
755         u32 nic_poll_irq;
756         int rx_ring_size;
757
758         /* media detection workaround.
759          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
760          */
761         int need_linktimer;
762         unsigned long link_timeout;
763         /*
764          * tx specific fields.
765          */
766         union ring_type get_tx, put_tx, first_tx, last_tx;
767         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
768         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
769         struct nv_skb_map *tx_skb;
770
771         union ring_type tx_ring;
772         u32 tx_flags;
773         int tx_ring_size;
774         int tx_stop;
775
776         /* vlan fields */
777         struct vlan_group *vlangrp;
778
779         /* msi/msi-x fields */
780         u32 msi_flags;
781         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
782
783         /* flow control */
784         u32 pause_flags;
785 };
786
787 /*
788  * Maximum number of loops until we assume that a bit in the irq mask
789  * is stuck. Overridable with module param.
790  */
791 static int max_interrupt_work = 5;
792
793 /*
794  * Optimization can be either throuput mode or cpu mode
795  *
796  * Throughput Mode: Every tx and rx packet will generate an interrupt.
797  * CPU Mode: Interrupts are controlled by a timer.
798  */
799 enum {
800         NV_OPTIMIZATION_MODE_THROUGHPUT,
801         NV_OPTIMIZATION_MODE_CPU
802 };
803 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
804
805 /*
806  * Poll interval for timer irq
807  *
808  * This interval determines how frequent an interrupt is generated.
809  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
810  * Min = 0, and Max = 65535
811  */
812 static int poll_interval = -1;
813
814 /*
815  * MSI interrupts
816  */
817 enum {
818         NV_MSI_INT_DISABLED,
819         NV_MSI_INT_ENABLED
820 };
821 static int msi = NV_MSI_INT_ENABLED;
822
823 /*
824  * MSIX interrupts
825  */
826 enum {
827         NV_MSIX_INT_DISABLED,
828         NV_MSIX_INT_ENABLED
829 };
830 static int msix = NV_MSIX_INT_ENABLED;
831
832 /*
833  * DMA 64bit
834  */
835 enum {
836         NV_DMA_64BIT_DISABLED,
837         NV_DMA_64BIT_ENABLED
838 };
839 static int dma_64bit = NV_DMA_64BIT_ENABLED;
840
841 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
842 {
843         return netdev_priv(dev);
844 }
845
846 static inline u8 __iomem *get_hwbase(struct net_device *dev)
847 {
848         return ((struct fe_priv *)netdev_priv(dev))->base;
849 }
850
851 static inline void pci_push(u8 __iomem *base)
852 {
853         /* force out pending posted writes */
854         readl(base);
855 }
856
857 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
858 {
859         return le32_to_cpu(prd->flaglen)
860                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
861 }
862
863 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
864 {
865         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
866 }
867
868 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
869                                 int delay, int delaymax, const char *msg)
870 {
871         u8 __iomem *base = get_hwbase(dev);
872
873         pci_push(base);
874         do {
875                 udelay(delay);
876                 delaymax -= delay;
877                 if (delaymax < 0) {
878                         if (msg)
879                                 printk(msg);
880                         return 1;
881                 }
882         } while ((readl(base + offset) & mask) != target);
883         return 0;
884 }
885
886 #define NV_SETUP_RX_RING 0x01
887 #define NV_SETUP_TX_RING 0x02
888
889 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
890 {
891         struct fe_priv *np = get_nvpriv(dev);
892         u8 __iomem *base = get_hwbase(dev);
893
894         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
895                 if (rxtx_flags & NV_SETUP_RX_RING) {
896                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
897                 }
898                 if (rxtx_flags & NV_SETUP_TX_RING) {
899                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
900                 }
901         } else {
902                 if (rxtx_flags & NV_SETUP_RX_RING) {
903                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
904                         writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
905                 }
906                 if (rxtx_flags & NV_SETUP_TX_RING) {
907                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
908                         writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
909                 }
910         }
911 }
912
913 static void free_rings(struct net_device *dev)
914 {
915         struct fe_priv *np = get_nvpriv(dev);
916
917         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
918                 if (np->rx_ring.orig)
919                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
920                                             np->rx_ring.orig, np->ring_addr);
921         } else {
922                 if (np->rx_ring.ex)
923                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
924                                             np->rx_ring.ex, np->ring_addr);
925         }
926         if (np->rx_skb)
927                 kfree(np->rx_skb);
928         if (np->tx_skb)
929                 kfree(np->tx_skb);
930 }
931
932 static int using_multi_irqs(struct net_device *dev)
933 {
934         struct fe_priv *np = get_nvpriv(dev);
935
936         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
937             ((np->msi_flags & NV_MSI_X_ENABLED) &&
938              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
939                 return 0;
940         else
941                 return 1;
942 }
943
944 static void nv_enable_irq(struct net_device *dev)
945 {
946         struct fe_priv *np = get_nvpriv(dev);
947
948         if (!using_multi_irqs(dev)) {
949                 if (np->msi_flags & NV_MSI_X_ENABLED)
950                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
951                 else
952                         enable_irq(dev->irq);
953         } else {
954                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
955                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
956                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
957         }
958 }
959
960 static void nv_disable_irq(struct net_device *dev)
961 {
962         struct fe_priv *np = get_nvpriv(dev);
963
964         if (!using_multi_irqs(dev)) {
965                 if (np->msi_flags & NV_MSI_X_ENABLED)
966                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
967                 else
968                         disable_irq(dev->irq);
969         } else {
970                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
971                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
972                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
973         }
974 }
975
976 /* In MSIX mode, a write to irqmask behaves as XOR */
977 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
978 {
979         u8 __iomem *base = get_hwbase(dev);
980
981         writel(mask, base + NvRegIrqMask);
982 }
983
984 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
985 {
986         struct fe_priv *np = get_nvpriv(dev);
987         u8 __iomem *base = get_hwbase(dev);
988
989         if (np->msi_flags & NV_MSI_X_ENABLED) {
990                 writel(mask, base + NvRegIrqMask);
991         } else {
992                 if (np->msi_flags & NV_MSI_ENABLED)
993                         writel(0, base + NvRegMSIIrqMask);
994                 writel(0, base + NvRegIrqMask);
995         }
996 }
997
998 #define MII_READ        (-1)
999 /* mii_rw: read/write a register on the PHY.
1000  *
1001  * Caller must guarantee serialization
1002  */
1003 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1004 {
1005         u8 __iomem *base = get_hwbase(dev);
1006         u32 reg;
1007         int retval;
1008
1009         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1010
1011         reg = readl(base + NvRegMIIControl);
1012         if (reg & NVREG_MIICTL_INUSE) {
1013                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1014                 udelay(NV_MIIBUSY_DELAY);
1015         }
1016
1017         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1018         if (value != MII_READ) {
1019                 writel(value, base + NvRegMIIData);
1020                 reg |= NVREG_MIICTL_WRITE;
1021         }
1022         writel(reg, base + NvRegMIIControl);
1023
1024         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1025                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1026                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1027                                 dev->name, miireg, addr);
1028                 retval = -1;
1029         } else if (value != MII_READ) {
1030                 /* it was a write operation - fewer failures are detectable */
1031                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1032                                 dev->name, value, miireg, addr);
1033                 retval = 0;
1034         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1035                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1036                                 dev->name, miireg, addr);
1037                 retval = -1;
1038         } else {
1039                 retval = readl(base + NvRegMIIData);
1040                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1041                                 dev->name, miireg, addr, retval);
1042         }
1043
1044         return retval;
1045 }
1046
1047 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1048 {
1049         struct fe_priv *np = netdev_priv(dev);
1050         u32 miicontrol;
1051         unsigned int tries = 0;
1052
1053         miicontrol = BMCR_RESET | bmcr_setup;
1054         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1055                 return -1;
1056         }
1057
1058         /* wait for 500ms */
1059         msleep(500);
1060
1061         /* must wait till reset is deasserted */
1062         while (miicontrol & BMCR_RESET) {
1063                 msleep(10);
1064                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1065                 /* FIXME: 100 tries seem excessive */
1066                 if (tries++ > 100)
1067                         return -1;
1068         }
1069         return 0;
1070 }
1071
1072 static int phy_init(struct net_device *dev)
1073 {
1074         struct fe_priv *np = get_nvpriv(dev);
1075         u8 __iomem *base = get_hwbase(dev);
1076         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1077
1078         /* phy errata for E3016 phy */
1079         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1080                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1081                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1082                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1083                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1084                         return PHY_ERROR;
1085                 }
1086         }
1087
1088         /* set advertise register */
1089         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1090         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1091         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1092                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1093                 return PHY_ERROR;
1094         }
1095
1096         /* get phy interface type */
1097         phyinterface = readl(base + NvRegPhyInterface);
1098
1099         /* see if gigabit phy */
1100         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1101         if (mii_status & PHY_GIGABIT) {
1102                 np->gigabit = PHY_GIGABIT;
1103                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1104                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1105                 if (phyinterface & PHY_RGMII)
1106                         mii_control_1000 |= ADVERTISE_1000FULL;
1107                 else
1108                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1109
1110                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1111                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1112                         return PHY_ERROR;
1113                 }
1114         }
1115         else
1116                 np->gigabit = 0;
1117
1118         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1119         mii_control |= BMCR_ANENABLE;
1120
1121         /* reset the phy
1122          * (certain phys need bmcr to be setup with reset)
1123          */
1124         if (phy_reset(dev, mii_control)) {
1125                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1126                 return PHY_ERROR;
1127         }
1128
1129         /* phy vendor specific configuration */
1130         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1131                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1132                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1133                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1134                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1135                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1136                         return PHY_ERROR;
1137                 }
1138                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1139                 phy_reserved |= PHY_INIT5;
1140                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1141                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1142                         return PHY_ERROR;
1143                 }
1144         }
1145         if (np->phy_oui == PHY_OUI_CICADA) {
1146                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1147                 phy_reserved |= PHY_INIT6;
1148                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1149                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1150                         return PHY_ERROR;
1151                 }
1152         }
1153         /* some phys clear out pause advertisment on reset, set it back */
1154         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1155
1156         /* restart auto negotiation */
1157         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1158         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1159         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1160                 return PHY_ERROR;
1161         }
1162
1163         return 0;
1164 }
1165
1166 static void nv_start_rx(struct net_device *dev)
1167 {
1168         struct fe_priv *np = netdev_priv(dev);
1169         u8 __iomem *base = get_hwbase(dev);
1170         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1171
1172         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1173         /* Already running? Stop it. */
1174         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1175                 rx_ctrl &= ~NVREG_RCVCTL_START;
1176                 writel(rx_ctrl, base + NvRegReceiverControl);
1177                 pci_push(base);
1178         }
1179         writel(np->linkspeed, base + NvRegLinkSpeed);
1180         pci_push(base);
1181         rx_ctrl |= NVREG_RCVCTL_START;
1182         if (np->mac_in_use)
1183                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1184         writel(rx_ctrl, base + NvRegReceiverControl);
1185         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1186                                 dev->name, np->duplex, np->linkspeed);
1187         pci_push(base);
1188 }
1189
1190 static void nv_stop_rx(struct net_device *dev)
1191 {
1192         struct fe_priv *np = netdev_priv(dev);
1193         u8 __iomem *base = get_hwbase(dev);
1194         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1195
1196         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1197         if (!np->mac_in_use)
1198                 rx_ctrl &= ~NVREG_RCVCTL_START;
1199         else
1200                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1201         writel(rx_ctrl, base + NvRegReceiverControl);
1202         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1203                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1204                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1205
1206         udelay(NV_RXSTOP_DELAY2);
1207         if (!np->mac_in_use)
1208                 writel(0, base + NvRegLinkSpeed);
1209 }
1210
1211 static void nv_start_tx(struct net_device *dev)
1212 {
1213         struct fe_priv *np = netdev_priv(dev);
1214         u8 __iomem *base = get_hwbase(dev);
1215         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1216
1217         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1218         tx_ctrl |= NVREG_XMITCTL_START;
1219         if (np->mac_in_use)
1220                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1221         writel(tx_ctrl, base + NvRegTransmitterControl);
1222         pci_push(base);
1223 }
1224
1225 static void nv_stop_tx(struct net_device *dev)
1226 {
1227         struct fe_priv *np = netdev_priv(dev);
1228         u8 __iomem *base = get_hwbase(dev);
1229         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1230
1231         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1232         if (!np->mac_in_use)
1233                 tx_ctrl &= ~NVREG_XMITCTL_START;
1234         else
1235                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1236         writel(tx_ctrl, base + NvRegTransmitterControl);
1237         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1238                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1239                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1240
1241         udelay(NV_TXSTOP_DELAY2);
1242         if (!np->mac_in_use)
1243                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1244                        base + NvRegTransmitPoll);
1245 }
1246
1247 static void nv_txrx_reset(struct net_device *dev)
1248 {
1249         struct fe_priv *np = netdev_priv(dev);
1250         u8 __iomem *base = get_hwbase(dev);
1251
1252         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1253         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1254         pci_push(base);
1255         udelay(NV_TXRX_RESET_DELAY);
1256         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1257         pci_push(base);
1258 }
1259
1260 static void nv_mac_reset(struct net_device *dev)
1261 {
1262         struct fe_priv *np = netdev_priv(dev);
1263         u8 __iomem *base = get_hwbase(dev);
1264
1265         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1266         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1267         pci_push(base);
1268         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1269         pci_push(base);
1270         udelay(NV_MAC_RESET_DELAY);
1271         writel(0, base + NvRegMacReset);
1272         pci_push(base);
1273         udelay(NV_MAC_RESET_DELAY);
1274         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1275         pci_push(base);
1276 }
1277
1278 /*
1279  * nv_get_stats: dev->get_stats function
1280  * Get latest stats value from the nic.
1281  * Called with read_lock(&dev_base_lock) held for read -
1282  * only synchronized against unregister_netdevice.
1283  */
1284 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1285 {
1286         struct fe_priv *np = netdev_priv(dev);
1287
1288         /* It seems that the nic always generates interrupts and doesn't
1289          * accumulate errors internally. Thus the current values in np->stats
1290          * are already up to date.
1291          */
1292         return &np->stats;
1293 }
1294
1295 /*
1296  * nv_alloc_rx: fill rx ring entries.
1297  * Return 1 if the allocations for the skbs failed and the
1298  * rx engine is without Available descriptors
1299  */
1300 static int nv_alloc_rx(struct net_device *dev)
1301 {
1302         struct fe_priv *np = netdev_priv(dev);
1303         struct ring_desc* less_rx;
1304
1305         less_rx = np->get_rx.orig;
1306         if (less_rx-- == np->first_rx.orig)
1307                 less_rx = np->last_rx.orig;
1308
1309         while (np->put_rx.orig != less_rx) {
1310                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1311                 if (skb) {
1312                         skb->dev = dev;
1313                         np->put_rx_ctx->skb = skb;
1314                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data,
1315                                                              skb->end-skb->data, PCI_DMA_FROMDEVICE);
1316                         np->put_rx_ctx->dma_len = skb->end-skb->data;
1317                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1318                         wmb();
1319                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1320                         if (np->put_rx.orig++ == np->last_rx.orig)
1321                                 np->put_rx.orig = np->first_rx.orig;
1322                         if (np->put_rx_ctx++ == np->last_rx_ctx)
1323                                 np->put_rx_ctx = np->first_rx_ctx;
1324                 } else {
1325                         return 1;
1326                 }
1327         }
1328         return 0;
1329 }
1330
1331 static int nv_alloc_rx_optimized(struct net_device *dev)
1332 {
1333         struct fe_priv *np = netdev_priv(dev);
1334         struct ring_desc_ex* less_rx;
1335
1336         less_rx = np->get_rx.ex;
1337         if (less_rx-- == np->first_rx.ex)
1338                 less_rx = np->last_rx.ex;
1339
1340         while (np->put_rx.ex != less_rx) {
1341                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1342                 if (skb) {
1343                         skb->dev = dev;
1344                         np->put_rx_ctx->skb = skb;
1345                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data,
1346                                                              skb->end-skb->data, PCI_DMA_FROMDEVICE);
1347                         np->put_rx_ctx->dma_len = skb->end-skb->data;
1348                         np->put_rx.ex->bufhigh = cpu_to_le64(np->put_rx_ctx->dma) >> 32;
1349                         np->put_rx.ex->buflow = cpu_to_le64(np->put_rx_ctx->dma) & 0x0FFFFFFFF;
1350                         wmb();
1351                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1352                         if (np->put_rx.ex++ == np->last_rx.ex)
1353                                 np->put_rx.ex = np->first_rx.ex;
1354                         if (np->put_rx_ctx++ == np->last_rx_ctx)
1355                                 np->put_rx_ctx = np->first_rx_ctx;
1356                 } else {
1357                         return 1;
1358                 }
1359         }
1360         return 0;
1361 }
1362
1363 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1364 #ifdef CONFIG_FORCEDETH_NAPI
1365 static void nv_do_rx_refill(unsigned long data)
1366 {
1367         struct net_device *dev = (struct net_device *) data;
1368
1369         /* Just reschedule NAPI rx processing */
1370         netif_rx_schedule(dev);
1371 }
1372 #else
1373 static void nv_do_rx_refill(unsigned long data)
1374 {
1375         struct net_device *dev = (struct net_device *) data;
1376         struct fe_priv *np = netdev_priv(dev);
1377         int retcode;
1378
1379         if (!using_multi_irqs(dev)) {
1380                 if (np->msi_flags & NV_MSI_X_ENABLED)
1381                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1382                 else
1383                         disable_irq(dev->irq);
1384         } else {
1385                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1386         }
1387         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1388                 retcode = nv_alloc_rx(dev);
1389         else
1390                 retcode = nv_alloc_rx_optimized(dev);
1391         if (retcode) {
1392                 spin_lock_irq(&np->lock);
1393                 if (!np->in_shutdown)
1394                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1395                 spin_unlock_irq(&np->lock);
1396         }
1397         if (!using_multi_irqs(dev)) {
1398                 if (np->msi_flags & NV_MSI_X_ENABLED)
1399                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1400                 else
1401                         enable_irq(dev->irq);
1402         } else {
1403                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1404         }
1405 }
1406 #endif
1407
1408 static void nv_init_rx(struct net_device *dev)
1409 {
1410         struct fe_priv *np = netdev_priv(dev);
1411         int i;
1412         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1413         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1414                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1415         else
1416                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1417         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1418         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1419
1420         for (i = 0; i < np->rx_ring_size; i++) {
1421                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1422                         np->rx_ring.orig[i].flaglen = 0;
1423                         np->rx_ring.orig[i].buf = 0;
1424                 } else {
1425                         np->rx_ring.ex[i].flaglen = 0;
1426                         np->rx_ring.ex[i].txvlan = 0;
1427                         np->rx_ring.ex[i].bufhigh = 0;
1428                         np->rx_ring.ex[i].buflow = 0;
1429                 }
1430                 np->rx_skb[i].skb = NULL;
1431                 np->rx_skb[i].dma = 0;
1432         }
1433 }
1434
1435 static void nv_init_tx(struct net_device *dev)
1436 {
1437         struct fe_priv *np = netdev_priv(dev);
1438         int i;
1439         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1440         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1441                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1442         else
1443                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1444         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1445         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1446
1447         for (i = 0; i < np->tx_ring_size; i++) {
1448                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1449                         np->tx_ring.orig[i].flaglen = 0;
1450                         np->tx_ring.orig[i].buf = 0;
1451                 } else {
1452                         np->tx_ring.ex[i].flaglen = 0;
1453                         np->tx_ring.ex[i].txvlan = 0;
1454                         np->tx_ring.ex[i].bufhigh = 0;
1455                         np->tx_ring.ex[i].buflow = 0;
1456                 }
1457                 np->tx_skb[i].skb = NULL;
1458                 np->tx_skb[i].dma = 0;
1459         }
1460 }
1461
1462 static int nv_init_ring(struct net_device *dev)
1463 {
1464         struct fe_priv *np = netdev_priv(dev);
1465
1466         nv_init_tx(dev);
1467         nv_init_rx(dev);
1468         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1469                 return nv_alloc_rx(dev);
1470         else
1471                 return nv_alloc_rx_optimized(dev);
1472 }
1473
1474 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1475 {
1476         struct fe_priv *np = netdev_priv(dev);
1477
1478         if (tx_skb->dma) {
1479                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1480                                tx_skb->dma_len,
1481                                PCI_DMA_TODEVICE);
1482                 tx_skb->dma = 0;
1483         }
1484         if (tx_skb->skb) {
1485                 dev_kfree_skb_any(tx_skb->skb);
1486                 tx_skb->skb = NULL;
1487                 return 1;
1488         } else {
1489                 return 0;
1490         }
1491 }
1492
1493 static void nv_drain_tx(struct net_device *dev)
1494 {
1495         struct fe_priv *np = netdev_priv(dev);
1496         unsigned int i;
1497
1498         for (i = 0; i < np->tx_ring_size; i++) {
1499                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1500                         np->tx_ring.orig[i].flaglen = 0;
1501                         np->tx_ring.orig[i].buf = 0;
1502                 } else {
1503                         np->tx_ring.ex[i].flaglen = 0;
1504                         np->tx_ring.ex[i].txvlan = 0;
1505                         np->tx_ring.ex[i].bufhigh = 0;
1506                         np->tx_ring.ex[i].buflow = 0;
1507                 }
1508                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1509                         np->stats.tx_dropped++;
1510         }
1511 }
1512
1513 static void nv_drain_rx(struct net_device *dev)
1514 {
1515         struct fe_priv *np = netdev_priv(dev);
1516         int i;
1517
1518         for (i = 0; i < np->rx_ring_size; i++) {
1519                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1520                         np->rx_ring.orig[i].flaglen = 0;
1521                         np->rx_ring.orig[i].buf = 0;
1522                 } else {
1523                         np->rx_ring.ex[i].flaglen = 0;
1524                         np->rx_ring.ex[i].txvlan = 0;
1525                         np->rx_ring.ex[i].bufhigh = 0;
1526                         np->rx_ring.ex[i].buflow = 0;
1527                 }
1528                 wmb();
1529                 if (np->rx_skb[i].skb) {
1530                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1531                                                 np->rx_skb[i].skb->end-np->rx_skb[i].skb->data,
1532                                                 PCI_DMA_FROMDEVICE);
1533                         dev_kfree_skb(np->rx_skb[i].skb);
1534                         np->rx_skb[i].skb = NULL;
1535                 }
1536         }
1537 }
1538
1539 static void drain_ring(struct net_device *dev)
1540 {
1541         nv_drain_tx(dev);
1542         nv_drain_rx(dev);
1543 }
1544
1545 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1546 {
1547         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1548 }
1549
1550 /*
1551  * nv_start_xmit: dev->hard_start_xmit function
1552  * Called with netif_tx_lock held.
1553  */
1554 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1555 {
1556         struct fe_priv *np = netdev_priv(dev);
1557         u32 tx_flags = 0;
1558         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1559         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1560         unsigned int i;
1561         u32 offset = 0;
1562         u32 bcnt;
1563         u32 size = skb->len-skb->data_len;
1564         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1565         u32 empty_slots;
1566         struct ring_desc* put_tx;
1567         struct ring_desc* start_tx;
1568         struct ring_desc* prev_tx;
1569         struct nv_skb_map* prev_tx_ctx;
1570
1571         /* add fragments to entries count */
1572         for (i = 0; i < fragments; i++) {
1573                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1574                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1575         }
1576
1577         empty_slots = nv_get_empty_tx_slots(np);
1578         if (unlikely(empty_slots <= entries)) {
1579                 spin_lock_irq(&np->lock);
1580                 netif_stop_queue(dev);
1581                 np->tx_stop = 1;
1582                 spin_unlock_irq(&np->lock);
1583                 return NETDEV_TX_BUSY;
1584         }
1585
1586         start_tx = put_tx = np->put_tx.orig;
1587
1588         /* setup the header buffer */
1589         do {
1590                 prev_tx = put_tx;
1591                 prev_tx_ctx = np->put_tx_ctx;
1592                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1593                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1594                                                 PCI_DMA_TODEVICE);
1595                 np->put_tx_ctx->dma_len = bcnt;
1596                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1597                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1598
1599                 tx_flags = np->tx_flags;
1600                 offset += bcnt;
1601                 size -= bcnt;
1602                 if (unlikely(put_tx++ == np->last_tx.orig))
1603                         put_tx = np->first_tx.orig;
1604                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1605                         np->put_tx_ctx = np->first_tx_ctx;
1606         } while (size);
1607
1608         /* setup the fragments */
1609         for (i = 0; i < fragments; i++) {
1610                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1611                 u32 size = frag->size;
1612                 offset = 0;
1613
1614                 do {
1615                         prev_tx = put_tx;
1616                         prev_tx_ctx = np->put_tx_ctx;
1617                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1618                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1619                                                            PCI_DMA_TODEVICE);
1620                         np->put_tx_ctx->dma_len = bcnt;
1621                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1622                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1623
1624                         offset += bcnt;
1625                         size -= bcnt;
1626                         if (unlikely(put_tx++ == np->last_tx.orig))
1627                                 put_tx = np->first_tx.orig;
1628                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1629                                 np->put_tx_ctx = np->first_tx_ctx;
1630                 } while (size);
1631         }
1632
1633         /* set last fragment flag  */
1634         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
1635
1636         /* save skb in this slot's context area */
1637         prev_tx_ctx->skb = skb;
1638
1639         if (skb_is_gso(skb))
1640                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1641         else
1642                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1643                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1644
1645         spin_lock_irq(&np->lock);
1646
1647         /* set tx flags */
1648         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1649         np->put_tx.orig = put_tx;
1650
1651         spin_unlock_irq(&np->lock);
1652
1653         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
1654                 dev->name, entries, tx_flags_extra);
1655         {
1656                 int j;
1657                 for (j=0; j<64; j++) {
1658                         if ((j%16) == 0)
1659                                 dprintk("\n%03x:", j);
1660                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1661                 }
1662                 dprintk("\n");
1663         }
1664
1665         dev->trans_start = jiffies;
1666         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1667         return NETDEV_TX_OK;
1668 }
1669
1670 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
1671 {
1672         struct fe_priv *np = netdev_priv(dev);
1673         u32 tx_flags = 0;
1674         u32 tx_flags_extra;
1675         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1676         unsigned int i;
1677         u32 offset = 0;
1678         u32 bcnt;
1679         u32 size = skb->len-skb->data_len;
1680         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1681         u32 empty_slots;
1682         struct ring_desc_ex* put_tx;
1683         struct ring_desc_ex* start_tx;
1684         struct ring_desc_ex* prev_tx;
1685         struct nv_skb_map* prev_tx_ctx;
1686
1687         /* add fragments to entries count */
1688         for (i = 0; i < fragments; i++) {
1689                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1690                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1691         }
1692
1693         empty_slots = nv_get_empty_tx_slots(np);
1694         if (unlikely(empty_slots <= entries)) {
1695                 spin_lock_irq(&np->lock);
1696                 netif_stop_queue(dev);
1697                 np->tx_stop = 1;
1698                 spin_unlock_irq(&np->lock);
1699                 return NETDEV_TX_BUSY;
1700         }
1701
1702         start_tx = put_tx = np->put_tx.ex;
1703
1704         /* setup the header buffer */
1705         do {
1706                 prev_tx = put_tx;
1707                 prev_tx_ctx = np->put_tx_ctx;
1708                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1709                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1710                                                 PCI_DMA_TODEVICE);
1711                 np->put_tx_ctx->dma_len = bcnt;
1712                 put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1713                 put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1714                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1715
1716                 tx_flags = NV_TX2_VALID;
1717                 offset += bcnt;
1718                 size -= bcnt;
1719                 if (unlikely(put_tx++ == np->last_tx.ex))
1720                         put_tx = np->first_tx.ex;
1721                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1722                         np->put_tx_ctx = np->first_tx_ctx;
1723         } while (size);
1724
1725         /* setup the fragments */
1726         for (i = 0; i < fragments; i++) {
1727                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1728                 u32 size = frag->size;
1729                 offset = 0;
1730
1731                 do {
1732                         prev_tx = put_tx;
1733                         prev_tx_ctx = np->put_tx_ctx;
1734                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1735                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1736                                                            PCI_DMA_TODEVICE);
1737                         np->put_tx_ctx->dma_len = bcnt;
1738                         put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1739                         put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1740                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1741
1742                         offset += bcnt;
1743                         size -= bcnt;
1744                         if (unlikely(put_tx++ == np->last_tx.ex))
1745                                 put_tx = np->first_tx.ex;
1746                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1747                                 np->put_tx_ctx = np->first_tx_ctx;
1748                 } while (size);
1749         }
1750
1751         /* set last fragment flag  */
1752         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
1753
1754         /* save skb in this slot's context area */
1755         prev_tx_ctx->skb = skb;
1756
1757         if (skb_is_gso(skb))
1758                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1759         else
1760                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1761                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1762
1763         /* vlan tag */
1764         if (likely(!np->vlangrp)) {
1765                 start_tx->txvlan = 0;
1766         } else {
1767                 if (vlan_tx_tag_present(skb))
1768                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
1769                 else
1770                         start_tx->txvlan = 0;
1771         }
1772
1773         spin_lock_irq(&np->lock);
1774
1775         /* set tx flags */
1776         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1777         np->put_tx.ex = put_tx;
1778
1779         spin_unlock_irq(&np->lock);
1780
1781         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
1782                 dev->name, entries, tx_flags_extra);
1783         {
1784                 int j;
1785                 for (j=0; j<64; j++) {
1786                         if ((j%16) == 0)
1787                                 dprintk("\n%03x:", j);
1788                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1789                 }
1790                 dprintk("\n");
1791         }
1792
1793         dev->trans_start = jiffies;
1794         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1795         return NETDEV_TX_OK;
1796 }
1797
1798 /*
1799  * nv_tx_done: check for completed packets, release the skbs.
1800  *
1801  * Caller must own np->lock.
1802  */
1803 static void nv_tx_done(struct net_device *dev)
1804 {
1805         struct fe_priv *np = netdev_priv(dev);
1806         u32 flags;
1807         struct ring_desc* orig_get_tx = np->get_tx.orig;
1808
1809         while ((np->get_tx.orig != np->put_tx.orig) &&
1810                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
1811
1812                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
1813                                         dev->name, flags);
1814
1815                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
1816                                np->get_tx_ctx->dma_len,
1817                                PCI_DMA_TODEVICE);
1818                 np->get_tx_ctx->dma = 0;
1819
1820                 if (np->desc_ver == DESC_VER_1) {
1821                         if (flags & NV_TX_LASTPACKET) {
1822                                 if (flags & NV_TX_ERROR) {
1823                                         if (flags & NV_TX_UNDERFLOW)
1824                                                 np->stats.tx_fifo_errors++;
1825                                         if (flags & NV_TX_CARRIERLOST)
1826                                                 np->stats.tx_carrier_errors++;
1827                                         np->stats.tx_errors++;
1828                                 } else {
1829                                         np->stats.tx_packets++;
1830                                         np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1831                                 }
1832                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
1833                                 np->get_tx_ctx->skb = NULL;
1834                         }
1835                 } else {
1836                         if (flags & NV_TX2_LASTPACKET) {
1837                                 if (flags & NV_TX2_ERROR) {
1838                                         if (flags & NV_TX2_UNDERFLOW)
1839                                                 np->stats.tx_fifo_errors++;
1840                                         if (flags & NV_TX2_CARRIERLOST)
1841                                                 np->stats.tx_carrier_errors++;
1842                                         np->stats.tx_errors++;
1843                                 } else {
1844                                         np->stats.tx_packets++;
1845                                         np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1846                                 }
1847                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
1848                                 np->get_tx_ctx->skb = NULL;
1849                         }
1850                 }
1851                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
1852                         np->get_tx.orig = np->first_tx.orig;
1853                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
1854                         np->get_tx_ctx = np->first_tx_ctx;
1855         }
1856         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
1857                 np->tx_stop = 0;
1858                 netif_wake_queue(dev);
1859         }
1860 }
1861
1862 static void nv_tx_done_optimized(struct net_device *dev)
1863 {
1864         struct fe_priv *np = netdev_priv(dev);
1865         u32 flags;
1866         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
1867
1868         while ((np->get_tx.ex != np->put_tx.ex) &&
1869                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID)) {
1870
1871                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
1872                                         dev->name, flags);
1873
1874                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
1875                                np->get_tx_ctx->dma_len,
1876                                PCI_DMA_TODEVICE);
1877                 np->get_tx_ctx->dma = 0;
1878
1879                 if (flags & NV_TX2_LASTPACKET) {
1880                         if (flags & NV_TX2_ERROR) {
1881                                 if (flags & NV_TX2_UNDERFLOW)
1882                                         np->stats.tx_fifo_errors++;
1883                                 if (flags & NV_TX2_CARRIERLOST)
1884                                         np->stats.tx_carrier_errors++;
1885                                 np->stats.tx_errors++;
1886                         } else {
1887                                 np->stats.tx_packets++;
1888                                 np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1889                         }
1890                         dev_kfree_skb_any(np->get_tx_ctx->skb);
1891                         np->get_tx_ctx->skb = NULL;
1892                 }
1893                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
1894                         np->get_tx.ex = np->first_tx.ex;
1895                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
1896                         np->get_tx_ctx = np->first_tx_ctx;
1897         }
1898         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
1899                 np->tx_stop = 0;
1900                 netif_wake_queue(dev);
1901         }
1902 }
1903
1904 /*
1905  * nv_tx_timeout: dev->tx_timeout function
1906  * Called with netif_tx_lock held.
1907  */
1908 static void nv_tx_timeout(struct net_device *dev)
1909 {
1910         struct fe_priv *np = netdev_priv(dev);
1911         u8 __iomem *base = get_hwbase(dev);
1912         u32 status;
1913
1914         if (np->msi_flags & NV_MSI_X_ENABLED)
1915                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1916         else
1917                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1918
1919         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1920
1921         {
1922                 int i;
1923
1924                 printk(KERN_INFO "%s: Ring at %lx\n",
1925                        dev->name, (unsigned long)np->ring_addr);
1926                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1927                 for (i=0;i<=np->register_size;i+= 32) {
1928                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1929                                         i,
1930                                         readl(base + i + 0), readl(base + i + 4),
1931                                         readl(base + i + 8), readl(base + i + 12),
1932                                         readl(base + i + 16), readl(base + i + 20),
1933                                         readl(base + i + 24), readl(base + i + 28));
1934                 }
1935                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1936                 for (i=0;i<np->tx_ring_size;i+= 4) {
1937                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1938                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1939                                        i,
1940                                        le32_to_cpu(np->tx_ring.orig[i].buf),
1941                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
1942                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
1943                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
1944                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
1945                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
1946                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
1947                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
1948                         } else {
1949                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1950                                        i,
1951                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
1952                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
1953                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
1954                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
1955                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
1956                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
1957                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
1958                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
1959                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
1960                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
1961                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
1962                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
1963                         }
1964                 }
1965         }
1966
1967         spin_lock_irq(&np->lock);
1968
1969         /* 1) stop tx engine */
1970         nv_stop_tx(dev);
1971
1972         /* 2) check that the packets were not sent already: */
1973         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1974                 nv_tx_done(dev);
1975         else
1976                 nv_tx_done_optimized(dev);
1977
1978         /* 3) if there are dead entries: clear everything */
1979         if (np->get_tx_ctx != np->put_tx_ctx) {
1980                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1981                 nv_drain_tx(dev);
1982                 nv_init_tx(dev);
1983                 setup_hw_rings(dev, NV_SETUP_TX_RING);
1984                 netif_wake_queue(dev);
1985         }
1986
1987         /* 4) restart tx engine */
1988         nv_start_tx(dev);
1989         spin_unlock_irq(&np->lock);
1990 }
1991
1992 /*
1993  * Called when the nic notices a mismatch between the actual data len on the
1994  * wire and the len indicated in the 802 header
1995  */
1996 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1997 {
1998         int hdrlen;     /* length of the 802 header */
1999         int protolen;   /* length as stored in the proto field */
2000
2001         /* 1) calculate len according to header */
2002         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2003                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2004                 hdrlen = VLAN_HLEN;
2005         } else {
2006                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2007                 hdrlen = ETH_HLEN;
2008         }
2009         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2010                                 dev->name, datalen, protolen, hdrlen);
2011         if (protolen > ETH_DATA_LEN)
2012                 return datalen; /* Value in proto field not a len, no checks possible */
2013
2014         protolen += hdrlen;
2015         /* consistency checks: */
2016         if (datalen > ETH_ZLEN) {
2017                 if (datalen >= protolen) {
2018                         /* more data on wire than in 802 header, trim of
2019                          * additional data.
2020                          */
2021                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2022                                         dev->name, protolen);
2023                         return protolen;
2024                 } else {
2025                         /* less data on wire than mentioned in header.
2026                          * Discard the packet.
2027                          */
2028                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2029                                         dev->name);
2030                         return -1;
2031                 }
2032         } else {
2033                 /* short packet. Accept only if 802 values are also short */
2034                 if (protolen > ETH_ZLEN) {
2035                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2036                                         dev->name);
2037                         return -1;
2038                 }
2039                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2040                                 dev->name, datalen);
2041                 return datalen;
2042         }
2043 }
2044
2045 static int nv_rx_process(struct net_device *dev, int limit)
2046 {
2047         struct fe_priv *np = netdev_priv(dev);
2048         u32 flags;
2049         u32 vlanflags = 0;
2050         int count;
2051
2052         for (count = 0; count < limit; ++count) {
2053                 struct sk_buff *skb;
2054                 int len;
2055
2056                 if (np->get_rx.orig == np->put_rx.orig)
2057                         break;  /* we scanned the whole ring - do not continue */
2058                 flags = le32_to_cpu(np->get_rx.orig->flaglen);
2059                 len = nv_descr_getlength(np->get_rx.orig, np->desc_ver);
2060
2061                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2062                                         dev->name, flags);
2063
2064                 if (flags & NV_RX_AVAIL)
2065                         break;  /* still owned by hardware, */
2066
2067                 /*
2068                  * the packet is for us - immediately tear down the pci mapping.
2069                  * TODO: check if a prefetch of the first cacheline improves
2070                  * the performance.
2071                  */
2072                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2073                                 np->get_rx_ctx->dma_len,
2074                                 PCI_DMA_FROMDEVICE);
2075                 skb = np->get_rx_ctx->skb;
2076                 np->get_rx_ctx->skb = NULL;
2077
2078                 {
2079                         int j;
2080                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2081                         for (j=0; j<64; j++) {
2082                                 if ((j%16) == 0)
2083                                         dprintk("\n%03x:", j);
2084                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2085                         }
2086                         dprintk("\n");
2087                 }
2088                 /* look at what we actually got: */
2089                 if (np->desc_ver == DESC_VER_1) {
2090                         if (!(flags & NV_RX_DESCRIPTORVALID)) {
2091                                 dev_kfree_skb(skb);
2092                                 goto next_pkt;
2093                         }
2094
2095                         if (flags & NV_RX_ERROR) {
2096                                 if (flags & NV_RX_MISSEDFRAME) {
2097                                         np->stats.rx_missed_errors++;
2098                                         np->stats.rx_errors++;
2099                                         dev_kfree_skb(skb);
2100                                         goto next_pkt;
2101                                 }
2102                                 if (flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
2103                                         np->stats.rx_errors++;
2104                                         dev_kfree_skb(skb);
2105                                         goto next_pkt;
2106                                 }
2107                                 if (flags & NV_RX_CRCERR) {
2108                                         np->stats.rx_crc_errors++;
2109                                         np->stats.rx_errors++;
2110                                         dev_kfree_skb(skb);
2111                                         goto next_pkt;
2112                                 }
2113                                 if (flags & NV_RX_OVERFLOW) {
2114                                         np->stats.rx_over_errors++;
2115                                         np->stats.rx_errors++;
2116                                         dev_kfree_skb(skb);
2117                                         goto next_pkt;
2118                                 }
2119                                 if (flags & NV_RX_ERROR4) {
2120                                         len = nv_getlen(dev, skb->data, len);
2121                                         if (len < 0) {
2122                                                 np->stats.rx_errors++;
2123                                                 dev_kfree_skb(skb);
2124                                                 goto next_pkt;
2125                                         }
2126                                 }
2127                                 /* framing errors are soft errors. */
2128                                 if (flags & NV_RX_FRAMINGERR) {
2129                                         if (flags & NV_RX_SUBSTRACT1) {
2130                                                 len--;
2131                                         }
2132                                 }
2133                         }
2134                 } else {
2135                         if (!(flags & NV_RX2_DESCRIPTORVALID)) {
2136                                 dev_kfree_skb(skb);
2137                                 goto next_pkt;
2138                         }
2139
2140                         if (flags & NV_RX2_ERROR) {
2141                                 if (flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
2142                                         np->stats.rx_errors++;
2143                                         dev_kfree_skb(skb);
2144                                         goto next_pkt;
2145                                 }
2146                                 if (flags & NV_RX2_CRCERR) {
2147                                         np->stats.rx_crc_errors++;
2148                                         np->stats.rx_errors++;
2149                                         dev_kfree_skb(skb);
2150                                         goto next_pkt;
2151                                 }
2152                                 if (flags & NV_RX2_OVERFLOW) {
2153                                         np->stats.rx_over_errors++;
2154                                         np->stats.rx_errors++;
2155                                         dev_kfree_skb(skb);
2156                                         goto next_pkt;
2157                                 }
2158                                 if (flags & NV_RX2_ERROR4) {
2159                                         len = nv_getlen(dev, skb->data, len);
2160                                         if (len < 0) {
2161                                                 np->stats.rx_errors++;
2162                                                 dev_kfree_skb(skb);
2163                                                 goto next_pkt;
2164                                         }
2165                                 }
2166                                 /* framing errors are soft errors */
2167                                 if (flags & NV_RX2_FRAMINGERR) {
2168                                         if (flags & NV_RX2_SUBSTRACT1) {
2169                                                 len--;
2170                                         }
2171                                 }
2172                         }
2173                         if (np->rx_csum) {
2174                                 flags &= NV_RX2_CHECKSUMMASK;
2175                                 if (flags == NV_RX2_CHECKSUMOK1 ||
2176                                     flags == NV_RX2_CHECKSUMOK2 ||
2177                                     flags == NV_RX2_CHECKSUMOK3) {
2178                                         dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
2179                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2180                                 } else {
2181                                         dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
2182                                 }
2183                         }
2184                 }
2185                 /* got a valid packet - forward it to the network core */
2186                 skb_put(skb, len);
2187                 skb->protocol = eth_type_trans(skb, dev);
2188                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2189                                         dev->name, len, skb->protocol);
2190 #ifdef CONFIG_FORCEDETH_NAPI
2191                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
2192                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2193                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2194                 else
2195                         netif_receive_skb(skb);
2196 #else
2197                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
2198                         vlan_hwaccel_rx(skb, np->vlangrp,
2199                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2200                 else
2201                         netif_rx(skb);
2202 #endif
2203                 dev->last_rx = jiffies;
2204                 np->stats.rx_packets++;
2205                 np->stats.rx_bytes += len;
2206 next_pkt:
2207                 if (np->get_rx.orig++ == np->last_rx.orig)
2208                         np->get_rx.orig = np->first_rx.orig;
2209                 if (np->get_rx_ctx++ == np->last_rx_ctx)
2210                         np->get_rx_ctx = np->first_rx_ctx;
2211         }
2212
2213         return count;
2214 }
2215
2216 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2217 {
2218         struct fe_priv *np = netdev_priv(dev);
2219         u32 flags;
2220         u32 vlanflags = 0;
2221         int count;
2222
2223         for (count = 0; count < limit; ++count) {
2224                 struct sk_buff *skb;
2225                 int len;
2226
2227                 if (np->get_rx.ex == np->put_rx.ex)
2228                         break;  /* we scanned the whole ring - do not continue */
2229                 flags = le32_to_cpu(np->get_rx.ex->flaglen);
2230                 len = nv_descr_getlength_ex(np->get_rx.ex, np->desc_ver);
2231                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2232
2233                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2234                                         dev->name, flags);
2235
2236                 if (flags & NV_RX_AVAIL)
2237                         break;  /* still owned by hardware, */
2238
2239                 /*
2240                  * the packet is for us - immediately tear down the pci mapping.
2241                  * TODO: check if a prefetch of the first cacheline improves
2242                  * the performance.
2243                  */
2244                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2245                                 np->get_rx_ctx->dma_len,
2246                                 PCI_DMA_FROMDEVICE);
2247                 skb = np->get_rx_ctx->skb;
2248                 np->get_rx_ctx->skb = NULL;
2249
2250                 {
2251                         int j;
2252                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2253                         for (j=0; j<64; j++) {
2254                                 if ((j%16) == 0)
2255                                         dprintk("\n%03x:", j);
2256                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2257                         }
2258                         dprintk("\n");
2259                 }
2260                 /* look at what we actually got: */
2261                 if (!(flags & NV_RX2_DESCRIPTORVALID)) {
2262                         dev_kfree_skb(skb);
2263                         goto next_pkt;
2264                 }
2265
2266                 if (flags & NV_RX2_ERROR) {
2267                         if (flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
2268                                 np->stats.rx_errors++;
2269                                 dev_kfree_skb(skb);
2270                                 goto next_pkt;
2271                         }
2272                         if (flags & NV_RX2_CRCERR) {
2273                                 np->stats.rx_crc_errors++;
2274                                 np->stats.rx_errors++;
2275                                 dev_kfree_skb(skb);
2276                                 goto next_pkt;
2277                         }
2278                         if (flags & NV_RX2_OVERFLOW) {
2279                                 np->stats.rx_over_errors++;
2280                                 np->stats.rx_errors++;
2281                                 dev_kfree_skb(skb);
2282                                 goto next_pkt;
2283                         }
2284                         if (flags & NV_RX2_ERROR4) {
2285                                 len = nv_getlen(dev, skb->data, len);
2286                                 if (len < 0) {
2287                                         np->stats.rx_errors++;
2288                                         dev_kfree_skb(skb);
2289                                         goto next_pkt;
2290                                 }
2291                         }
2292                         /* framing errors are soft errors */
2293                         if (flags & NV_RX2_FRAMINGERR) {
2294                                 if (flags & NV_RX2_SUBSTRACT1) {
2295                                         len--;
2296                                 }
2297                         }
2298                 }
2299                 if (np->rx_csum) {
2300                         flags &= NV_RX2_CHECKSUMMASK;
2301                         if (flags == NV_RX2_CHECKSUMOK1 ||
2302                             flags == NV_RX2_CHECKSUMOK2 ||
2303                             flags == NV_RX2_CHECKSUMOK3) {
2304                                 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
2305                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2306                         } else {
2307                                 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
2308                         }
2309                 }
2310                 /* got a valid packet - forward it to the network core */
2311                 skb_put(skb, len);
2312                 skb->protocol = eth_type_trans(skb, dev);
2313                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2314                                         dev->name, len, skb->protocol);
2315 #ifdef CONFIG_FORCEDETH_NAPI
2316                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
2317                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2318                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2319                 else
2320                         netif_receive_skb(skb);
2321 #else
2322                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
2323                         vlan_hwaccel_rx(skb, np->vlangrp,
2324                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2325                 else
2326                         netif_rx(skb);
2327 #endif
2328                 dev->last_rx = jiffies;
2329                 np->stats.rx_packets++;
2330                 np->stats.rx_bytes += len;
2331 next_pkt:
2332                 if (np->get_rx.ex++ == np->last_rx.ex)
2333                         np->get_rx.ex = np->first_rx.ex;
2334                 if (np->get_rx_ctx++ == np->last_rx_ctx)
2335                         np->get_rx_ctx = np->first_rx_ctx;
2336         }
2337
2338         return count;
2339 }
2340
2341 static void set_bufsize(struct net_device *dev)
2342 {
2343         struct fe_priv *np = netdev_priv(dev);
2344
2345         if (dev->mtu <= ETH_DATA_LEN)
2346                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2347         else
2348                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2349 }
2350
2351 /*
2352  * nv_change_mtu: dev->change_mtu function
2353  * Called with dev_base_lock held for read.
2354  */
2355 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2356 {
2357         struct fe_priv *np = netdev_priv(dev);
2358         int old_mtu;
2359
2360         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2361                 return -EINVAL;
2362
2363         old_mtu = dev->mtu;
2364         dev->mtu = new_mtu;
2365
2366         /* return early if the buffer sizes will not change */
2367         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2368                 return 0;
2369         if (old_mtu == new_mtu)
2370                 return 0;
2371
2372         /* synchronized against open : rtnl_lock() held by caller */
2373         if (netif_running(dev)) {
2374                 u8 __iomem *base = get_hwbase(dev);
2375                 /*
2376                  * It seems that the nic preloads valid ring entries into an
2377                  * internal buffer. The procedure for flushing everything is
2378                  * guessed, there is probably a simpler approach.
2379                  * Changing the MTU is a rare event, it shouldn't matter.
2380                  */
2381                 nv_disable_irq(dev);
2382                 netif_tx_lock_bh(dev);
2383                 spin_lock(&np->lock);
2384                 /* stop engines */
2385                 nv_stop_rx(dev);
2386                 nv_stop_tx(dev);
2387                 nv_txrx_reset(dev);
2388                 /* drain rx queue */
2389                 nv_drain_rx(dev);
2390                 nv_drain_tx(dev);
2391                 /* reinit driver view of the rx queue */
2392                 set_bufsize(dev);
2393                 if (nv_init_ring(dev)) {
2394                         if (!np->in_shutdown)
2395                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2396                 }
2397                 /* reinit nic view of the rx queue */
2398                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2399                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2400                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2401                         base + NvRegRingSizes);
2402                 pci_push(base);
2403                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2404                 pci_push(base);
2405
2406                 /* restart rx engine */
2407                 nv_start_rx(dev);
2408                 nv_start_tx(dev);
2409                 spin_unlock(&np->lock);
2410                 netif_tx_unlock_bh(dev);
2411                 nv_enable_irq(dev);
2412         }
2413         return 0;
2414 }
2415
2416 static void nv_copy_mac_to_hw(struct net_device *dev)
2417 {
2418         u8 __iomem *base = get_hwbase(dev);
2419         u32 mac[2];
2420
2421         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2422                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2423         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2424
2425         writel(mac[0], base + NvRegMacAddrA);
2426         writel(mac[1], base + NvRegMacAddrB);
2427 }
2428
2429 /*
2430  * nv_set_mac_address: dev->set_mac_address function
2431  * Called with rtnl_lock() held.
2432  */
2433 static int nv_set_mac_address(struct net_device *dev, void *addr)
2434 {
2435         struct fe_priv *np = netdev_priv(dev);
2436         struct sockaddr *macaddr = (struct sockaddr*)addr;
2437
2438         if (!is_valid_ether_addr(macaddr->sa_data))
2439                 return -EADDRNOTAVAIL;
2440
2441         /* synchronized against open : rtnl_lock() held by caller */
2442         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2443
2444         if (netif_running(dev)) {
2445                 netif_tx_lock_bh(dev);
2446                 spin_lock_irq(&np->lock);
2447
2448                 /* stop rx engine */
2449                 nv_stop_rx(dev);
2450
2451                 /* set mac address */
2452                 nv_copy_mac_to_hw(dev);
2453
2454                 /* restart rx engine */
2455                 nv_start_rx(dev);
2456                 spin_unlock_irq(&np->lock);
2457                 netif_tx_unlock_bh(dev);
2458         } else {
2459                 nv_copy_mac_to_hw(dev);
2460         }
2461         return 0;
2462 }
2463
2464 /*
2465  * nv_set_multicast: dev->set_multicast function
2466  * Called with netif_tx_lock held.
2467  */
2468 static void nv_set_multicast(struct net_device *dev)
2469 {
2470         struct fe_priv *np = netdev_priv(dev);
2471         u8 __iomem *base = get_hwbase(dev);
2472         u32 addr[2];
2473         u32 mask[2];
2474         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2475
2476         memset(addr, 0, sizeof(addr));
2477         memset(mask, 0, sizeof(mask));
2478
2479         if (dev->flags & IFF_PROMISC) {
2480                 pff |= NVREG_PFF_PROMISC;
2481         } else {
2482                 pff |= NVREG_PFF_MYADDR;
2483
2484                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2485                         u32 alwaysOff[2];
2486                         u32 alwaysOn[2];
2487
2488                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2489                         if (dev->flags & IFF_ALLMULTI) {
2490                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2491                         } else {
2492                                 struct dev_mc_list *walk;
2493
2494                                 walk = dev->mc_list;
2495                                 while (walk != NULL) {
2496                                         u32 a, b;
2497                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2498                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2499                                         alwaysOn[0] &= a;
2500                                         alwaysOff[0] &= ~a;
2501                                         alwaysOn[1] &= b;
2502                                         alwaysOff[1] &= ~b;
2503                                         walk = walk->next;
2504                                 }
2505                         }
2506                         addr[0] = alwaysOn[0];
2507                         addr[1] = alwaysOn[1];
2508                         mask[0] = alwaysOn[0] | alwaysOff[0];
2509                         mask[1] = alwaysOn[1] | alwaysOff[1];
2510                 }
2511         }
2512         addr[0] |= NVREG_MCASTADDRA_FORCE;
2513         pff |= NVREG_PFF_ALWAYS;
2514         spin_lock_irq(&np->lock);
2515         nv_stop_rx(dev);
2516         writel(addr[0], base + NvRegMulticastAddrA);
2517         writel(addr[1], base + NvRegMulticastAddrB);
2518         writel(mask[0], base + NvRegMulticastMaskA);
2519         writel(mask[1], base + NvRegMulticastMaskB);
2520         writel(pff, base + NvRegPacketFilterFlags);
2521         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2522                 dev->name);
2523         nv_start_rx(dev);
2524         spin_unlock_irq(&np->lock);
2525 }
2526
2527 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2528 {
2529         struct fe_priv *np = netdev_priv(dev);
2530         u8 __iomem *base = get_hwbase(dev);
2531
2532         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2533
2534         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2535                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2536                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2537                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2538                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2539                 } else {
2540                         writel(pff, base + NvRegPacketFilterFlags);
2541                 }
2542         }
2543         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2544                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2545                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2546                         writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
2547                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2548                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2549                 } else {
2550                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2551                         writel(regmisc, base + NvRegMisc1);
2552                 }
2553         }
2554 }
2555
2556 /**
2557  * nv_update_linkspeed: Setup the MAC according to the link partner
2558  * @dev: Network device to be configured
2559  *
2560  * The function queries the PHY and checks if there is a link partner.
2561  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2562  * set to 10 MBit HD.
2563  *
2564  * The function returns 0 if there is no link partner and 1 if there is
2565  * a good link partner.
2566  */
2567 static int nv_update_linkspeed(struct net_device *dev)
2568 {
2569         struct fe_priv *np = netdev_priv(dev);
2570         u8 __iomem *base = get_hwbase(dev);
2571         int adv = 0;
2572         int lpa = 0;
2573         int adv_lpa, adv_pause, lpa_pause;
2574         int newls = np->linkspeed;
2575         int newdup = np->duplex;
2576         int mii_status;
2577         int retval = 0;
2578         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2579
2580         /* BMSR_LSTATUS is latched, read it twice:
2581          * we want the current value.
2582          */
2583         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2584         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2585
2586         if (!(mii_status & BMSR_LSTATUS)) {
2587                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2588                                 dev->name);
2589                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2590                 newdup = 0;
2591                 retval = 0;
2592                 goto set_speed;
2593         }
2594
2595         if (np->autoneg == 0) {
2596                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2597                                 dev->name, np->fixed_mode);
2598                 if (np->fixed_mode & LPA_100FULL) {
2599                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2600                         newdup = 1;
2601                 } else if (np->fixed_mode & LPA_100HALF) {
2602                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2603                         newdup = 0;
2604                 } else if (np->fixed_mode & LPA_10FULL) {
2605                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2606                         newdup = 1;
2607                 } else {
2608                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2609                         newdup = 0;
2610                 }
2611                 retval = 1;
2612                 goto set_speed;
2613         }
2614         /* check auto negotiation is complete */
2615         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2616                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2617                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2618                 newdup = 0;
2619                 retval = 0;
2620                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2621                 goto set_speed;
2622         }
2623
2624         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2625         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2626         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2627                                 dev->name, adv, lpa);
2628
2629         retval = 1;
2630         if (np->gigabit == PHY_GIGABIT) {
2631                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2632                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2633
2634                 if ((control_1000 & ADVERTISE_1000FULL) &&
2635                         (status_1000 & LPA_1000FULL)) {
2636                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2637                                 dev->name);
2638                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2639                         newdup = 1;
2640                         goto set_speed;
2641                 }
2642         }
2643
2644         /* FIXME: handle parallel detection properly */
2645         adv_lpa = lpa & adv;
2646         if (adv_lpa & LPA_100FULL) {
2647                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2648                 newdup = 1;
2649         } else if (adv_lpa & LPA_100HALF) {
2650                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2651                 newdup = 0;
2652         } else if (adv_lpa & LPA_10FULL) {
2653                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2654                 newdup = 1;
2655         } else if (adv_lpa & LPA_10HALF) {
2656                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2657                 newdup = 0;
2658         } else {
2659                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2660                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2661                 newdup = 0;
2662         }
2663
2664 set_speed:
2665         if (np->duplex == newdup && np->linkspeed == newls)
2666                 return retval;
2667
2668         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2669                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2670
2671         np->duplex = newdup;
2672         np->linkspeed = newls;
2673
2674         if (np->gigabit == PHY_GIGABIT) {
2675                 phyreg = readl(base + NvRegRandomSeed);
2676                 phyreg &= ~(0x3FF00);
2677                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2678                         phyreg |= NVREG_RNDSEED_FORCE3;
2679                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2680                         phyreg |= NVREG_RNDSEED_FORCE2;
2681                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2682                         phyreg |= NVREG_RNDSEED_FORCE;
2683                 writel(phyreg, base + NvRegRandomSeed);
2684         }
2685
2686         phyreg = readl(base + NvRegPhyInterface);
2687         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2688         if (np->duplex == 0)
2689                 phyreg |= PHY_HALF;
2690         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2691                 phyreg |= PHY_100;
2692         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2693                 phyreg |= PHY_1000;
2694         writel(phyreg, base + NvRegPhyInterface);
2695
2696         if (phyreg & PHY_RGMII) {
2697                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2698                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2699                 else
2700                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2701         } else {
2702                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2703         }
2704         writel(txreg, base + NvRegTxDeferral);
2705
2706         if (np->desc_ver == DESC_VER_1) {
2707                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2708         } else {
2709                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2710                         txreg = NVREG_TX_WM_DESC2_3_1000;
2711                 else
2712                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2713         }
2714         writel(txreg, base + NvRegTxWatermark);
2715
2716         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2717                 base + NvRegMisc1);
2718         pci_push(base);
2719         writel(np->linkspeed, base + NvRegLinkSpeed);
2720         pci_push(base);
2721
2722         pause_flags = 0;
2723         /* setup pause frame */
2724         if (np->duplex != 0) {
2725                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2726                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2727                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2728
2729                         switch (adv_pause) {
2730                         case ADVERTISE_PAUSE_CAP:
2731                                 if (lpa_pause & LPA_PAUSE_CAP) {
2732                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2733                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2734                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2735                                 }
2736                                 break;
2737                         case ADVERTISE_PAUSE_ASYM:
2738                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2739                                 {
2740                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2741                                 }
2742                                 break;
2743                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2744                                 if (lpa_pause & LPA_PAUSE_CAP)
2745                                 {
2746                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
2747                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2748                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2749                                 }
2750                                 if (lpa_pause == LPA_PAUSE_ASYM)
2751                                 {
2752                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2753                                 }
2754                                 break;
2755                         }
2756                 } else {
2757                         pause_flags = np->pause_flags;
2758                 }
2759         }
2760         nv_update_pause(dev, pause_flags);
2761
2762         return retval;
2763 }
2764
2765 static void nv_linkchange(struct net_device *dev)
2766 {
2767         if (nv_update_linkspeed(dev)) {
2768                 if (!netif_carrier_ok(dev)) {
2769                         netif_carrier_on(dev);
2770                         printk(KERN_INFO "%s: link up.\n", dev->name);
2771                         nv_start_rx(dev);
2772                 }
2773         } else {
2774                 if (netif_carrier_ok(dev)) {
2775                         netif_carrier_off(dev);
2776                         printk(KERN_INFO "%s: link down.\n", dev->name);
2777                         nv_stop_rx(dev);
2778                 }
2779         }
2780 }
2781
2782 static void nv_link_irq(struct net_device *dev)
2783 {
2784         u8 __iomem *base = get_hwbase(dev);
2785         u32 miistat;
2786
2787         miistat = readl(base + NvRegMIIStatus);
2788         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2789         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2790
2791         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2792                 nv_linkchange(dev);
2793         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2794 }
2795
2796 static irqreturn_t nv_nic_irq(int foo, void *data)
2797 {
2798         struct net_device *dev = (struct net_device *) data;
2799         struct fe_priv *np = netdev_priv(dev);
2800         u8 __iomem *base = get_hwbase(dev);
2801         u32 events;
2802         int i;
2803
2804         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2805
2806         for (i=0; ; i++) {
2807                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2808                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2809                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2810                 } else {
2811                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2812                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2813                 }
2814                 pci_push(base);
2815                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2816                 if (!(events & np->irqmask))
2817                         break;
2818
2819                 spin_lock(&np->lock);
2820                 nv_tx_done(dev);
2821                 spin_unlock(&np->lock);
2822
2823                 if (events & NVREG_IRQ_LINK) {
2824                         spin_lock(&np->lock);
2825                         nv_link_irq(dev);
2826                         spin_unlock(&np->lock);
2827                 }
2828                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2829                         spin_lock(&np->lock);
2830                         nv_linkchange(dev);
2831                         spin_unlock(&np->lock);
2832                         np->link_timeout = jiffies + LINK_TIMEOUT;
2833                 }
2834                 if (events & (NVREG_IRQ_TX_ERR)) {
2835                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2836                                                 dev->name, events);
2837                 }
2838                 if (events & (NVREG_IRQ_UNKNOWN)) {
2839                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2840                                                 dev->name, events);
2841                 }
2842                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
2843                         spin_lock(&np->lock);
2844                         /* disable interrupts on the nic */
2845                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2846                                 writel(0, base + NvRegIrqMask);
2847                         else
2848                                 writel(np->irqmask, base + NvRegIrqMask);
2849                         pci_push(base);
2850
2851                         if (!np->in_shutdown) {
2852                                 np->nic_poll_irq = np->irqmask;
2853                                 np->recover_error = 1;
2854                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2855                         }
2856                         spin_unlock(&np->lock);
2857                         break;
2858                 }
2859 #ifdef CONFIG_FORCEDETH_NAPI
2860                 if (events & NVREG_IRQ_RX_ALL) {
2861                         netif_rx_schedule(dev);
2862
2863                         /* Disable furthur receive irq's */
2864                         spin_lock(&np->lock);
2865                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
2866
2867                         if (np->msi_flags & NV_MSI_X_ENABLED)
2868                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2869                         else
2870                                 writel(np->irqmask, base + NvRegIrqMask);
2871                         spin_unlock(&np->lock);
2872                 }
2873 #else
2874                 nv_rx_process(dev, dev->weight);
2875                 if (nv_alloc_rx(dev)) {
2876                         spin_lock(&np->lock);
2877                         if (!np->in_shutdown)
2878                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2879                         spin_unlock(&np->lock);
2880                 }
2881 #endif
2882                 if (i > max_interrupt_work) {
2883                         spin_lock(&np->lock);
2884                         /* disable interrupts on the nic */
2885                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2886                                 writel(0, base + NvRegIrqMask);
2887                         else
2888                                 writel(np->irqmask, base + NvRegIrqMask);
2889                         pci_push(base);
2890
2891                         if (!np->in_shutdown) {
2892                                 np->nic_poll_irq = np->irqmask;
2893                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2894                         }
2895                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2896                         spin_unlock(&np->lock);
2897                         break;
2898                 }
2899
2900         }
2901         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2902
2903         return IRQ_RETVAL(i);
2904 }
2905
2906 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
2907 {
2908         struct net_device *dev = (struct net_device *) data;
2909         struct fe_priv *np = netdev_priv(dev);
2910         u8 __iomem *base = get_hwbase(dev);
2911         u32 events;
2912         int i;
2913
2914         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
2915
2916         for (i=0; ; i++) {
2917                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2918                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2919                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2920                 } else {
2921                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2922                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2923                 }
2924                 pci_push(base);
2925                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2926                 if (!(events & np->irqmask))
2927                         break;
2928
2929                 spin_lock(&np->lock);
2930                 nv_tx_done_optimized(dev);
2931                 spin_unlock(&np->lock);
2932
2933                 if (events & NVREG_IRQ_LINK) {
2934                         spin_lock(&np->lock);
2935                         nv_link_irq(dev);
2936                         spin_unlock(&np->lock);
2937                 }
2938                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2939                         spin_lock(&np->lock);
2940                         nv_linkchange(dev);
2941                         spin_unlock(&np->lock);
2942                         np->link_timeout = jiffies + LINK_TIMEOUT;
2943                 }
2944                 if (events & (NVREG_IRQ_TX_ERR)) {
2945                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2946                                                 dev->name, events);
2947                 }
2948                 if (events & (NVREG_IRQ_UNKNOWN)) {
2949                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2950                                                 dev->name, events);
2951                 }
2952                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
2953                         spin_lock(&np->lock);
2954                         /* disable interrupts on the nic */
2955                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2956                                 writel(0, base + NvRegIrqMask);
2957                         else
2958                                 writel(np->irqmask, base + NvRegIrqMask);
2959                         pci_push(base);
2960
2961                         if (!np->in_shutdown) {
2962                                 np->nic_poll_irq = np->irqmask;
2963                                 np->recover_error = 1;
2964                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2965                         }
2966                         spin_unlock(&np->lock);
2967                         break;
2968                 }
2969
2970 #ifdef CONFIG_FORCEDETH_NAPI
2971                 if (events & NVREG_IRQ_RX_ALL) {
2972                         netif_rx_schedule(dev);
2973
2974                         /* Disable furthur receive irq's */
2975                         spin_lock(&np->lock);
2976                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
2977
2978                         if (np->msi_flags & NV_MSI_X_ENABLED)
2979                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2980                         else
2981                                 writel(np->irqmask, base + NvRegIrqMask);
2982                         spin_unlock(&np->lock);
2983                 }
2984 #else
2985                 nv_rx_process_optimized(dev, dev->weight);
2986                 if (nv_alloc_rx_optimized(dev)) {
2987                         spin_lock(&np->lock);
2988                         if (!np->in_shutdown)
2989                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2990                         spin_unlock(&np->lock);
2991                 }
2992 #endif
2993                 if (i > max_interrupt_work) {
2994                         spin_lock(&np->lock);
2995                         /* disable interrupts on the nic */
2996                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2997                                 writel(0, base + NvRegIrqMask);
2998                         else
2999                                 writel(np->irqmask, base + NvRegIrqMask);
3000                         pci_push(base);
3001
3002                         if (!np->in_shutdown) {
3003                                 np->nic_poll_irq = np->irqmask;
3004                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3005                         }
3006                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3007                         spin_unlock(&np->lock);
3008                         break;
3009                 }
3010
3011         }
3012         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3013
3014         return IRQ_RETVAL(i);
3015 }
3016
3017 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3018 {
3019         struct net_device *dev = (struct net_device *) data;
3020         struct fe_priv *np = netdev_priv(dev);
3021         u8 __iomem *base = get_hwbase(dev);
3022         u32 events;
3023         int i;
3024         unsigned long flags;
3025
3026         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3027
3028         for (i=0; ; i++) {
3029                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3030                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3031                 pci_push(base);
3032                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3033                 if (!(events & np->irqmask))
3034                         break;
3035
3036                 spin_lock_irqsave(&np->lock, flags);
3037                 nv_tx_done_optimized(dev);
3038                 spin_unlock_irqrestore(&np->lock, flags);
3039
3040                 if (events & (NVREG_IRQ_TX_ERR)) {
3041                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3042                                                 dev->name, events);
3043                 }
3044                 if (i > max_interrupt_work) {
3045                         spin_lock_irqsave(&np->lock, flags);
3046                         /* disable interrupts on the nic */
3047                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3048                         pci_push(base);
3049
3050                         if (!np->in_shutdown) {
3051                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3052                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3053                         }
3054                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3055                         spin_unlock_irqrestore(&np->lock, flags);
3056                         break;
3057                 }
3058
3059         }
3060         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3061
3062         return IRQ_RETVAL(i);
3063 }
3064
3065 #ifdef CONFIG_FORCEDETH_NAPI
3066 static int nv_napi_poll(struct net_device *dev, int *budget)
3067 {
3068         int pkts, limit = min(*budget, dev->quota);
3069         struct fe_priv *np = netdev_priv(dev);
3070         u8 __iomem *base = get_hwbase(dev);
3071         unsigned long flags;
3072
3073         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
3074                 pkts = nv_rx_process(dev, limit);
3075         else
3076                 pkts = nv_rx_process_optimized(dev, limit);
3077
3078         if (nv_alloc_rx(dev)) {
3079                 spin_lock_irqsave(&np->lock, flags);
3080                 if (!np->in_shutdown)
3081                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3082                 spin_unlock_irqrestore(&np->lock, flags);
3083         }
3084
3085         if (pkts < limit) {
3086                 /* all done, no more packets present */
3087                 netif_rx_complete(dev);
3088
3089                 /* re-enable receive interrupts */
3090                 spin_lock_irqsave(&np->lock, flags);
3091
3092                 np->irqmask |= NVREG_IRQ_RX_ALL;
3093                 if (np->msi_flags & NV_MSI_X_ENABLED)
3094                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3095                 else
3096                         writel(np->irqmask, base + NvRegIrqMask);
3097
3098                 spin_unlock_irqrestore(&np->lock, flags);
3099                 return 0;
3100         } else {
3101                 /* used up our quantum, so reschedule */
3102                 dev->quota -= pkts;
3103                 *budget -= pkts;
3104                 return 1;
3105         }
3106 }
3107 #endif
3108
3109 #ifdef CONFIG_FORCEDETH_NAPI
3110 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3111 {
3112         struct net_device *dev = (struct net_device *) data;
3113         u8 __iomem *base = get_hwbase(dev);
3114         u32 events;
3115
3116         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3117         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3118
3119         if (events) {
3120                 netif_rx_schedule(dev);
3121                 /* disable receive interrupts on the nic */
3122                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3123                 pci_push(base);
3124         }
3125         return IRQ_HANDLED;
3126 }
3127 #else
3128 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3129 {