drivers/net/bnx2.c

   1 /* bnx2.c: Broadcom NX2 network driver.
   2  *
   3  * Copyright (c) 2004-2007 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Written by: Michael Chan  (mchan@broadcom.com)
  10  */
  11
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/timer.h>
  18 #include <linux/errno.h>
  19 #include <linux/ioport.h>
  20 #include <linux/slab.h>
  21 #include <linux/vmalloc.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/pci.h>
  24 #include <linux/init.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/dma-mapping.h>
  29 #include <asm/bitops.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <linux/delay.h>
  33 #include <asm/byteorder.h>
  34 #include <asm/page.h>
  35 #include <linux/time.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/mii.h>
  38 #ifdef NETIF_F_HW_VLAN_TX
  39 #include <linux/if_vlan.h>
  40 #define BCM_VLAN 1
  41 #endif
  42 #include <net/ip.h>
  43 #include <net/tcp.h>
  44 #include <net/checksum.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/crc32.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/zlib.h>
  50
  51 #include "bnx2.h"
  52 #include "bnx2_fw.h"
  53 #include "bnx2_fw2.h"
  54
  55 #define FW_BUF_SIZE             0x8000
  56
  57 #define DRV_MODULE_NAME         "bnx2"
  58 #define PFX DRV_MODULE_NAME     ": "
  59 #define DRV_MODULE_VERSION      "1.6.5"
  60 #define DRV_MODULE_RELDATE      "September 20, 2007"
  61
  62 #define RUN_AT(x) (jiffies + (x))
  63
  64 /* Time in jiffies before concluding the transmitter is hung. */
  65 #define TX_TIMEOUT  (5*HZ)
  66
  67 static const char version[] __devinitdata =
  68         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  69
  70 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  71 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
  72 MODULE_LICENSE("GPL");
  73 MODULE_VERSION(DRV_MODULE_VERSION);
  74
  75 static int disable_msi = 0;
  76
  77 module_param(disable_msi, int, 0);
  78 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  79
  80 typedef enum {
  81         BCM5706 = 0,
  82         NC370T,
  83         NC370I,
  84         BCM5706S,
  85         NC370F,
  86         BCM5708,
  87         BCM5708S,
  88         BCM5709,
  89         BCM5709S,
  90 } board_t;
  91
  92 /* indexed by board_t, above */
  93 static const struct {
  94         char *name;
  95 } board_info[] __devinitdata = {
  96         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
  97         { "HP NC370T Multifunction Gigabit Server Adapter" },
  98         { "HP NC370i Multifunction Gigabit Server Adapter" },
  99         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 100         { "HP NC370F Multifunction Gigabit Server Adapter" },
 101         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
 102         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
 103         { "Broadcom NetXtreme II BCM5709 1000Base-T" },
 104         { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 105         };
 106
 107 static struct pci_device_id bnx2_pci_tbl[] = {
 108         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 109           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
 110         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 111           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
 112         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 113           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
 114         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
 115           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
 116         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 117           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
 118         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 119           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
 120         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
 121           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
 122         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
 123           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
 124         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
 125           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
 126         { 0, }
 127 };
 128
 129 static struct flash_spec flash_table[] =
 130 {
 131 #define BUFFERED_FLAGS          (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
 132 #define NONBUFFERED_FLAGS       (BNX2_NV_WREN)
 133         /* Slow EEPROM */
 134         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 135          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 136          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 137          "EEPROM - slow"},
 138         /* Expansion entry 0001 */
 139         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 140          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 141          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 142          "Entry 0001"},
 143         /* Saifun SA25F010 (non-buffered flash) */
 144         /* strap, cfg1, & write1 need updates */
 145         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 146          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 147          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 148          "Non-buffered flash (128kB)"},
 149         /* Saifun SA25F020 (non-buffered flash) */
 150         /* strap, cfg1, & write1 need updates */
 151         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 152          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 153          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 154          "Non-buffered flash (256kB)"},
 155         /* Expansion entry 0100 */
 156         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 157          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 158          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 159          "Entry 0100"},
 160         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 161         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 162          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 163          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 164          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 165         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 166         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 167          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 168          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 169          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 170         /* Saifun SA25F005 (non-buffered flash) */
 171         /* strap, cfg1, & write1 need updates */
 172         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 173          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 174          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 175          "Non-buffered flash (64kB)"},
 176         /* Fast EEPROM */
 177         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 178          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 179          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 180          "EEPROM - fast"},
 181         /* Expansion entry 1001 */
 182         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 183          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 184          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 185          "Entry 1001"},
 186         /* Expansion entry 1010 */
 187         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 188          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 189          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 190          "Entry 1010"},
 191         /* ATMEL AT45DB011B (buffered flash) */
 192         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 193          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 194          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 195          "Buffered flash (128kB)"},
 196         /* Expansion entry 1100 */
 197         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 198          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 199          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 200          "Entry 1100"},
 201         /* Expansion entry 1101 */
 202         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 203          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 204          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 205          "Entry 1101"},
 206         /* Ateml Expansion entry 1110 */
 207         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 208          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 209          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 210          "Entry 1110 (Atmel)"},
 211         /* ATMEL AT45DB021B (buffered flash) */
 212         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 213          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 214          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 215          "Buffered flash (256kB)"},
 216 };
 217
 218 static struct flash_spec flash_5709 = {
 219         .flags          = BNX2_NV_BUFFERED,
 220         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 221         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 222         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 223         .total_size     = BUFFERED_FLASH_TOTAL_SIZE*2,
 224         .name           = "5709 Buffered flash (256kB)",
 225 };
 226
 227 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
 228
 229 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
 230 {
 231         u32 diff;
 232
 233         smp_mb();
 234
 235         /* The ring uses 256 indices for 255 entries, one of them
 236          * needs to be skipped.
 237          */
 238         diff = bp->tx_prod - bp->tx_cons;
 239         if (unlikely(diff >= TX_DESC_CNT)) {
 240                 diff &= 0xffff;
 241                 if (diff == TX_DESC_CNT)
 242                         diff = MAX_TX_DESC_CNT;
 243         }
 244         return (bp->tx_ring_size - diff);
 245 }
 246
 247 static u32
 248 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
 249 {
 250         u32 val;
 251
 252         spin_lock_bh(&bp->indirect_lock);
 253         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 254         val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
 255         spin_unlock_bh(&bp->indirect_lock);
 256         return val;
 257 }
 258
 259 static void
 260 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
 261 {
 262         spin_lock_bh(&bp->indirect_lock);
 263         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 264         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
 265         spin_unlock_bh(&bp->indirect_lock);
 266 }
 267
 268 static void
 269 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 270 {
 271         offset += cid_addr;
 272         spin_lock_bh(&bp->indirect_lock);
 273         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 274                 int i;
 275
 276                 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
 277                 REG_WR(bp, BNX2_CTX_CTX_CTRL,
 278                        offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
 279                 for (i = 0; i < 5; i++) {
 280                         u32 val;
 281                         val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
 282                         if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
 283                                 break;
 284                         udelay(5);
 285                 }
 286         } else {
 287                 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
 288                 REG_WR(bp, BNX2_CTX_DATA, val);
 289         }
 290         spin_unlock_bh(&bp->indirect_lock);
 291 }
 292
 293 static int
 294 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
 295 {
 296         u32 val1;
 297         int i, ret;
 298
 299         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 300                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 301                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 302
 303                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 304                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 305
 306                 udelay(40);
 307         }
 308
 309         val1 = (bp->phy_addr << 21) | (reg << 16) |
 310                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
 311                 BNX2_EMAC_MDIO_COMM_START_BUSY;
 312         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 313
 314         for (i = 0; i < 50; i++) {
 315                 udelay(10);
 316
 317                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 318                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 319                         udelay(5);
 320
 321                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 322                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
 323
 324                         break;
 325                 }
 326         }
 327
 328         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
 329                 *val = 0x0;
 330                 ret = -EBUSY;
 331         }
 332         else {
 333                 *val = val1;
 334                 ret = 0;
 335         }
 336
 337         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 338                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 339                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 340
 341                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 342                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 343
 344                 udelay(40);
 345         }
 346
 347         return ret;
 348 }
 349
 350 static int
 351 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
 352 {
 353         u32 val1;
 354         int i, ret;
 355
 356         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 357                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 358                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 359
 360                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 361                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 362
 363                 udelay(40);
 364         }
 365
 366         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
 367                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
 368                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
 369         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 370
 371         for (i = 0; i < 50; i++) {
 372                 udelay(10);
 373
 374                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 375                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 376                         udelay(5);
 377                         break;
 378                 }
 379         }
 380
 381         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
 382                 ret = -EBUSY;
 383         else
 384                 ret = 0;
 385
 386         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 387                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 388                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 389
 390                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 391                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 392
 393                 udelay(40);
 394         }
 395
 396         return ret;
 397 }
 398
 399 static void
 400 bnx2_disable_int(struct bnx2 *bp)
 401 {
 402         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 403                BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 404         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
 405 }
 406
 407 static void
 408 bnx2_enable_int(struct bnx2 *bp)
 409 {
 410         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 411                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 412                BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
 413
 414         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 415                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
 416
 417         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
 418 }
 419
 420 static void
 421 bnx2_disable_int_sync(struct bnx2 *bp)
 422 {
 423         atomic_inc(&bp->intr_sem);
 424         bnx2_disable_int(bp);
 425         synchronize_irq(bp->pdev->irq);
 426 }
 427
 428 static void
 429 bnx2_netif_stop(struct bnx2 *bp)
 430 {
 431         bnx2_disable_int_sync(bp);
 432         if (netif_running(bp->dev)) {
 433                 napi_disable(&bp->napi);
 434                 netif_tx_disable(bp->dev);
 435                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
 436         }
 437 }
 438
 439 static void
 440 bnx2_netif_start(struct bnx2 *bp)
 441 {
 442         if (atomic_dec_and_test(&bp->intr_sem)) {
 443                 if (netif_running(bp->dev)) {
 444                         netif_wake_queue(bp->dev);
 445                         napi_enable(&bp->napi);
 446                         bnx2_enable_int(bp);
 447                 }
 448         }
 449 }
 450
 451 static void
 452 bnx2_free_mem(struct bnx2 *bp)
 453 {
 454         int i;
 455
 456         for (i = 0; i < bp->ctx_pages; i++) {
 457                 if (bp->ctx_blk[i]) {
 458                         pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
 459                                             bp->ctx_blk[i],
 460                                             bp->ctx_blk_mapping[i]);
 461                         bp->ctx_blk[i] = NULL;
 462                 }
 463         }
 464         if (bp->status_blk) {
 465                 pci_free_consistent(bp->pdev, bp->status_stats_size,
 466                                     bp->status_blk, bp->status_blk_mapping);
 467                 bp->status_blk = NULL;
 468                 bp->stats_blk = NULL;
 469         }
 470         if (bp->tx_desc_ring) {
 471                 pci_free_consistent(bp->pdev,
 472                                     sizeof(struct tx_bd) * TX_DESC_CNT,
 473                                     bp->tx_desc_ring, bp->tx_desc_mapping);
 474                 bp->tx_desc_ring = NULL;
 475         }
 476         kfree(bp->tx_buf_ring);
 477         bp->tx_buf_ring = NULL;
 478         for (i = 0; i < bp->rx_max_ring; i++) {
 479                 if (bp->rx_desc_ring[i])
 480                         pci_free_consistent(bp->pdev,
 481                                             sizeof(struct rx_bd) * RX_DESC_CNT,
 482                                             bp->rx_desc_ring[i],
 483                                             bp->rx_desc_mapping[i]);
 484                 bp->rx_desc_ring[i] = NULL;
 485         }
 486         vfree(bp->rx_buf_ring);
 487         bp->rx_buf_ring = NULL;
 488 }
 489
 490 static int
 491 bnx2_alloc_mem(struct bnx2 *bp)
 492 {
 493         int i, status_blk_size;
 494
 495         bp->tx_buf_ring = kzalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
 496                                   GFP_KERNEL);
 497         if (bp->tx_buf_ring == NULL)
 498                 return -ENOMEM;
 499
 500         bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
 501                                                 sizeof(struct tx_bd) *
 502                                                 TX_DESC_CNT,
 503                                                 &bp->tx_desc_mapping);
 504         if (bp->tx_desc_ring == NULL)
 505                 goto alloc_mem_err;
 506
 507         bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT *
 508                                   bp->rx_max_ring);
 509         if (bp->rx_buf_ring == NULL)
 510                 goto alloc_mem_err;
 511
 512         memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT *
 513                                    bp->rx_max_ring);
 514
 515         for (i = 0; i < bp->rx_max_ring; i++) {
 516                 bp->rx_desc_ring[i] =
 517                         pci_alloc_consistent(bp->pdev,
 518                                              sizeof(struct rx_bd) * RX_DESC_CNT,
 519                                              &bp->rx_desc_mapping[i]);
 520                 if (bp->rx_desc_ring[i] == NULL)
 521                         goto alloc_mem_err;
 522
 523         }
 524
 525         /* Combine status and statistics blocks into one allocation. */
 526         status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
 527         bp->status_stats_size = status_blk_size +
 528                                 sizeof(struct statistics_block);
 529
 530         bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
 531                                               &bp->status_blk_mapping);
 532         if (bp->status_blk == NULL)
 533                 goto alloc_mem_err;
 534
 535         memset(bp->status_blk, 0, bp->status_stats_size);
 536
 537         bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
 538                                   status_blk_size);
 539
 540         bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
 541
 542         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 543                 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
 544                 if (bp->ctx_pages == 0)
 545                         bp->ctx_pages = 1;
 546                 for (i = 0; i < bp->ctx_pages; i++) {
 547                         bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
 548                                                 BCM_PAGE_SIZE,
 549                                                 &bp->ctx_blk_mapping[i]);
 550                         if (bp->ctx_blk[i] == NULL)
 551                                 goto alloc_mem_err;
 552                 }
 553         }
 554         return 0;
 555
 556 alloc_mem_err:
 557         bnx2_free_mem(bp);
 558         return -ENOMEM;
 559 }
 560
 561 static void
 562 bnx2_report_fw_link(struct bnx2 *bp)
 563 {
 564         u32 fw_link_status = 0;
 565
 566         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
 567                 return;
 568
 569         if (bp->link_up) {
 570                 u32 bmsr;
 571
 572                 switch (bp->line_speed) {
 573                 case SPEED_10:
 574                         if (bp->duplex == DUPLEX_HALF)
 575                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
 576                         else
 577                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
 578                         break;
 579                 case SPEED_100:
 580                         if (bp->duplex == DUPLEX_HALF)
 581                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
 582                         else
 583                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
 584                         break;
 585                 case SPEED_1000:
 586                         if (bp->duplex == DUPLEX_HALF)
 587                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
 588                         else
 589                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
 590                         break;
 591                 case SPEED_2500:
 592                         if (bp->duplex == DUPLEX_HALF)
 593                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
 594                         else
 595                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
 596                         break;
 597                 }
 598
 599                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
 600
 601                 if (bp->autoneg) {
 602                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
 603
 604                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 605                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 606
 607                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
 608                             bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
 609                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
 610                         else
 611                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
 612                 }
 613         }
 614         else
 615                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
 616
 617         REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
 618 }
 619
 620 static char *
 621 bnx2_xceiver_str(struct bnx2 *bp)
 622 {
 623         return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
 624                 ((bp->phy_flags & PHY_SERDES_FLAG) ? "Remote Copper" :
 625                  "Copper"));
 626 }
 627
 628 static void
 629 bnx2_report_link(struct bnx2 *bp)
 630 {
 631         if (bp->link_up) {
 632                 netif_carrier_on(bp->dev);
 633                 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
 634                        bnx2_xceiver_str(bp));
 635
 636                 printk("%d Mbps ", bp->line_speed);
 637
 638                 if (bp->duplex == DUPLEX_FULL)
 639                         printk("full duplex");
 640                 else
 641                         printk("half duplex");
 642
 643                 if (bp->flow_ctrl) {
 644                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
 645                                 printk(", receive ");
 646                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
 647                                         printk("& transmit ");
 648                         }
 649                         else {
 650                                 printk(", transmit ");
 651                         }
 652                         printk("flow control ON");
 653                 }
 654                 printk("\n");
 655         }
 656         else {
 657                 netif_carrier_off(bp->dev);
 658                 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
 659                        bnx2_xceiver_str(bp));
 660         }
 661
 662         bnx2_report_fw_link(bp);
 663 }
 664
 665 static void
 666 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
 667 {
 668         u32 local_adv, remote_adv;
 669
 670         bp->flow_ctrl = 0;
 671         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
 672                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
 673
 674                 if (bp->duplex == DUPLEX_FULL) {
 675                         bp->flow_ctrl = bp->req_flow_ctrl;
 676                 }
 677                 return;
 678         }
 679
 680         if (bp->duplex != DUPLEX_FULL) {
 681                 return;
 682         }
 683
 684         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 685             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
 686                 u32 val;
 687
 688                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 689                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
 690                         bp->flow_ctrl |= FLOW_CTRL_TX;
 691                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
 692                         bp->flow_ctrl |= FLOW_CTRL_RX;
 693                 return;
 694         }
 695
 696         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 697         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
 698
 699         if (bp->phy_flags & PHY_SERDES_FLAG) {
 700                 u32 new_local_adv = 0;
 701                 u32 new_remote_adv = 0;
 702
 703                 if (local_adv & ADVERTISE_1000XPAUSE)
 704                         new_local_adv |= ADVERTISE_PAUSE_CAP;
 705                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
 706                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
 707                 if (remote_adv & ADVERTISE_1000XPAUSE)
 708                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
 709                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
 710                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
 711
 712                 local_adv = new_local_adv;
 713                 remote_adv = new_remote_adv;
 714         }
 715
 716         /* See Table 28B-3 of 802.3ab-1999 spec. */
 717         if (local_adv & ADVERTISE_PAUSE_CAP) {
 718                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
 719                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 720                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 721                         }
 722                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
 723                                 bp->flow_ctrl = FLOW_CTRL_RX;
 724                         }
 725                 }
 726                 else {
 727                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 728                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 729                         }
 730                 }
 731         }
 732         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
 733                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
 734                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
 735
 736                         bp->flow_ctrl = FLOW_CTRL_TX;
 737                 }
 738         }
 739 }
 740
 741 static int
 742 bnx2_5709s_linkup(struct bnx2 *bp)
 743 {
 744         u32 val, speed;
 745
 746         bp->link_up = 1;
 747
 748         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
 749         bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
 750         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
 751
 752         if ((bp->autoneg & AUTONEG_SPEED) == 0) {
 753                 bp->line_speed = bp->req_line_speed;
 754                 bp->duplex = bp->req_duplex;
 755                 return 0;
 756         }
 757         speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
 758         switch (speed) {
 759                 case MII_BNX2_GP_TOP_AN_SPEED_10:
 760                         bp->line_speed = SPEED_10;
 761                         break;
 762                 case MII_BNX2_GP_TOP_AN_SPEED_100:
 763                         bp->line_speed = SPEED_100;
 764                         break;
 765                 case MII_BNX2_GP_TOP_AN_SPEED_1G:
 766                 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
 767                         bp->line_speed = SPEED_1000;
 768                         break;
 769                 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
 770                         bp->line_speed = SPEED_2500;
 771                         break;
 772         }
 773         if (val & MII_BNX2_GP_TOP_AN_FD)
 774                 bp->duplex = DUPLEX_FULL;
 775         else
 776                 bp->duplex = DUPLEX_HALF;
 777         return 0;
 778 }
 779
 780 static int
 781 bnx2_5708s_linkup(struct bnx2 *bp)
 782 {
 783         u32 val;
 784
 785         bp->link_up = 1;
 786         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 787         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
 788                 case BCM5708S_1000X_STAT1_SPEED_10:
 789                         bp->line_speed = SPEED_10;
 790                         break;
 791                 case BCM5708S_1000X_STAT1_SPEED_100:
 792                         bp->line_speed = SPEED_100;
 793                         break;
 794                 case BCM5708S_1000X_STAT1_SPEED_1G:
 795                         bp->line_speed = SPEED_1000;
 796                         break;
 797                 case BCM5708S_1000X_STAT1_SPEED_2G5:
 798                         bp->line_speed = SPEED_2500;
 799                         break;
 800         }
 801         if (val & BCM5708S_1000X_STAT1_FD)
 802                 bp->duplex = DUPLEX_FULL;
 803         else
 804                 bp->duplex = DUPLEX_HALF;
 805
 806         return 0;
 807 }
 808
 809 static int
 810 bnx2_5706s_linkup(struct bnx2 *bp)
 811 {
 812         u32 bmcr, local_adv, remote_adv, common;
 813
 814         bp->link_up = 1;
 815         bp->line_speed = SPEED_1000;
 816
 817         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
 818         if (bmcr & BMCR_FULLDPLX) {
 819                 bp->duplex = DUPLEX_FULL;
 820         }
 821         else {
 822                 bp->duplex = DUPLEX_HALF;
 823         }
 824
 825         if (!(bmcr & BMCR_ANENABLE)) {
 826                 return 0;
 827         }
 828
 829         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 830         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
 831
 832         common = local_adv & remote_adv;
 833         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
 834
 835                 if (common & ADVERTISE_1000XFULL) {
 836                         bp->duplex = DUPLEX_FULL;
 837                 }
 838                 else {
 839                         bp->duplex = DUPLEX_HALF;
 840                 }
 841         }
 842
 843         return 0;
 844 }
 845
 846 static int
 847 bnx2_copper_linkup(struct bnx2 *bp)
 848 {
 849         u32 bmcr;
 850
 851         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
 852         if (bmcr & BMCR_ANENABLE) {
 853                 u32 local_adv, remote_adv, common;
 854
 855                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
 856                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
 857
 858                 common = local_adv & (remote_adv >> 2);
 859                 if (common & ADVERTISE_1000FULL) {
 860                         bp->line_speed = SPEED_1000;
 861                         bp->duplex = DUPLEX_FULL;
 862                 }
 863                 else if (common & ADVERTISE_1000HALF) {
 864                         bp->line_speed = SPEED_1000;
 865                         bp->duplex = DUPLEX_HALF;
 866                 }
 867                 else {
 868                         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 869                         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
 870
 871                         common = local_adv & remote_adv;
 872                         if (common & ADVERTISE_100FULL) {
 873                                 bp->line_speed = SPEED_100;
 874                                 bp->duplex = DUPLEX_FULL;
 875                         }
 876                         else if (common & ADVERTISE_100HALF) {
 877                                 bp->line_speed = SPEED_100;
 878                                 bp->duplex = DUPLEX_HALF;
 879                         }
 880                         else if (common & ADVERTISE_10FULL) {
 881                                 bp->line_speed = SPEED_10;
 882                                 bp->duplex = DUPLEX_FULL;
 883                         }
 884                         else if (common & ADVERTISE_10HALF) {
 885                                 bp->line_speed = SPEED_10;
 886                                 bp->duplex = DUPLEX_HALF;
 887                         }
 888                         else {
 889                                 bp->line_speed = 0;
 890                                 bp->link_up = 0;
 891                         }
 892                 }
 893         }
 894         else {
 895                 if (bmcr & BMCR_SPEED100) {
 896                         bp->line_speed = SPEED_100;
 897                 }
 898                 else {
 899                         bp->line_speed = SPEED_10;
 900                 }
 901                 if (bmcr & BMCR_FULLDPLX) {
 902                         bp->duplex = DUPLEX_FULL;
 903                 }
 904                 else {
 905                         bp->duplex = DUPLEX_HALF;
 906                 }
 907         }
 908
 909         return 0;
 910 }
 911
 912 static int
 913 bnx2_set_mac_link(struct bnx2 *bp)
 914 {
 915         u32 val;
 916
 917         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
 918         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
 919                 (bp->duplex == DUPLEX_HALF)) {
 920                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
 921         }
 922
 923         /* Configure the EMAC mode register. */
 924         val = REG_RD(bp, BNX2_EMAC_MODE);
 925
 926         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
 927                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
 928                 BNX2_EMAC_MODE_25G_MODE);
 929
 930         if (bp->link_up) {
 931                 switch (bp->line_speed) {
 932                         case SPEED_10:
 933                                 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
 934                                         val |= BNX2_EMAC_MODE_PORT_MII_10M;
 935                                         break;
 936                                 }
 937                                 /* fall through */
 938                         case SPEED_100:
 939                                 val |= BNX2_EMAC_MODE_PORT_MII;
 940                                 break;
 941                         case SPEED_2500:
 942                                 val |= BNX2_EMAC_MODE_25G_MODE;
 943                                 /* fall through */
 944                         case SPEED_1000:
 945                                 val |= BNX2_EMAC_MODE_PORT_GMII;
 946                                 break;
 947                 }
 948         }
 949         else {
 950                 val |= BNX2_EMAC_MODE_PORT_GMII;
 951         }
 952
 953         /* Set the MAC to operate in the appropriate duplex mode. */
 954         if (bp->duplex == DUPLEX_HALF)
 955                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
 956         REG_WR(bp, BNX2_EMAC_MODE, val);
 957
 958         /* Enable/disable rx PAUSE. */
 959         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
 960
 961         if (bp->flow_ctrl & FLOW_CTRL_RX)
 962                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
 963         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
 964
 965         /* Enable/disable tx PAUSE. */
 966         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
 967         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
 968
 969         if (bp->flow_ctrl & FLOW_CTRL_TX)
 970                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
 971         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
 972
 973         /* Acknowledge the interrupt. */
 974         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
 975
 976         return 0;
 977 }
 978
 979 static void
 980 bnx2_enable_bmsr1(struct bnx2 *bp)
 981 {
 982         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 983             (CHIP_NUM(bp) == CHIP_NUM_5709))
 984                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
 985                                MII_BNX2_BLK_ADDR_GP_STATUS);
 986 }
 987
 988 static void
 989 bnx2_disable_bmsr1(struct bnx2 *bp)
 990 {
 991         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 992             (CHIP_NUM(bp) == CHIP_NUM_5709))
 993                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
 994                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
 995 }
 996
 997 static int
 998 bnx2_test_and_enable_2g5(struct bnx2 *bp)
 999 {
1000         u32 up1;
1001         int ret = 1;
1002
1003         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1004                 return 0;
1005
1006         if (bp->autoneg & AUTONEG_SPEED)
1007                 bp->advertising |= ADVERTISED_2500baseX_Full;
1008
1009         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1010                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1011
1012         bnx2_read_phy(bp, bp->mii_up1, &up1);
1013         if (!(up1 & BCM5708S_UP1_2G5)) {
1014                 up1 |= BCM5708S_UP1_2G5;
1015                 bnx2_write_phy(bp, bp->mii_up1, up1);
1016                 ret = 0;
1017         }
1018
1019         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1020                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1021                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1022
1023         return ret;
1024 }
1025
1026 static int
1027 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1028 {
1029         u32 up1;
1030         int ret = 0;
1031
1032         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1033                 return 0;
1034
1035         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1036                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1037
1038         bnx2_read_phy(bp, bp->mii_up1, &up1);
1039         if (up1 & BCM5708S_UP1_2G5) {
1040                 up1 &= ~BCM5708S_UP1_2G5;
1041                 bnx2_write_phy(bp, bp->mii_up1, up1);
1042                 ret = 1;
1043         }
1044
1045         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1046                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1047                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1048
1049         return ret;
1050 }
1051
1052 static void
1053 bnx2_enable_forced_2g5(struct bnx2 *bp)
1054 {
1055         u32 bmcr;
1056
1057         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1058                 return;
1059
1060         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1061                 u32 val;
1062
1063                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1064                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1065                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1066                 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1067                 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1068                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1069
1070                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1071                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1072                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1073
1074         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1075                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1076                 bmcr |= BCM5708S_BMCR_FORCE_2500;
1077         }
1078
1079         if (bp->autoneg & AUTONEG_SPEED) {
1080                 bmcr &= ~BMCR_ANENABLE;
1081                 if (bp->req_duplex == DUPLEX_FULL)
1082                         bmcr |= BMCR_FULLDPLX;
1083         }
1084         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1085 }
1086
1087 static void
1088 bnx2_disable_forced_2g5(struct bnx2 *bp)
1089 {
1090         u32 bmcr;
1091
1092         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1093                 return;
1094
1095         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1096                 u32 val;
1097
1098                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1099                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1100                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1101                 val &= ~MII_BNX2_SD_MISC1_FORCE;
1102                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1103
1104                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1105                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1106                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1107
1108         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1109                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1110                 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1111         }
1112
1113         if (bp->autoneg & AUTONEG_SPEED)
1114                 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1115         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1116 }
1117
1118 static int
1119 bnx2_set_link(struct bnx2 *bp)
1120 {
1121         u32 bmsr;
1122         u8 link_up;
1123
1124         if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1125                 bp->link_up = 1;
1126                 return 0;
1127         }
1128
1129         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1130                 return 0;
1131
1132         link_up = bp->link_up;
1133
1134         bnx2_enable_bmsr1(bp);
1135         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1136         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1137         bnx2_disable_bmsr1(bp);
1138
1139         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1140             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1141                 u32 val;
1142
1143                 val = REG_RD(bp, BNX2_EMAC_STATUS);
1144                 if (val & BNX2_EMAC_STATUS_LINK)
1145                         bmsr |= BMSR_LSTATUS;
1146                 else
1147                         bmsr &= ~BMSR_LSTATUS;
1148         }
1149
1150         if (bmsr & BMSR_LSTATUS) {
1151                 bp->link_up = 1;
1152
1153                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1154                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1155                                 bnx2_5706s_linkup(bp);
1156                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1157                                 bnx2_5708s_linkup(bp);
1158                         else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1159                                 bnx2_5709s_linkup(bp);
1160                 }
1161                 else {
1162                         bnx2_copper_linkup(bp);
1163                 }
1164                 bnx2_resolve_flow_ctrl(bp);
1165         }
1166         else {
1167                 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1168                     (bp->autoneg & AUTONEG_SPEED))
1169                         bnx2_disable_forced_2g5(bp);
1170
1171                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1172                 bp->link_up = 0;
1173         }
1174
1175         if (bp->link_up != link_up) {
1176                 bnx2_report_link(bp);
1177         }
1178
1179         bnx2_set_mac_link(bp);
1180
1181         return 0;
1182 }
1183
1184 static int
1185 bnx2_reset_phy(struct bnx2 *bp)
1186 {
1187         int i;
1188         u32 reg;
1189
1190         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1191
1192 #define PHY_RESET_MAX_WAIT 100
1193         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1194                 udelay(10);
1195
1196                 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1197                 if (!(reg & BMCR_RESET)) {
1198                         udelay(20);
1199                         break;
1200                 }
1201         }
1202         if (i == PHY_RESET_MAX_WAIT) {
1203                 return -EBUSY;
1204         }
1205         return 0;
1206 }
1207
1208 static u32
1209 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1210 {
1211         u32 adv = 0;
1212
1213         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1214                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1215
1216                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1217                         adv = ADVERTISE_1000XPAUSE;
1218                 }
1219                 else {
1220                         adv = ADVERTISE_PAUSE_CAP;
1221                 }
1222         }
1223         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1224                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1225                         adv = ADVERTISE_1000XPSE_ASYM;
1226                 }
1227                 else {
1228                         adv = ADVERTISE_PAUSE_ASYM;
1229                 }
1230         }
1231         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1232                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1233                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1234                 }
1235                 else {
1236                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1237                 }
1238         }
1239         return adv;
1240 }
1241
1242 static int bnx2_fw_sync(struct bnx2 *, u32, int);
1243
1244 static int
1245 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1246 {
1247         u32 speed_arg = 0, pause_adv;
1248
1249         pause_adv = bnx2_phy_get_pause_adv(bp);
1250
1251         if (bp->autoneg & AUTONEG_SPEED) {
1252                 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1253                 if (bp->advertising & ADVERTISED_10baseT_Half)
1254                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1255                 if (bp->advertising & ADVERTISED_10baseT_Full)
1256                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1257                 if (bp->advertising & ADVERTISED_100baseT_Half)
1258                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1259                 if (bp->advertising & ADVERTISED_100baseT_Full)
1260                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1261                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1262                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1263                 if (bp->advertising & ADVERTISED_2500baseX_Full)
1264                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1265         } else {
1266                 if (bp->req_line_speed == SPEED_2500)
1267                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1268                 else if (bp->req_line_speed == SPEED_1000)
1269                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1270                 else if (bp->req_line_speed == SPEED_100) {
1271                         if (bp->req_duplex == DUPLEX_FULL)
1272                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1273                         else
1274                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1275                 } else if (bp->req_line_speed == SPEED_10) {
1276                         if (bp->req_duplex == DUPLEX_FULL)
1277                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1278                         else
1279                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1280                 }
1281         }
1282
1283         if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1284                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1285         if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_1000XPSE_ASYM))
1286                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1287
1288         if (port == PORT_TP)
1289                 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1290                              BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1291
1292         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB_ARG0, speed_arg);
1293
1294         spin_unlock_bh(&bp->phy_lock);
1295         bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
1296         spin_lock_bh(&bp->phy_lock);
1297
1298         return 0;
1299 }
1300
1301 static int
1302 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1303 {
1304         u32 adv, bmcr;
1305         u32 new_adv = 0;
1306
1307         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1308                 return (bnx2_setup_remote_phy(bp, port));
1309
1310         if (!(bp->autoneg & AUTONEG_SPEED)) {
1311                 u32 new_bmcr;
1312                 int force_link_down = 0;
1313
1314                 if (bp->req_line_speed == SPEED_2500) {
1315                         if (!bnx2_test_and_enable_2g5(bp))
1316                                 force_link_down = 1;
1317                 } else if (bp->req_line_speed == SPEED_1000) {
1318                         if (bnx2_test_and_disable_2g5(bp))
1319                                 force_link_down = 1;
1320                 }
1321                 bnx2_read_phy(bp, bp->mii_adv, &adv);
1322                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1323
1324                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1325                 new_bmcr = bmcr & ~BMCR_ANENABLE;
1326                 new_bmcr |= BMCR_SPEED1000;
1327
1328                 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1329                         if (bp->req_line_speed == SPEED_2500)
1330                                 bnx2_enable_forced_2g5(bp);
1331                         else if (bp->req_line_speed == SPEED_1000) {
1332                                 bnx2_disable_forced_2g5(bp);
1333                                 new_bmcr &= ~0x2000;
1334                         }
1335
1336                 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1337                         if (bp->req_line_speed == SPEED_2500)
1338                                 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1339                         else
1340                                 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1341                 }
1342
1343                 if (bp->req_duplex == DUPLEX_FULL) {
1344                         adv |= ADVERTISE_1000XFULL;
1345                         new_bmcr |= BMCR_FULLDPLX;
1346                 }
1347                 else {
1348                         adv |= ADVERTISE_1000XHALF;
1349                         new_bmcr &= ~BMCR_FULLDPLX;
1350                 }
1351                 if ((new_bmcr != bmcr) || (force_link_down)) {
1352                         /* Force a link down visible on the other side */
1353                         if (bp->link_up) {
1354                                 bnx2_write_phy(bp, bp->mii_adv, adv &
1355                                                ~(ADVERTISE_1000XFULL |
1356                                                  ADVERTISE_1000XHALF));
1357                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1358                                         BMCR_ANRESTART | BMCR_ANENABLE);
1359
1360                                 bp->link_up = 0;
1361                                 netif_carrier_off(bp->dev);
1362                                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1363                                 bnx2_report_link(bp);
1364                         }
1365                         bnx2_write_phy(bp, bp->mii_adv, adv);
1366                         bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1367                 } else {
1368                         bnx2_resolve_flow_ctrl(bp);
1369                         bnx2_set_mac_link(bp);
1370                 }
1371                 return 0;
1372         }
1373
1374         bnx2_test_and_enable_2g5(bp);
1375
1376         if (bp->advertising & ADVERTISED_1000baseT_Full)
1377                 new_adv |= ADVERTISE_1000XFULL;
1378
1379         new_adv |= bnx2_phy_get_pause_adv(bp);
1380
1381         bnx2_read_phy(bp, bp->mii_adv, &adv);
1382         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1383
1384         bp->serdes_an_pending = 0;
1385         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1386                 /* Force a link down visible on the other side */
1387                 if (bp->link_up) {
1388                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1389                         spin_unlock_bh(&bp->phy_lock);
1390                         msleep(20);
1391                         spin_lock_bh(&bp->phy_lock);
1392                 }
1393
1394                 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1395                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1396                         BMCR_ANENABLE);
1397                 /* Speed up link-up time when the link partner
1398                  * does not autonegotiate which is very common
1399                  * in blade servers. Some blade servers use
1400                  * IPMI for kerboard input and it's important
1401                  * to minimize link disruptions. Autoneg. involves
1402                  * exchanging base pages plus 3 next pages and
1403                  * normally completes in about 120 msec.
1404                  */
1405                 bp->current_interval = SERDES_AN_TIMEOUT;
1406                 bp->serdes_an_pending = 1;
1407                 mod_timer(&bp->timer, jiffies + bp->current_interval);
1408         } else {
1409                 bnx2_resolve_flow_ctrl(bp);
1410                 bnx2_set_mac_link(bp);
1411         }
1412
1413         return 0;
1414 }
1415
1416 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1417         (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) ?                       \
1418                 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1419                 (ADVERTISED_1000baseT_Full)
1420
1421 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1422         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1423         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1424         ADVERTISED_1000baseT_Full)
1425
1426 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1427         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1428
1429 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1430
1431 static void
1432 bnx2_set_default_remote_link(struct bnx2 *bp)
1433 {
1434         u32 link;
1435
1436         if (bp->phy_port == PORT_TP)
1437                 link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_COPPER_LINK);
1438         else
1439                 link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_SERDES_LINK);
1440
1441         if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1442                 bp->req_line_speed = 0;
1443                 bp->autoneg |= AUTONEG_SPEED;
1444                 bp->advertising = ADVERTISED_Autoneg;
1445                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1446                         bp->advertising |= ADVERTISED_10baseT_Half;
1447                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1448                         bp->advertising |= ADVERTISED_10baseT_Full;
1449                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1450                         bp->advertising |= ADVERTISED_100baseT_Half;
1451                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1452                         bp->advertising |= ADVERTISED_100baseT_Full;
1453                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1454                         bp->advertising |= ADVERTISED_1000baseT_Full;
1455                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1456                         bp->advertising |= ADVERTISED_2500baseX_Full;
1457         } else {
1458                 bp->autoneg = 0;
1459                 bp->advertising = 0;
1460                 bp->req_duplex = DUPLEX_FULL;
1461                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1462                         bp->req_line_speed = SPEED_10;
1463                         if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1464                                 bp->req_duplex = DUPLEX_HALF;
1465                 }
1466                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1467                         bp->req_line_speed = SPEED_100;
1468                         if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1469                                 bp->req_duplex = DUPLEX_HALF;
1470                 }
1471                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1472                         bp->req_line_speed = SPEED_1000;
1473                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1474                         bp->req_line_speed = SPEED_2500;
1475         }
1476 }
1477
1478 static void
1479 bnx2_set_default_link(struct bnx2 *bp)
1480 {
1481         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1482                 return bnx2_set_default_remote_link(bp);
1483
1484         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1485         bp->req_line_speed = 0;
1486         if (bp->phy_flags & PHY_SERDES_FLAG) {
1487                 u32 reg;
1488
1489                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1490
1491                 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
1492                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1493                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1494                         bp->autoneg = 0;
1495                         bp->req_line_speed = bp->line_speed = SPEED_1000;
1496                         bp->req_duplex = DUPLEX_FULL;
1497                 }
1498         } else
1499                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1500 }
1501
1502 static void
1503 bnx2_send_heart_beat(struct bnx2 *bp)
1504 {
1505         u32 msg;
1506         u32 addr;
1507
1508         spin_lock(&bp->indirect_lock);
1509         msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1510         addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1511         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1512         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1513         spin_unlock(&bp->indirect_lock);
1514 }
1515
1516 static void
1517 bnx2_remote_phy_event(struct bnx2 *bp)
1518 {
1519         u32 msg;
1520         u8 link_up = bp->link_up;
1521         u8 old_port;
1522
1523         msg = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
1524
1525         if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1526                 bnx2_send_heart_beat(bp);
1527
1528         msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1529
1530         if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1531                 bp->link_up = 0;
1532         else {
1533                 u32 speed;
1534
1535                 bp->link_up = 1;
1536                 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1537                 bp->duplex = DUPLEX_FULL;
1538                 switch (speed) {
1539                         case BNX2_LINK_STATUS_10HALF:
1540                                 bp->duplex = DUPLEX_HALF;
1541                         case BNX2_LINK_STATUS_10FULL:
1542                                 bp->line_speed = SPEED_10;
1543                                 break;
1544                         case BNX2_LINK_STATUS_100HALF:
1545                                 bp->duplex = DUPLEX_HALF;
1546                         case BNX2_LINK_STATUS_100BASE_T4:
1547                         case BNX2_LINK_STATUS_100FULL:
1548                                 bp->line_speed = SPEED_100;
1549                                 break;
1550                         case BNX2_LINK_STATUS_1000HALF:
1551                                 bp->duplex = DUPLEX_HALF;
1552                         case BNX2_LINK_STATUS_1000FULL:
1553                                 bp->line_speed = SPEED_1000;
1554                                 break;
1555                         case BNX2_LINK_STATUS_2500HALF:
1556                                 bp->duplex = DUPLEX_HALF;
1557                         case BNX2_LINK_STATUS_2500FULL:
1558                                 bp->line_speed = SPEED_2500;
1559                                 break;
1560                         default:
1561                                 bp->line_speed = 0;
1562                                 break;
1563                 }
1564
1565                 spin_lock(&bp->phy_lock);
1566                 bp->flow_ctrl = 0;
1567                 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1568                     (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1569                         if (bp->duplex == DUPLEX_FULL)
1570                                 bp->flow_ctrl = bp->req_flow_ctrl;
1571                 } else {
1572                         if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1573                                 bp->flow_ctrl |= FLOW_CTRL_TX;
1574                         if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1575                                 bp->flow_ctrl |= FLOW_CTRL_RX;
1576                 }
1577
1578                 old_port = bp->phy_port;
1579                 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1580                         bp->phy_port = PORT_FIBRE;
1581                 else
1582                         bp->phy_port = PORT_TP;
1583
1584                 if (old_port != bp->phy_port)
1585                         bnx2_set_default_link(bp);
1586
1587                 spin_unlock(&bp->phy_lock);
1588         }
1589         if (bp->link_up != link_up)
1590                 bnx2_report_link(bp);
1591
1592         bnx2_set_mac_link(bp);
1593 }
1594
1595 static int
1596 bnx2_set_remote_link(struct bnx2 *bp)
1597 {
1598         u32 evt_code;
1599
1600         evt_code = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_EVT_CODE_MB);
1601         switch (evt_code) {
1602                 case BNX2_FW_EVT_CODE_LINK_EVENT:
1603                         bnx2_remote_phy_event(bp);
1604                         break;
1605                 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1606                 default:
1607                         bnx2_send_heart_beat(bp);
1608                         break;
1609         }
1610         return 0;
1611 }
1612
1613 static int
1614 bnx2_setup_copper_phy(struct bnx2 *bp)
1615 {
1616         u32 bmcr;
1617         u32 new_bmcr;
1618
1619         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1620
1621         if (bp->autoneg & AUTONEG_SPEED) {
1622                 u32 adv_reg, adv1000_reg;
1623                 u32 new_adv_reg = 0;
1624                 u32 new_adv1000_reg = 0;
1625
1626                 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1627                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1628                         ADVERTISE_PAUSE_ASYM);
1629
1630                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1631                 adv1000_reg &= PHY_ALL_1000_SPEED;
1632
1633                 if (bp->advertising & ADVERTISED_10baseT_Half)
1634                         new_adv_reg |= ADVERTISE_10HALF;
1635                 if (bp->advertising & ADVERTISED_10baseT_Full)
1636                         new_adv_reg |= ADVERTISE_10FULL;
1637                 if (bp->advertising & ADVERTISED_100baseT_Half)
1638                         new_adv_reg |= ADVERTISE_100HALF;
1639                 if (bp->advertising & ADVERTISED_100baseT_Full)
1640                         new_adv_reg |= ADVERTISE_100FULL;
1641                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1642                         new_adv1000_reg |= ADVERTISE_1000FULL;
1643
1644                 new_adv_reg |= ADVERTISE_CSMA;
1645
1646                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1647
1648                 if ((adv1000_reg != new_adv1000_reg) ||
1649                         (adv_reg != new_adv_reg) ||
1650                         ((bmcr & BMCR_ANENABLE) == 0)) {
1651
1652                         bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1653                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1654                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1655                                 BMCR_ANENABLE);
1656                 }
1657                 else if (bp->link_up) {
1658                         /* Flow ctrl may have changed from auto to forced */
1659                         /* or vice-versa. */
1660
1661                         bnx2_resolve_flow_ctrl(bp);
1662                         bnx2_set_mac_link(bp);
1663                 }
1664                 return 0;
1665         }
1666
1667         new_bmcr = 0;
1668         if (bp->req_line_speed == SPEED_100) {
1669                 new_bmcr |= BMCR_SPEED100;
1670         }
1671         if (bp->req_duplex == DUPLEX_FULL) {
1672                 new_bmcr |= BMCR_FULLDPLX;
1673         }
1674         if (new_bmcr != bmcr) {
1675                 u32 bmsr;
1676
1677                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1678                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1679
1680                 if (bmsr & BMSR_LSTATUS) {
1681                         /* Force link down */
1682                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1683                         spin_unlock_bh(&bp->phy_lock);
1684                         msleep(50);
1685                         spin_lock_bh(&bp->phy_lock);
1686
1687                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1688                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1689                 }
1690
1691                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1692
1693                 /* Normally, the new speed is setup after the link has
1694                  * gone down and up again. In some cases, link will not go
1695                  * down so we need to set up the new speed here.
1696                  */
1697                 if (bmsr & BMSR_LSTATUS) {
1698                         bp->line_speed = bp->req_line_speed;
1699                         bp->duplex = bp->req_duplex;
1700                         bnx2_resolve_flow_ctrl(bp);
1701                         bnx2_set_mac_link(bp);
1702                 }
1703         } else {
1704                 bnx2_resolve_flow_ctrl(bp);
1705                 bnx2_set_mac_link(bp);
1706         }
1707         return 0;
1708 }
1709
1710 static int
1711 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1712 {
1713         if (bp->loopback == MAC_LOOPBACK)
1714                 return 0;
1715
1716         if (bp->phy_flags & PHY_SERDES_FLAG) {
1717                 return (bnx2_setup_serdes_phy(bp, port));
1718         }
1719         else {
1720                 return (bnx2_setup_copper_phy(bp));
1721         }
1722 }
1723
1724 static int
1725 bnx2_init_5709s_phy(struct bnx2 *bp)
1726 {
1727         u32 val;
1728
1729         bp->mii_bmcr = MII_BMCR + 0x10;
1730         bp->mii_bmsr = MII_BMSR + 0x10;
1731         bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1732         bp->mii_adv = MII_ADVERTISE + 0x10;
1733         bp->mii_lpa = MII_LPA + 0x10;
1734         bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1735
1736         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1737         bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1738
1739         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1740         bnx2_reset_phy(bp);
1741
1742         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1743
1744         bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1745         val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1746         val |= MII_BNX2_SD_1000XCTL1_FIBER;
1747         bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1748
1749         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1750         bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
1751         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
1752                 val |= BCM5708S_UP1_2G5;
1753         else
1754                 val &= ~BCM5708S_UP1_2G5;
1755         bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1756
1757         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1758         bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1759         val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1760         bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1761
1762         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1763
1764         val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1765               MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1766         bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1767
1768         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1769
1770         return 0;
1771 }
1772
1773 static int
1774 bnx2_init_5708s_phy(struct bnx2 *bp)
1775 {
1776         u32 val;
1777
1778         bnx2_reset_phy(bp);
1779
1780         bp->mii_up1 = BCM5708S_UP1;
1781
1782         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1783         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1784         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1785
1786         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1787         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1788         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1789
1790         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1791         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1792         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1793
1794         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1795                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1796                 val |= BCM5708S_UP1_2G5;
1797                 bnx2_write_phy(bp, BCM5708S_UP1, val);
1798         }
1799
1800         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1801             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1802             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1803                 /* increase tx signal amplitude */
1804                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1805                                BCM5708S_BLK_ADDR_TX_MISC);
1806                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1807                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1808                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1809                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1810         }
1811
1812         val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1813               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1814
1815         if (val) {
1816                 u32 is_backplane;
1817
1818                 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1819                                           BNX2_SHARED_HW_CFG_CONFIG);
1820                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1821                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1822                                        BCM5708S_BLK_ADDR_TX_MISC);
1823                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1824                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1825                                        BCM5708S_BLK_ADDR_DIG);
1826                 }
1827         }
1828         return 0;
1829 }
1830
1831 static int
1832 bnx2_init_5706s_phy(struct bnx2 *bp)
1833 {
1834         bnx2_reset_phy(bp);
1835
1836         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1837
1838         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1839                 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
1840
1841         if (bp->dev->mtu > 1500) {
1842                 u32 val;
1843
1844                 /* Set extended packet length bit */
1845                 bnx2_write_phy(bp, 0x18, 0x7);
1846                 bnx2_read_phy(bp, 0x18, &val);
1847                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1848
1849                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1850                 bnx2_read_phy(bp, 0x1c, &val);
1851                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1852         }
1853         else {
1854                 u32 val;
1855
1856                 bnx2_write_phy(bp, 0x18, 0x7);
1857                 bnx2_read_phy(bp, 0x18, &val);
1858                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1859
1860                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1861                 bnx2_read_phy(bp, 0x1c, &val);
1862                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1863         }
1864
1865         return 0;
1866 }
1867
1868 static int
1869 bnx2_init_copper_phy(struct bnx2 *bp)
1870 {
1871         u32 val;
1872
1873         bnx2_reset_phy(bp);
1874
1875         if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1876                 bnx2_write_phy(bp, 0x18, 0x0c00);
1877                 bnx2_write_phy(bp, 0x17, 0x000a);
1878                 bnx2_write_phy(bp, 0x15, 0x310b);
1879                 bnx2_write_phy(bp, 0x17, 0x201f);
1880                 bnx2_write_phy(bp, 0x15, 0x9506);
1881                 bnx2_write_phy(bp, 0x17, 0x401f);
1882                 bnx2_write_phy(bp, 0x15, 0x14e2);
1883                 bnx2_write_phy(bp, 0x18, 0x0400);
1884         }
1885
1886         if (bp->phy_flags & PHY_DIS_EARLY_DAC_FLAG) {
1887                 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
1888                                MII_BNX2_DSP_EXPAND_REG | 0x8);
1889                 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1890                 val &= ~(1 << 8);
1891                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
1892         }
1893
1894         if (bp->dev->mtu > 1500) {
1895                 /* Set extended packet length bit */
1896                 bnx2_write_phy(bp, 0x18, 0x7);
1897                 bnx2_read_phy(bp, 0x18, &val);
1898                 bnx2_write_phy(bp, 0x18, val | 0x4000);
1899
1900                 bnx2_read_phy(bp, 0x10, &val);
1901                 bnx2_write_phy(bp, 0x10, val | 0x1);
1902         }
1903         else {
1904                 bnx2_write_phy(bp, 0x18, 0x7);
1905                 bnx2_read_phy(bp, 0x18, &val);
1906                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1907
1908                 bnx2_read_phy(bp, 0x10, &val);
1909                 bnx2_write_phy(bp, 0x10, val & ~0x1);
1910         }
1911
1912         /* ethernet@wirespeed */
1913         bnx2_write_phy(bp, 0x18, 0x7007);
1914         bnx2_read_phy(bp, 0x18, &val);
1915         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1916         return 0;
1917 }
1918
1919
1920 static int
1921 bnx2_init_phy(struct bnx2 *bp)
1922 {
1923         u32 val;
1924         int rc = 0;
1925
1926         bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1927         bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1928
1929         bp->mii_bmcr = MII_BMCR;
1930         bp->mii_bmsr = MII_BMSR;
1931         bp->mii_bmsr1 = MII_BMSR;
1932         bp->mii_adv = MII_ADVERTISE;
1933         bp->mii_lpa = MII_LPA;
1934
1935         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1936
1937         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1938                 goto setup_phy;
1939
1940         bnx2_read_phy(bp, MII_PHYSID1, &val);
1941         bp->phy_id = val << 16;
1942         bnx2_read_phy(bp, MII_PHYSID2, &val);
1943         bp->phy_id |= val & 0xffff;
1944
1945         if (bp->phy_flags & PHY_SERDES_FLAG) {
1946                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1947                         rc = bnx2_init_5706s_phy(bp);
1948                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1949                         rc = bnx2_init_5708s_phy(bp);
1950                 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1951                         rc = bnx2_init_5709s_phy(bp);
1952         }
1953         else {
1954                 rc = bnx2_init_copper_phy(bp);
1955         }
1956
1957 setup_phy:
1958         if (!rc)
1959                 rc = bnx2_setup_phy(bp, bp->phy_port);
1960
1961         return rc;
1962 }
1963
1964 static int
1965 bnx2_set_mac_loopback(struct bnx2 *bp)
1966 {
1967         u32 mac_mode;
1968
1969         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1970         mac_mode &= ~BNX2_EMAC_MODE_PORT;
1971         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1972         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1973         bp->link_up = 1;
1974         return 0;
1975 }
1976
1977 static int bnx2_test_link(struct bnx2 *);
1978
1979 static int
1980 bnx2_set_phy_loopback(struct bnx2 *bp)
1981 {
1982         u32 mac_mode;
1983         int rc, i;
1984
1985         spin_lock_bh(&bp->phy_lock);
1986         rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
1987                             BMCR_SPEED1000);
1988         spin_unlock_bh(&bp->phy_lock);
1989         if (rc)
1990                 return rc;
1991
1992         for (i = 0; i < 10; i++) {
1993                 if (bnx2_test_link(bp) == 0)
1994                         break;
1995                 msleep(100);
1996         }
1997
1998         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1999         mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2000                       BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2001                       BNX2_EMAC_MODE_25G_MODE);
2002
2003         mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2004         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2005         bp->link_up = 1;
2006         return 0;
2007 }
2008
2009 static int
2010 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
2011 {
2012         int i;
2013         u32 val;
2014
2015         bp->fw_wr_seq++;
2016         msg_data |= bp->fw_wr_seq;
2017
2018         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
2019
2020         /* wait for an acknowledgement. */
2021         for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2022                 msleep(10);
2023
2024                 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
2025
2026                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2027                         break;
2028         }
2029         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2030                 return 0;
2031
2032         /* If we timed out, inform the firmware that this is the case. */
2033         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2034                 if (!silent)
2035                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
2036                                             "%x\n", msg_data);
2037
2038                 msg_data &= ~BNX2_DRV_MSG_CODE;
2039                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2040
2041                 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
2042
2043                 return -EBUSY;
2044         }
2045
2046         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2047                 return -EIO;
2048
2049         return 0;
2050 }
2051
2052 static int
2053 bnx2_init_5709_context(struct bnx2 *bp)
2054 {
2055         int i, ret = 0;
2056         u32 val;
2057
2058         val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2059         val |= (BCM_PAGE_BITS - 8) << 16;
2060         REG_WR(bp, BNX2_CTX_COMMAND, val);
2061         for (i = 0; i < 10; i++) {
2062                 val = REG_RD(bp, BNX2_CTX_COMMAND);
2063                 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2064                         break;
2065                 udelay(2);
2066         }
2067         if (val & BNX2_CTX_COMMAND_MEM_INIT)
2068                 return -EBUSY;
2069
2070         for (i = 0; i < bp->ctx_pages; i++) {
2071                 int j;
2072
2073                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2074                        (bp->ctx_blk_mapping[i] & 0xffffffff) |
2075                        BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2076                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2077                        (u64) bp->ctx_blk_mapping[i] >> 32);
2078                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2079                        BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2080                 for (j = 0; j < 10; j++) {
2081
2082                         val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2083                         if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2084                                 break;
2085                         udelay(5);
2086                 }
2087                 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2088                         ret = -EBUSY;
2089                         break;
2090                 }
2091         }
2092         return ret;
2093 }
2094
2095 static void
2096 bnx2_init_context(struct bnx2 *bp)
2097 {
2098         u32 vcid;
2099
2100         vcid = 96;
2101         while (vcid) {
2102                 u32 vcid_addr, pcid_addr, offset;
2103                 int i;
2104
2105                 vcid--;
2106
2107                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2108                         u32 new_vcid;
2109
2110                         vcid_addr = GET_PCID_ADDR(vcid);
2111                         if (vcid & 0x8) {
2112                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2113                         }
2114                         else {
2115                                 new_vcid = vcid;
2116                         }
2117                         pcid_addr = GET_PCID_ADDR(new_vcid);
2118                 }
2119                 else {
2120                         vcid_addr = GET_CID_ADDR(vcid);
2121                         pcid_addr = vcid_addr;
2122                 }
2123
2124                 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2125                         vcid_addr += (i << PHY_CTX_SHIFT);
2126                         pcid_addr += (i << PHY_CTX_SHIFT);
2127
2128                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
2129                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2130
2131                         /* Zero out the context. */
2132                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2133                                 CTX_WR(bp, 0x00, offset, 0);
2134
2135                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2136                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2137                 }
2138         }
2139 }
2140
2141 static int
2142 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2143 {
2144         u16 *good_mbuf;
2145         u32 good_mbuf_cnt;
2146         u32 val;
2147
2148         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2149         if (good_mbuf == NULL) {
2150                 printk(KERN_ERR PFX "Failed to allocate memory in "
2151                                     "bnx2_alloc_bad_rbuf\n");
2152                 return -ENOMEM;
2153         }
2154
2155         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2156                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2157
2158         good_mbuf_cnt = 0;
2159
2160         /* Allocate a bunch of mbufs and save the good ones in an array. */
2161         val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
2162         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2163                 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
2164
2165                 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
2166
2167                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2168
2169                 /* The addresses with Bit 9 set are bad memory blocks. */
2170                 if (!(val & (1 << 9))) {
2171                         good_mbuf[good_mbuf_cnt] = (u16) val;
2172                         good_mbuf_cnt++;
2173                 }
2174
2175                 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
2176         }
2177
2178         /* Free the good ones back to the mbuf pool thus discarding
2179          * all the bad ones. */
2180         while (good_mbuf_cnt) {
2181                 good_mbuf_cnt--;
2182
2183                 val = good_mbuf[good_mbuf_cnt];
2184                 val = (val << 9) | val | 1;
2185
2186                 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
2187         }
2188         kfree(good_mbuf);
2189         return 0;
2190 }
2191
2192 static void
2193 bnx2_set_mac_addr(struct bnx2 *bp)
2194 {
2195         u32 val;
2196         u8 *mac_addr = bp->dev->dev_addr;
2197
2198         val = (mac_addr[0] << 8) | mac_addr[1];
2199
2200         REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
2201
2202         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2203                 (mac_addr[4] << 8) | mac_addr[5];
2204
2205         REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
2206 }
2207
2208 static inline int
2209 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
2210 {
2211         struct sk_buff *skb;
2212         struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
2213         dma_addr_t mapping;
2214         struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2215         unsigned long align;
2216
2217         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2218         if (skb == NULL) {
2219                 return -ENOMEM;
2220         }
2221
2222         if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2223                 skb_reserve(skb, BNX2_RX_ALIGN - align);
2224
2225         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2226                 PCI_DMA_FROMDEVICE);
2227
2228         rx_buf->skb = skb;
2229         pci_unmap_addr_set(rx_buf, mapping, mapping);
2230
2231         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2232         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2233
2234         bp->rx_prod_bseq += bp->rx_buf_use_size;
2235
2236         return 0;
2237 }
2238
2239 static int
2240 bnx2_phy_event_is_set(struct bnx2 *bp, u32 event)
2241 {
2242         struct status_block *sblk = bp->status_blk;
2243         u32 new_link_state, old_link_state;
2244         int is_set = 1;
2245
2246         new_link_state = sblk->status_attn_bits & event;
2247         old_link_state = sblk->status_attn_bits_ack & event;
2248         if (new_link_state != old_link_state) {
2249                 if (new_link_state)
2250                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2251                 else
2252                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2253         } else
2254                 is_set = 0;
2255
2256         return is_set;
2257 }
2258
2259 static void
2260 bnx2_phy_int(struct bnx2 *bp)
2261 {
2262         if (bnx2_phy_event_is_set(bp, STATUS_ATTN_BITS_LINK_STATE)) {
2263                 spin_lock(&bp->phy_lock);
2264                 bnx2_set_link(bp);
2265                 spin_unlock(&bp->phy_lock);
2266         }
2267         if (bnx2_phy_event_is_set(bp, STATUS_ATTN_BITS_TIMER_ABORT))
2268                 bnx2_set_remote_link(bp);
2269
2270 }
2271
2272 static void
2273 bnx2_tx_int(struct bnx2 *bp)
2274 {
2275         struct status_block *sblk = bp->status_blk;
2276         u16 hw_cons, sw_cons, sw_ring_cons;
2277         int tx_free_bd = 0;
2278
2279         hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
2280         if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2281                 hw_cons++;
2282         }
2283         sw_cons = bp->tx_cons;
2284
2285         while (sw_cons != hw_cons) {
2286                 struct sw_bd *tx_buf;
2287                 struct sk_buff *skb;
2288                 int i, last;
2289
2290                 sw_ring_cons = TX_RING_IDX(sw_cons);
2291
2292                 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2293                 skb = tx_buf->skb;
2294
2295                 /* partial BD completions possible with TSO packets */
2296                 if (skb_is_gso(skb)) {
2297                         u16 last_idx, last_ring_idx;
2298
2299                         last_idx = sw_cons +
2300                                 skb_shinfo(skb)->nr_frags + 1;
2301                         last_ring_idx = sw_ring_cons +
2302                                 skb_shinfo(skb)->nr_frags + 1;
2303                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2304                                 last_idx++;
2305                         }
2306                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2307                                 break;
2308                         }
2309                 }
2310
2311                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2312                         skb_headlen(skb), PCI_DMA_TODEVICE);
2313
2314                 tx_buf->skb = NULL;
2315                 last = skb_shinfo(skb)->nr_frags;
2316
2317                 for (i = 0; i < last; i++) {
2318                         sw_cons = NEXT_TX_BD(sw_cons);
2319
2320                         pci_unmap_page(bp->pdev,
2321                                 pci_unmap_addr(
2322                                         &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2323                                         mapping),
2324                                 skb_shinfo(skb)->frags[i].size,
2325                                 PCI_DMA_TODEVICE);
2326                 }
2327
2328                 sw_cons = NEXT_TX_BD(sw_cons);
2329
2330                 tx_free_bd += last + 1;
2331
2332                 dev_kfree_skb(skb);
2333
2334                 hw_cons = bp->hw_tx_cons =
2335                         sblk->status_tx_quick_consumer_index0;
2336
2337                 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2338                         hw_cons++;
2339                 }
2340         }
2341
2342         bp->tx_cons = sw_cons;
2343         /* Need to make the tx_cons update visible to bnx2_start_xmit()
2344          * before checking for netif_queue_stopped().  Without the
2345          * memory barrier, there is a small possibility that bnx2_start_xmit()
2346          * will miss it and cause the queue to be stopped forever.
2347          */
2348         smp_mb();
2349
2350         if (unlikely(netif_queue_stopped(bp->dev)) &&
2351                      (bnx2_tx_avail(bp) > bp->tx_wake_thresh)) {
2352                 netif_tx_lock(bp->dev);
2353                 if ((netif_queue_stopped(bp->dev)) &&
2354                     (bnx2_tx_avail(bp) > bp->tx_wake_thresh))
2355                         netif_wake_queue(bp->dev);
2356                 netif_tx_unlock(bp->dev);
2357         }
2358 }
2359
2360 static inline void
2361 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
2362         u16 cons, u16 prod)
2363 {
2364         struct sw_bd *cons_rx_buf, *prod_rx_buf;
2365         struct rx_bd *cons_bd, *prod_bd;
2366
2367         cons_rx_buf = &bp->rx_buf_ring[cons];
2368         prod_rx_buf = &bp->rx_buf_ring[prod];
2369
2370         pci_dma_sync_single_for_device(bp->pdev,
2371                 pci_unmap_addr(cons_rx_buf, mapping),
2372                 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2373
2374         bp->rx_prod_bseq += bp->rx_buf_use_size;
2375
2376         prod_rx_buf->skb = skb;
2377
2378         if (cons == prod)
2379                 return;
2380
2381         pci_unmap_addr_set(prod_rx_buf, mapping,
2382                         pci_unmap_addr(cons_rx_buf, mapping));
2383
2384         cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2385         prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2386         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2387         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2388 }
2389
2390 static int
2391 bnx2_rx_int(struct bnx2 *bp, int budget)
2392 {
2393         struct status_block *sblk = bp->status_blk;
2394         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2395         struct l2_fhdr *rx_hdr;
2396         int rx_pkt = 0;
2397
2398         hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
2399         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
2400                 hw_cons++;
2401         }
2402         sw_cons = bp->rx_cons;
2403         sw_prod = bp->rx_prod;
2404
2405         /* Memory barrier necessary as speculative reads of the rx
2406          * buffer can be ahead of the index in the status block
2407          */
2408         rmb();
2409         while (sw_cons != hw_cons) {
2410                 unsigned int len;
2411                 u32 status;
2412                 struct sw_bd *rx_buf;
2413                 struct sk_buff *skb;
2414                 dma_addr_t dma_addr;
2415
2416                 sw_ring_cons = RX_RING_IDX(sw_cons);
2417                 sw_ring_prod = RX_RING_IDX(sw_prod);
2418
2419                 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2420                 skb = rx_buf->skb;
2421
2422                 rx_buf->skb = NULL;
2423
2424                 dma_addr = pci_unmap_addr(rx_buf, mapping);
2425
2426                 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2427                         bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2428
2429                 rx_hdr = (struct l2_fhdr *) skb->data;
2430                 len = rx_hdr->l2_fhdr_pkt_len - 4;
2431
2432                 if ((status = rx_hdr->l2_fhdr_status) &
2433                         (L2_FHDR_ERRORS_BAD_CRC |
2434                         L2_FHDR_ERRORS_PHY_DECODE |
2435                         L2_FHDR_ERRORS_ALIGNMENT |
2436                         L2_FHDR_ERRORS_TOO_SHORT |
2437                         L2_FHDR_ERRORS_GIANT_FRAME)) {
2438
2439                         goto reuse_rx;
2440                 }
2441
2442                 /* Since we don't have a jumbo ring, copy small packets
2443                  * if mtu > 1500
2444                  */
2445                 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
2446                         struct sk_buff *new_skb;
2447
2448                         new_skb = netdev_alloc_skb(bp->dev, len + 2);
2449                         if (new_skb == NULL)
2450                                 goto reuse_rx;
2451
2452                         /* aligned copy */
2453                         skb_copy_from_linear_data_offset(skb, bp->rx_offset - 2,
2454                                       new_skb->data, len + 2);
2455                         skb_reserve(new_skb, 2);
2456                         skb_put(new_skb, len);
2457
2458                         bnx2_reuse_rx_skb(bp, skb,
2459                                 sw_ring_cons, sw_ring_prod);
2460
2461                         skb = new_skb;
2462                 }
2463                 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
2464                         pci_unmap_single(bp->pdev, dma_addr,
2465                                 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
2466
2467                         skb_reserve(skb, bp->rx_offset);
2468                         skb_put(skb, len);
2469                 }
2470                 else {
2471 reuse_rx:
2472                         bnx2_reuse_rx_skb(bp, skb,
2473                                 sw_ring_cons, sw_ring_prod);
2474                         goto next_rx;
2475                 }
2476
2477                 skb->protocol = eth_type_trans(skb, bp->dev);
2478
2479                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2480                         (ntohs(skb->protocol) != 0x8100)) {
2481
2482                         dev_kfree_skb(skb);
2483                         goto next_rx;
2484
2485                 }
2486
2487                 skb->ip_summed = CHECKSUM_NONE;
2488                 if (bp->rx_csum &&
2489                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2490                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
2491
2492                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2493                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2494                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2495                 }
2496
2497 #ifdef BCM_VLAN
2498                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
2499                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2500                                 rx_hdr->l2_fhdr_vlan_tag);
2501                 }
2502                 else
2503 #endif
2504                         netif_receive_skb(skb);
2505
2506                 bp->dev->last_rx = jiffies;
2507                 rx_pkt++;
2508
2509 next_rx:
2510                 sw_cons = NEXT_RX_BD(sw_cons);
2511                 sw_prod = NEXT_RX_BD(sw_prod);
2512
2513                 if ((rx_pkt == budget))
2514                         break;
2515
2516                 /* Refresh hw_cons to see if there is new work */
2517                 if (sw_cons == hw_cons) {
2518                         hw_cons = bp->hw_rx_cons =
2519                                 sblk->status_rx_quick_consumer_index0;
2520                         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
2521                                 hw_cons++;
2522                         rmb();
2523                 }
2524         }
2525         bp->rx_cons = sw_cons;
2526         bp->rx_prod = sw_prod;
2527
2528         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2529
2530         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2531
2532         mmiowb();
2533
2534         return rx_pkt;
2535
2536 }
2537
2538 /* MSI ISR - The only difference between this and the INTx ISR
2539  * is that the MSI interrupt is always serviced.
2540  */
2541 static irqreturn_t
2542 bnx2_msi(int irq, void *dev_instance)
2543 {
2544         struct net_device *dev = dev_instance;
2545         struct bnx2 *bp = netdev_priv(dev);
2546
2547         prefetch(bp->status_blk);
2548         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2549                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2550                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2551
2552         /* Return here if interrupt is disabled. */
2553         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2554                 return IRQ_HANDLED;
2555
2556         netif_rx_schedule(dev, &bp->napi);
2557
2558         return IRQ_HANDLED;
2559 }
2560
2561 static irqreturn_t
2562 bnx2_msi_1shot(int irq, void *dev_instance)
2563 {
2564         struct net_device *dev = dev_instance;
2565         struct bnx2 *bp = netdev_priv(dev);
2566
2567         prefetch(bp->status_blk);
2568
2569         /* Return here if interrupt is disabled. */
2570         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2571                 return IRQ_HANDLED;
2572
2573         netif_rx_schedule(dev, &bp->napi);
2574
2575         return IRQ_HANDLED;
2576 }
2577
2578 static irqreturn_t
2579 bnx2_interrupt(int irq, void *dev_instance)
2580 {
2581         struct net_device *dev = dev_instance;
2582         struct bnx2 *bp = netdev_priv(dev);
2583         struct status_block *sblk = bp->status_blk;
2584
2585         /* When using INTx, it is possible for the interrupt to arrive
2586          * at the CPU before the status block posted prior to the
2587          * interrupt. Reading a register will flush the status block.
2588          * When using MSI, the MSI message will always complete after
2589          * the status block write.
2590          */
2591         if ((sblk->status_idx == bp->last_status_idx) &&
2592             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2593              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
2594                 return IRQ_NONE;
2595
2596         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2597                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2598                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2599
2600         /* Read back to deassert IRQ immediately to avoid too many
2601          * spurious interrupts.
2602          */
2603         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
2604
2605         /* Return here if interrupt is shared and is disabled. */
2606         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2607                 return IRQ_HANDLED;
2608
2609         if (netif_rx_schedule_prep(dev, &bp->napi)) {
2610                 bp->last_status_idx = sblk->status_idx;
2611                 __netif_rx_schedule(dev, &bp->napi);
2612         }
2613
2614         return IRQ_HANDLED;
2615 }
2616
2617 #define STATUS_ATTN_EVENTS      (STATUS_ATTN_BITS_LINK_STATE | \
2618                                  STATUS_ATTN_BITS_TIMER_ABORT)
2619
2620 static inline int
2621 bnx2_has_work(struct bnx2 *bp)
2622 {
2623         struct status_block *sblk = bp->status_blk;
2624
2625         if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
2626             (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
2627                 return 1;
2628
2629         if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
2630             (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
2631                 return 1;
2632
2633         return 0;
2634 }
2635
2636 static int
2637 bnx2_poll(struct napi_struct *napi, int budget)
2638 {
2639         struct bnx2 *bp = container_of(napi, struct bnx2, napi);
2640         struct net_device *dev = bp->dev;
2641         struct status_block *sblk = bp->status_blk;
2642         u32 status_attn_bits = sblk->status_attn_bits;
2643         u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
2644         int work_done = 0;
2645
2646         if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
2647             (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
2648
2649                 bnx2_phy_int(bp);
2650
2651                 /* This is needed to take care of transient status
2652                  * during link changes.
2653                  */
2654                 REG_WR(bp, BNX2_HC_COMMAND,
2655                        bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2656                 REG_RD(bp, BNX2_HC_COMMAND);
2657         }
2658
2659         if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
2660                 bnx2_tx_int(bp);
2661
2662         if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons)
2663                 work_done = bnx2_rx_int(bp, budget);
2664
2665         bp->last_status_idx = bp->status_blk->status_idx;
2666         rmb();
2667
2668         if (!bnx2_has_work(bp)) {
2669                 netif_rx_complete(dev, napi);
2670                 if (likely(bp->flags & USING_MSI_FLAG)) {
2671                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2672                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2673                                bp->last_status_idx);
2674                         return 0;
2675                 }
2676                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2677                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2678                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2679                        bp->last_status_idx);
2680
2681                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2682                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2683                        bp->last_status_idx);
2684         }
2685
2686         return work_done;
2687 }
2688
2689 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
2690  * from set_multicast.
2691  */
2692 static void
2693 bnx2_set_rx_mode(struct net_device *dev)
2694 {
2695         struct bnx2 *bp = netdev_priv(dev);
2696         u32 rx_mode, sort_mode;
2697         int i;
2698
2699         spin_lock_bh(&bp->phy_lock);
2700
2701         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
2702                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
2703         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
2704 #ifdef BCM_VLAN
2705         if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
2706                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2707 #else
2708         if (!(bp->flags & ASF_ENABLE_FLAG))
2709                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2710 #endif
2711         if (dev->flags & IFF_PROMISC) {
2712                 /* Promiscuous mode. */
2713                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
2714                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
2715                              BNX2_RPM_SORT_USER0_PROM_VLAN;
2716         }
2717         else if (dev->flags & IFF_ALLMULTI) {
2718                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2719                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2720                                0xffffffff);
2721                 }
2722                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
2723         }
2724         else {
2725                 /* Accept one or more multicast(s). */
2726                 struct dev_mc_list *mclist;
2727                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
2728                 u32 regidx;
2729                 u32 bit;
2730                 u32 crc;
2731
2732                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
2733
2734                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2735                      i++, mclist = mclist->next) {
2736
2737                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
2738                         bit = crc & 0xff;
2739                         regidx = (bit & 0xe0) >> 5;
2740                         bit &= 0x1f;
2741                         mc_filter[regidx] |= (1 << bit);
2742                 }
2743
2744                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2745                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2746                                mc_filter[i]);
2747                 }
2748
2749                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
2750         }
2751
2752         if (rx_mode != bp->rx_mode) {
2753                 bp->rx_mode = rx_mode;
2754                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
2755         }
2756
2757         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2758         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
2759         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
2760
2761         spin_unlock_bh(&bp->phy_lock);
2762 }
2763
2764 /* To be moved to generic lib/ */
2765 static int
2766 bnx2_gunzip(void *gunzip_buf, unsigned sz, u8 *zbuf, int len)
2767 {
2768         struct z_stream_s *strm;
2769         int rc;
2770
2771         /* gzip header (1f,8b,08... 10 bytes total + possible asciz filename)
2772          * is stripped */
2773
2774         rc = -ENOMEM;
2775         strm = kmalloc(sizeof(*strm), GFP_KERNEL);
2776         if (strm == NULL)
2777                 goto gunzip_nomem2;
2778         strm->workspace = kmalloc(zlib_inflate_workspacesize(), GFP_KERNEL);
2779         if (strm->workspace == NULL)
2780                 goto gunzip_nomem3;
2781
2782         strm->next_in = zbuf;
2783         strm->avail_in = len;
2784         strm->next_out = gunzip_buf;
2785         strm->avail_out = sz;
2786
2787         rc = zlib_inflateInit2(strm, -MAX_WBITS);
2788         if (rc == Z_OK) {
2789                 rc = zlib_inflate(strm, Z_FINISH);
2790                 /* after Z_FINISH, only Z_STREAM_END is "we unpacked it all" */
2791                 if (rc == Z_STREAM_END)
2792                         rc = sz - strm->avail_out;
2793                 else
2794                         rc = -EINVAL;
2795                 zlib_inflateEnd(strm);
2796         } else
2797                 rc = -EINVAL;
2798
2799         kfree(strm->workspace);
2800 gunzip_nomem3:
2801         kfree(strm);
2802 gunzip_nomem2:
2803         return rc;
2804 }
2805
2806 static void
2807 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
2808         u32 rv2p_proc)
2809 {
2810         int i;
2811         u32 val;
2812
2813
2814         for (i = 0; i < rv2p_code_len; i += 8) {
2815                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code));
2816                 rv2p_code++;
2817                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code));
2818                 rv2p_code++;
2819
2820                 if (rv2p_proc == RV2P_PROC1) {
2821                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
2822                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
2823                 }
2824                 else {
2825                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
2826                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2827                 }
2828         }
2829
2830         /* Reset the processor, un-stall is done later. */
2831         if (rv2p_proc == RV2P_PROC1) {
2832                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2833         }
2834         else {
2835                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2836         }
2837 }
2838
2839 static int
2840 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2841 {
2842         u32 offset;
2843         u32 val;
2844         int rc;
2845
2846         /* Halt the CPU. */
2847         val = REG_RD_IND(bp, cpu_reg->mode);
2848         val |= cpu_reg->mode_value_halt;
2849         REG_WR_IND(bp, cpu_reg->mode, val);
2850         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2851
2852         /* Load the Text area. */
2853         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2854         if (fw->gz_text) {
2855                 u32 *text;
2856                 int j;
2857
2858                 text = vmalloc(FW_BUF_SIZE);
2859                 if (!text)
2860                         return -ENOMEM;
2861                 rc = bnx2_gunzip(text, FW_BUF_SIZE, fw->gz_text, fw->gz_text_len);
2862                 if (rc < 0) {
2863                         vfree(text);
2864                         return rc;
2865                 }
2866                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2867                         REG_WR_IND(bp, offset, cpu_to_le32(text[j]));
2868                 }
2869                 vfree(text);
2870         }
2871
2872         /* Load the Data area. */
2873         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2874         if (fw->data) {
2875                 int j;
2876
2877                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2878                         REG_WR_IND(bp, offset, fw->data[j]);
2879                 }
2880         }
2881
2882         /* Load the SBSS area. */
2883         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2884         if (fw->sbss) {
2885                 int j;
2886
2887                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2888                         REG_WR_IND(bp, offset, fw->sbss[j]);
2889                 }
2890         }
2891
2892         /* Load the BSS area. */
2893         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2894         if (fw->bss) {
2895                 int j;
2896
2897                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2898                         REG_WR_IND(bp, offset, fw->bss[j]);
2899                 }
2900         }
2901
2902         /* Load the Read-Only area. */
2903         offset = cpu_reg->spad_base +
2904                 (fw->rodata_addr - cpu_reg->mips_view_base);
2905         if (fw->rodata) {
2906                 int j;
2907
2908                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2909                         REG_WR_IND(bp, offset, fw->rodata[j]);
2910                 }
2911         }
2912
2913         /* Clear the pre-fetch instruction. */
2914         REG_WR_IND(bp, cpu_reg->inst, 0);
2915         REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2916
2917         /* Start the CPU. */
2918         val = REG_RD_IND(bp, cpu_reg->mode);
2919         val &= ~cpu_reg->mode_value_halt;
2920         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2921         REG_WR_IND(bp, cpu_reg->mode, val);
2922
2923         return 0;
2924 }
2925
2926 static int
2927 bnx2_init_cpus(struct bnx2 *bp)
2928 {
2929         struct cpu_reg cpu_reg;
2930         struct fw_info *fw;
2931         int rc;
2932         void *text;
2933
2934         /* Initialize the RV2P processor. */
2935         text = vmalloc(FW_BUF_SIZE);
2936         if (!text)
2937                 return -ENOMEM;
2938         rc = bnx2_gunzip(text, FW_BUF_SIZE, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1));
2939         if (rc < 0) {
2940                 vfree(text);
2941                 goto init_cpu_err;
2942         }
2943         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
2944
2945         rc = bnx2_gunzip(text, FW_BUF_SIZE, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2));
2946         if (rc < 0) {
2947                 vfree(text);
2948                 goto init_cpu_err;
2949         }
2950         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
2951         vfree(text);
2952
2953         /* Initialize the RX Processor. */
2954         cpu_reg.mode = BNX2_RXP_CPU_MODE;
2955         cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2956         cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2957         cpu_reg.state = BNX2_RXP_CPU_STATE;
2958         cpu_reg.state_value_clear = 0xffffff;
2959         cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2960         cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2961         cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2962         cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2963         cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2964         cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2965         cpu_reg.mips_view_base = 0x8000000;
2966
2967         if (CHIP_NUM(bp) == CHIP_NUM_5709)
2968                 fw = &bnx2_rxp_fw_09;
2969         else
2970                 fw = &bnx2_rxp_fw_06;
2971
2972         rc = load_cpu_fw(bp, &cpu_reg, fw);
2973         if (rc)
2974                 goto init_cpu_err;
2975
2976         /* Initialize the TX Processor. */
2977         cpu_reg.mode = BNX2_TXP_CPU_MODE;
2978         cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2979         cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2980         cpu_reg.state = BNX2_TXP_CPU_STATE;
2981         cpu_reg.state_value_clear = 0xffffff;
2982         cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2983         cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2984         cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2985         cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2986         cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2987         cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2988         cpu_reg.mips_view_base = 0x8000000;
2989
2990         if (CHIP_NUM(bp) == CHIP_NUM_5709)
2991                 fw = &bnx2_txp_fw_09;
2992         else
2993                 fw = &bnx2_txp_fw_06;
2994
2995         rc = load_cpu_fw(bp, &cpu_reg, fw);
2996         if (rc)
2997                 goto init_cpu_err;
2998
2999         /* Initialize the TX Patch-up Processor. */
3000         cpu_reg.mode = BNX2_TPAT_CPU_MODE;
3001         cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
3002         cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
3003         cpu_reg.state = BNX2_TPAT_CPU_STATE;
3004         cpu_reg.state_value_clear = 0xffffff;
3005         cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
3006         cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
3007         cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
3008         cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
3009         cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
3010         cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
3011         cpu_reg.mips_view_base = 0x8000000;
3012
3013         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3014                 fw = &bnx2_tpat_fw_09;
3015         else
3016                 fw = &bnx2_tpat_fw_06;
3017
3018         rc = load_cpu_fw(bp, &cpu_reg, fw);
3019         if (rc)
3020                 goto init_cpu_err;
3021
3022         /* Initialize the Completion Processor. */
3023         cpu_reg.mode = BNX2_COM_CPU_MODE;
3024         cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
3025         cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
3026         cpu_reg.state = BNX2_COM_CPU_STATE;
3027         cpu_reg.state_value_clear = 0xffffff;
3028         cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
3029         cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
3030         cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
3031         cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
3032         cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
3033         cpu_reg.spad_base = BNX2_COM_SCRATCH;
3034         cpu_reg.mips_view_base = 0x8000000;
3035
3036         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3037                 fw = &bnx2_com_fw_09;
3038         else
3039                 fw = &bnx2_com_fw_06;
3040
3041         rc = load_cpu_fw(bp, &cpu_reg, fw);
3042         if (rc)
3043                 goto init_cpu_err;
3044
3045         /* Initialize the Command Processor. */
3046         cpu_reg.mode = BNX2_CP_CPU_MODE;
3047         cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
3048         cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
3049         cpu_reg.state = BNX2_CP_CPU_STATE;
3050         cpu_reg.state_value_clear = 0xffffff;
3051         cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
3052         cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
3053         cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
3054         cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
3055         cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
3056         cpu_reg.spad_base = BNX2_CP_SCRATCH;
3057         cpu_reg.mips_view_base = 0x8000000;
3058
3059         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3060                 fw = &bnx2_cp_fw_09;
3061
3062                 rc = load_cpu_fw(bp, &cpu_reg, fw);
3063                 if (rc)
3064                         goto init_cpu_err;
3065         }
3066 init_cpu_err:
3067         return rc;
3068 }
3069
3070 static int
3071 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3072 {
3073         u16 pmcsr;
3074
3075         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3076
3077         switch (state) {
3078         case PCI_D0: {
3079                 u32 val;
3080
3081                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3082                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3083                         PCI_PM_CTRL_PME_STATUS);
3084
3085                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3086                         /* delay required during transition out of D3hot */
3087                         msleep(20);
3088
3089                 val = REG_RD(bp, BNX2_EMAC_MODE);
3090                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3091                 val &= ~BNX2_EMAC_MODE_MPKT;
3092                 REG_WR(bp, BNX2_EMAC_MODE, val);
3093
3094                 val = REG_RD(bp, BNX2_RPM_CONFIG);
3095                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3096                 REG_WR(bp, BNX2_RPM_CONFIG, val);
3097                 break;
3098         }
3099         case PCI_D3hot: {
3100                 int i;
3101                 u32 val, wol_msg;
3102
3103                 if (bp->wol) {
3104                         u32 advertising;
3105                         u8 autoneg;
3106
3107                         autoneg = bp->autoneg;
3108                         advertising = bp->advertising;
3109
3110                         bp->autoneg = AUTONEG_SPEED;
3111                         bp->advertising = ADVERTISED_10baseT_Half |
3112                                 ADVERTISED_10baseT_Full |
3113                                 ADVERTISED_100baseT_Half |
3114                                 ADVERTISED_100baseT_Full |
3115                                 ADVERTISED_Autoneg;
3116
3117                         bnx2_setup_copper_phy(bp);
3118
3119                         bp->autoneg = autoneg;
3120                         bp->advertising = advertising;
3121
3122                         bnx2_set_mac_addr(bp);
3123
3124                         val = REG_RD(bp, BNX2_EMAC_MODE);
3125
3126                         /* Enable port mode. */
3127                         val &= ~BNX2_EMAC_MODE_PORT;
3128                         val |= BNX2_EMAC_MODE_PORT_MII |
3129                                BNX2_EMAC_MODE_MPKT_RCVD |
3130                                BNX2_EMAC_MODE_ACPI_RCVD |
3131                                BNX2_EMAC_MODE_MPKT;
3132
3133                         REG_WR(bp, BNX2_EMAC_MODE, val);
3134
3135                         /* receive all multicast */
3136                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3137                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3138                                        0xffffffff);
3139                         }
3140                         REG_WR(bp, BNX2_EMAC_RX_MODE,
3141                                BNX2_EMAC_RX_MODE_SORT_MODE);
3142
3143                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3144                               BNX2_RPM_SORT_USER0_MC_EN;
3145                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3146                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3147                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3148                                BNX2_RPM_SORT_USER0_ENA);
3149
3150                         /* Need to enable EMAC and RPM for WOL. */
3151                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3152                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3153                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3154                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3155
3156                         val = REG_RD(bp, BNX2_RPM_CONFIG);
3157                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3158                         REG_WR(bp, BNX2_RPM_CONFIG, val);
3159
3160                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3161                 }
3162                 else {
3163                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3164                 }
3165
3166                 if (!(bp->flags & NO_WOL_FLAG))
3167                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
3168
3169                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3170                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3171                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3172
3173                         if (bp->wol)
3174                                 pmcsr |= 3;
3175                 }
3176                 else {
3177                         pmcsr |= 3;
3178                 }
3179                 if (bp->wol) {
3180                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3181                 }
3182                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3183                                       pmcsr);
3184
3185                 /* No more memory access after this point until
3186                  * device is brought back to D0.
3187                  */
3188                 udelay(50);
3189                 break;
3190         }
3191         default:
3192                 return -EINVAL;
3193         }
3194         return 0;
3195 }
3196
3197 static int
3198 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3199 {
3200         u32 val;
3201         int j;
3202
3203         /* Request access to the flash interface. */
3204         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3205         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3206                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3207                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3208                         break;
3209
3210                 udelay(5);
3211         }
3212
3213         if (j >= NVRAM_TIMEOUT_COUNT)
3214                 return -EBUSY;
3215
3216         return 0;
3217 }
3218
3219 static int
3220 bnx2_release_nvram_lock(struct bnx2 *bp)
3221 {
3222         int j;
3223         u32 val;
3224
3225         /* Relinquish nvram interface. */
3226         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3227
3228         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3229                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3230                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3231                         break;
3232
3233                 udelay(5);
3234         }
3235
3236         if (j >= NVRAM_TIMEOUT_COUNT)
3237                 return -EBUSY;
3238
3239         return 0;
3240 }
3241
3242
3243 static int
3244 bnx2_enable_nvram_write(struct bnx2 *bp)
3245 {
3246         u32 val;
3247
3248         val = REG_RD(bp, BNX2_MISC_CFG);
3249         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3250
3251         if (bp->flash_info->flags & BNX2_NV_WREN) {
3252                 int j;
3253
3254                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3255                 REG_WR(bp, BNX2_NVM_COMMAND,
3256                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3257
3258                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3259                         udelay(5);
3260
3261                         val = REG_RD(bp, BNX2_NVM_COMMAND);
3262                         if (val & BNX2_NVM_COMMAND_DONE)
3263                                 break;
3264                 }
3265
3266                 if (j >= NVRAM_TIMEOUT_COUNT)
3267                         return -EBUSY;
3268         }
3269         return 0;
3270 }
3271
3272 static void
3273 bnx2_disable_nvram_write(struct bnx2 *bp)
3274 {
3275         u32 val;
3276
3277         val = REG_RD(bp, BNX2_MISC_CFG);
3278         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3279 }
3280
3281
3282 static void
3283 bnx2_enable_nvram_access(struct bnx2 *bp)
3284 {
3285         u32 val;
3286
3287         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3288         /* Enable both bits, even on read. */
3289         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3290                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3291 }
3292
3293 static void
3294 bnx2_disable_nvram_access(struct bnx2 *bp)
3295 {
3296         u32 val;
3297
3298         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3299         /* Disable both bits, even after read. */
3300         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3301                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3302                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
3303 }
3304
3305 static int
3306 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3307 {
3308         u32 cmd;
3309         int j;
3310
3311         if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3312                 /* Buffered flash, no erase needed */
3313                 return 0;
3314
3315         /* Build an erase command */
3316         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3317               BNX2_NVM_COMMAND_DOIT;
3318
3319         /* Need to clear DONE bit separately. */
3320         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3321
3322         /* Address of the NVRAM to read from. */
3323         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3324
3325         /* Issue an erase command. */
3326         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3327
3328         /* Wait for completion. */
3329         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3330                 u32 val;
3331
3332                 udelay(5);
3333
3334                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3335                 if (val & BNX2_NVM_COMMAND_DONE)
3336                         break;
3337         }
3338
3339         if (j >= NVRAM_TIMEOUT_COUNT)
3340                 return -EBUSY;
3341
3342         return 0;
3343 }
3344
3345 static int
3346 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3347 {
3348         u32 cmd;
3349         int j;
3350
3351         /* Build the command word. */
3352         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3353
3354         /* Calculate an offset of a buffered flash, not needed for 5709. */
3355         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3356                 offset = ((offset / bp->flash_info->page_size) <<
3357                            bp->flash_info->page_bits) +
3358                           (offset % bp->flash_info->page_size);
3359         }
3360
3361         /* Need to clear DONE bit separately. */
3362         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3363
3364         /* Address of the NVRAM to read from. */
3365         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3366
3367         /* Issue a read command. */
3368         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3369
3370         /* Wait for completion. */
3371         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3372                 u32 val;
3373
3374                 udelay(5);
3375
3376                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3377                 if (val & BNX2_NVM_COMMAND_DONE) {
3378                         val = REG_RD(bp, BNX2_NVM_READ);
3379
3380                         val = be32_to_cpu(val);
3381                         memcpy(ret_val, &val, 4);
3382                         break;
3383                 }
3384         }
3385         if (j >= NVRAM_TIMEOUT_COUNT)
3386                 return -EBUSY;
3387
3388         return 0;
3389 }
3390
3391
3392 static int
3393 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3394 {
3395         u32 cmd, val32;
3396         int j;
3397
3398         /* Build the command word. */
3399         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3400
3401         /* Calculate an offset of a buffered flash, not needed for 5709. */
3402         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3403                 offset = ((offset / bp->flash_info->page_size) <<
3404                           bp->flash_info->page_bits) +
3405                          (offset % bp->flash_info->page_size);
3406         }
3407
3408         /* Need to clear DONE bit separately. */
3409         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3410
3411         memcpy(&val32, val, 4);
3412         val32 = cpu_to_be32(val32);
3413
3414         /* Write the data. */
3415         REG_WR(bp, BNX2_NVM_WRITE, val32);
3416
3417         /* Address of the NVRAM to write to. */
3418         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3419
3420         /* Issue the write command. */
3421         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3422
3423         /* Wait for completion. */
3424         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3425                 udelay(5);
3426
3427                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3428                         break;
3429         }
3430         if (j >= NVRAM_TIMEOUT_COUNT)
3431                 return -EBUSY;
3432
3433         return 0;
3434 }
3435
3436 static int
3437 bnx2_init_nvram(struct bnx2 *bp)
3438 {
3439         u32 val;
3440         int j, entry_count, rc = 0;
3441         struct flash_spec *flash;
3442
3443         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3444                 bp->flash_info = &flash_5709;
3445                 goto get_flash_size;
3446         }
3447
3448         /* Determine the selected interface. */
3449         val = REG_RD(bp, BNX2_NVM_CFG1);
3450
3451         entry_count = ARRAY_SIZE(flash_table);
3452
3453         if (val & 0x40000000) {
3454
3455                 /* Flash interface has been reconfigured */
3456                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3457                      j++, flash++) {
3458                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
3459                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3460                                 bp->flash_info = flash;
3461                                 break;
3462                         }
3463                 }
3464         }
3465         else {
3466                 u32 mask;
3467                 /* Not yet been reconfigured */
3468
3469                 if (val & (1 << 23))
3470                         mask = FLASH_BACKUP_STRAP_MASK;
3471                 else
3472                         mask = FLASH_STRAP_MASK;
3473
3474                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3475                         j++, flash++) {
3476
3477                         if ((val & mask) == (flash->strapping & mask)) {
3478                                 bp->flash_info = flash;
3479
3480                                 /* Request access to the flash interface. */
3481                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3482                                         return rc;
3483
3484                                 /* Enable access to flash interface */
3485                                 bnx2_enable_nvram_access(bp);
3486
3487                                 /* Reconfigure the flash interface */
3488                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3489                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3490                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3491                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3492
3493                                 /* Disable access to flash interface */
3494                                 bnx2_disable_nvram_access(bp);
3495                                 bnx2_release_nvram_lock(bp);
3496
3497                                 break;
3498                         }
3499                 }
3500         } /* if (val & 0x40000000) */
3501
3502         if (j == entry_count) {
3503                 bp->flash_info = NULL;
3504                 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
3505                 return -ENODEV;
3506         }
3507
3508 get_flash_size:
3509         val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
3510         val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
3511         if (val)
3512                 bp->flash_size = val;
3513         else
3514                 bp->flash_size = bp->flash_info->total_size;
3515
3516         return rc;
3517 }
3518
3519 static int
3520 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
3521                 int buf_size)
3522 {
3523         int rc = 0;
3524         u32 cmd_flags, offset32, len32, extra;
3525
3526         if (buf_size == 0)
3527                 return 0;
3528
3529         /* Request access to the flash interface. */
3530         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3531                 return rc;
3532
3533         /* Enable access to flash interface */
3534         bnx2_enable_nvram_access(bp);
3535
3536         len32 = buf_size;
3537         offset32 = offset;
3538         extra = 0;
3539
3540         cmd_flags = 0;
3541
3542         if (offset32 & 3) {
3543                 u8 buf[4];
3544                 u32 pre_len;
3545
3546                 offset32 &= ~3;
3547                 pre_len = 4 - (offset & 3);
3548
3549                 if (pre_len >= len32) {
3550                         pre_len = len32;
3551                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
3552                                     BNX2_NVM_COMMAND_LAST;
3553                 }
3554                 else {
3555                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
3556                 }
3557
3558                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3559
3560                 if (rc)
3561                         return rc;
3562
3563                 memcpy(ret_buf, buf + (offset & 3), pre_len);
3564
3565                 offset32 += 4;
3566                 ret_buf += pre_len;
3567                 len32 -= pre_len;
3568         }
3569         if (len32 & 3) {
3570                 extra = 4 - (len32 & 3);
3571                 len32 = (len32 + 4) & ~3;
3572         }
3573
3574         if (len32 == 4) {
3575                 u8 buf[4];
3576
3577                 if (cmd_flags)
3578                         cmd_flags = BNX2_NVM_COMMAND_LAST;
3579                 else
3580                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
3581                                     BNX2_NVM_COMMAND_LAST;
3582
3583                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3584
3585                 memcpy(ret_buf, buf, 4 - extra);
3586         }
3587         else if (len32 > 0) {
3588                 u8 buf[4];
3589
3590                 /* Read the first word. */
3591                 if (cmd_flags)
3592                         cmd_flags = 0;
3593                 else
3594                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
3595
3596                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3597
3598                 /* Advance to the next dword. */
3599                 offset32 += 4;
3600                 ret_buf += 4;
3601                 len32 -= 4;
3602
3603                 while (len32 > 4 && rc == 0) {
3604                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
3605
3606                         /* Advance to the next dword. */
3607                         offset32 += 4;
3608                         ret_buf += 4;
3609                         len32 -= 4;
3610                 }
3611
3612                 if (rc)
3613                         return rc;
3614
3615                 cmd_flags = BNX2_NVM_COMMAND_LAST;
3616                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3617
3618                 memcpy(ret_buf, buf, 4 - extra);
3619         }
3620
3621         /* Disable access to flash interface */
3622         bnx2_disable_nvram_access(bp);
3623
3624         bnx2_release_nvram_lock(bp);
3625
3626         return rc;
3627 }
3628
3629 static int
3630 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
3631                 int buf_size)
3632 {
3633         u32 written, offset32, len32;
3634         u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
3635         int rc = 0;
3636         int align_start, align_end;
3637
3638         buf = data_buf;
3639         offset32 = offset;
3640         len32 = buf_size;
3641         align_start = align_end = 0;
3642
3643         if ((align_start = (offset32 & 3))) {
3644                 offset32 &= ~3;
3645                 len32 += align_start;
3646                 if (len32 < 4)
3647                         len32 = 4;
3648                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
3649                         return rc;
3650         }
3651
3652         if (len32 & 3) {
3653                 align_end = 4 - (len32 & 3);
3654                 len32 += align_end;
3655                 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
3656                         return rc;
3657         }
3658
3659         if (align_start || align_end) {
3660                 align_buf = kmalloc(len32, GFP_KERNEL);
3661                 if (align_buf == NULL)
3662                         return -ENOMEM;
3663                 if (align_start) {
3664                         memcpy(align_buf, start, 4);
3665                 }
3666                 if (align_end) {
3667                         memcpy(align_buf + len32 - 4, end, 4);
3668                 }
3669                 memcpy(align_buf + align_start, data_buf, buf_size);
3670                 buf = align_buf;
3671         }
3672
3673         if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3674                 flash_buffer = kmalloc(264, GFP_KERNEL);
3675                 if (flash_buffer == NULL) {
3676                         rc = -ENOMEM;
3677                         goto nvram_write_end;
3678                 }
3679         }
3680
3681         written = 0;
3682         while ((written < len32) && (rc == 0)) {
3683                 u32 page_start, page_end, data_start, data_end;
3684                 u32 addr, cmd_flags;
3685                 int i;
3686
3687                 /* Find the page_start addr */
3688                 page_start = offset32 + written;
3689                 page_start -= (page_start % bp->flash_info->page_size);
3690                 /* Find the page_end addr */
3691                 page_end = page_start + bp->flash_info->page_size;
3692                 /* Find the data_start addr */
3693                 data_start = (written == 0) ? offset32 : page_start;
3694                 /* Find the data_end addr */
3695                 data_end = (page_end > offset32 + len32) ?
3696                         (offset32 + len32) : page_end;
3697
3698                 /* Request access to the flash interface. */
3699                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3700                         goto nvram_write_end;
3701
3702                 /* Enable access to flash interface */
3703                 bnx2_enable_nvram_access(bp);
3704
3705                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3706                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3707                         int j;
3708
3709                         /* Read the whole page into the buffer
3710                          * (non-buffer flash only) */
3711                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
3712                                 if (j == (bp->flash_info->page_size - 4)) {
3713                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
3714                                 }
3715                                 rc = bnx2_nvram_read_dword(bp,
3716                                         page_start + j,
3717                                         &flash_buffer[j],
3718                                         cmd_flags);
3719
3720                                 if (rc)
3721                                         goto nvram_write_end;
3722
3723                                 cmd_flags = 0;
3724                         }
3725                 }
3726
3727                 /* Enable writes to flash interface (unlock write-protect) */
3728                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
3729                         goto nvram_write_end;
3730
3731                 /* Loop to write back the buffer data from page_start to
3732                  * data_start */
3733                 i = 0;
3734                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3735                         /* Erase the page */
3736                         if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
3737                                 goto nvram_write_end;
3738
3739                         /* Re-enable the write again for the actual write */
3740                         bnx2_enable_nvram_write(bp);
3741
3742                         for (addr = page_start; addr < data_start;
3743                                 addr += 4, i += 4) {
3744
3745                                 rc = bnx2_nvram_write_dword(bp, addr,
3746                                         &flash_buffer[i], cmd_flags);
3747
3748                                 if (rc != 0)
3749                                         goto nvram_write_end;
3750
3751                                 cmd_flags = 0;
3752                         }
3753                 }
3754
3755                 /* Loop to write the new data from data_start to data_end */
3756                 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
3757                         if ((addr == page_end - 4) ||
3758                                 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
3759                                  (addr == data_end - 4))) {
3760
3761                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3762                         }
3763                         rc = bnx2_nvram_write_dword(bp, addr, buf,
3764                                 cmd_flags);
3765
3766                         if (rc != 0)
3767                                 goto nvram_write_end;
3768
3769                         cmd_flags = 0;
3770                         buf += 4;
3771                 }
3772
3773                 /* Loop to write back the buffer data from data_end
3774                  * to page_end */
3775                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3776                         for (addr = data_end; addr < page_end;
3777                                 addr += 4, i += 4) {
3778
3779                                 if (addr == page_end-4) {
3780                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
3781                                 }
3782                                 rc = bnx2_nvram_write_dword(bp, addr,
3783                                         &flash_buffer[i], cmd_flags);
3784
3785                                 if (rc != 0)
3786                                         goto nvram_write_end;
3787
3788                                 cmd_flags = 0;
3789                         }
3790                 }
3791
3792                 /* Disable writes to flash interface (lock write-protect) */
3793                 bnx2_disable_nvram_write(bp);
3794
3795                 /* Disable access to flash interface */
3796                 bnx2_disable_nvram_access(bp);
3797                 bnx2_release_nvram_lock(bp);
3798
3799                 /* Increment written */
3800                 written += data_end - data_start;
3801         }
3802
3803 nvram_write_end:
3804         kfree(flash_buffer);
3805         kfree(align_buf);
3806         return rc;
3807 }
3808
3809 static void
3810 bnx2_init_remote_phy(struct bnx2 *bp)
3811 {
3812         u32 val;
3813
3814         bp->phy_flags &= ~REMOTE_PHY_CAP_FLAG;
3815         if (!(bp->phy_flags & PHY_SERDES_FLAG))
3816                 return;
3817
3818         val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_CAP_MB);
3819         if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
3820                 return;
3821
3822         if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
3823                 if (netif_running(bp->dev)) {
3824                         val = BNX2_DRV_ACK_CAP_SIGNATURE |
3825                               BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
3826                         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_ACK_CAP_MB,
3827                                    val);
3828                 }
3829                 bp->phy_flags |= REMOTE_PHY_CAP_FLAG;
3830
3831                 val = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
3832                 if (val & BNX2_LINK_STATUS_SERDES_LINK)
3833                         bp->phy_port = PORT_FIBRE;
3834                 else
3835                         bp->phy_port = PORT_TP;
3836         }
3837 }
3838
3839 static int
3840 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3841 {
3842         u32 val;
3843         int i, rc = 0;
3844
3845         /* Wait for the current PCI transaction to complete before
3846          * issuing a reset. */
3847         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3848                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3849                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3850                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3851                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3852         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3853         udelay(5);
3854
3855         /* Wait for the firmware to tell us it is ok to issue a reset. */
3856         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3857
3858         /* Deposit a driver reset signature so the firmware knows that
3859          * this is a soft reset. */
3860         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
3861                    BNX2_DRV_RESET_SIGNATURE_MAGIC);
3862
3863         /* Do a dummy read to force the chip to complete all current transaction
3864      &nb