drivers/net/bnx2.c

   1 /* bnx2.c: Broadcom NX2 network driver.
   2  *
   3  * Copyright (c) 2004-2007 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Written by: Michael Chan  (mchan@broadcom.com)
  10  */
  11
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/timer.h>
  18 #include <linux/errno.h>
  19 #include <linux/ioport.h>
  20 #include <linux/slab.h>
  21 #include <linux/vmalloc.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/pci.h>
  24 #include <linux/init.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/dma-mapping.h>
  29 #include <asm/bitops.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <linux/delay.h>
  33 #include <asm/byteorder.h>
  34 #include <asm/page.h>
  35 #include <linux/time.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/mii.h>
  38 #ifdef NETIF_F_HW_VLAN_TX
  39 #include <linux/if_vlan.h>
  40 #define BCM_VLAN 1
  41 #endif
  42 #include <net/ip.h>
  43 #include <net/tcp.h>
  44 #include <net/checksum.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/crc32.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/zlib.h>
  50
  51 #include "bnx2.h"
  52 #include "bnx2_fw.h"
  53 #include "bnx2_fw2.h"
  54
  55 #define DRV_MODULE_NAME         "bnx2"
  56 #define PFX DRV_MODULE_NAME     ": "
  57 #define DRV_MODULE_VERSION      "1.6.5"
  58 #define DRV_MODULE_RELDATE      "September 20, 2007"
  59
  60 #define RUN_AT(x) (jiffies + (x))
  61
  62 /* Time in jiffies before concluding the transmitter is hung. */
  63 #define TX_TIMEOUT  (5*HZ)
  64
  65 static const char version[] __devinitdata =
  66         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  67
  68 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  69 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
  70 MODULE_LICENSE("GPL");
  71 MODULE_VERSION(DRV_MODULE_VERSION);
  72
  73 static int disable_msi = 0;
  74
  75 module_param(disable_msi, int, 0);
  76 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  77
  78 typedef enum {
  79         BCM5706 = 0,
  80         NC370T,
  81         NC370I,
  82         BCM5706S,
  83         NC370F,
  84         BCM5708,
  85         BCM5708S,
  86         BCM5709,
  87         BCM5709S,
  88 } board_t;
  89
  90 /* indexed by board_t, above */
  91 static const struct {
  92         char *name;
  93 } board_info[] __devinitdata = {
  94         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
  95         { "HP NC370T Multifunction Gigabit Server Adapter" },
  96         { "HP NC370i Multifunction Gigabit Server Adapter" },
  97         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
  98         { "HP NC370F Multifunction Gigabit Server Adapter" },
  99         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
 100         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
 101         { "Broadcom NetXtreme II BCM5709 1000Base-T" },
 102         { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 103         };
 104
 105 static struct pci_device_id bnx2_pci_tbl[] = {
 106         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 107           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
 108         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 109           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
 110         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 111           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
 112         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
 113           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
 114         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 115           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
 116         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 117           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
 118         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
 119           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
 120         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
 121           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
 122         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
 123           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
 124         { 0, }
 125 };
 126
 127 static struct flash_spec flash_table[] =
 128 {
 129 #define BUFFERED_FLAGS          (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
 130 #define NONBUFFERED_FLAGS       (BNX2_NV_WREN)
 131         /* Slow EEPROM */
 132         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 133          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 134          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 135          "EEPROM - slow"},
 136         /* Expansion entry 0001 */
 137         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 138          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 139          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 140          "Entry 0001"},
 141         /* Saifun SA25F010 (non-buffered flash) */
 142         /* strap, cfg1, & write1 need updates */
 143         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 144          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 145          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 146          "Non-buffered flash (128kB)"},
 147         /* Saifun SA25F020 (non-buffered flash) */
 148         /* strap, cfg1, & write1 need updates */
 149         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 150          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 151          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 152          "Non-buffered flash (256kB)"},
 153         /* Expansion entry 0100 */
 154         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 155          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 156          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 157          "Entry 0100"},
 158         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 159         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 160          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 161          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 162          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 163         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 164         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 165          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 166          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 167          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 168         /* Saifun SA25F005 (non-buffered flash) */
 169         /* strap, cfg1, & write1 need updates */
 170         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 171          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 172          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 173          "Non-buffered flash (64kB)"},
 174         /* Fast EEPROM */
 175         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 176          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 177          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 178          "EEPROM - fast"},
 179         /* Expansion entry 1001 */
 180         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 181          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 182          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 183          "Entry 1001"},
 184         /* Expansion entry 1010 */
 185         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 186          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 187          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 188          "Entry 1010"},
 189         /* ATMEL AT45DB011B (buffered flash) */
 190         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 191          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 192          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 193          "Buffered flash (128kB)"},
 194         /* Expansion entry 1100 */
 195         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 196          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 197          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 198          "Entry 1100"},
 199         /* Expansion entry 1101 */
 200         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 201          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 202          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 203          "Entry 1101"},
 204         /* Ateml Expansion entry 1110 */
 205         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 206          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 207          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 208          "Entry 1110 (Atmel)"},
 209         /* ATMEL AT45DB021B (buffered flash) */
 210         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 211          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 212          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 213          "Buffered flash (256kB)"},
 214 };
 215
 216 static struct flash_spec flash_5709 = {
 217         .flags          = BNX2_NV_BUFFERED,
 218         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 219         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 220         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 221         .total_size     = BUFFERED_FLASH_TOTAL_SIZE*2,
 222         .name           = "5709 Buffered flash (256kB)",
 223 };
 224
 225 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
 226
 227 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
 228 {
 229         u32 diff;
 230
 231         smp_mb();
 232
 233         /* The ring uses 256 indices for 255 entries, one of them
 234          * needs to be skipped.
 235          */
 236         diff = bp->tx_prod - bp->tx_cons;
 237         if (unlikely(diff >= TX_DESC_CNT)) {
 238                 diff &= 0xffff;
 239                 if (diff == TX_DESC_CNT)
 240                         diff = MAX_TX_DESC_CNT;
 241         }
 242         return (bp->tx_ring_size - diff);
 243 }
 244
 245 static u32
 246 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
 247 {
 248         u32 val;
 249
 250         spin_lock_bh(&bp->indirect_lock);
 251         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 252         val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
 253         spin_unlock_bh(&bp->indirect_lock);
 254         return val;
 255 }
 256
 257 static void
 258 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
 259 {
 260         spin_lock_bh(&bp->indirect_lock);
 261         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 262         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
 263         spin_unlock_bh(&bp->indirect_lock);
 264 }
 265
 266 static void
 267 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 268 {
 269         offset += cid_addr;
 270         spin_lock_bh(&bp->indirect_lock);
 271         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 272                 int i;
 273
 274                 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
 275                 REG_WR(bp, BNX2_CTX_CTX_CTRL,
 276                        offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
 277                 for (i = 0; i < 5; i++) {
 278                         u32 val;
 279                         val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
 280                         if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
 281                                 break;
 282                         udelay(5);
 283                 }
 284         } else {
 285                 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
 286                 REG_WR(bp, BNX2_CTX_DATA, val);
 287         }
 288         spin_unlock_bh(&bp->indirect_lock);
 289 }
 290
 291 static int
 292 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
 293 {
 294         u32 val1;
 295         int i, ret;
 296
 297         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 298                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 299                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 300
 301                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 302                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 303
 304                 udelay(40);
 305         }
 306
 307         val1 = (bp->phy_addr << 21) | (reg << 16) |
 308                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
 309                 BNX2_EMAC_MDIO_COMM_START_BUSY;
 310         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 311
 312         for (i = 0; i < 50; i++) {
 313                 udelay(10);
 314
 315                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 316                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 317                         udelay(5);
 318
 319                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 320                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
 321
 322                         break;
 323                 }
 324         }
 325
 326         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
 327                 *val = 0x0;
 328                 ret = -EBUSY;
 329         }
 330         else {
 331                 *val = val1;
 332                 ret = 0;
 333         }
 334
 335         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 336                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 337                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 338
 339                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 340                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 341
 342                 udelay(40);
 343         }
 344
 345         return ret;
 346 }
 347
 348 static int
 349 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
 350 {
 351         u32 val1;
 352         int i, ret;
 353
 354         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 355                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 356                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 357
 358                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 359                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 360
 361                 udelay(40);
 362         }
 363
 364         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
 365                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
 366                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
 367         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 368
 369         for (i = 0; i < 50; i++) {
 370                 udelay(10);
 371
 372                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 373                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 374                         udelay(5);
 375                         break;
 376                 }
 377         }
 378
 379         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
 380                 ret = -EBUSY;
 381         else
 382                 ret = 0;
 383
 384         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 385                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 386                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 387
 388                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 389                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 390
 391                 udelay(40);
 392         }
 393
 394         return ret;
 395 }
 396
 397 static void
 398 bnx2_disable_int(struct bnx2 *bp)
 399 {
 400         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 401                BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 402         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
 403 }
 404
 405 static void
 406 bnx2_enable_int(struct bnx2 *bp)
 407 {
 408         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 409                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 410                BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
 411
 412         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 413                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
 414
 415         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
 416 }
 417
 418 static void
 419 bnx2_disable_int_sync(struct bnx2 *bp)
 420 {
 421         atomic_inc(&bp->intr_sem);
 422         bnx2_disable_int(bp);
 423         synchronize_irq(bp->pdev->irq);
 424 }
 425
 426 static void
 427 bnx2_netif_stop(struct bnx2 *bp)
 428 {
 429         bnx2_disable_int_sync(bp);
 430         if (netif_running(bp->dev)) {
 431                 napi_disable(&bp->napi);
 432                 netif_tx_disable(bp->dev);
 433                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
 434         }
 435 }
 436
 437 static void
 438 bnx2_netif_start(struct bnx2 *bp)
 439 {
 440         if (atomic_dec_and_test(&bp->intr_sem)) {
 441                 if (netif_running(bp->dev)) {
 442                         netif_wake_queue(bp->dev);
 443                         napi_enable(&bp->napi);
 444                         bnx2_enable_int(bp);
 445                 }
 446         }
 447 }
 448
 449 static void
 450 bnx2_free_mem(struct bnx2 *bp)
 451 {
 452         int i;
 453
 454         for (i = 0; i < bp->ctx_pages; i++) {
 455                 if (bp->ctx_blk[i]) {
 456                         pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
 457                                             bp->ctx_blk[i],
 458                                             bp->ctx_blk_mapping[i]);
 459                         bp->ctx_blk[i] = NULL;
 460                 }
 461         }
 462         if (bp->status_blk) {
 463                 pci_free_consistent(bp->pdev, bp->status_stats_size,
 464                                     bp->status_blk, bp->status_blk_mapping);
 465                 bp->status_blk = NULL;
 466                 bp->stats_blk = NULL;
 467         }
 468         if (bp->tx_desc_ring) {
 469                 pci_free_consistent(bp->pdev,
 470                                     sizeof(struct tx_bd) * TX_DESC_CNT,
 471                                     bp->tx_desc_ring, bp->tx_desc_mapping);
 472                 bp->tx_desc_ring = NULL;
 473         }
 474         kfree(bp->tx_buf_ring);
 475         bp->tx_buf_ring = NULL;
 476         for (i = 0; i < bp->rx_max_ring; i++) {
 477                 if (bp->rx_desc_ring[i])
 478                         pci_free_consistent(bp->pdev,
 479                                             sizeof(struct rx_bd) * RX_DESC_CNT,
 480                                             bp->rx_desc_ring[i],
 481                                             bp->rx_desc_mapping[i]);
 482                 bp->rx_desc_ring[i] = NULL;
 483         }
 484         vfree(bp->rx_buf_ring);
 485         bp->rx_buf_ring = NULL;
 486 }
 487
 488 static int
 489 bnx2_alloc_mem(struct bnx2 *bp)
 490 {
 491         int i, status_blk_size;
 492
 493         bp->tx_buf_ring = kzalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
 494                                   GFP_KERNEL);
 495         if (bp->tx_buf_ring == NULL)
 496                 return -ENOMEM;
 497
 498         bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
 499                                                 sizeof(struct tx_bd) *
 500                                                 TX_DESC_CNT,
 501                                                 &bp->tx_desc_mapping);
 502         if (bp->tx_desc_ring == NULL)
 503                 goto alloc_mem_err;
 504
 505         bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT *
 506                                   bp->rx_max_ring);
 507         if (bp->rx_buf_ring == NULL)
 508                 goto alloc_mem_err;
 509
 510         memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT *
 511                                    bp->rx_max_ring);
 512
 513         for (i = 0; i < bp->rx_max_ring; i++) {
 514                 bp->rx_desc_ring[i] =
 515                         pci_alloc_consistent(bp->pdev,
 516                                              sizeof(struct rx_bd) * RX_DESC_CNT,
 517                                              &bp->rx_desc_mapping[i]);
 518                 if (bp->rx_desc_ring[i] == NULL)
 519                         goto alloc_mem_err;
 520
 521         }
 522
 523         /* Combine status and statistics blocks into one allocation. */
 524         status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
 525         bp->status_stats_size = status_blk_size +
 526                                 sizeof(struct statistics_block);
 527
 528         bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
 529                                               &bp->status_blk_mapping);
 530         if (bp->status_blk == NULL)
 531                 goto alloc_mem_err;
 532
 533         memset(bp->status_blk, 0, bp->status_stats_size);
 534
 535         bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
 536                                   status_blk_size);
 537
 538         bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
 539
 540         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 541                 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
 542                 if (bp->ctx_pages == 0)
 543                         bp->ctx_pages = 1;
 544                 for (i = 0; i < bp->ctx_pages; i++) {
 545                         bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
 546                                                 BCM_PAGE_SIZE,
 547                                                 &bp->ctx_blk_mapping[i]);
 548                         if (bp->ctx_blk[i] == NULL)
 549                                 goto alloc_mem_err;
 550                 }
 551         }
 552         return 0;
 553
 554 alloc_mem_err:
 555         bnx2_free_mem(bp);
 556         return -ENOMEM;
 557 }
 558
 559 static void
 560 bnx2_report_fw_link(struct bnx2 *bp)
 561 {
 562         u32 fw_link_status = 0;
 563
 564         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
 565                 return;
 566
 567         if (bp->link_up) {
 568                 u32 bmsr;
 569
 570                 switch (bp->line_speed) {
 571                 case SPEED_10:
 572                         if (bp->duplex == DUPLEX_HALF)
 573                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
 574                         else
 575                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
 576                         break;
 577                 case SPEED_100:
 578                         if (bp->duplex == DUPLEX_HALF)
 579                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
 580                         else
 581                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
 582                         break;
 583                 case SPEED_1000:
 584                         if (bp->duplex == DUPLEX_HALF)
 585                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
 586                         else
 587                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
 588                         break;
 589                 case SPEED_2500:
 590                         if (bp->duplex == DUPLEX_HALF)
 591                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
 592                         else
 593                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
 594                         break;
 595                 }
 596
 597                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
 598
 599                 if (bp->autoneg) {
 600                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
 601
 602                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 603                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 604
 605                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
 606                             bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
 607                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
 608                         else
 609                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
 610                 }
 611         }
 612         else
 613                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
 614
 615         REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
 616 }
 617
 618 static char *
 619 bnx2_xceiver_str(struct bnx2 *bp)
 620 {
 621         return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
 622                 ((bp->phy_flags & PHY_SERDES_FLAG) ? "Remote Copper" :
 623                  "Copper"));
 624 }
 625
 626 static void
 627 bnx2_report_link(struct bnx2 *bp)
 628 {
 629         if (bp->link_up) {
 630                 netif_carrier_on(bp->dev);
 631                 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
 632                        bnx2_xceiver_str(bp));
 633
 634                 printk("%d Mbps ", bp->line_speed);
 635
 636                 if (bp->duplex == DUPLEX_FULL)
 637                         printk("full duplex");
 638                 else
 639                         printk("half duplex");
 640
 641                 if (bp->flow_ctrl) {
 642                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
 643                                 printk(", receive ");
 644                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
 645                                         printk("& transmit ");
 646                         }
 647                         else {
 648                                 printk(", transmit ");
 649                         }
 650                         printk("flow control ON");
 651                 }
 652                 printk("\n");
 653         }
 654         else {
 655                 netif_carrier_off(bp->dev);
 656                 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
 657                        bnx2_xceiver_str(bp));
 658         }
 659
 660         bnx2_report_fw_link(bp);
 661 }
 662
 663 static void
 664 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
 665 {
 666         u32 local_adv, remote_adv;
 667
 668         bp->flow_ctrl = 0;
 669         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
 670                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
 671
 672                 if (bp->duplex == DUPLEX_FULL) {
 673                         bp->flow_ctrl = bp->req_flow_ctrl;
 674                 }
 675                 return;
 676         }
 677
 678         if (bp->duplex != DUPLEX_FULL) {
 679                 return;
 680         }
 681
 682         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 683             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
 684                 u32 val;
 685
 686                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 687                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
 688                         bp->flow_ctrl |= FLOW_CTRL_TX;
 689                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
 690                         bp->flow_ctrl |= FLOW_CTRL_RX;
 691                 return;
 692         }
 693
 694         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 695         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
 696
 697         if (bp->phy_flags & PHY_SERDES_FLAG) {
 698                 u32 new_local_adv = 0;
 699                 u32 new_remote_adv = 0;
 700
 701                 if (local_adv & ADVERTISE_1000XPAUSE)
 702                         new_local_adv |= ADVERTISE_PAUSE_CAP;
 703                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
 704                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
 705                 if (remote_adv & ADVERTISE_1000XPAUSE)
 706                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
 707                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
 708                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
 709
 710                 local_adv = new_local_adv;
 711                 remote_adv = new_remote_adv;
 712         }
 713
 714         /* See Table 28B-3 of 802.3ab-1999 spec. */
 715         if (local_adv & ADVERTISE_PAUSE_CAP) {
 716                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
 717                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 718                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 719                         }
 720                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
 721                                 bp->flow_ctrl = FLOW_CTRL_RX;
 722                         }
 723                 }
 724                 else {
 725                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 726                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 727                         }
 728                 }
 729         }
 730         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
 731                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
 732                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
 733
 734                         bp->flow_ctrl = FLOW_CTRL_TX;
 735                 }
 736         }
 737 }
 738
 739 static int
 740 bnx2_5709s_linkup(struct bnx2 *bp)
 741 {
 742         u32 val, speed;
 743
 744         bp->link_up = 1;
 745
 746         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
 747         bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
 748         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
 749
 750         if ((bp->autoneg & AUTONEG_SPEED) == 0) {
 751                 bp->line_speed = bp->req_line_speed;
 752                 bp->duplex = bp->req_duplex;
 753                 return 0;
 754         }
 755         speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
 756         switch (speed) {
 757                 case MII_BNX2_GP_TOP_AN_SPEED_10:
 758                         bp->line_speed = SPEED_10;
 759                         break;
 760                 case MII_BNX2_GP_TOP_AN_SPEED_100:
 761                         bp->line_speed = SPEED_100;
 762                         break;
 763                 case MII_BNX2_GP_TOP_AN_SPEED_1G:
 764                 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
 765                         bp->line_speed = SPEED_1000;
 766                         break;
 767                 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
 768                         bp->line_speed = SPEED_2500;
 769                         break;
 770         }
 771         if (val & MII_BNX2_GP_TOP_AN_FD)
 772                 bp->duplex = DUPLEX_FULL;
 773         else
 774                 bp->duplex = DUPLEX_HALF;
 775         return 0;
 776 }
 777
 778 static int
 779 bnx2_5708s_linkup(struct bnx2 *bp)
 780 {
 781         u32 val;
 782
 783         bp->link_up = 1;
 784         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 785         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
 786                 case BCM5708S_1000X_STAT1_SPEED_10:
 787                         bp->line_speed = SPEED_10;
 788                         break;
 789                 case BCM5708S_1000X_STAT1_SPEED_100:
 790                         bp->line_speed = SPEED_100;
 791                         break;
 792                 case BCM5708S_1000X_STAT1_SPEED_1G:
 793                         bp->line_speed = SPEED_1000;
 794                         break;
 795                 case BCM5708S_1000X_STAT1_SPEED_2G5:
 796                         bp->line_speed = SPEED_2500;
 797                         break;
 798         }
 799         if (val & BCM5708S_1000X_STAT1_FD)
 800                 bp->duplex = DUPLEX_FULL;
 801         else
 802                 bp->duplex = DUPLEX_HALF;
 803
 804         return 0;
 805 }
 806
 807 static int
 808 bnx2_5706s_linkup(struct bnx2 *bp)
 809 {
 810         u32 bmcr, local_adv, remote_adv, common;
 811
 812         bp->link_up = 1;
 813         bp->line_speed = SPEED_1000;
 814
 815         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
 816         if (bmcr & BMCR_FULLDPLX) {
 817                 bp->duplex = DUPLEX_FULL;
 818         }
 819         else {
 820                 bp->duplex = DUPLEX_HALF;
 821         }
 822
 823         if (!(bmcr & BMCR_ANENABLE)) {
 824                 return 0;
 825         }
 826
 827         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 828         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
 829
 830         common = local_adv & remote_adv;
 831         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
 832
 833                 if (common & ADVERTISE_1000XFULL) {
 834                         bp->duplex = DUPLEX_FULL;
 835                 }
 836                 else {
 837                         bp->duplex = DUPLEX_HALF;
 838                 }
 839         }
 840
 841         return 0;
 842 }
 843
 844 static int
 845 bnx2_copper_linkup(struct bnx2 *bp)
 846 {
 847         u32 bmcr;
 848
 849         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
 850         if (bmcr & BMCR_ANENABLE) {
 851                 u32 local_adv, remote_adv, common;
 852
 853                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
 854                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
 855
 856                 common = local_adv & (remote_adv >> 2);
 857                 if (common & ADVERTISE_1000FULL) {
 858                         bp->line_speed = SPEED_1000;
 859                         bp->duplex = DUPLEX_FULL;
 860                 }
 861                 else if (common & ADVERTISE_1000HALF) {
 862                         bp->line_speed = SPEED_1000;
 863                         bp->duplex = DUPLEX_HALF;
 864                 }
 865                 else {
 866                         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 867                         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
 868
 869                         common = local_adv & remote_adv;
 870                         if (common & ADVERTISE_100FULL) {
 871                                 bp->line_speed = SPEED_100;
 872                                 bp->duplex = DUPLEX_FULL;
 873                         }
 874                         else if (common & ADVERTISE_100HALF) {
 875                                 bp->line_speed = SPEED_100;
 876                                 bp->duplex = DUPLEX_HALF;
 877                         }
 878                         else if (common & ADVERTISE_10FULL) {
 879                                 bp->line_speed = SPEED_10;
 880                                 bp->duplex = DUPLEX_FULL;
 881                         }
 882                         else if (common & ADVERTISE_10HALF) {
 883                                 bp->line_speed = SPEED_10;
 884                                 bp->duplex = DUPLEX_HALF;
 885                         }
 886                         else {
 887                                 bp->line_speed = 0;
 888                                 bp->link_up = 0;
 889                         }
 890                 }
 891         }
 892         else {
 893                 if (bmcr & BMCR_SPEED100) {
 894                         bp->line_speed = SPEED_100;
 895                 }
 896                 else {
 897                         bp->line_speed = SPEED_10;
 898                 }
 899                 if (bmcr & BMCR_FULLDPLX) {
 900                         bp->duplex = DUPLEX_FULL;
 901                 }
 902                 else {
 903                         bp->duplex = DUPLEX_HALF;
 904                 }
 905         }
 906
 907         return 0;
 908 }
 909
 910 static int
 911 bnx2_set_mac_link(struct bnx2 *bp)
 912 {
 913         u32 val;
 914
 915         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
 916         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
 917                 (bp->duplex == DUPLEX_HALF)) {
 918                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
 919         }
 920
 921         /* Configure the EMAC mode register. */
 922         val = REG_RD(bp, BNX2_EMAC_MODE);
 923
 924         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
 925                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
 926                 BNX2_EMAC_MODE_25G_MODE);
 927
 928         if (bp->link_up) {
 929                 switch (bp->line_speed) {
 930                         case SPEED_10:
 931                                 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
 932                                         val |= BNX2_EMAC_MODE_PORT_MII_10M;
 933                                         break;
 934                                 }
 935                                 /* fall through */
 936                         case SPEED_100:
 937                                 val |= BNX2_EMAC_MODE_PORT_MII;
 938                                 break;
 939                         case SPEED_2500:
 940                                 val |= BNX2_EMAC_MODE_25G_MODE;
 941                                 /* fall through */
 942                         case SPEED_1000:
 943                                 val |= BNX2_EMAC_MODE_PORT_GMII;
 944                                 break;
 945                 }
 946         }
 947         else {
 948                 val |= BNX2_EMAC_MODE_PORT_GMII;
 949         }
 950
 951         /* Set the MAC to operate in the appropriate duplex mode. */
 952         if (bp->duplex == DUPLEX_HALF)
 953                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
 954         REG_WR(bp, BNX2_EMAC_MODE, val);
 955
 956         /* Enable/disable rx PAUSE. */
 957         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
 958
 959         if (bp->flow_ctrl & FLOW_CTRL_RX)
 960                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
 961         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
 962
 963         /* Enable/disable tx PAUSE. */
 964         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
 965         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
 966
 967         if (bp->flow_ctrl & FLOW_CTRL_TX)
 968                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
 969         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
 970
 971         /* Acknowledge the interrupt. */
 972         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
 973
 974         return 0;
 975 }
 976
 977 static void
 978 bnx2_enable_bmsr1(struct bnx2 *bp)
 979 {
 980         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 981             (CHIP_NUM(bp) == CHIP_NUM_5709))
 982                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
 983                                MII_BNX2_BLK_ADDR_GP_STATUS);
 984 }
 985
 986 static void
 987 bnx2_disable_bmsr1(struct bnx2 *bp)
 988 {
 989         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 990             (CHIP_NUM(bp) == CHIP_NUM_5709))
 991                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
 992                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
 993 }
 994
 995 static int
 996 bnx2_test_and_enable_2g5(struct bnx2 *bp)
 997 {
 998         u32 up1;
 999         int ret = 1;
1000
1001         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1002                 return 0;
1003
1004         if (bp->autoneg & AUTONEG_SPEED)
1005                 bp->advertising |= ADVERTISED_2500baseX_Full;
1006
1007         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1008                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1009
1010         bnx2_read_phy(bp, bp->mii_up1, &up1);
1011         if (!(up1 & BCM5708S_UP1_2G5)) {
1012                 up1 |= BCM5708S_UP1_2G5;
1013                 bnx2_write_phy(bp, bp->mii_up1, up1);
1014                 ret = 0;
1015         }
1016
1017         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1018                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1019                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1020
1021         return ret;
1022 }
1023
1024 static int
1025 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1026 {
1027         u32 up1;
1028         int ret = 0;
1029
1030         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1031                 return 0;
1032
1033         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1034                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1035
1036         bnx2_read_phy(bp, bp->mii_up1, &up1);
1037         if (up1 & BCM5708S_UP1_2G5) {
1038                 up1 &= ~BCM5708S_UP1_2G5;
1039                 bnx2_write_phy(bp, bp->mii_up1, up1);
1040                 ret = 1;
1041         }
1042
1043         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1044                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1045                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1046
1047         return ret;
1048 }
1049
1050 static void
1051 bnx2_enable_forced_2g5(struct bnx2 *bp)
1052 {
1053         u32 bmcr;
1054
1055         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1056                 return;
1057
1058         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1059                 u32 val;
1060
1061                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1062                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1063                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1064                 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1065                 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1066                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1067
1068                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1069                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1070                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1071
1072         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1073                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1074                 bmcr |= BCM5708S_BMCR_FORCE_2500;
1075         }
1076
1077         if (bp->autoneg & AUTONEG_SPEED) {
1078                 bmcr &= ~BMCR_ANENABLE;
1079                 if (bp->req_duplex == DUPLEX_FULL)
1080                         bmcr |= BMCR_FULLDPLX;
1081         }
1082         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1083 }
1084
1085 static void
1086 bnx2_disable_forced_2g5(struct bnx2 *bp)
1087 {
1088         u32 bmcr;
1089
1090         if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1091                 return;
1092
1093         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1094                 u32 val;
1095
1096                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1097                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1098                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1099                 val &= ~MII_BNX2_SD_MISC1_FORCE;
1100                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1101
1102                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1103                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1104                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1105
1106         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1107                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1108                 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1109         }
1110
1111         if (bp->autoneg & AUTONEG_SPEED)
1112                 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1113         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1114 }
1115
1116 static int
1117 bnx2_set_link(struct bnx2 *bp)
1118 {
1119         u32 bmsr;
1120         u8 link_up;
1121
1122         if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1123                 bp->link_up = 1;
1124                 return 0;
1125         }
1126
1127         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1128                 return 0;
1129
1130         link_up = bp->link_up;
1131
1132         bnx2_enable_bmsr1(bp);
1133         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1134         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1135         bnx2_disable_bmsr1(bp);
1136
1137         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1138             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1139                 u32 val;
1140
1141                 val = REG_RD(bp, BNX2_EMAC_STATUS);
1142                 if (val & BNX2_EMAC_STATUS_LINK)
1143                         bmsr |= BMSR_LSTATUS;
1144                 else
1145                         bmsr &= ~BMSR_LSTATUS;
1146         }
1147
1148         if (bmsr & BMSR_LSTATUS) {
1149                 bp->link_up = 1;
1150
1151                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1152                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1153                                 bnx2_5706s_linkup(bp);
1154                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1155                                 bnx2_5708s_linkup(bp);
1156                         else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1157                                 bnx2_5709s_linkup(bp);
1158                 }
1159                 else {
1160                         bnx2_copper_linkup(bp);
1161                 }
1162                 bnx2_resolve_flow_ctrl(bp);
1163         }
1164         else {
1165                 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1166                     (bp->autoneg & AUTONEG_SPEED))
1167                         bnx2_disable_forced_2g5(bp);
1168
1169                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1170                 bp->link_up = 0;
1171         }
1172
1173         if (bp->link_up != link_up) {
1174                 bnx2_report_link(bp);
1175         }
1176
1177         bnx2_set_mac_link(bp);
1178
1179         return 0;
1180 }
1181
1182 static int
1183 bnx2_reset_phy(struct bnx2 *bp)
1184 {
1185         int i;
1186         u32 reg;
1187
1188         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1189
1190 #define PHY_RESET_MAX_WAIT 100
1191         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1192                 udelay(10);
1193
1194                 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1195                 if (!(reg & BMCR_RESET)) {
1196                         udelay(20);
1197                         break;
1198                 }
1199         }
1200         if (i == PHY_RESET_MAX_WAIT) {
1201                 return -EBUSY;
1202         }
1203         return 0;
1204 }
1205
1206 static u32
1207 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1208 {
1209         u32 adv = 0;
1210
1211         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1212                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1213
1214                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1215                         adv = ADVERTISE_1000XPAUSE;
1216                 }
1217                 else {
1218                         adv = ADVERTISE_PAUSE_CAP;
1219                 }
1220         }
1221         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1222                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1223                         adv = ADVERTISE_1000XPSE_ASYM;
1224                 }
1225                 else {
1226                         adv = ADVERTISE_PAUSE_ASYM;
1227                 }
1228         }
1229         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1230                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1231                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1232                 }
1233                 else {
1234                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1235                 }
1236         }
1237         return adv;
1238 }
1239
1240 static int bnx2_fw_sync(struct bnx2 *, u32, int);
1241
1242 static int
1243 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1244 {
1245         u32 speed_arg = 0, pause_adv;
1246
1247         pause_adv = bnx2_phy_get_pause_adv(bp);
1248
1249         if (bp->autoneg & AUTONEG_SPEED) {
1250                 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1251                 if (bp->advertising & ADVERTISED_10baseT_Half)
1252                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1253                 if (bp->advertising & ADVERTISED_10baseT_Full)
1254                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1255                 if (bp->advertising & ADVERTISED_100baseT_Half)
1256                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1257                 if (bp->advertising & ADVERTISED_100baseT_Full)
1258                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1259                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1260                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1261                 if (bp->advertising & ADVERTISED_2500baseX_Full)
1262                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1263         } else {
1264                 if (bp->req_line_speed == SPEED_2500)
1265                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1266                 else if (bp->req_line_speed == SPEED_1000)
1267                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1268                 else if (bp->req_line_speed == SPEED_100) {
1269                         if (bp->req_duplex == DUPLEX_FULL)
1270                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1271                         else
1272                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1273                 } else if (bp->req_line_speed == SPEED_10) {
1274                         if (bp->req_duplex == DUPLEX_FULL)
1275                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1276                         else
1277                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1278                 }
1279         }
1280
1281         if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1282                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1283         if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_1000XPSE_ASYM))
1284                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1285
1286         if (port == PORT_TP)
1287                 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1288                              BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1289
1290         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB_ARG0, speed_arg);
1291
1292         spin_unlock_bh(&bp->phy_lock);
1293         bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
1294         spin_lock_bh(&bp->phy_lock);
1295
1296         return 0;
1297 }
1298
1299 static int
1300 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1301 {
1302         u32 adv, bmcr;
1303         u32 new_adv = 0;
1304
1305         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1306                 return (bnx2_setup_remote_phy(bp, port));
1307
1308         if (!(bp->autoneg & AUTONEG_SPEED)) {
1309                 u32 new_bmcr;
1310                 int force_link_down = 0;
1311
1312                 if (bp->req_line_speed == SPEED_2500) {
1313                         if (!bnx2_test_and_enable_2g5(bp))
1314                                 force_link_down = 1;
1315                 } else if (bp->req_line_speed == SPEED_1000) {
1316                         if (bnx2_test_and_disable_2g5(bp))
1317                                 force_link_down = 1;
1318                 }
1319                 bnx2_read_phy(bp, bp->mii_adv, &adv);
1320                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1321
1322                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1323                 new_bmcr = bmcr & ~BMCR_ANENABLE;
1324                 new_bmcr |= BMCR_SPEED1000;
1325
1326                 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1327                         if (bp->req_line_speed == SPEED_2500)
1328                                 bnx2_enable_forced_2g5(bp);
1329                         else if (bp->req_line_speed == SPEED_1000) {
1330                                 bnx2_disable_forced_2g5(bp);
1331                                 new_bmcr &= ~0x2000;
1332                         }
1333
1334                 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1335                         if (bp->req_line_speed == SPEED_2500)
1336                                 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1337                         else
1338                                 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1339                 }
1340
1341                 if (bp->req_duplex == DUPLEX_FULL) {
1342                         adv |= ADVERTISE_1000XFULL;
1343                         new_bmcr |= BMCR_FULLDPLX;
1344                 }
1345                 else {
1346                         adv |= ADVERTISE_1000XHALF;
1347                         new_bmcr &= ~BMCR_FULLDPLX;
1348                 }
1349                 if ((new_bmcr != bmcr) || (force_link_down)) {
1350                         /* Force a link down visible on the other side */
1351                         if (bp->link_up) {
1352                                 bnx2_write_phy(bp, bp->mii_adv, adv &
1353                                                ~(ADVERTISE_1000XFULL |
1354                                                  ADVERTISE_1000XHALF));
1355                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1356                                         BMCR_ANRESTART | BMCR_ANENABLE);
1357
1358                                 bp->link_up = 0;
1359                                 netif_carrier_off(bp->dev);
1360                                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1361                                 bnx2_report_link(bp);
1362                         }
1363                         bnx2_write_phy(bp, bp->mii_adv, adv);
1364                         bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1365                 } else {
1366                         bnx2_resolve_flow_ctrl(bp);
1367                         bnx2_set_mac_link(bp);
1368                 }
1369                 return 0;
1370         }
1371
1372         bnx2_test_and_enable_2g5(bp);
1373
1374         if (bp->advertising & ADVERTISED_1000baseT_Full)
1375                 new_adv |= ADVERTISE_1000XFULL;
1376
1377         new_adv |= bnx2_phy_get_pause_adv(bp);
1378
1379         bnx2_read_phy(bp, bp->mii_adv, &adv);
1380         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1381
1382         bp->serdes_an_pending = 0;
1383         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1384                 /* Force a link down visible on the other side */
1385                 if (bp->link_up) {
1386                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1387                         spin_unlock_bh(&bp->phy_lock);
1388                         msleep(20);
1389                         spin_lock_bh(&bp->phy_lock);
1390                 }
1391
1392                 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1393                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1394                         BMCR_ANENABLE);
1395                 /* Speed up link-up time when the link partner
1396                  * does not autonegotiate which is very common
1397                  * in blade servers. Some blade servers use
1398                  * IPMI for kerboard input and it's important
1399                  * to minimize link disruptions. Autoneg. involves
1400                  * exchanging base pages plus 3 next pages and
1401                  * normally completes in about 120 msec.
1402                  */
1403                 bp->current_interval = SERDES_AN_TIMEOUT;
1404                 bp->serdes_an_pending = 1;
1405                 mod_timer(&bp->timer, jiffies + bp->current_interval);
1406         } else {
1407                 bnx2_resolve_flow_ctrl(bp);
1408                 bnx2_set_mac_link(bp);
1409         }
1410
1411         return 0;
1412 }
1413
1414 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1415         (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) ?                       \
1416                 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1417                 (ADVERTISED_1000baseT_Full)
1418
1419 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1420         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1421         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1422         ADVERTISED_1000baseT_Full)
1423
1424 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1425         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1426
1427 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1428
1429 static void
1430 bnx2_set_default_remote_link(struct bnx2 *bp)
1431 {
1432         u32 link;
1433
1434         if (bp->phy_port == PORT_TP)
1435                 link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_COPPER_LINK);
1436         else
1437                 link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_SERDES_LINK);
1438
1439         if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1440                 bp->req_line_speed = 0;
1441                 bp->autoneg |= AUTONEG_SPEED;
1442                 bp->advertising = ADVERTISED_Autoneg;
1443                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1444                         bp->advertising |= ADVERTISED_10baseT_Half;
1445                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1446                         bp->advertising |= ADVERTISED_10baseT_Full;
1447                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1448                         bp->advertising |= ADVERTISED_100baseT_Half;
1449                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1450                         bp->advertising |= ADVERTISED_100baseT_Full;
1451                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1452                         bp->advertising |= ADVERTISED_1000baseT_Full;
1453                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1454                         bp->advertising |= ADVERTISED_2500baseX_Full;
1455         } else {
1456                 bp->autoneg = 0;
1457                 bp->advertising = 0;
1458                 bp->req_duplex = DUPLEX_FULL;
1459                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1460                         bp->req_line_speed = SPEED_10;
1461                         if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1462                                 bp->req_duplex = DUPLEX_HALF;
1463                 }
1464                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1465                         bp->req_line_speed = SPEED_100;
1466                         if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1467                                 bp->req_duplex = DUPLEX_HALF;
1468                 }
1469                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1470                         bp->req_line_speed = SPEED_1000;
1471                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1472                         bp->req_line_speed = SPEED_2500;
1473         }
1474 }
1475
1476 static void
1477 bnx2_set_default_link(struct bnx2 *bp)
1478 {
1479         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1480                 return bnx2_set_default_remote_link(bp);
1481
1482         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1483         bp->req_line_speed = 0;
1484         if (bp->phy_flags & PHY_SERDES_FLAG) {
1485                 u32 reg;
1486
1487                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1488
1489                 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
1490                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1491                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1492                         bp->autoneg = 0;
1493                         bp->req_line_speed = bp->line_speed = SPEED_1000;
1494                         bp->req_duplex = DUPLEX_FULL;
1495                 }
1496         } else
1497                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1498 }
1499
1500 static void
1501 bnx2_send_heart_beat(struct bnx2 *bp)
1502 {
1503         u32 msg;
1504         u32 addr;
1505
1506         spin_lock(&bp->indirect_lock);
1507         msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1508         addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1509         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1510         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1511         spin_unlock(&bp->indirect_lock);
1512 }
1513
1514 static void
1515 bnx2_remote_phy_event(struct bnx2 *bp)
1516 {
1517         u32 msg;
1518         u8 link_up = bp->link_up;
1519         u8 old_port;
1520
1521         msg = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
1522
1523         if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1524                 bnx2_send_heart_beat(bp);
1525
1526         msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1527
1528         if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1529                 bp->link_up = 0;
1530         else {
1531                 u32 speed;
1532
1533                 bp->link_up = 1;
1534                 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1535                 bp->duplex = DUPLEX_FULL;
1536                 switch (speed) {
1537                         case BNX2_LINK_STATUS_10HALF:
1538                                 bp->duplex = DUPLEX_HALF;
1539                         case BNX2_LINK_STATUS_10FULL:
1540                                 bp->line_speed = SPEED_10;
1541                                 break;
1542                         case BNX2_LINK_STATUS_100HALF:
1543                                 bp->duplex = DUPLEX_HALF;
1544                         case BNX2_LINK_STATUS_100BASE_T4:
1545                         case BNX2_LINK_STATUS_100FULL:
1546                                 bp->line_speed = SPEED_100;
1547                                 break;
1548                         case BNX2_LINK_STATUS_1000HALF:
1549                                 bp->duplex = DUPLEX_HALF;
1550                         case BNX2_LINK_STATUS_1000FULL:
1551                                 bp->line_speed = SPEED_1000;
1552                                 break;
1553                         case BNX2_LINK_STATUS_2500HALF:
1554                                 bp->duplex = DUPLEX_HALF;
1555                         case BNX2_LINK_STATUS_2500FULL:
1556                                 bp->line_speed = SPEED_2500;
1557                                 break;
1558                         default:
1559                                 bp->line_speed = 0;
1560                                 break;
1561                 }
1562
1563                 spin_lock(&bp->phy_lock);
1564                 bp->flow_ctrl = 0;
1565                 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1566                     (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1567                         if (bp->duplex == DUPLEX_FULL)
1568                                 bp->flow_ctrl = bp->req_flow_ctrl;
1569                 } else {
1570                         if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1571                                 bp->flow_ctrl |= FLOW_CTRL_TX;
1572                         if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1573                                 bp->flow_ctrl |= FLOW_CTRL_RX;
1574                 }
1575
1576                 old_port = bp->phy_port;
1577                 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1578                         bp->phy_port = PORT_FIBRE;
1579                 else
1580                         bp->phy_port = PORT_TP;
1581
1582                 if (old_port != bp->phy_port)
1583                         bnx2_set_default_link(bp);
1584
1585                 spin_unlock(&bp->phy_lock);
1586         }
1587         if (bp->link_up != link_up)
1588                 bnx2_report_link(bp);
1589
1590         bnx2_set_mac_link(bp);
1591 }
1592
1593 static int
1594 bnx2_set_remote_link(struct bnx2 *bp)
1595 {
1596         u32 evt_code;
1597
1598         evt_code = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_EVT_CODE_MB);
1599         switch (evt_code) {
1600                 case BNX2_FW_EVT_CODE_LINK_EVENT:
1601                         bnx2_remote_phy_event(bp);
1602                         break;
1603                 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1604                 default:
1605                         bnx2_send_heart_beat(bp);
1606                         break;
1607         }
1608         return 0;
1609 }
1610
1611 static int
1612 bnx2_setup_copper_phy(struct bnx2 *bp)
1613 {
1614         u32 bmcr;
1615         u32 new_bmcr;
1616
1617         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1618
1619         if (bp->autoneg & AUTONEG_SPEED) {
1620                 u32 adv_reg, adv1000_reg;
1621                 u32 new_adv_reg = 0;
1622                 u32 new_adv1000_reg = 0;
1623
1624                 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1625                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1626                         ADVERTISE_PAUSE_ASYM);
1627
1628                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1629                 adv1000_reg &= PHY_ALL_1000_SPEED;
1630
1631                 if (bp->advertising & ADVERTISED_10baseT_Half)
1632                         new_adv_reg |= ADVERTISE_10HALF;
1633                 if (bp->advertising & ADVERTISED_10baseT_Full)
1634                         new_adv_reg |= ADVERTISE_10FULL;
1635                 if (bp->advertising & ADVERTISED_100baseT_Half)
1636                         new_adv_reg |= ADVERTISE_100HALF;
1637                 if (bp->advertising & ADVERTISED_100baseT_Full)
1638                         new_adv_reg |= ADVERTISE_100FULL;
1639                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1640                         new_adv1000_reg |= ADVERTISE_1000FULL;
1641
1642                 new_adv_reg |= ADVERTISE_CSMA;
1643
1644                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1645
1646                 if ((adv1000_reg != new_adv1000_reg) ||
1647                         (adv_reg != new_adv_reg) ||
1648                         ((bmcr & BMCR_ANENABLE) == 0)) {
1649
1650                         bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1651                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1652                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1653                                 BMCR_ANENABLE);
1654                 }
1655                 else if (bp->link_up) {
1656                         /* Flow ctrl may have changed from auto to forced */
1657                         /* or vice-versa. */
1658
1659                         bnx2_resolve_flow_ctrl(bp);
1660                         bnx2_set_mac_link(bp);
1661                 }
1662                 return 0;
1663         }
1664
1665         new_bmcr = 0;
1666         if (bp->req_line_speed == SPEED_100) {
1667                 new_bmcr |= BMCR_SPEED100;
1668         }
1669         if (bp->req_duplex == DUPLEX_FULL) {
1670                 new_bmcr |= BMCR_FULLDPLX;
1671         }
1672         if (new_bmcr != bmcr) {
1673                 u32 bmsr;
1674
1675                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1676                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1677
1678                 if (bmsr & BMSR_LSTATUS) {
1679                         /* Force link down */
1680                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1681                         spin_unlock_bh(&bp->phy_lock);
1682                         msleep(50);
1683                         spin_lock_bh(&bp->phy_lock);
1684
1685                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1686                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1687                 }
1688
1689                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1690
1691                 /* Normally, the new speed is setup after the link has
1692                  * gone down and up again. In some cases, link will not go
1693                  * down so we need to set up the new speed here.
1694                  */
1695                 if (bmsr & BMSR_LSTATUS) {
1696                         bp->line_speed = bp->req_line_speed;
1697                         bp->duplex = bp->req_duplex;
1698                         bnx2_resolve_flow_ctrl(bp);
1699                         bnx2_set_mac_link(bp);
1700                 }
1701         } else {
1702                 bnx2_resolve_flow_ctrl(bp);
1703                 bnx2_set_mac_link(bp);
1704         }
1705         return 0;
1706 }
1707
1708 static int
1709 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1710 {
1711         if (bp->loopback == MAC_LOOPBACK)
1712                 return 0;
1713
1714         if (bp->phy_flags & PHY_SERDES_FLAG) {
1715                 return (bnx2_setup_serdes_phy(bp, port));
1716         }
1717         else {
1718                 return (bnx2_setup_copper_phy(bp));
1719         }
1720 }
1721
1722 static int
1723 bnx2_init_5709s_phy(struct bnx2 *bp)
1724 {
1725         u32 val;
1726
1727         bp->mii_bmcr = MII_BMCR + 0x10;
1728         bp->mii_bmsr = MII_BMSR + 0x10;
1729         bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1730         bp->mii_adv = MII_ADVERTISE + 0x10;
1731         bp->mii_lpa = MII_LPA + 0x10;
1732         bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1733
1734         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1735         bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1736
1737         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1738         bnx2_reset_phy(bp);
1739
1740         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1741
1742         bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1743         val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1744         val |= MII_BNX2_SD_1000XCTL1_FIBER;
1745         bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1746
1747         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1748         bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
1749         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
1750                 val |= BCM5708S_UP1_2G5;
1751         else
1752                 val &= ~BCM5708S_UP1_2G5;
1753         bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1754
1755         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1756         bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1757         val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1758         bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1759
1760         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1761
1762         val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1763               MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1764         bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1765
1766         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1767
1768         return 0;
1769 }
1770
1771 static int
1772 bnx2_init_5708s_phy(struct bnx2 *bp)
1773 {
1774         u32 val;
1775
1776         bnx2_reset_phy(bp);
1777
1778         bp->mii_up1 = BCM5708S_UP1;
1779
1780         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1781         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1782         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1783
1784         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1785         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1786         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1787
1788         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1789         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1790         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1791
1792         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1793                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1794                 val |= BCM5708S_UP1_2G5;
1795                 bnx2_write_phy(bp, BCM5708S_UP1, val);
1796         }
1797
1798         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1799             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1800             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1801                 /* increase tx signal amplitude */
1802                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1803                                BCM5708S_BLK_ADDR_TX_MISC);
1804                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1805                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1806                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1807                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1808         }
1809
1810         val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1811               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1812
1813         if (val) {
1814                 u32 is_backplane;
1815
1816                 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1817                                           BNX2_SHARED_HW_CFG_CONFIG);
1818                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1819                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1820                                        BCM5708S_BLK_ADDR_TX_MISC);
1821                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1822                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1823                                        BCM5708S_BLK_ADDR_DIG);
1824                 }
1825         }
1826         return 0;
1827 }
1828
1829 static int
1830 bnx2_init_5706s_phy(struct bnx2 *bp)
1831 {
1832         bnx2_reset_phy(bp);
1833
1834         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1835
1836         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1837                 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
1838
1839         if (bp->dev->mtu > 1500) {
1840                 u32 val;
1841
1842                 /* Set extended packet length bit */
1843                 bnx2_write_phy(bp, 0x18, 0x7);
1844                 bnx2_read_phy(bp, 0x18, &val);
1845                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1846
1847                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1848                 bnx2_read_phy(bp, 0x1c, &val);
1849                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1850         }
1851         else {
1852                 u32 val;
1853
1854                 bnx2_write_phy(bp, 0x18, 0x7);
1855                 bnx2_read_phy(bp, 0x18, &val);
1856                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1857
1858                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1859                 bnx2_read_phy(bp, 0x1c, &val);
1860                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1861         }
1862
1863         return 0;
1864 }
1865
1866 static int
1867 bnx2_init_copper_phy(struct bnx2 *bp)
1868 {
1869         u32 val;
1870
1871         bnx2_reset_phy(bp);
1872
1873         if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1874                 bnx2_write_phy(bp, 0x18, 0x0c00);
1875                 bnx2_write_phy(bp, 0x17, 0x000a);
1876                 bnx2_write_phy(bp, 0x15, 0x310b);
1877                 bnx2_write_phy(bp, 0x17, 0x201f);
1878                 bnx2_write_phy(bp, 0x15, 0x9506);
1879                 bnx2_write_phy(bp, 0x17, 0x401f);
1880                 bnx2_write_phy(bp, 0x15, 0x14e2);
1881                 bnx2_write_phy(bp, 0x18, 0x0400);
1882         }
1883
1884         if (bp->phy_flags & PHY_DIS_EARLY_DAC_FLAG) {
1885                 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
1886                                MII_BNX2_DSP_EXPAND_REG | 0x8);
1887                 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1888                 val &= ~(1 << 8);
1889                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
1890         }
1891
1892         if (bp->dev->mtu > 1500) {
1893                 /* Set extended packet length bit */
1894                 bnx2_write_phy(bp, 0x18, 0x7);
1895                 bnx2_read_phy(bp, 0x18, &val);
1896                 bnx2_write_phy(bp, 0x18, val | 0x4000);
1897
1898                 bnx2_read_phy(bp, 0x10, &val);
1899                 bnx2_write_phy(bp, 0x10, val | 0x1);
1900         }
1901         else {
1902                 bnx2_write_phy(bp, 0x18, 0x7);
1903                 bnx2_read_phy(bp, 0x18, &val);
1904                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1905
1906                 bnx2_read_phy(bp, 0x10, &val);
1907                 bnx2_write_phy(bp, 0x10, val & ~0x1);
1908         }
1909
1910         /* ethernet@wirespeed */
1911         bnx2_write_phy(bp, 0x18, 0x7007);
1912         bnx2_read_phy(bp, 0x18, &val);
1913         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1914         return 0;
1915 }
1916
1917
1918 static int
1919 bnx2_init_phy(struct bnx2 *bp)
1920 {
1921         u32 val;
1922         int rc = 0;
1923
1924         bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1925         bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1926
1927         bp->mii_bmcr = MII_BMCR;
1928         bp->mii_bmsr = MII_BMSR;
1929         bp->mii_bmsr1 = MII_BMSR;
1930         bp->mii_adv = MII_ADVERTISE;
1931         bp->mii_lpa = MII_LPA;
1932
1933         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1934
1935         if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1936                 goto setup_phy;
1937
1938         bnx2_read_phy(bp, MII_PHYSID1, &val);
1939         bp->phy_id = val << 16;
1940         bnx2_read_phy(bp, MII_PHYSID2, &val);
1941         bp->phy_id |= val & 0xffff;
1942
1943         if (bp->phy_flags & PHY_SERDES_FLAG) {
1944                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1945                         rc = bnx2_init_5706s_phy(bp);
1946                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1947                         rc = bnx2_init_5708s_phy(bp);
1948                 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1949                         rc = bnx2_init_5709s_phy(bp);
1950         }
1951         else {
1952                 rc = bnx2_init_copper_phy(bp);
1953         }
1954
1955 setup_phy:
1956         if (!rc)
1957                 rc = bnx2_setup_phy(bp, bp->phy_port);
1958
1959         return rc;
1960 }
1961
1962 static int
1963 bnx2_set_mac_loopback(struct bnx2 *bp)
1964 {
1965         u32 mac_mode;
1966
1967         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1968         mac_mode &= ~BNX2_EMAC_MODE_PORT;
1969         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1970         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1971         bp->link_up = 1;
1972         return 0;
1973 }
1974
1975 static int bnx2_test_link(struct bnx2 *);
1976
1977 static int
1978 bnx2_set_phy_loopback(struct bnx2 *bp)
1979 {
1980         u32 mac_mode;
1981         int rc, i;
1982
1983         spin_lock_bh(&bp->phy_lock);
1984         rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
1985                             BMCR_SPEED1000);
1986         spin_unlock_bh(&bp->phy_lock);
1987         if (rc)
1988                 return rc;
1989
1990         for (i = 0; i < 10; i++) {
1991                 if (bnx2_test_link(bp) == 0)
1992                         break;
1993                 msleep(100);
1994         }
1995
1996         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1997         mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1998                       BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1999                       BNX2_EMAC_MODE_25G_MODE);
2000
2001         mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2002         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2003         bp->link_up = 1;
2004         return 0;
2005 }
2006
2007 static int
2008 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
2009 {
2010         int i;
2011         u32 val;
2012
2013         bp->fw_wr_seq++;
2014         msg_data |= bp->fw_wr_seq;
2015
2016         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
2017
2018         /* wait for an acknowledgement. */
2019         for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2020                 msleep(10);
2021
2022                 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
2023
2024                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2025                         break;
2026         }
2027         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2028                 return 0;
2029
2030         /* If we timed out, inform the firmware that this is the case. */
2031         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2032                 if (!silent)
2033                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
2034                                             "%x\n", msg_data);
2035
2036                 msg_data &= ~BNX2_DRV_MSG_CODE;
2037                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2038
2039                 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
2040
2041                 return -EBUSY;
2042         }
2043
2044         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2045                 return -EIO;
2046
2047         return 0;
2048 }
2049
2050 static int
2051 bnx2_init_5709_context(struct bnx2 *bp)
2052 {
2053         int i, ret = 0;
2054         u32 val;
2055
2056         val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2057         val |= (BCM_PAGE_BITS - 8) << 16;
2058         REG_WR(bp, BNX2_CTX_COMMAND, val);
2059         for (i = 0; i < 10; i++) {
2060                 val = REG_RD(bp, BNX2_CTX_COMMAND);
2061                 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2062                         break;
2063                 udelay(2);
2064         }
2065         if (val & BNX2_CTX_COMMAND_MEM_INIT)
2066                 return -EBUSY;
2067
2068         for (i = 0; i < bp->ctx_pages; i++) {
2069                 int j;
2070
2071                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2072                        (bp->ctx_blk_mapping[i] & 0xffffffff) |
2073                        BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2074                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2075                        (u64) bp->ctx_blk_mapping[i] >> 32);
2076                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2077                        BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2078                 for (j = 0; j < 10; j++) {
2079
2080                         val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2081                         if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2082                                 break;
2083                         udelay(5);
2084                 }
2085                 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2086                         ret = -EBUSY;
2087                         break;
2088                 }
2089         }
2090         return ret;
2091 }
2092
2093 static void
2094 bnx2_init_context(struct bnx2 *bp)
2095 {
2096         u32 vcid;
2097
2098         vcid = 96;
2099         while (vcid) {
2100                 u32 vcid_addr, pcid_addr, offset;
2101                 int i;
2102
2103                 vcid--;
2104
2105                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2106                         u32 new_vcid;
2107
2108                         vcid_addr = GET_PCID_ADDR(vcid);
2109                         if (vcid & 0x8) {
2110                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2111                         }
2112                         else {
2113                                 new_vcid = vcid;
2114                         }
2115                         pcid_addr = GET_PCID_ADDR(new_vcid);
2116                 }
2117                 else {
2118                         vcid_addr = GET_CID_ADDR(vcid);
2119                         pcid_addr = vcid_addr;
2120                 }
2121
2122                 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2123                         vcid_addr += (i << PHY_CTX_SHIFT);
2124                         pcid_addr += (i << PHY_CTX_SHIFT);
2125
2126                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
2127                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2128
2129                         /* Zero out the context. */
2130                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2131                                 CTX_WR(bp, 0x00, offset, 0);
2132
2133                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2134                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2135                 }
2136         }
2137 }
2138
2139 static int
2140 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2141 {
2142         u16 *good_mbuf;
2143         u32 good_mbuf_cnt;
2144         u32 val;
2145
2146         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2147         if (good_mbuf == NULL) {
2148                 printk(KERN_ERR PFX "Failed to allocate memory in "
2149                                     "bnx2_alloc_bad_rbuf\n");
2150                 return -ENOMEM;
2151         }
2152
2153         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2154                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2155
2156         good_mbuf_cnt = 0;
2157
2158         /* Allocate a bunch of mbufs and save the good ones in an array. */
2159         val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
2160         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2161                 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
2162
2163                 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
2164
2165                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2166
2167                 /* The addresses with Bit 9 set are bad memory blocks. */
2168                 if (!(val & (1 << 9))) {
2169                         good_mbuf[good_mbuf_cnt] = (u16) val;
2170                         good_mbuf_cnt++;
2171                 }
2172
2173                 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
2174         }
2175
2176         /* Free the good ones back to the mbuf pool thus discarding
2177          * all the bad ones. */
2178         while (good_mbuf_cnt) {
2179                 good_mbuf_cnt--;
2180
2181                 val = good_mbuf[good_mbuf_cnt];
2182                 val = (val << 9) | val | 1;
2183
2184                 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
2185         }
2186         kfree(good_mbuf);
2187         return 0;
2188 }
2189
2190 static void
2191 bnx2_set_mac_addr(struct bnx2 *bp)
2192 {
2193         u32 val;
2194         u8 *mac_addr = bp->dev->dev_addr;
2195
2196         val = (mac_addr[0] << 8) | mac_addr[1];
2197
2198         REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
2199
2200         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2201                 (mac_addr[4] << 8) | mac_addr[5];
2202
2203         REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
2204 }
2205
2206 static inline int
2207 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
2208 {
2209         struct sk_buff *skb;
2210         struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
2211         dma_addr_t mapping;
2212         struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2213         unsigned long align;
2214
2215         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2216         if (skb == NULL) {
2217                 return -ENOMEM;
2218         }
2219
2220         if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2221                 skb_reserve(skb, BNX2_RX_ALIGN - align);
2222
2223         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2224                 PCI_DMA_FROMDEVICE);
2225
2226         rx_buf->skb = skb;
2227         pci_unmap_addr_set(rx_buf, mapping, mapping);
2228
2229         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2230         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2231
2232         bp->rx_prod_bseq += bp->rx_buf_use_size;
2233
2234         return 0;
2235 }
2236
2237 static int
2238 bnx2_phy_event_is_set(struct bnx2 *bp, u32 event)
2239 {
2240         struct status_block *sblk = bp->status_blk;
2241         u32 new_link_state, old_link_state;
2242         int is_set = 1;
2243
2244         new_link_state = sblk->status_attn_bits & event;
2245         old_link_state = sblk->status_attn_bits_ack & event;
2246         if (new_link_state != old_link_state) {
2247                 if (new_link_state)
2248                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2249                 else
2250                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2251         } else
2252                 is_set = 0;
2253
2254         return is_set;
2255 }
2256
2257 static void
2258 bnx2_phy_int(struct bnx2 *bp)
2259 {
2260         if (bnx2_phy_event_is_set(bp, STATUS_ATTN_BITS_LINK_STATE)) {
2261                 spin_lock(&bp->phy_lock);
2262                 bnx2_set_link(bp);
2263                 spin_unlock(&bp->phy_lock);
2264         }
2265         if (bnx2_phy_event_is_set(bp, STATUS_ATTN_BITS_TIMER_ABORT))
2266                 bnx2_set_remote_link(bp);
2267
2268 }
2269
2270 static void
2271 bnx2_tx_int(struct bnx2 *bp)
2272 {
2273         struct status_block *sblk = bp->status_blk;
2274         u16 hw_cons, sw_cons, sw_ring_cons;
2275         int tx_free_bd = 0;
2276
2277         hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
2278         if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2279                 hw_cons++;
2280         }
2281         sw_cons = bp->tx_cons;
2282
2283         while (sw_cons != hw_cons) {
2284                 struct sw_bd *tx_buf;
2285                 struct sk_buff *skb;
2286                 int i, last;
2287
2288                 sw_ring_cons = TX_RING_IDX(sw_cons);
2289
2290                 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2291                 skb = tx_buf->skb;
2292
2293                 /* partial BD completions possible with TSO packets */
2294                 if (skb_is_gso(skb)) {
2295                         u16 last_idx, last_ring_idx;
2296
2297                         last_idx = sw_cons +
2298                                 skb_shinfo(skb)->nr_frags + 1;
2299                         last_ring_idx = sw_ring_cons +
2300                                 skb_shinfo(skb)->nr_frags + 1;
2301                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2302                                 last_idx++;
2303                         }
2304                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2305                                 break;
2306                         }
2307                 }
2308
2309                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2310                         skb_headlen(skb), PCI_DMA_TODEVICE);
2311
2312                 tx_buf->skb = NULL;
2313                 last = skb_shinfo(skb)->nr_frags;
2314
2315                 for (i = 0; i < last; i++) {
2316                         sw_cons = NEXT_TX_BD(sw_cons);
2317
2318                         pci_unmap_page(bp->pdev,
2319                                 pci_unmap_addr(
2320                                         &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2321                                         mapping),
2322                                 skb_shinfo(skb)->frags[i].size,
2323                                 PCI_DMA_TODEVICE);
2324                 }
2325
2326                 sw_cons = NEXT_TX_BD(sw_cons);
2327
2328                 tx_free_bd += last + 1;
2329
2330                 dev_kfree_skb(skb);
2331
2332                 hw_cons = bp->hw_tx_cons =
2333                         sblk->status_tx_quick_consumer_index0;
2334
2335                 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2336                         hw_cons++;
2337                 }
2338         }
2339
2340         bp->tx_cons = sw_cons;
2341         /* Need to make the tx_cons update visible to bnx2_start_xmit()
2342          * before checking for netif_queue_stopped().  Without the
2343          * memory barrier, there is a small possibility that bnx2_start_xmit()
2344          * will miss it and cause the queue to be stopped forever.
2345          */
2346         smp_mb();
2347
2348         if (unlikely(netif_queue_stopped(bp->dev)) &&
2349                      (bnx2_tx_avail(bp) > bp->tx_wake_thresh)) {
2350                 netif_tx_lock(bp->dev);
2351                 if ((netif_queue_stopped(bp->dev)) &&
2352                     (bnx2_tx_avail(bp) > bp->tx_wake_thresh))
2353                         netif_wake_queue(bp->dev);
2354                 netif_tx_unlock(bp->dev);
2355         }
2356 }
2357
2358 static inline void
2359 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
2360         u16 cons, u16 prod)
2361 {
2362         struct sw_bd *cons_rx_buf, *prod_rx_buf;
2363         struct rx_bd *cons_bd, *prod_bd;
2364
2365         cons_rx_buf = &bp->rx_buf_ring[cons];
2366         prod_rx_buf = &bp->rx_buf_ring[prod];
2367
2368         pci_dma_sync_single_for_device(bp->pdev,
2369                 pci_unmap_addr(cons_rx_buf, mapping),
2370                 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2371
2372         bp->rx_prod_bseq += bp->rx_buf_use_size;
2373
2374         prod_rx_buf->skb = skb;
2375
2376         if (cons == prod)
2377                 return;
2378
2379         pci_unmap_addr_set(prod_rx_buf, mapping,
2380                         pci_unmap_addr(cons_rx_buf, mapping));
2381
2382         cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2383         prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2384         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2385         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2386 }
2387
2388 static int
2389 bnx2_rx_int(struct bnx2 *bp, int budget)
2390 {
2391         struct status_block *sblk = bp->status_blk;
2392         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2393         struct l2_fhdr *rx_hdr;
2394         int rx_pkt = 0;
2395
2396         hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
2397         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
2398                 hw_cons++;
2399         }
2400         sw_cons = bp->rx_cons;
2401         sw_prod = bp->rx_prod;
2402
2403         /* Memory barrier necessary as speculative reads of the rx
2404          * buffer can be ahead of the index in the status block
2405          */
2406         rmb();
2407         while (sw_cons != hw_cons) {
2408                 unsigned int len;
2409                 u32 status;
2410                 struct sw_bd *rx_buf;
2411                 struct sk_buff *skb;
2412                 dma_addr_t dma_addr;
2413
2414                 sw_ring_cons = RX_RING_IDX(sw_cons);
2415                 sw_ring_prod = RX_RING_IDX(sw_prod);
2416
2417                 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2418                 skb = rx_buf->skb;
2419
2420                 rx_buf->skb = NULL;
2421
2422                 dma_addr = pci_unmap_addr(rx_buf, mapping);
2423
2424                 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2425                         bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2426
2427                 rx_hdr = (struct l2_fhdr *) skb->data;
2428                 len = rx_hdr->l2_fhdr_pkt_len - 4;
2429
2430                 if ((status = rx_hdr->l2_fhdr_status) &
2431                         (L2_FHDR_ERRORS_BAD_CRC |
2432                         L2_FHDR_ERRORS_PHY_DECODE |
2433                         L2_FHDR_ERRORS_ALIGNMENT |
2434                         L2_FHDR_ERRORS_TOO_SHORT |
2435                         L2_FHDR_ERRORS_GIANT_FRAME)) {
2436
2437                         goto reuse_rx;
2438                 }
2439
2440                 /* Since we don't have a jumbo ring, copy small packets
2441                  * if mtu > 1500
2442                  */
2443                 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
2444                         struct sk_buff *new_skb;
2445
2446                         new_skb = netdev_alloc_skb(bp->dev, len + 2);
2447                         if (new_skb == NULL)
2448                                 goto reuse_rx;
2449
2450                         /* aligned copy */
2451                         skb_copy_from_linear_data_offset(skb, bp->rx_offset - 2,
2452                                       new_skb->data, len + 2);
2453                         skb_reserve(new_skb, 2);
2454                         skb_put(new_skb, len);
2455
2456                         bnx2_reuse_rx_skb(bp, skb,
2457                                 sw_ring_cons, sw_ring_prod);
2458
2459                         skb = new_skb;
2460                 }
2461                 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
2462                         pci_unmap_single(bp->pdev, dma_addr,
2463                                 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
2464
2465                         skb_reserve(skb, bp->rx_offset);
2466                         skb_put(skb, len);
2467                 }
2468                 else {
2469 reuse_rx:
2470                         bnx2_reuse_rx_skb(bp, skb,
2471                                 sw_ring_cons, sw_ring_prod);
2472                         goto next_rx;
2473                 }
2474
2475                 skb->protocol = eth_type_trans(skb, bp->dev);
2476
2477                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2478                         (ntohs(skb->protocol) != 0x8100)) {
2479
2480                         dev_kfree_skb(skb);
2481                         goto next_rx;
2482
2483                 }
2484
2485                 skb->ip_summed = CHECKSUM_NONE;
2486                 if (bp->rx_csum &&
2487                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2488                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
2489
2490                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2491                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2492                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2493                 }
2494
2495 #ifdef BCM_VLAN
2496                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
2497                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2498                                 rx_hdr->l2_fhdr_vlan_tag);
2499                 }
2500                 else
2501 #endif
2502                         netif_receive_skb(skb);
2503
2504                 bp->dev->last_rx = jiffies;
2505                 rx_pkt++;
2506
2507 next_rx:
2508                 sw_cons = NEXT_RX_BD(sw_cons);
2509                 sw_prod = NEXT_RX_BD(sw_prod);
2510
2511                 if ((rx_pkt == budget))
2512                         break;
2513
2514                 /* Refresh hw_cons to see if there is new work */
2515                 if (sw_cons == hw_cons) {
2516                         hw_cons = bp->hw_rx_cons =
2517                                 sblk->status_rx_quick_consumer_index0;
2518                         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
2519                                 hw_cons++;
2520                         rmb();
2521                 }
2522         }
2523         bp->rx_cons = sw_cons;
2524         bp->rx_prod = sw_prod;
2525
2526         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2527
2528         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2529
2530         mmiowb();
2531
2532         return rx_pkt;
2533
2534 }
2535
2536 /* MSI ISR - The only difference between this and the INTx ISR
2537  * is that the MSI interrupt is always serviced.
2538  */
2539 static irqreturn_t
2540 bnx2_msi(int irq, void *dev_instance)
2541 {
2542         struct net_device *dev = dev_instance;
2543         struct bnx2 *bp = netdev_priv(dev);
2544
2545         prefetch(bp->status_blk);
2546         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2547                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2548                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2549
2550         /* Return here if interrupt is disabled. */
2551         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2552                 return IRQ_HANDLED;
2553
2554         netif_rx_schedule(dev, &bp->napi);
2555
2556         return IRQ_HANDLED;
2557 }
2558
2559 static irqreturn_t
2560 bnx2_msi_1shot(int irq, void *dev_instance)
2561 {
2562         struct net_device *dev = dev_instance;
2563         struct bnx2 *bp = netdev_priv(dev);
2564
2565         prefetch(bp->status_blk);
2566
2567         /* Return here if interrupt is disabled. */
2568         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2569                 return IRQ_HANDLED;
2570
2571         netif_rx_schedule(dev, &bp->napi);
2572
2573         return IRQ_HANDLED;
2574 }
2575
2576 static irqreturn_t
2577 bnx2_interrupt(int irq, void *dev_instance)
2578 {
2579         struct net_device *dev = dev_instance;
2580         struct bnx2 *bp = netdev_priv(dev);
2581         struct status_block *sblk = bp->status_blk;
2582
2583         /* When using INTx, it is possible for the interrupt to arrive
2584          * at the CPU before the status block posted prior to the
2585          * interrupt. Reading a register will flush the status block.
2586          * When using MSI, the MSI message will always complete after
2587          * the status block write.
2588          */
2589         if ((sblk->status_idx == bp->last_status_idx) &&
2590             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2591              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
2592                 return IRQ_NONE;
2593
2594         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2595                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2596                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2597
2598         /* Read back to deassert IRQ immediately to avoid too many
2599          * spurious interrupts.
2600          */
2601         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
2602
2603         /* Return here if interrupt is shared and is disabled. */
2604         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2605                 return IRQ_HANDLED;
2606
2607         if (netif_rx_schedule_prep(dev, &bp->napi)) {
2608                 bp->last_status_idx = sblk->status_idx;
2609                 __netif_rx_schedule(dev, &bp->napi);
2610         }
2611
2612         return IRQ_HANDLED;
2613 }
2614
2615 #define STATUS_ATTN_EVENTS      (STATUS_ATTN_BITS_LINK_STATE | \
2616                                  STATUS_ATTN_BITS_TIMER_ABORT)
2617
2618 static inline int
2619 bnx2_has_work(struct bnx2 *bp)
2620 {
2621         struct status_block *sblk = bp->status_blk;
2622
2623         if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
2624             (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
2625                 return 1;
2626
2627         if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
2628             (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
2629                 return 1;
2630
2631         return 0;
2632 }
2633
2634 static int
2635 bnx2_poll(struct napi_struct *napi, int budget)
2636 {
2637         struct bnx2 *bp = container_of(napi, struct bnx2, napi);
2638         struct net_device *dev = bp->dev;
2639         struct status_block *sblk = bp->status_blk;
2640         u32 status_attn_bits = sblk->status_attn_bits;
2641         u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
2642         int work_done = 0;
2643
2644         if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
2645             (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
2646
2647                 bnx2_phy_int(bp);
2648
2649                 /* This is needed to take care of transient status
2650                  * during link changes.
2651                  */
2652                 REG_WR(bp, BNX2_HC_COMMAND,
2653                        bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2654                 REG_RD(bp, BNX2_HC_COMMAND);
2655         }
2656
2657         if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
2658                 bnx2_tx_int(bp);
2659
2660         if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons)
2661                 work_done = bnx2_rx_int(bp, budget);
2662
2663         bp->last_status_idx = bp->status_blk->status_idx;
2664         rmb();
2665
2666         if (!bnx2_has_work(bp)) {
2667                 netif_rx_complete(dev, napi);
2668                 if (likely(bp->flags & USING_MSI_FLAG)) {
2669                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2670                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2671                                bp->last_status_idx);
2672                         return 0;
2673                 }
2674                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2675                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2676                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2677                        bp->last_status_idx);
2678
2679                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2680                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2681                        bp->last_status_idx);
2682         }
2683
2684         return work_done;
2685 }
2686
2687 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
2688  * from set_multicast.
2689  */
2690 static void
2691 bnx2_set_rx_mode(struct net_device *dev)
2692 {
2693         struct bnx2 *bp = netdev_priv(dev);
2694         u32 rx_mode, sort_mode;
2695         int i;
2696
2697         spin_lock_bh(&bp->phy_lock);
2698
2699         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
2700                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
2701         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
2702 #ifdef BCM_VLAN
2703         if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
2704                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2705 #else
2706         if (!(bp->flags & ASF_ENABLE_FLAG))
2707                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2708 #endif
2709         if (dev->flags & IFF_PROMISC) {
2710                 /* Promiscuous mode. */
2711                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
2712                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
2713                              BNX2_RPM_SORT_USER0_PROM_VLAN;
2714         }
2715         else if (dev->flags & IFF_ALLMULTI) {
2716                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2717                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2718                                0xffffffff);
2719                 }
2720                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
2721         }
2722         else {
2723                 /* Accept one or more multicast(s). */
2724                 struct dev_mc_list *mclist;
2725                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
2726                 u32 regidx;
2727                 u32 bit;
2728                 u32 crc;
2729
2730                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
2731
2732                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2733                      i++, mclist = mclist->next) {
2734
2735                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
2736                         bit = crc & 0xff;
2737                         regidx = (bit & 0xe0) >> 5;
2738                         bit &= 0x1f;
2739                         mc_filter[regidx] |= (1 << bit);
2740                 }
2741
2742                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2743                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2744                                mc_filter[i]);
2745                 }
2746
2747                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
2748         }
2749
2750         if (rx_mode != bp->rx_mode) {
2751                 bp->rx_mode = rx_mode;
2752                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
2753         }
2754
2755         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2756         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
2757         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
2758
2759         spin_unlock_bh(&bp->phy_lock);
2760 }
2761
2762 #define FW_BUF_SIZE     0x8000
2763
2764 static int
2765 bnx2_gunzip_init(struct bnx2 *bp)
2766 {
2767         if ((bp->gunzip_buf = vmalloc(FW_BUF_SIZE)) == NULL)
2768                 goto gunzip_nomem1;
2769
2770         if ((bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL)) == NULL)
2771                 goto gunzip_nomem2;
2772
2773         bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(), GFP_KERNEL);
2774         if (bp->strm->workspace == NULL)
2775                 goto gunzip_nomem3;
2776
2777         return 0;
2778
2779 gunzip_nomem3:
2780         kfree(bp->strm);
2781         bp->strm = NULL;
2782
2783 gunzip_nomem2:
2784         vfree(bp->gunzip_buf);
2785         bp->gunzip_buf = NULL;
2786
2787 gunzip_nomem1:
2788         printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for "
2789                             "uncompression.\n", bp->dev->name);
2790         return -ENOMEM;
2791 }
2792
2793 static void
2794 bnx2_gunzip_end(struct bnx2 *bp)
2795 {
2796         kfree(bp->strm->workspace);
2797
2798         kfree(bp->strm);
2799         bp->strm = NULL;
2800
2801         if (bp->gunzip_buf) {
2802                 vfree(bp->gunzip_buf);
2803                 bp->gunzip_buf = NULL;
2804         }
2805 }
2806
2807 static int
2808 bnx2_gunzip(struct bnx2 *bp, u8 *zbuf, int len, void **outbuf, int *outlen)
2809 {
2810         int n, rc;
2811
2812         /* check gzip header */
2813         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
2814                 return -EINVAL;
2815
2816         n = 10;
2817
2818 #define FNAME   0x8
2819         if (zbuf[3] & FNAME)
2820                 while ((zbuf[n++] != 0) && (n < len));
2821
2822         bp->strm->next_in = zbuf + n;
2823         bp->strm->avail_in = len - n;
2824         bp->strm->next_out = bp->gunzip_buf;
2825         bp->strm->avail_out = FW_BUF_SIZE;
2826
2827         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
2828         if (rc != Z_OK)
2829                 return rc;
2830
2831         rc = zlib_inflate(bp->strm, Z_FINISH);
2832
2833         *outlen = FW_BUF_SIZE - bp->strm->avail_out;
2834         *outbuf = bp->gunzip_buf;
2835
2836         if ((rc != Z_OK) && (rc != Z_STREAM_END))
2837                 printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
2838                        bp->dev->name, bp->strm->msg);
2839
2840         zlib_inflateEnd(bp->strm);
2841
2842         if (rc == Z_STREAM_END)
2843                 return 0;
2844
2845         return rc;
2846 }
2847
2848 static void
2849 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
2850         u32 rv2p_proc)
2851 {
2852         int i;
2853         u32 val;
2854
2855
2856         for (i = 0; i < rv2p_code_len; i += 8) {
2857                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code));
2858                 rv2p_code++;
2859                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code));
2860                 rv2p_code++;
2861
2862                 if (rv2p_proc == RV2P_PROC1) {
2863                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
2864                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
2865                 }
2866                 else {
2867                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
2868                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2869                 }
2870         }
2871
2872         /* Reset the processor, un-stall is done later. */
2873         if (rv2p_proc == RV2P_PROC1) {
2874                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2875         }
2876         else {
2877                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2878         }
2879 }
2880
2881 static int
2882 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2883 {
2884         u32 offset;
2885         u32 val;
2886         int rc;
2887
2888         /* Halt the CPU. */
2889         val = REG_RD_IND(bp, cpu_reg->mode);
2890         val |= cpu_reg->mode_value_halt;
2891         REG_WR_IND(bp, cpu_reg->mode, val);
2892         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2893
2894         /* Load the Text area. */
2895         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2896         if (fw->gz_text) {
2897                 u32 text_len;
2898                 void *text;
2899
2900                 rc = bnx2_gunzip(bp, fw->gz_text, fw->gz_text_len, &text,
2901                                  &text_len);
2902                 if (rc)
2903                         return rc;
2904
2905                 fw->text = text;
2906         }
2907         if (fw->gz_text) {
2908                 int j;
2909
2910                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2911                         REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j]));
2912                 }
2913         }
2914
2915         /* Load the Data area. */
2916         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2917         if (fw->data) {
2918                 int j;
2919
2920                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2921                         REG_WR_IND(bp, offset, fw->data[j]);
2922                 }
2923         }
2924
2925         /* Load the SBSS area. */
2926         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2927         if (fw->sbss) {
2928                 int j;
2929
2930                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2931                         REG_WR_IND(bp, offset, fw->sbss[j]);
2932                 }
2933         }
2934
2935         /* Load the BSS area. */
2936         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2937         if (fw->bss) {
2938                 int j;
2939
2940                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2941                         REG_WR_IND(bp, offset, fw->bss[j]);
2942                 }
2943         }
2944
2945         /* Load the Read-Only area. */
2946         offset = cpu_reg->spad_base +
2947                 (fw->rodata_addr - cpu_reg->mips_view_base);
2948         if (fw->rodata) {
2949                 int j;
2950
2951                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2952                         REG_WR_IND(bp, offset, fw->rodata[j]);
2953                 }
2954         }
2955
2956         /* Clear the pre-fetch instruction. */
2957         REG_WR_IND(bp, cpu_reg->inst, 0);
2958         REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2959
2960         /* Start the CPU. */
2961         val = REG_RD_IND(bp, cpu_reg->mode);
2962         val &= ~cpu_reg->mode_value_halt;
2963         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2964         REG_WR_IND(bp, cpu_reg->mode, val);
2965
2966         return 0;
2967 }
2968
2969 static int
2970 bnx2_init_cpus(struct bnx2 *bp)
2971 {
2972         struct cpu_reg cpu_reg;
2973         struct fw_info *fw;
2974         int rc = 0;
2975         void *text;
2976         u32 text_len;
2977
2978         if ((rc = bnx2_gunzip_init(bp)) != 0)
2979                 return rc;
2980
2981         /* Initialize the RV2P processor. */
2982         rc = bnx2_gunzip(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), &text,
2983                          &text_len);
2984         if (rc)
2985                 goto init_cpu_err;
2986
2987         load_rv2p_fw(bp, text, text_len, RV2P_PROC1);
2988
2989         rc = bnx2_gunzip(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), &text,
2990                          &text_len);
2991         if (rc)
2992                 goto init_cpu_err;
2993
2994         load_rv2p_fw(bp, text, text_len, RV2P_PROC2);
2995
2996         /* Initialize the RX Processor. */
2997         cpu_reg.mode = BNX2_RXP_CPU_MODE;
2998         cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2999         cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
3000         cpu_reg.state = BNX2_RXP_CPU_STATE;
3001         cpu_reg.state_value_clear = 0xffffff;
3002         cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
3003         cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
3004         cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
3005         cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
3006         cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
3007         cpu_reg.spad_base = BNX2_RXP_SCRATCH;
3008         cpu_reg.mips_view_base = 0x8000000;
3009
3010         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3011                 fw = &bnx2_rxp_fw_09;
3012         else
3013                 fw = &bnx2_rxp_fw_06;
3014
3015         rc = load_cpu_fw(bp, &cpu_reg, fw);
3016         if (rc)
3017                 goto init_cpu_err;
3018
3019         /* Initialize the TX Processor. */
3020         cpu_reg.mode = BNX2_TXP_CPU_MODE;
3021         cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
3022         cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
3023         cpu_reg.state = BNX2_TXP_CPU_STATE;
3024         cpu_reg.state_value_clear = 0xffffff;
3025         cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
3026         cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
3027         cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
3028         cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
3029         cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
3030         cpu_reg.spad_base = BNX2_TXP_SCRATCH;
3031         cpu_reg.mips_view_base = 0x8000000;
3032
3033         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3034                 fw = &bnx2_txp_fw_09;
3035         else
3036                 fw = &bnx2_txp_fw_06;
3037
3038         rc = load_cpu_fw(bp, &cpu_reg, fw);
3039         if (rc)
3040                 goto init_cpu_err;
3041
3042         /* Initialize the TX Patch-up Processor. */
3043         cpu_reg.mode = BNX2_TPAT_CPU_MODE;
3044         cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
3045         cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
3046         cpu_reg.state = BNX2_TPAT_CPU_STATE;
3047         cpu_reg.state_value_clear = 0xffffff;
3048         cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
3049         cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
3050         cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
3051         cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
3052         cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
3053         cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
3054         cpu_reg.mips_view_base = 0x8000000;
3055
3056         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3057                 fw = &bnx2_tpat_fw_09;
3058         else
3059                 fw = &bnx2_tpat_fw_06;
3060
3061         rc = load_cpu_fw(bp, &cpu_reg, fw);
3062         if (rc)
3063                 goto init_cpu_err;
3064
3065         /* Initialize the Completion Processor. */
3066         cpu_reg.mode = BNX2_COM_CPU_MODE;
3067         cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
3068         cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
3069         cpu_reg.state = BNX2_COM_CPU_STATE;
3070         cpu_reg.state_value_clear = 0xffffff;
3071         cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
3072         cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
3073         cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
3074         cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
3075         cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
3076         cpu_reg.spad_base = BNX2_COM_SCRATCH;
3077         cpu_reg.mips_view_base = 0x8000000;
3078
3079         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3080                 fw = &bnx2_com_fw_09;
3081         else
3082                 fw = &bnx2_com_fw_06;
3083
3084         rc = load_cpu_fw(bp, &cpu_reg, fw);
3085         if (rc)
3086                 goto init_cpu_err;
3087
3088         /* Initialize the Command Processor. */
3089         cpu_reg.mode = BNX2_CP_CPU_MODE;
3090         cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
3091         cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
3092         cpu_reg.state = BNX2_CP_CPU_STATE;
3093         cpu_reg.state_value_clear = 0xffffff;
3094         cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
3095         cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
3096         cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
3097         cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
3098         cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
3099         cpu_reg.spad_base = BNX2_CP_SCRATCH;
3100         cpu_reg.mips_view_base = 0x8000000;
3101
3102         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3103                 fw = &bnx2_cp_fw_09;
3104
3105                 rc = load_cpu_fw(bp, &cpu_reg, fw);
3106                 if (rc)
3107                         goto init_cpu_err;
3108         }
3109 init_cpu_err:
3110         bnx2_gunzip_end(bp);
3111         return rc;
3112 }
3113
3114 static int
3115 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3116 {
3117         u16 pmcsr;
3118
3119         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3120
3121         switch (state) {
3122         case PCI_D0: {
3123                 u32 val;
3124
3125                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3126                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3127                         PCI_PM_CTRL_PME_STATUS);
3128
3129                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3130                         /* delay required during transition out of D3hot */
3131                         msleep(20);
3132
3133                 val = REG_RD(bp, BNX2_EMAC_MODE);
3134                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3135                 val &= ~BNX2_EMAC_MODE_MPKT;
3136                 REG_WR(bp, BNX2_EMAC_MODE, val);
3137
3138                 val = REG_RD(bp, BNX2_RPM_CONFIG);
3139                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3140                 REG_WR(bp, BNX2_RPM_CONFIG, val);
3141                 break;
3142         }
3143         case PCI_D3hot: {
3144                 int i;
3145                 u32 val, wol_msg;
3146
3147                 if (bp->wol) {
3148                         u32 advertising;
3149                         u8 autoneg;
3150
3151                         autoneg = bp->autoneg;
3152                         advertising = bp->advertising;
3153
3154                         bp->autoneg = AUTONEG_SPEED;
3155                         bp->advertising = ADVERTISED_10baseT_Half |
3156                                 ADVERTISED_10baseT_Full |
3157                                 ADVERTISED_100baseT_Half |
3158                                 ADVERTISED_100baseT_Full |
3159                                 ADVERTISED_Autoneg;
3160
3161                         bnx2_setup_copper_phy(bp);
3162
3163                         bp->autoneg = autoneg;
3164                         bp->advertising = advertising;
3165
3166                         bnx2_set_mac_addr(bp);
3167
3168                         val = REG_RD(bp, BNX2_EMAC_MODE);
3169
3170                         /* Enable port mode. */
3171                         val &= ~BNX2_EMAC_MODE_PORT;
3172                         val |= BNX2_EMAC_MODE_PORT_MII |
3173                                BNX2_EMAC_MODE_MPKT_RCVD |
3174                                BNX2_EMAC_MODE_ACPI_RCVD |
3175                                BNX2_EMAC_MODE_MPKT;
3176
3177                         REG_WR(bp, BNX2_EMAC_MODE, val);
3178
3179                         /* receive all multicast */
3180                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3181                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3182                                        0xffffffff);
3183                         }
3184                         REG_WR(bp, BNX2_EMAC_RX_MODE,
3185                                BNX2_EMAC_RX_MODE_SORT_MODE);
3186
3187                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3188                               BNX2_RPM_SORT_USER0_MC_EN;
3189                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3190                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3191                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3192                                BNX2_RPM_SORT_USER0_ENA);
3193
3194                         /* Need to enable EMAC and RPM for WOL. */
3195                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3196                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3197                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3198                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3199
3200                         val = REG_RD(bp, BNX2_RPM_CONFIG);
3201                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3202                         REG_WR(bp, BNX2_RPM_CONFIG, val);
3203
3204                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3205                 }
3206                 else {
3207                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3208                 }
3209
3210                 if (!(bp->flags & NO_WOL_FLAG))
3211                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
3212
3213                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3214                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3215                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3216
3217                         if (bp->wol)
3218                                 pmcsr |= 3;
3219                 }
3220                 else {
3221                         pmcsr |= 3;
3222                 }
3223                 if (bp->wol) {
3224                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3225                 }
3226                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3227                                       pmcsr);
3228
3229                 /* No more memory access after this point until
3230                  * device is brought back to D0.
3231                  */
3232                 udelay(50);
3233                 break;
3234         }
3235         default:
3236                 return -EINVAL;
3237         }
3238         return 0;
3239 }
3240
3241 static int
3242 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3243 {
3244         u32 val;
3245         int j;
3246
3247         /* Request access to the flash interface. */
3248         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3249         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3250                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3251                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3252                         break;
3253
3254                 udelay(5);
3255         }
3256
3257         if (j >= NVRAM_TIMEOUT_COUNT)
3258                 return -EBUSY;
3259
3260         return 0;
3261 }
3262
3263 static int
3264 bnx2_release_nvram_lock(struct bnx2 *bp)
3265 {
3266         int j;
3267         u32 val;
3268
3269         /* Relinquish nvram interface. */
3270         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3271
3272         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3273                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3274                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3275                         break;
3276
3277                 udelay(5);
3278         }
3279
3280         if (j >= NVRAM_TIMEOUT_COUNT)
3281                 return -EBUSY;
3282
3283         return 0;
3284 }
3285
3286
3287 static int
3288 bnx2_enable_nvram_write(struct bnx2 *bp)
3289 {
3290         u32 val;
3291
3292         val = REG_RD(bp, BNX2_MISC_CFG);
3293         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3294
3295         if (bp->flash_info->flags & BNX2_NV_WREN) {
3296                 int j;
3297
3298                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3299                 REG_WR(bp, BNX2_NVM_COMMAND,
3300                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3301
3302                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3303                         udelay(5);
3304
3305                         val = REG_RD(bp, BNX2_NVM_COMMAND);
3306                         if (val & BNX2_NVM_COMMAND_DONE)
3307                                 break;
3308                 }
3309
3310                 if (j >= NVRAM_TIMEOUT_COUNT)
3311                         return -EBUSY;
3312         }
3313         return 0;
3314 }
3315
3316 static void
3317 bnx2_disable_nvram_write(struct bnx2 *bp)
3318 {
3319         u32 val;
3320
3321         val = REG_RD(bp, BNX2_MISC_CFG);
3322         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3323 }
3324
3325
3326 static void
3327 bnx2_enable_nvram_access(struct bnx2 *bp)
3328 {
3329         u32 val;
3330
3331         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3332         /* Enable both bits, even on read. */
3333         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3334                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3335 }
3336
3337 static void
3338 bnx2_disable_nvram_access(struct bnx2 *bp)
3339 {
3340         u32 val;
3341
3342         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3343         /* Disable both bits, even after read. */
3344         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3345                 val &a