cxgb3 - Fix dev->priv usage
[linux-3.10.git] / drivers / infiniband / hw / cxgb3 / cxio_hal.c
1 /*
2  * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 #include <asm/delay.h>
33
34 #include <linux/mutex.h>
35 #include <linux/netdevice.h>
36 #include <linux/sched.h>
37 #include <linux/spinlock.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40
41 #include "cxio_resource.h"
42 #include "cxio_hal.h"
43 #include "cxgb3_offload.h"
44 #include "sge_defs.h"
45
46 static LIST_HEAD(rdev_list);
47 static cxio_hal_ev_callback_func_t cxio_ev_cb = NULL;
48
49 static struct cxio_rdev *cxio_hal_find_rdev_by_name(char *dev_name)
50 {
51         struct cxio_rdev *rdev;
52
53         list_for_each_entry(rdev, &rdev_list, entry)
54                 if (!strcmp(rdev->dev_name, dev_name))
55                         return rdev;
56         return NULL;
57 }
58
59 static struct cxio_rdev *cxio_hal_find_rdev_by_t3cdev(struct t3cdev *tdev)
60 {
61         struct cxio_rdev *rdev;
62
63         list_for_each_entry(rdev, &rdev_list, entry)
64                 if (rdev->t3cdev_p == tdev)
65                         return rdev;
66         return NULL;
67 }
68
69 int cxio_hal_cq_op(struct cxio_rdev *rdev_p, struct t3_cq *cq,
70                    enum t3_cq_opcode op, u32 credit)
71 {
72         int ret;
73         struct t3_cqe *cqe;
74         u32 rptr;
75
76         struct rdma_cq_op setup;
77         setup.id = cq->cqid;
78         setup.credits = (op == CQ_CREDIT_UPDATE) ? credit : 0;
79         setup.op = op;
80         ret = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_OP, &setup);
81
82         if ((ret < 0) || (op == CQ_CREDIT_UPDATE))
83                 return ret;
84
85         /*
86          * If the rearm returned an index other than our current index,
87          * then there might be CQE's in flight (being DMA'd).  We must wait
88          * here for them to complete or the consumer can miss a notification.
89          */
90         if (Q_PTR2IDX((cq->rptr), cq->size_log2) != ret) {
91                 int i=0;
92
93                 rptr = cq->rptr;
94
95                 /*
96                  * Keep the generation correct by bumping rptr until it
97                  * matches the index returned by the rearm - 1.
98                  */
99                 while (Q_PTR2IDX((rptr+1), cq->size_log2) != ret)
100                         rptr++;
101
102                 /*
103                  * Now rptr is the index for the (last) cqe that was
104                  * in-flight at the time the HW rearmed the CQ.  We
105                  * spin until that CQE is valid.
106                  */
107                 cqe = cq->queue + Q_PTR2IDX(rptr, cq->size_log2);
108                 while (!CQ_VLD_ENTRY(rptr, cq->size_log2, cqe)) {
109                         udelay(1);
110                         if (i++ > 1000000) {
111                                 BUG_ON(1);
112                                 printk(KERN_ERR "%s: stalled rnic\n",
113                                        rdev_p->dev_name);
114                                 return -EIO;
115                         }
116                 }
117
118                 return 1;
119         }
120
121         return 0;
122 }
123
124 static int cxio_hal_clear_cq_ctx(struct cxio_rdev *rdev_p, u32 cqid)
125 {
126         struct rdma_cq_setup setup;
127         setup.id = cqid;
128         setup.base_addr = 0;    /* NULL address */
129         setup.size = 0;         /* disaable the CQ */
130         setup.credits = 0;
131         setup.credit_thres = 0;
132         setup.ovfl_mode = 0;
133         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
134 }
135
136 static int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid)
137 {
138         u64 sge_cmd;
139         struct t3_modify_qp_wr *wqe;
140         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
141         if (!skb) {
142                 PDBG("%s alloc_skb failed\n", __FUNCTION__);
143                 return -ENOMEM;
144         }
145         wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
146         memset(wqe, 0, sizeof(*wqe));
147         build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 3, 0, qpid, 7);
148         wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
149         sge_cmd = qpid << 8 | 3;
150         wqe->sge_cmd = cpu_to_be64(sge_cmd);
151         skb->priority = CPL_PRIORITY_CONTROL;
152         return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb));
153 }
154
155 int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
156 {
157         struct rdma_cq_setup setup;
158         int size = (1UL << (cq->size_log2)) * sizeof(struct t3_cqe);
159
160         cq->cqid = cxio_hal_get_cqid(rdev_p->rscp);
161         if (!cq->cqid)
162                 return -ENOMEM;
163         cq->sw_queue = kzalloc(size, GFP_KERNEL);
164         if (!cq->sw_queue)
165                 return -ENOMEM;
166         cq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
167                                              (1UL << (cq->size_log2)) *
168                                              sizeof(struct t3_cqe),
169                                              &(cq->dma_addr), GFP_KERNEL);
170         if (!cq->queue) {
171                 kfree(cq->sw_queue);
172                 return -ENOMEM;
173         }
174         pci_unmap_addr_set(cq, mapping, cq->dma_addr);
175         memset(cq->queue, 0, size);
176         setup.id = cq->cqid;
177         setup.base_addr = (u64) (cq->dma_addr);
178         setup.size = 1UL << cq->size_log2;
179         setup.credits = 65535;
180         setup.credit_thres = 1;
181         if (rdev_p->t3cdev_p->type == T3B)
182                 setup.ovfl_mode = 0;
183         else
184                 setup.ovfl_mode = 1;
185         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
186 }
187
188 int cxio_resize_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
189 {
190         struct rdma_cq_setup setup;
191         setup.id = cq->cqid;
192         setup.base_addr = (u64) (cq->dma_addr);
193         setup.size = 1UL << cq->size_log2;
194         setup.credits = setup.size;
195         setup.credit_thres = setup.size;        /* TBD: overflow recovery */
196         setup.ovfl_mode = 1;
197         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
198 }
199
200 static u32 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
201 {
202         struct cxio_qpid_list *entry;
203         u32 qpid;
204         int i;
205
206         mutex_lock(&uctx->lock);
207         if (!list_empty(&uctx->qpids)) {
208                 entry = list_entry(uctx->qpids.next, struct cxio_qpid_list,
209                                    entry);
210                 list_del(&entry->entry);
211                 qpid = entry->qpid;
212                 kfree(entry);
213         } else {
214                 qpid = cxio_hal_get_qpid(rdev_p->rscp);
215                 if (!qpid)
216                         goto out;
217                 for (i = qpid+1; i & rdev_p->qpmask; i++) {
218                         entry = kmalloc(sizeof *entry, GFP_KERNEL);
219                         if (!entry)
220                                 break;
221                         entry->qpid = i;
222                         list_add_tail(&entry->entry, &uctx->qpids);
223                 }
224         }
225 out:
226         mutex_unlock(&uctx->lock);
227         PDBG("%s qpid 0x%x\n", __FUNCTION__, qpid);
228         return qpid;
229 }
230
231 static void put_qpid(struct cxio_rdev *rdev_p, u32 qpid,
232                      struct cxio_ucontext *uctx)
233 {
234         struct cxio_qpid_list *entry;
235
236         entry = kmalloc(sizeof *entry, GFP_KERNEL);
237         if (!entry)
238                 return;
239         PDBG("%s qpid 0x%x\n", __FUNCTION__, qpid);
240         entry->qpid = qpid;
241         mutex_lock(&uctx->lock);
242         list_add_tail(&entry->entry, &uctx->qpids);
243         mutex_unlock(&uctx->lock);
244 }
245
246 void cxio_release_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
247 {
248         struct list_head *pos, *nxt;
249         struct cxio_qpid_list *entry;
250
251         mutex_lock(&uctx->lock);
252         list_for_each_safe(pos, nxt, &uctx->qpids) {
253                 entry = list_entry(pos, struct cxio_qpid_list, entry);
254                 list_del_init(&entry->entry);
255                 if (!(entry->qpid & rdev_p->qpmask))
256                         cxio_hal_put_qpid(rdev_p->rscp, entry->qpid);
257                 kfree(entry);
258         }
259         mutex_unlock(&uctx->lock);
260 }
261
262 void cxio_init_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
263 {
264         INIT_LIST_HEAD(&uctx->qpids);
265         mutex_init(&uctx->lock);
266 }
267
268 int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
269                    struct t3_wq *wq, struct cxio_ucontext *uctx)
270 {
271         int depth = 1UL << wq->size_log2;
272         int rqsize = 1UL << wq->rq_size_log2;
273
274         wq->qpid = get_qpid(rdev_p, uctx);
275         if (!wq->qpid)
276                 return -ENOMEM;
277
278         wq->rq = kzalloc(depth * sizeof(u64), GFP_KERNEL);
279         if (!wq->rq)
280                 goto err1;
281
282         wq->rq_addr = cxio_hal_rqtpool_alloc(rdev_p, rqsize);
283         if (!wq->rq_addr)
284                 goto err2;
285
286         wq->sq = kzalloc(depth * sizeof(struct t3_swsq), GFP_KERNEL);
287         if (!wq->sq)
288                 goto err3;
289
290         wq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
291                                              depth * sizeof(union t3_wr),
292                                              &(wq->dma_addr), GFP_KERNEL);
293         if (!wq->queue)
294                 goto err4;
295
296         memset(wq->queue, 0, depth * sizeof(union t3_wr));
297         pci_unmap_addr_set(wq, mapping, wq->dma_addr);
298         wq->doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
299         if (!kernel_domain)
300                 wq->udb = (u64)rdev_p->rnic_info.udbell_physbase +
301                                         (wq->qpid << rdev_p->qpshift);
302         PDBG("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n", __FUNCTION__,
303              wq->qpid, wq->doorbell, (unsigned long long) wq->udb);
304         return 0;
305 err4:
306         kfree(wq->sq);
307 err3:
308         cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, rqsize);
309 err2:
310         kfree(wq->rq);
311 err1:
312         put_qpid(rdev_p, wq->qpid, uctx);
313         return -ENOMEM;
314 }
315
316 int cxio_destroy_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
317 {
318         int err;
319         err = cxio_hal_clear_cq_ctx(rdev_p, cq->cqid);
320         kfree(cq->sw_queue);
321         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
322                           (1UL << (cq->size_log2))
323                           * sizeof(struct t3_cqe), cq->queue,
324                           pci_unmap_addr(cq, mapping));
325         cxio_hal_put_cqid(rdev_p->rscp, cq->cqid);
326         return err;
327 }
328
329 int cxio_destroy_qp(struct cxio_rdev *rdev_p, struct t3_wq *wq,
330                     struct cxio_ucontext *uctx)
331 {
332         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
333                           (1UL << (wq->size_log2))
334                           * sizeof(union t3_wr), wq->queue,
335                           pci_unmap_addr(wq, mapping));
336         kfree(wq->sq);
337         cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, (1UL << wq->rq_size_log2));
338         kfree(wq->rq);
339         put_qpid(rdev_p, wq->qpid, uctx);
340         return 0;
341 }
342
343 static void insert_recv_cqe(struct t3_wq *wq, struct t3_cq *cq)
344 {
345         struct t3_cqe cqe;
346
347         PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __FUNCTION__,
348              wq, cq, cq->sw_rptr, cq->sw_wptr);
349         memset(&cqe, 0, sizeof(cqe));
350         cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
351                                  V_CQE_OPCODE(T3_SEND) |
352                                  V_CQE_TYPE(0) |
353                                  V_CQE_SWCQE(1) |
354                                  V_CQE_QPID(wq->qpid) |
355                                  V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
356                                                        cq->size_log2)));
357         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
358         cq->sw_wptr++;
359 }
360
361 void cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count)
362 {
363         u32 ptr;
364
365         PDBG("%s wq %p cq %p\n", __FUNCTION__, wq, cq);
366
367         /* flush RQ */
368         PDBG("%s rq_rptr %u rq_wptr %u skip count %u\n", __FUNCTION__,
369             wq->rq_rptr, wq->rq_wptr, count);
370         ptr = wq->rq_rptr + count;
371         while (ptr++ != wq->rq_wptr)
372                 insert_recv_cqe(wq, cq);
373 }
374
375 static void insert_sq_cqe(struct t3_wq *wq, struct t3_cq *cq,
376                           struct t3_swsq *sqp)
377 {
378         struct t3_cqe cqe;
379
380         PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __FUNCTION__,
381              wq, cq, cq->sw_rptr, cq->sw_wptr);
382         memset(&cqe, 0, sizeof(cqe));
383         cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
384                                  V_CQE_OPCODE(sqp->opcode) |
385                                  V_CQE_TYPE(1) |
386                                  V_CQE_SWCQE(1) |
387                                  V_CQE_QPID(wq->qpid) |
388                                  V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
389                                                        cq->size_log2)));
390         cqe.u.scqe.wrid_hi = sqp->sq_wptr;
391
392         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
393         cq->sw_wptr++;
394 }
395
396 void cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count)
397 {
398         __u32 ptr;
399         struct t3_swsq *sqp = wq->sq + Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2);
400
401         ptr = wq->sq_rptr + count;
402         sqp += count;
403         while (ptr != wq->sq_wptr) {
404                 insert_sq_cqe(wq, cq, sqp);
405                 sqp++;
406                 ptr++;
407         }
408 }
409
410 /*
411  * Move all CQEs from the HWCQ into the SWCQ.
412  */
413 void cxio_flush_hw_cq(struct t3_cq *cq)
414 {
415         struct t3_cqe *cqe, *swcqe;
416
417         PDBG("%s cq %p cqid 0x%x\n", __FUNCTION__, cq, cq->cqid);
418         cqe = cxio_next_hw_cqe(cq);
419         while (cqe) {
420                 PDBG("%s flushing hwcq rptr 0x%x to swcq wptr 0x%x\n",
421                      __FUNCTION__, cq->rptr, cq->sw_wptr);
422                 swcqe = cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2);
423                 *swcqe = *cqe;
424                 swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1));
425                 cq->sw_wptr++;
426                 cq->rptr++;
427                 cqe = cxio_next_hw_cqe(cq);
428         }
429 }
430
431 static int cqe_completes_wr(struct t3_cqe *cqe, struct t3_wq *wq)
432 {
433         if (CQE_OPCODE(*cqe) == T3_TERMINATE)
434                 return 0;
435
436         if ((CQE_OPCODE(*cqe) == T3_RDMA_WRITE) && RQ_TYPE(*cqe))
437                 return 0;
438
439         if ((CQE_OPCODE(*cqe) == T3_READ_RESP) && SQ_TYPE(*cqe))
440                 return 0;
441
442         if ((CQE_OPCODE(*cqe) == T3_SEND) && RQ_TYPE(*cqe) &&
443             Q_EMPTY(wq->rq_rptr, wq->rq_wptr))
444                 return 0;
445
446         return 1;
447 }
448
449 void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
450 {
451         struct t3_cqe *cqe;
452         u32 ptr;
453
454         *count = 0;
455         ptr = cq->sw_rptr;
456         while (!Q_EMPTY(ptr, cq->sw_wptr)) {
457                 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
458                 if ((SQ_TYPE(*cqe) || (CQE_OPCODE(*cqe) == T3_READ_RESP)) &&
459                     (CQE_QPID(*cqe) == wq->qpid))
460                         (*count)++;
461                 ptr++;
462         }
463         PDBG("%s cq %p count %d\n", __FUNCTION__, cq, *count);
464 }
465
466 void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
467 {
468         struct t3_cqe *cqe;
469         u32 ptr;
470
471         *count = 0;
472         PDBG("%s count zero %d\n", __FUNCTION__, *count);
473         ptr = cq->sw_rptr;
474         while (!Q_EMPTY(ptr, cq->sw_wptr)) {
475                 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
476                 if (RQ_TYPE(*cqe) && (CQE_OPCODE(*cqe) != T3_READ_RESP) &&
477                     (CQE_QPID(*cqe) == wq->qpid) && cqe_completes_wr(cqe, wq))
478                         (*count)++;
479                 ptr++;
480         }
481         PDBG("%s cq %p count %d\n", __FUNCTION__, cq, *count);
482 }
483
484 static int cxio_hal_init_ctrl_cq(struct cxio_rdev *rdev_p)
485 {
486         struct rdma_cq_setup setup;
487         setup.id = 0;
488         setup.base_addr = 0;    /* NULL address */
489         setup.size = 1;         /* enable the CQ */
490         setup.credits = 0;
491
492         /* force SGE to redirect to RspQ and interrupt */
493         setup.credit_thres = 0;
494         setup.ovfl_mode = 1;
495         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
496 }
497
498 static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p)
499 {
500         int err;
501         u64 sge_cmd, ctx0, ctx1;
502         u64 base_addr;
503         struct t3_modify_qp_wr *wqe;
504         struct sk_buff *skb;
505
506         skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
507         if (!skb) {
508                 PDBG("%s alloc_skb failed\n", __FUNCTION__);
509                 return -ENOMEM;
510         }
511         err = cxio_hal_init_ctrl_cq(rdev_p);
512         if (err) {
513                 PDBG("%s err %d initializing ctrl_cq\n", __FUNCTION__, err);
514                 goto err;
515         }
516         rdev_p->ctrl_qp.workq = dma_alloc_coherent(
517                                         &(rdev_p->rnic_info.pdev->dev),
518                                         (1 << T3_CTRL_QP_SIZE_LOG2) *
519                                         sizeof(union t3_wr),
520                                         &(rdev_p->ctrl_qp.dma_addr),
521                                         GFP_KERNEL);
522         if (!rdev_p->ctrl_qp.workq) {
523                 PDBG("%s dma_alloc_coherent failed\n", __FUNCTION__);
524                 err = -ENOMEM;
525                 goto err;
526         }
527         pci_unmap_addr_set(&rdev_p->ctrl_qp, mapping,
528                            rdev_p->ctrl_qp.dma_addr);
529         rdev_p->ctrl_qp.doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
530         memset(rdev_p->ctrl_qp.workq, 0,
531                (1 << T3_CTRL_QP_SIZE_LOG2) * sizeof(union t3_wr));
532
533         mutex_init(&rdev_p->ctrl_qp.lock);
534         init_waitqueue_head(&rdev_p->ctrl_qp.waitq);
535
536         /* update HW Ctrl QP context */
537         base_addr = rdev_p->ctrl_qp.dma_addr;
538         base_addr >>= 12;
539         ctx0 = (V_EC_SIZE((1 << T3_CTRL_QP_SIZE_LOG2)) |
540                 V_EC_BASE_LO((u32) base_addr & 0xffff));
541         ctx0 <<= 32;
542         ctx0 |= V_EC_CREDITS(FW_WR_NUM);
543         base_addr >>= 16;
544         ctx1 = (u32) base_addr;
545         base_addr >>= 32;
546         ctx1 |= ((u64) (V_EC_BASE_HI((u32) base_addr & 0xf) | V_EC_RESPQ(0) |
547                         V_EC_TYPE(0) | V_EC_GEN(1) |
548                         V_EC_UP_TOKEN(T3_CTL_QP_TID) | F_EC_VALID)) << 32;
549         wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
550         memset(wqe, 0, sizeof(*wqe));
551         build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 0, 0,
552                        T3_CTL_QP_TID, 7);
553         wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
554         sge_cmd = (3ULL << 56) | FW_RI_SGEEC_START << 8 | 3;
555         wqe->sge_cmd = cpu_to_be64(sge_cmd);
556         wqe->ctx1 = cpu_to_be64(ctx1);
557         wqe->ctx0 = cpu_to_be64(ctx0);
558         PDBG("CtrlQP dma_addr 0x%llx workq %p size %d\n",
559              (unsigned long long) rdev_p->ctrl_qp.dma_addr,
560              rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2);
561         skb->priority = CPL_PRIORITY_CONTROL;
562         return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb));
563 err:
564         kfree_skb(skb);
565         return err;
566 }
567
568 static int cxio_hal_destroy_ctrl_qp(struct cxio_rdev *rdev_p)
569 {
570         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
571                           (1UL << T3_CTRL_QP_SIZE_LOG2)
572                           * sizeof(union t3_wr), rdev_p->ctrl_qp.workq,
573                           pci_unmap_addr(&rdev_p->ctrl_qp, mapping));
574         return cxio_hal_clear_qp_ctx(rdev_p, T3_CTRL_QP_ID);
575 }
576
577 /* write len bytes of data into addr (32B aligned address)
578  * If data is NULL, clear len byte of memory to zero.
579  * caller aquires the ctrl_qp lock before the call
580  */
581 static int cxio_hal_ctrl_qp_write_mem(struct cxio_rdev *rdev_p, u32 addr,
582                                       u32 len, void *data, int completion)
583 {
584         u32 i, nr_wqe, copy_len;
585         u8 *copy_data;
586         u8 wr_len, utx_len;     /* lenght in 8 byte flit */
587         enum t3_wr_flags flag;
588         __be64 *wqe;
589         u64 utx_cmd;
590         addr &= 0x7FFFFFF;
591         nr_wqe = len % 96 ? len / 96 + 1 : len / 96;    /* 96B max per WQE */
592         PDBG("%s wptr 0x%x rptr 0x%x len %d, nr_wqe %d data %p addr 0x%0x\n",
593              __FUNCTION__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len,
594              nr_wqe, data, addr);
595         utx_len = 3;            /* in 32B unit */
596         for (i = 0; i < nr_wqe; i++) {
597                 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr,
598                            T3_CTRL_QP_SIZE_LOG2)) {
599                         PDBG("%s ctrl_qp full wtpr 0x%0x rptr 0x%0x, "
600                              "wait for more space i %d\n", __FUNCTION__,
601                              rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i);
602                         if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
603                                              !Q_FULL(rdev_p->ctrl_qp.rptr,
604                                                      rdev_p->ctrl_qp.wptr,
605                                                      T3_CTRL_QP_SIZE_LOG2))) {
606                                 PDBG("%s ctrl_qp workq interrupted\n",
607                                      __FUNCTION__);
608                                 return -ERESTARTSYS;
609                         }
610                         PDBG("%s ctrl_qp wakeup, continue posting work request "
611                              "i %d\n", __FUNCTION__, i);
612                 }
613                 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
614                                                 (1 << T3_CTRL_QP_SIZE_LOG2)));
615                 flag = 0;
616                 if (i == (nr_wqe - 1)) {
617                         /* last WQE */
618                         flag = completion ? T3_COMPLETION_FLAG : 0;
619                         if (len % 32)
620                                 utx_len = len / 32 + 1;
621                         else
622                                 utx_len = len / 32;
623                 }
624
625                 /*
626                  * Force a CQE to return the credit to the workq in case
627                  * we posted more than half the max QP size of WRs
628                  */
629                 if ((i != 0) &&
630                     (i % (((1 << T3_CTRL_QP_SIZE_LOG2)) >> 1) == 0)) {
631                         flag = T3_COMPLETION_FLAG;
632                         PDBG("%s force completion at i %d\n", __FUNCTION__, i);
633                 }
634
635                 /* build the utx mem command */
636                 wqe += (sizeof(struct t3_bypass_wr) >> 3);
637                 utx_cmd = (T3_UTX_MEM_WRITE << 28) | (addr + i * 3);
638                 utx_cmd <<= 32;
639                 utx_cmd |= (utx_len << 28) | ((utx_len << 2) + 1);
640                 *wqe = cpu_to_be64(utx_cmd);
641                 wqe++;
642                 copy_data = (u8 *) data + i * 96;
643                 copy_len = len > 96 ? 96 : len;
644
645                 /* clear memory content if data is NULL */
646                 if (data)
647                         memcpy(wqe, copy_data, copy_len);
648                 else
649                         memset(wqe, 0, copy_len);
650                 if (copy_len % 32)
651                         memset(((u8 *) wqe) + copy_len, 0,
652                                32 - (copy_len % 32));
653                 wr_len = ((sizeof(struct t3_bypass_wr)) >> 3) + 1 +
654                          (utx_len << 2);
655                 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
656                               (1 << T3_CTRL_QP_SIZE_LOG2)));
657
658                 /* wptr in the WRID[31:0] */
659                 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr;
660
661                 /*
662                  * This must be the last write with a memory barrier
663                  * for the genbit
664                  */
665                 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_BP, flag,
666                                Q_GENBIT(rdev_p->ctrl_qp.wptr,
667                                         T3_CTRL_QP_SIZE_LOG2), T3_CTRL_QP_ID,
668                                wr_len);
669                 if (flag == T3_COMPLETION_FLAG)
670                         ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID);
671                 len -= 96;
672                 rdev_p->ctrl_qp.wptr++;
673         }
674         return 0;
675 }
676
677 /* IN: stag key, pdid, perm, zbva, to, len, page_size, pbl, and pbl_size
678  * OUT: stag index, actual pbl_size, pbl_addr allocated.
679  * TBD: shared memory region support
680  */
681 static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry,
682                          u32 *stag, u8 stag_state, u32 pdid,
683                          enum tpt_mem_type type, enum tpt_mem_perm perm,
684                          u32 zbva, u64 to, u32 len, u8 page_size, __be64 *pbl,
685                          u32 *pbl_size, u32 *pbl_addr)
686 {
687         int err;
688         struct tpt_entry tpt;
689         u32 stag_idx;
690         u32 wptr;
691         int rereg = (*stag != T3_STAG_UNSET);
692
693         stag_state = stag_state > 0;
694         stag_idx = (*stag) >> 8;
695
696         if ((!reset_tpt_entry) && !(*stag != T3_STAG_UNSET)) {
697                 stag_idx = cxio_hal_get_stag(rdev_p->rscp);
698                 if (!stag_idx)
699                         return -ENOMEM;
700                 *stag = (stag_idx << 8) | ((*stag) & 0xFF);
701         }
702         PDBG("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
703              __FUNCTION__, stag_state, type, pdid, stag_idx);
704
705         if (reset_tpt_entry)
706                 cxio_hal_pblpool_free(rdev_p, *pbl_addr, *pbl_size << 3);
707         else if (!rereg) {
708                 *pbl_addr = cxio_hal_pblpool_alloc(rdev_p, *pbl_size << 3);
709                 if (!*pbl_addr) {
710                         return -ENOMEM;
711                 }
712         }
713
714         mutex_lock(&rdev_p->ctrl_qp.lock);
715
716         /* write PBL first if any - update pbl only if pbl list exist */
717         if (pbl) {
718
719                 PDBG("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
720                      __FUNCTION__, *pbl_addr, rdev_p->rnic_info.pbl_base,
721                      *pbl_size);
722                 err = cxio_hal_ctrl_qp_write_mem(rdev_p,
723                                 (*pbl_addr >> 5),
724                                 (*pbl_size << 3), pbl, 0);
725                 if (err)
726                         goto ret;
727         }
728
729         /* write TPT entry */
730         if (reset_tpt_entry)
731                 memset(&tpt, 0, sizeof(tpt));
732         else {
733                 tpt.valid_stag_pdid = cpu_to_be32(F_TPT_VALID |
734                                 V_TPT_STAG_KEY((*stag) & M_TPT_STAG_KEY) |
735                                 V_TPT_STAG_STATE(stag_state) |
736                                 V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid));
737                 BUG_ON(page_size >= 28);
738                 tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) |
739                                 F_TPT_MW_BIND_ENABLE |
740                                 V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) |
741                                 V_TPT_PAGE_SIZE(page_size));
742                 tpt.rsvd_pbl_addr = reset_tpt_entry ? 0 :
743                                     cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, *pbl_addr)>>3));
744                 tpt.len = cpu_to_be32(len);
745                 tpt.va_hi = cpu_to_be32((u32) (to >> 32));
746                 tpt.va_low_or_fbo = cpu_to_be32((u32) (to & 0xFFFFFFFFULL));
747                 tpt.rsvd_bind_cnt_or_pstag = 0;
748                 tpt.rsvd_pbl_size = reset_tpt_entry ? 0 :
749                                   cpu_to_be32(V_TPT_PBL_SIZE((*pbl_size) >> 2));
750         }
751         err = cxio_hal_ctrl_qp_write_mem(rdev_p,
752                                        stag_idx +
753                                        (rdev_p->rnic_info.tpt_base >> 5),
754                                        sizeof(tpt), &tpt, 1);
755
756         /* release the stag index to free pool */
757         if (reset_tpt_entry)
758                 cxio_hal_put_stag(rdev_p->rscp, stag_idx);
759 ret:
760         wptr = rdev_p->ctrl_qp.wptr;
761         mutex_unlock(&rdev_p->ctrl_qp.lock);
762         if (!err)
763                 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
764                                              SEQ32_GE(rdev_p->ctrl_qp.rptr,
765                                                       wptr)))
766                         return -ERESTARTSYS;
767         return err;
768 }
769
770 int cxio_register_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
771                            enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
772                            u8 page_size, __be64 *pbl, u32 *pbl_size,
773                            u32 *pbl_addr)
774 {
775         *stag = T3_STAG_UNSET;
776         return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
777                              zbva, to, len, page_size, pbl, pbl_size, pbl_addr);
778 }
779
780 int cxio_reregister_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
781                            enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
782                            u8 page_size, __be64 *pbl, u32 *pbl_size,
783                            u32 *pbl_addr)
784 {
785         return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
786                              zbva, to, len, page_size, pbl, pbl_size, pbl_addr);
787 }
788
789 int cxio_dereg_mem(struct cxio_rdev *rdev_p, u32 stag, u32 pbl_size,
790                    u32 pbl_addr)
791 {
792         return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0, NULL,
793                              &pbl_size, &pbl_addr);
794 }
795
796 int cxio_allocate_window(struct cxio_rdev *rdev_p, u32 * stag, u32 pdid)
797 {
798         u32 pbl_size = 0;
799         *stag = T3_STAG_UNSET;
800         return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_MW, 0, 0, 0ULL, 0, 0,
801                              NULL, &pbl_size, NULL);
802 }
803
804 int cxio_deallocate_window(struct cxio_rdev *rdev_p, u32 stag)
805 {
806         return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0, NULL,
807                              NULL, NULL);
808 }
809
810 int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr)
811 {
812         struct t3_rdma_init_wr *wqe;
813         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_ATOMIC);
814         if (!skb)
815                 return -ENOMEM;
816         PDBG("%s rdev_p %p\n", __FUNCTION__, rdev_p);
817         wqe = (struct t3_rdma_init_wr *) __skb_put(skb, sizeof(*wqe));
818         wqe->wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_INIT));
819         wqe->wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(attr->tid) |
820                                            V_FW_RIWR_LEN(sizeof(*wqe) >> 3));
821         wqe->wrid.id1 = 0;
822         wqe->qpid = cpu_to_be32(attr->qpid);
823         wqe->pdid = cpu_to_be32(attr->pdid);
824         wqe->scqid = cpu_to_be32(attr->scqid);
825         wqe->rcqid = cpu_to_be32(attr->rcqid);
826         wqe->rq_addr = cpu_to_be32(attr->rq_addr - rdev_p->rnic_info.rqt_base);
827         wqe->rq_size = cpu_to_be32(attr->rq_size);
828         wqe->mpaattrs = attr->mpaattrs;
829         wqe->qpcaps = attr->qpcaps;
830         wqe->ulpdu_size = cpu_to_be16(attr->tcp_emss);
831         wqe->flags = cpu_to_be32(attr->flags);
832         wqe->ord = cpu_to_be32(attr->ord);
833         wqe->ird = cpu_to_be32(attr->ird);
834         wqe->qp_dma_addr = cpu_to_be64(attr->qp_dma_addr);
835         wqe->qp_dma_size = cpu_to_be32(attr->qp_dma_size);
836         wqe->irs = cpu_to_be32(attr->irs);
837         skb->priority = 0;      /* 0=>ToeQ; 1=>CtrlQ */
838         return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb));
839 }
840
841 void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
842 {
843         cxio_ev_cb = ev_cb;
844 }
845
846 void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
847 {
848         cxio_ev_cb = NULL;
849 }
850
851 static int cxio_hal_ev_handler(struct t3cdev *t3cdev_p, struct sk_buff *skb)
852 {
853         static int cnt;
854         struct cxio_rdev *rdev_p = NULL;
855         struct respQ_msg_t *rsp_msg = (struct respQ_msg_t *) skb->data;
856         PDBG("%d: %s cq_id 0x%x cq_ptr 0x%x genbit %0x overflow %0x an %0x"
857              " se %0x notify %0x cqbranch %0x creditth %0x\n",
858              cnt, __FUNCTION__, RSPQ_CQID(rsp_msg), RSPQ_CQPTR(rsp_msg),
859              RSPQ_GENBIT(rsp_msg), RSPQ_OVERFLOW(rsp_msg), RSPQ_AN(rsp_msg),
860              RSPQ_SE(rsp_msg), RSPQ_NOTIFY(rsp_msg), RSPQ_CQBRANCH(rsp_msg),
861              RSPQ_CREDIT_THRESH(rsp_msg));
862         PDBG("CQE: QPID 0x%0x genbit %0x type 0x%0x status 0x%0x opcode %d "
863              "len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
864              CQE_QPID(rsp_msg->cqe), CQE_GENBIT(rsp_msg->cqe),
865              CQE_TYPE(rsp_msg->cqe), CQE_STATUS(rsp_msg->cqe),
866              CQE_OPCODE(rsp_msg->cqe), CQE_LEN(rsp_msg->cqe),
867              CQE_WRID_HI(rsp_msg->cqe), CQE_WRID_LOW(rsp_msg->cqe));
868         rdev_p = (struct cxio_rdev *)t3cdev_p->ulp;
869         if (!rdev_p) {
870                 PDBG("%s called by t3cdev %p with null ulp\n", __FUNCTION__,
871                      t3cdev_p);
872                 return 0;
873         }
874         if (CQE_QPID(rsp_msg->cqe) == T3_CTRL_QP_ID) {
875                 rdev_p->ctrl_qp.rptr = CQE_WRID_LOW(rsp_msg->cqe) + 1;
876                 wake_up_interruptible(&rdev_p->ctrl_qp.waitq);
877                 dev_kfree_skb_irq(skb);
878         } else if (CQE_QPID(rsp_msg->cqe) == 0xfff8)
879                 dev_kfree_skb_irq(skb);
880         else if (cxio_ev_cb)
881                 (*cxio_ev_cb) (rdev_p, skb);
882         else
883                 dev_kfree_skb_irq(skb);
884         cnt++;
885         return 0;
886 }
887
888 /* Caller takes care of locking if needed */
889 int cxio_rdev_open(struct cxio_rdev *rdev_p)
890 {
891         struct net_device *netdev_p = NULL;
892         int err = 0;
893         if (strlen(rdev_p->dev_name)) {
894                 if (cxio_hal_find_rdev_by_name(rdev_p->dev_name)) {
895                         return -EBUSY;
896                 }
897                 netdev_p = dev_get_by_name(rdev_p->dev_name);
898                 if (!netdev_p) {
899                         return -EINVAL;
900                 }
901                 dev_put(netdev_p);
902         } else if (rdev_p->t3cdev_p) {
903                 if (cxio_hal_find_rdev_by_t3cdev(rdev_p->t3cdev_p)) {
904                         return -EBUSY;
905                 }
906                 netdev_p = rdev_p->t3cdev_p->lldev;
907                 strncpy(rdev_p->dev_name, rdev_p->t3cdev_p->name,
908                         T3_MAX_DEV_NAME_LEN);
909         } else {
910                 PDBG("%s t3cdev_p or dev_name must be set\n", __FUNCTION__);
911                 return -EINVAL;
912         }
913
914         list_add_tail(&rdev_p->entry, &rdev_list);
915
916         PDBG("%s opening rnic dev %s\n", __FUNCTION__, rdev_p->dev_name);
917         memset(&rdev_p->ctrl_qp, 0, sizeof(rdev_p->ctrl_qp));
918         if (!rdev_p->t3cdev_p)
919                 rdev_p->t3cdev_p = dev2t3cdev(netdev_p);
920         rdev_p->t3cdev_p->ulp = (void *) rdev_p;
921         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_GET_PARAMS,
922                                          &(rdev_p->rnic_info));
923         if (err) {
924                 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
925                      __FUNCTION__, rdev_p->t3cdev_p, err);
926                 goto err1;
927         }
928         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_PORTS,
929                                     &(rdev_p->port_info));
930         if (err) {
931                 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
932                      __FUNCTION__, rdev_p->t3cdev_p, err);
933                 goto err1;
934         }
935
936         /*
937          * qpshift is the number of bits to shift the qpid left in order
938          * to get the correct address of the doorbell for that qp.
939          */
940         cxio_init_ucontext(rdev_p, &rdev_p->uctx);
941         rdev_p->qpshift = PAGE_SHIFT -
942                           ilog2(65536 >>
943                                     ilog2(rdev_p->rnic_info.udbell_len >>
944                                               PAGE_SHIFT));
945         rdev_p->qpnr = rdev_p->rnic_info.udbell_len >> PAGE_SHIFT;
946         rdev_p->qpmask = (65536 >> ilog2(rdev_p->qpnr)) - 1;
947         PDBG("%s rnic %s info: tpt_base 0x%0x tpt_top 0x%0x num stags %d "
948              "pbl_base 0x%0x pbl_top 0x%0x rqt_base 0x%0x, rqt_top 0x%0x\n",
949              __FUNCTION__, rdev_p->dev_name, rdev_p->rnic_info.tpt_base,
950              rdev_p->rnic_info.tpt_top, cxio_num_stags(rdev_p),
951              rdev_p->rnic_info.pbl_base,
952              rdev_p->rnic_info.pbl_top, rdev_p->rnic_info.rqt_base,
953              rdev_p->rnic_info.rqt_top);
954         PDBG("udbell_len 0x%0x udbell_physbase 0x%lx kdb_addr %p qpshift %lu "
955              "qpnr %d qpmask 0x%x\n",
956              rdev_p->rnic_info.udbell_len,
957              rdev_p->rnic_info.udbell_physbase, rdev_p->rnic_info.kdb_addr,
958              rdev_p->qpshift, rdev_p->qpnr, rdev_p->qpmask);
959
960         err = cxio_hal_init_ctrl_qp(rdev_p);
961         if (err) {
962                 printk(KERN_ERR "%s error %d initializing ctrl_qp.\n",
963                        __FUNCTION__, err);
964                 goto err1;
965         }
966         err = cxio_hal_init_resource(rdev_p, cxio_num_stags(rdev_p), 0,
967                                      0, T3_MAX_NUM_QP, T3_MAX_NUM_CQ,
968                                      T3_MAX_NUM_PD);
969         if (err) {
970                 printk(KERN_ERR "%s error %d initializing hal resources.\n",
971                        __FUNCTION__, err);
972                 goto err2;
973         }
974         err = cxio_hal_pblpool_create(rdev_p);
975         if (err) {
976                 printk(KERN_ERR "%s error %d initializing pbl mem pool.\n",
977                        __FUNCTION__, err);
978                 goto err3;
979         }
980         err = cxio_hal_rqtpool_create(rdev_p);
981         if (err) {
982                 printk(KERN_ERR "%s error %d initializing rqt mem pool.\n",
983                        __FUNCTION__, err);
984                 goto err4;
985         }
986         return 0;
987 err4:
988         cxio_hal_pblpool_destroy(rdev_p);
989 err3:
990         cxio_hal_destroy_resource(rdev_p->rscp);
991 err2:
992         cxio_hal_destroy_ctrl_qp(rdev_p);
993 err1:
994         list_del(&rdev_p->entry);
995         return err;
996 }
997
998 void cxio_rdev_close(struct cxio_rdev *rdev_p)
999 {
1000         if (rdev_p) {
1001                 cxio_hal_pblpool_destroy(rdev_p);
1002                 cxio_hal_rqtpool_destroy(rdev_p);
1003                 list_del(&rdev_p->entry);
1004                 rdev_p->t3cdev_p->ulp = NULL;
1005                 cxio_hal_destroy_ctrl_qp(rdev_p);
1006                 cxio_hal_destroy_resource(rdev_p->rscp);
1007         }
1008 }
1009
1010 int __init cxio_hal_init(void)
1011 {
1012         if (cxio_hal_init_rhdl_resource(T3_MAX_NUM_RI))
1013                 return -ENOMEM;
1014         t3_register_cpl_handler(CPL_ASYNC_NOTIF, cxio_hal_ev_handler);
1015         return 0;
1016 }
1017
1018 void __exit cxio_hal_exit(void)
1019 {
1020         struct cxio_rdev *rdev, *tmp;
1021
1022         t3_register_cpl_handler(CPL_ASYNC_NOTIF, NULL);
1023         list_for_each_entry_safe(rdev, tmp, &rdev_list, entry)
1024                 cxio_rdev_close(rdev);
1025         cxio_hal_destroy_rhdl_resource();
1026 }
1027
1028 static void flush_completed_wrs(struct t3_wq *wq, struct t3_cq *cq)
1029 {
1030         struct t3_swsq *sqp;
1031         __u32 ptr = wq->sq_rptr;
1032         int count = Q_COUNT(wq->sq_rptr, wq->sq_wptr);
1033
1034         sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
1035         while (count--)
1036                 if (!sqp->signaled) {
1037                         ptr++;
1038                         sqp = wq->sq + Q_PTR2IDX(ptr,  wq->sq_size_log2);
1039                 } else if (sqp->complete) {
1040
1041                         /*
1042                          * Insert this completed cqe into the swcq.
1043                          */
1044                         PDBG("%s moving cqe into swcq sq idx %ld cq idx %ld\n",
1045                              __FUNCTION__, Q_PTR2IDX(ptr,  wq->sq_size_log2),
1046                              Q_PTR2IDX(cq->sw_wptr, cq->size_log2));
1047                         sqp->cqe.header |= htonl(V_CQE_SWCQE(1));
1048                         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2))
1049                                 = sqp->cqe;
1050                         cq->sw_wptr++;
1051                         sqp->signaled = 0;
1052                         break;
1053                 } else
1054                         break;
1055 }
1056
1057 static void create_read_req_cqe(struct t3_wq *wq, struct t3_cqe *hw_cqe,
1058                                 struct t3_cqe *read_cqe)
1059 {
1060         read_cqe->u.scqe.wrid_hi = wq->oldest_read->sq_wptr;
1061         read_cqe->len = wq->oldest_read->read_len;
1062         read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(*hw_cqe)) |
1063                                  V_CQE_SWCQE(SW_CQE(*hw_cqe)) |
1064                                  V_CQE_OPCODE(T3_READ_REQ) |
1065                                  V_CQE_TYPE(1));
1066 }
1067
1068 /*
1069  * Return a ptr to the next read wr in the SWSQ or NULL.
1070  */
1071 static void advance_oldest_read(struct t3_wq *wq)
1072 {
1073
1074         u32 rptr = wq->oldest_read - wq->sq + 1;
1075         u32 wptr = Q_PTR2IDX(wq->sq_wptr, wq->sq_size_log2);
1076
1077         while (Q_PTR2IDX(rptr, wq->sq_size_log2) != wptr) {
1078                 wq->oldest_read = wq->sq + Q_PTR2IDX(rptr, wq->sq_size_log2);
1079
1080                 if (wq->oldest_read->opcode == T3_READ_REQ)
1081                         return;
1082                 rptr++;
1083         }
1084         wq->oldest_read = NULL;
1085 }
1086
1087 /*
1088  * cxio_poll_cq
1089  *
1090  * Caller must:
1091  *     check the validity of the first CQE,
1092  *     supply the wq assicated with the qpid.
1093  *
1094  * credit: cq credit to return to sge.
1095  * cqe_flushed: 1 iff the CQE is flushed.
1096  * cqe: copy of the polled CQE.
1097  *
1098  * return value:
1099  *     0       CQE returned,
1100  *    -1       CQE skipped, try again.
1101  */
1102 int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
1103                      u8 *cqe_flushed, u64 *cookie, u32 *credit)
1104 {
1105         int ret = 0;
1106         struct t3_cqe *hw_cqe, read_cqe;
1107
1108         *cqe_flushed = 0;
1109         *credit = 0;
1110         hw_cqe = cxio_next_cqe(cq);
1111
1112         PDBG("%s CQE OOO %d qpid 0x%0x genbit %d type %d status 0x%0x"
1113              " opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
1114              __FUNCTION__, CQE_OOO(*hw_cqe), CQE_QPID(*hw_cqe),
1115              CQE_GENBIT(*hw_cqe), CQE_TYPE(*hw_cqe), CQE_STATUS(*hw_cqe),
1116              CQE_OPCODE(*hw_cqe), CQE_LEN(*hw_cqe), CQE_WRID_HI(*hw_cqe),
1117              CQE_WRID_LOW(*hw_cqe));
1118
1119         /*
1120          * skip cqe's not affiliated with a QP.
1121          */
1122         if (wq == NULL) {
1123                 ret = -1;
1124                 goto skip_cqe;
1125         }
1126
1127         /*
1128          * Gotta tweak READ completions:
1129          *      1) the cqe doesn't contain the sq_wptr from the wr.
1130          *      2) opcode not reflected from the wr.
1131          *      3) read_len not reflected from the wr.
1132          *      4) cq_type is RQ_TYPE not SQ_TYPE.
1133          */
1134         if (RQ_TYPE(*hw_cqe) && (CQE_OPCODE(*hw_cqe) == T3_READ_RESP)) {
1135
1136                 /*
1137                  * Don't write to the HWCQ, so create a new read req CQE
1138                  * in local memory.
1139                  */
1140                 create_read_req_cqe(wq, hw_cqe, &read_cqe);
1141                 hw_cqe = &read_cqe;
1142                 advance_oldest_read(wq);
1143         }
1144
1145         /*
1146          * T3A: Discard TERMINATE CQEs.
1147          */
1148         if (CQE_OPCODE(*hw_cqe) == T3_TERMINATE) {
1149                 ret = -1;
1150                 wq->error = 1;
1151                 goto skip_cqe;
1152         }
1153
1154         if (CQE_STATUS(*hw_cqe) || wq->error) {
1155                 *cqe_flushed = wq->error;
1156                 wq->error = 1;
1157
1158                 /*
1159                  * T3A inserts errors into the CQE.  We cannot return
1160                  * these as work completions.
1161                  */
1162                 /* incoming write failures */
1163                 if ((CQE_OPCODE(*hw_cqe) == T3_RDMA_WRITE)
1164                      && RQ_TYPE(*hw_cqe)) {
1165                         ret = -1;
1166                         goto skip_cqe;
1167                 }
1168                 /* incoming read request failures */
1169                 if ((CQE_OPCODE(*hw_cqe) == T3_READ_RESP) && SQ_TYPE(*hw_cqe)) {
1170                         ret = -1;
1171                         goto skip_cqe;
1172                 }
1173
1174                 /* incoming SEND with no receive posted failures */
1175                 if ((CQE_OPCODE(*hw_cqe) == T3_SEND) && RQ_TYPE(*hw_cqe) &&
1176                     Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1177                         ret = -1;
1178                         goto skip_cqe;
1179                 }
1180                 goto proc_cqe;
1181         }
1182
1183         /*
1184          * RECV completion.
1185          */
1186         if (RQ_TYPE(*hw_cqe)) {
1187
1188                 /*
1189                  * HW only validates 4 bits of MSN.  So we must validate that
1190                  * the MSN in the SEND is the next expected MSN.  If its not,
1191                  * then we complete this with TPT_ERR_MSN and mark the wq in
1192                  * error.
1193                  */
1194                 if (unlikely((CQE_WRID_MSN(*hw_cqe) != (wq->rq_rptr + 1)))) {
1195                         wq->error = 1;
1196                         hw_cqe->header |= htonl(V_CQE_STATUS(TPT_ERR_MSN));
1197                         goto proc_cqe;
1198                 }
1199                 goto proc_cqe;
1200         }
1201
1202         /*
1203          * If we get here its a send completion.
1204          *
1205          * Handle out of order completion. These get stuffed
1206          * in the SW SQ. Then the SW SQ is walked to move any
1207          * now in-order completions into the SW CQ.  This handles
1208          * 2 cases:
1209          *      1) reaping unsignaled WRs when the first subsequent
1210          *         signaled WR is completed.
1211          *      2) out of order read completions.
1212          */
1213         if (!SW_CQE(*hw_cqe) && (CQE_WRID_SQ_WPTR(*hw_cqe) != wq->sq_rptr)) {
1214                 struct t3_swsq *sqp;
1215
1216                 PDBG("%s out of order completion going in swsq at idx %ld\n",
1217                      __FUNCTION__,
1218                      Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2));
1219                 sqp = wq->sq +
1220                       Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2);
1221                 sqp->cqe = *hw_cqe;
1222                 sqp->complete = 1;
1223                 ret = -1;
1224                 goto flush_wq;
1225         }
1226
1227 proc_cqe:
1228         *cqe = *hw_cqe;
1229
1230         /*
1231          * Reap the associated WR(s) that are freed up with this
1232          * completion.
1233          */
1234         if (SQ_TYPE(*hw_cqe)) {
1235                 wq->sq_rptr = CQE_WRID_SQ_WPTR(*hw_cqe);
1236                 PDBG("%s completing sq idx %ld\n", __FUNCTION__,
1237                      Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2));
1238                 *cookie = (wq->sq +
1239                            Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2))->wr_id;
1240                 wq->sq_rptr++;
1241         } else {
1242                 PDBG("%s completing rq idx %ld\n", __FUNCTION__,
1243                      Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1244                 *cookie = *(wq->rq + Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1245                 wq->rq_rptr++;
1246         }
1247
1248 flush_wq:
1249         /*
1250          * Flush any completed cqes that are now in-order.
1251          */
1252         flush_completed_wrs(wq, cq);
1253
1254 skip_cqe:
1255         if (SW_CQE(*hw_cqe)) {
1256                 PDBG("%s cq %p cqid 0x%x skip sw cqe sw_rptr 0x%x\n",
1257                      __FUNCTION__, cq, cq->cqid, cq->sw_rptr);
1258                 ++cq->sw_rptr;
1259         } else {
1260                 PDBG("%s cq %p cqid 0x%x skip hw cqe rptr 0x%x\n",
1261                      __FUNCTION__, cq, cq->cqid, cq->rptr);
1262                 ++cq->rptr;
1263
1264                 /*
1265                  * T3A: compute credits.
1266                  */
1267                 if (((cq->rptr - cq->wptr) > (1 << (cq->size_log2 - 1)))
1268                     || ((cq->rptr - cq->wptr) >= 128)) {
1269                         *credit = cq->rptr - cq->wptr;
1270                         cq->wptr = cq->rptr;
1271                 }
1272         }
1273         return ret;
1274 }