553c74e1e4e3f876155d8511ef86b04d9ebb7c67
[linux-3.10.git] / drivers / firewire / ohci.c
1 /*
2  * Driver for OHCI 1394 controllers
3  *
4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software Foundation,
18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/firewire.h>
26 #include <linux/firewire-constants.h>
27 #include <linux/gfp.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/mm.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/pci.h>
37 #include <linux/pci_ids.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
40
41 #include <asm/atomic.h>
42 #include <asm/byteorder.h>
43 #include <asm/page.h>
44 #include <asm/system.h>
45
46 #ifdef CONFIG_PPC_PMAC
47 #include <asm/pmac_feature.h>
48 #endif
49
50 #include "core.h"
51 #include "ohci.h"
52
53 #define DESCRIPTOR_OUTPUT_MORE          0
54 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
55 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
56 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
57 #define DESCRIPTOR_STATUS               (1 << 11)
58 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
59 #define DESCRIPTOR_PING                 (1 << 7)
60 #define DESCRIPTOR_YY                   (1 << 6)
61 #define DESCRIPTOR_NO_IRQ               (0 << 4)
62 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
63 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
64 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
65 #define DESCRIPTOR_WAIT                 (3 << 0)
66
67 struct descriptor {
68         __le16 req_count;
69         __le16 control;
70         __le32 data_address;
71         __le32 branch_address;
72         __le16 res_count;
73         __le16 transfer_status;
74 } __attribute__((aligned(16)));
75
76 struct db_descriptor {
77         __le16 first_size;
78         __le16 control;
79         __le16 second_req_count;
80         __le16 first_req_count;
81         __le32 branch_address;
82         __le16 second_res_count;
83         __le16 first_res_count;
84         __le32 reserved0;
85         __le32 first_buffer;
86         __le32 second_buffer;
87         __le32 reserved1;
88 } __attribute__((aligned(16)));
89
90 #define CONTROL_SET(regs)       (regs)
91 #define CONTROL_CLEAR(regs)     ((regs) + 4)
92 #define COMMAND_PTR(regs)       ((regs) + 12)
93 #define CONTEXT_MATCH(regs)     ((regs) + 16)
94
95 struct ar_buffer {
96         struct descriptor descriptor;
97         struct ar_buffer *next;
98         __le32 data[0];
99 };
100
101 struct ar_context {
102         struct fw_ohci *ohci;
103         struct ar_buffer *current_buffer;
104         struct ar_buffer *last_buffer;
105         void *pointer;
106         u32 regs;
107         struct tasklet_struct tasklet;
108 };
109
110 struct context;
111
112 typedef int (*descriptor_callback_t)(struct context *ctx,
113                                      struct descriptor *d,
114                                      struct descriptor *last);
115
116 /*
117  * A buffer that contains a block of DMA-able coherent memory used for
118  * storing a portion of a DMA descriptor program.
119  */
120 struct descriptor_buffer {
121         struct list_head list;
122         dma_addr_t buffer_bus;
123         size_t buffer_size;
124         size_t used;
125         struct descriptor buffer[0];
126 };
127
128 struct context {
129         struct fw_ohci *ohci;
130         u32 regs;
131         int total_allocation;
132
133         /*
134          * List of page-sized buffers for storing DMA descriptors.
135          * Head of list contains buffers in use and tail of list contains
136          * free buffers.
137          */
138         struct list_head buffer_list;
139
140         /*
141          * Pointer to a buffer inside buffer_list that contains the tail
142          * end of the current DMA program.
143          */
144         struct descriptor_buffer *buffer_tail;
145
146         /*
147          * The descriptor containing the branch address of the first
148          * descriptor that has not yet been filled by the device.
149          */
150         struct descriptor *last;
151
152         /*
153          * The last descriptor in the DMA program.  It contains the branch
154          * address that must be updated upon appending a new descriptor.
155          */
156         struct descriptor *prev;
157
158         descriptor_callback_t callback;
159
160         struct tasklet_struct tasklet;
161 };
162
163 #define IT_HEADER_SY(v)          ((v) <<  0)
164 #define IT_HEADER_TCODE(v)       ((v) <<  4)
165 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
166 #define IT_HEADER_TAG(v)         ((v) << 14)
167 #define IT_HEADER_SPEED(v)       ((v) << 16)
168 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
169
170 struct iso_context {
171         struct fw_iso_context base;
172         struct context context;
173         int excess_bytes;
174         void *header;
175         size_t header_length;
176 };
177
178 #define CONFIG_ROM_SIZE 1024
179
180 struct fw_ohci {
181         struct fw_card card;
182
183         __iomem char *registers;
184         dma_addr_t self_id_bus;
185         __le32 *self_id_cpu;
186         struct tasklet_struct bus_reset_tasklet;
187         int node_id;
188         int generation;
189         int request_generation; /* for timestamping incoming requests */
190         atomic_t bus_seconds;
191
192         bool use_dualbuffer;
193         bool old_uninorth;
194         bool bus_reset_packet_quirk;
195
196         /*
197          * Spinlock for accessing fw_ohci data.  Never call out of
198          * this driver with this lock held.
199          */
200         spinlock_t lock;
201         u32 self_id_buffer[512];
202
203         /* Config rom buffers */
204         __be32 *config_rom;
205         dma_addr_t config_rom_bus;
206         __be32 *next_config_rom;
207         dma_addr_t next_config_rom_bus;
208         __be32 next_header;
209
210         struct ar_context ar_request_ctx;
211         struct ar_context ar_response_ctx;
212         struct context at_request_ctx;
213         struct context at_response_ctx;
214
215         u32 it_context_mask;
216         struct iso_context *it_context_list;
217         u64 ir_context_channels;
218         u32 ir_context_mask;
219         struct iso_context *ir_context_list;
220 };
221
222 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
223 {
224         return container_of(card, struct fw_ohci, card);
225 }
226
227 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
228 #define IR_CONTEXT_BUFFER_FILL          0x80000000
229 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
230 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
231 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
232 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
233
234 #define CONTEXT_RUN     0x8000
235 #define CONTEXT_WAKE    0x1000
236 #define CONTEXT_DEAD    0x0800
237 #define CONTEXT_ACTIVE  0x0400
238
239 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
240 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
241 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
242
243 #define OHCI1394_REGISTER_SIZE          0x800
244 #define OHCI_LOOP_COUNT                 500
245 #define OHCI1394_PCI_HCI_Control        0x40
246 #define SELF_ID_BUF_SIZE                0x800
247 #define OHCI_TCODE_PHY_PACKET           0x0e
248 #define OHCI_VERSION_1_1                0x010010
249
250 static char ohci_driver_name[] = KBUILD_MODNAME;
251
252 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
253
254 #define OHCI_PARAM_DEBUG_AT_AR          1
255 #define OHCI_PARAM_DEBUG_SELFIDS        2
256 #define OHCI_PARAM_DEBUG_IRQS           4
257 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
258
259 static int param_debug;
260 module_param_named(debug, param_debug, int, 0644);
261 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
262         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
263         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
264         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
265         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
266         ", or a combination, or all = -1)");
267
268 static void log_irqs(u32 evt)
269 {
270         if (likely(!(param_debug &
271                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
272                 return;
273
274         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
275             !(evt & OHCI1394_busReset))
276                 return;
277
278         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
279             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
280             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
281             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
282             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
283             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
284             evt & OHCI1394_isochRx              ? " IR"                 : "",
285             evt & OHCI1394_isochTx              ? " IT"                 : "",
286             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
287             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
288             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
289             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
290             evt & OHCI1394_busReset             ? " busReset"           : "",
291             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
292                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
293                     OHCI1394_respTxComplete | OHCI1394_isochRx |
294                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
295                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
296                     OHCI1394_regAccessFail | OHCI1394_busReset)
297                                                 ? " ?"                  : "");
298 }
299
300 static const char *speed[] = {
301         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
302 };
303 static const char *power[] = {
304         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
305         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
306 };
307 static const char port[] = { '.', '-', 'p', 'c', };
308
309 static char _p(u32 *s, int shift)
310 {
311         return port[*s >> shift & 3];
312 }
313
314 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
315 {
316         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
317                 return;
318
319         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
320                   self_id_count, generation, node_id);
321
322         for (; self_id_count--; ++s)
323                 if ((*s & 1 << 23) == 0)
324                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
325                             "%s gc=%d %s %s%s%s\n",
326                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
327                             speed[*s >> 14 & 3], *s >> 16 & 63,
328                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
329                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
330                 else
331                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
332                             *s, *s >> 24 & 63,
333                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
334                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
335 }
336
337 static const char *evts[] = {
338         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
339         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
340         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
341         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
342         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
343         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
344         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
345         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
346         [0x10] = "-reserved-",          [0x11] = "ack_complete",
347         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
348         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
349         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
350         [0x18] = "-reserved-",          [0x19] = "-reserved-",
351         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
352         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
353         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
354         [0x20] = "pending/cancelled",
355 };
356 static const char *tcodes[] = {
357         [0x0] = "QW req",               [0x1] = "BW req",
358         [0x2] = "W resp",               [0x3] = "-reserved-",
359         [0x4] = "QR req",               [0x5] = "BR req",
360         [0x6] = "QR resp",              [0x7] = "BR resp",
361         [0x8] = "cycle start",          [0x9] = "Lk req",
362         [0xa] = "async stream packet",  [0xb] = "Lk resp",
363         [0xc] = "-reserved-",           [0xd] = "-reserved-",
364         [0xe] = "link internal",        [0xf] = "-reserved-",
365 };
366 static const char *phys[] = {
367         [0x0] = "phy config packet",    [0x1] = "link-on packet",
368         [0x2] = "self-id packet",       [0x3] = "-reserved-",
369 };
370
371 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
372 {
373         int tcode = header[0] >> 4 & 0xf;
374         char specific[12];
375
376         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
377                 return;
378
379         if (unlikely(evt >= ARRAY_SIZE(evts)))
380                         evt = 0x1f;
381
382         if (evt == OHCI1394_evt_bus_reset) {
383                 fw_notify("A%c evt_bus_reset, generation %d\n",
384                     dir, (header[2] >> 16) & 0xff);
385                 return;
386         }
387
388         if (header[0] == ~header[1]) {
389                 fw_notify("A%c %s, %s, %08x\n",
390                     dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
391                 return;
392         }
393
394         switch (tcode) {
395         case 0x0: case 0x6: case 0x8:
396                 snprintf(specific, sizeof(specific), " = %08x",
397                          be32_to_cpu((__force __be32)header[3]));
398                 break;
399         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
400                 snprintf(specific, sizeof(specific), " %x,%x",
401                          header[3] >> 16, header[3] & 0xffff);
402                 break;
403         default:
404                 specific[0] = '\0';
405         }
406
407         switch (tcode) {
408         case 0xe: case 0xa:
409                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
410                 break;
411         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
412                 fw_notify("A%c spd %x tl %02x, "
413                     "%04x -> %04x, %s, "
414                     "%s, %04x%08x%s\n",
415                     dir, speed, header[0] >> 10 & 0x3f,
416                     header[1] >> 16, header[0] >> 16, evts[evt],
417                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
418                 break;
419         default:
420                 fw_notify("A%c spd %x tl %02x, "
421                     "%04x -> %04x, %s, "
422                     "%s%s\n",
423                     dir, speed, header[0] >> 10 & 0x3f,
424                     header[1] >> 16, header[0] >> 16, evts[evt],
425                     tcodes[tcode], specific);
426         }
427 }
428
429 #else
430
431 #define log_irqs(evt)
432 #define log_selfids(node_id, generation, self_id_count, sid)
433 #define log_ar_at_event(dir, speed, header, evt)
434
435 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
436
437 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
438 {
439         writel(data, ohci->registers + offset);
440 }
441
442 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
443 {
444         return readl(ohci->registers + offset);
445 }
446
447 static inline void flush_writes(const struct fw_ohci *ohci)
448 {
449         /* Do a dummy read to flush writes. */
450         reg_read(ohci, OHCI1394_Version);
451 }
452
453 static int ohci_update_phy_reg(struct fw_card *card, int addr,
454                                int clear_bits, int set_bits)
455 {
456         struct fw_ohci *ohci = fw_ohci(card);
457         u32 val, old;
458
459         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
460         flush_writes(ohci);
461         msleep(2);
462         val = reg_read(ohci, OHCI1394_PhyControl);
463         if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
464                 fw_error("failed to set phy reg bits.\n");
465                 return -EBUSY;
466         }
467
468         old = OHCI1394_PhyControl_ReadData(val);
469         old = (old & ~clear_bits) | set_bits;
470         reg_write(ohci, OHCI1394_PhyControl,
471                   OHCI1394_PhyControl_Write(addr, old));
472
473         return 0;
474 }
475
476 static int ar_context_add_page(struct ar_context *ctx)
477 {
478         struct device *dev = ctx->ohci->card.device;
479         struct ar_buffer *ab;
480         dma_addr_t uninitialized_var(ab_bus);
481         size_t offset;
482
483         ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
484         if (ab == NULL)
485                 return -ENOMEM;
486
487         ab->next = NULL;
488         memset(&ab->descriptor, 0, sizeof(ab->descriptor));
489         ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
490                                                     DESCRIPTOR_STATUS |
491                                                     DESCRIPTOR_BRANCH_ALWAYS);
492         offset = offsetof(struct ar_buffer, data);
493         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
494         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
495         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
496         ab->descriptor.branch_address = 0;
497
498         ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
499         ctx->last_buffer->next = ab;
500         ctx->last_buffer = ab;
501
502         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
503         flush_writes(ctx->ohci);
504
505         return 0;
506 }
507
508 static void ar_context_release(struct ar_context *ctx)
509 {
510         struct ar_buffer *ab, *ab_next;
511         size_t offset;
512         dma_addr_t ab_bus;
513
514         for (ab = ctx->current_buffer; ab; ab = ab_next) {
515                 ab_next = ab->next;
516                 offset = offsetof(struct ar_buffer, data);
517                 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
518                 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
519                                   ab, ab_bus);
520         }
521 }
522
523 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
524 #define cond_le32_to_cpu(v) \
525         (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
526 #else
527 #define cond_le32_to_cpu(v) le32_to_cpu(v)
528 #endif
529
530 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
531 {
532         struct fw_ohci *ohci = ctx->ohci;
533         struct fw_packet p;
534         u32 status, length, tcode;
535         int evt;
536
537         p.header[0] = cond_le32_to_cpu(buffer[0]);
538         p.header[1] = cond_le32_to_cpu(buffer[1]);
539         p.header[2] = cond_le32_to_cpu(buffer[2]);
540
541         tcode = (p.header[0] >> 4) & 0x0f;
542         switch (tcode) {
543         case TCODE_WRITE_QUADLET_REQUEST:
544         case TCODE_READ_QUADLET_RESPONSE:
545                 p.header[3] = (__force __u32) buffer[3];
546                 p.header_length = 16;
547                 p.payload_length = 0;
548                 break;
549
550         case TCODE_READ_BLOCK_REQUEST :
551                 p.header[3] = cond_le32_to_cpu(buffer[3]);
552                 p.header_length = 16;
553                 p.payload_length = 0;
554                 break;
555
556         case TCODE_WRITE_BLOCK_REQUEST:
557         case TCODE_READ_BLOCK_RESPONSE:
558         case TCODE_LOCK_REQUEST:
559         case TCODE_LOCK_RESPONSE:
560                 p.header[3] = cond_le32_to_cpu(buffer[3]);
561                 p.header_length = 16;
562                 p.payload_length = p.header[3] >> 16;
563                 break;
564
565         case TCODE_WRITE_RESPONSE:
566         case TCODE_READ_QUADLET_REQUEST:
567         case OHCI_TCODE_PHY_PACKET:
568                 p.header_length = 12;
569                 p.payload_length = 0;
570                 break;
571
572         default:
573                 /* FIXME: Stop context, discard everything, and restart? */
574                 p.header_length = 0;
575                 p.payload_length = 0;
576         }
577
578         p.payload = (void *) buffer + p.header_length;
579
580         /* FIXME: What to do about evt_* errors? */
581         length = (p.header_length + p.payload_length + 3) / 4;
582         status = cond_le32_to_cpu(buffer[length]);
583         evt    = (status >> 16) & 0x1f;
584
585         p.ack        = evt - 16;
586         p.speed      = (status >> 21) & 0x7;
587         p.timestamp  = status & 0xffff;
588         p.generation = ohci->request_generation;
589
590         log_ar_at_event('R', p.speed, p.header, evt);
591
592         /*
593          * The OHCI bus reset handler synthesizes a phy packet with
594          * the new generation number when a bus reset happens (see
595          * section 8.4.2.3).  This helps us determine when a request
596          * was received and make sure we send the response in the same
597          * generation.  We only need this for requests; for responses
598          * we use the unique tlabel for finding the matching
599          * request.
600          *
601          * Alas some chips sometimes emit bus reset packets with a
602          * wrong generation.  We set the correct generation for these
603          * at a slightly incorrect time (in bus_reset_tasklet).
604          */
605         if (evt == OHCI1394_evt_bus_reset) {
606                 if (!ohci->bus_reset_packet_quirk)
607                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
608         } else if (ctx == &ohci->ar_request_ctx) {
609                 fw_core_handle_request(&ohci->card, &p);
610         } else {
611                 fw_core_handle_response(&ohci->card, &p);
612         }
613
614         return buffer + length + 1;
615 }
616
617 static void ar_context_tasklet(unsigned long data)
618 {
619         struct ar_context *ctx = (struct ar_context *)data;
620         struct fw_ohci *ohci = ctx->ohci;
621         struct ar_buffer *ab;
622         struct descriptor *d;
623         void *buffer, *end;
624
625         ab = ctx->current_buffer;
626         d = &ab->descriptor;
627
628         if (d->res_count == 0) {
629                 size_t size, rest, offset;
630                 dma_addr_t start_bus;
631                 void *start;
632
633                 /*
634                  * This descriptor is finished and we may have a
635                  * packet split across this and the next buffer. We
636                  * reuse the page for reassembling the split packet.
637                  */
638
639                 offset = offsetof(struct ar_buffer, data);
640                 start = buffer = ab;
641                 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
642
643                 ab = ab->next;
644                 d = &ab->descriptor;
645                 size = buffer + PAGE_SIZE - ctx->pointer;
646                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
647                 memmove(buffer, ctx->pointer, size);
648                 memcpy(buffer + size, ab->data, rest);
649                 ctx->current_buffer = ab;
650                 ctx->pointer = (void *) ab->data + rest;
651                 end = buffer + size + rest;
652
653                 while (buffer < end)
654                         buffer = handle_ar_packet(ctx, buffer);
655
656                 dma_free_coherent(ohci->card.device, PAGE_SIZE,
657                                   start, start_bus);
658                 ar_context_add_page(ctx);
659         } else {
660                 buffer = ctx->pointer;
661                 ctx->pointer = end =
662                         (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
663
664                 while (buffer < end)
665                         buffer = handle_ar_packet(ctx, buffer);
666         }
667 }
668
669 static int ar_context_init(struct ar_context *ctx,
670                            struct fw_ohci *ohci, u32 regs)
671 {
672         struct ar_buffer ab;
673
674         ctx->regs        = regs;
675         ctx->ohci        = ohci;
676         ctx->last_buffer = &ab;
677         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
678
679         ar_context_add_page(ctx);
680         ar_context_add_page(ctx);
681         ctx->current_buffer = ab.next;
682         ctx->pointer = ctx->current_buffer->data;
683
684         return 0;
685 }
686
687 static void ar_context_run(struct ar_context *ctx)
688 {
689         struct ar_buffer *ab = ctx->current_buffer;
690         dma_addr_t ab_bus;
691         size_t offset;
692
693         offset = offsetof(struct ar_buffer, data);
694         ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
695
696         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
697         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
698         flush_writes(ctx->ohci);
699 }
700
701 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
702 {
703         int b, key;
704
705         b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
706         key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
707
708         /* figure out which descriptor the branch address goes in */
709         if (z == 2 && (b == 3 || key == 2))
710                 return d;
711         else
712                 return d + z - 1;
713 }
714
715 static void context_tasklet(unsigned long data)
716 {
717         struct context *ctx = (struct context *) data;
718         struct descriptor *d, *last;
719         u32 address;
720         int z;
721         struct descriptor_buffer *desc;
722
723         desc = list_entry(ctx->buffer_list.next,
724                         struct descriptor_buffer, list);
725         last = ctx->last;
726         while (last->branch_address != 0) {
727                 struct descriptor_buffer *old_desc = desc;
728                 address = le32_to_cpu(last->branch_address);
729                 z = address & 0xf;
730                 address &= ~0xf;
731
732                 /* If the branch address points to a buffer outside of the
733                  * current buffer, advance to the next buffer. */
734                 if (address < desc->buffer_bus ||
735                                 address >= desc->buffer_bus + desc->used)
736                         desc = list_entry(desc->list.next,
737                                         struct descriptor_buffer, list);
738                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
739                 last = find_branch_descriptor(d, z);
740
741                 if (!ctx->callback(ctx, d, last))
742                         break;
743
744                 if (old_desc != desc) {
745                         /* If we've advanced to the next buffer, move the
746                          * previous buffer to the free list. */
747                         unsigned long flags;
748                         old_desc->used = 0;
749                         spin_lock_irqsave(&ctx->ohci->lock, flags);
750                         list_move_tail(&old_desc->list, &ctx->buffer_list);
751                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
752                 }
753                 ctx->last = last;
754         }
755 }
756
757 /*
758  * Allocate a new buffer and add it to the list of free buffers for this
759  * context.  Must be called with ohci->lock held.
760  */
761 static int context_add_buffer(struct context *ctx)
762 {
763         struct descriptor_buffer *desc;
764         dma_addr_t uninitialized_var(bus_addr);
765         int offset;
766
767         /*
768          * 16MB of descriptors should be far more than enough for any DMA
769          * program.  This will catch run-away userspace or DoS attacks.
770          */
771         if (ctx->total_allocation >= 16*1024*1024)
772                 return -ENOMEM;
773
774         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
775                         &bus_addr, GFP_ATOMIC);
776         if (!desc)
777                 return -ENOMEM;
778
779         offset = (void *)&desc->buffer - (void *)desc;
780         desc->buffer_size = PAGE_SIZE - offset;
781         desc->buffer_bus = bus_addr + offset;
782         desc->used = 0;
783
784         list_add_tail(&desc->list, &ctx->buffer_list);
785         ctx->total_allocation += PAGE_SIZE;
786
787         return 0;
788 }
789
790 static int context_init(struct context *ctx, struct fw_ohci *ohci,
791                         u32 regs, descriptor_callback_t callback)
792 {
793         ctx->ohci = ohci;
794         ctx->regs = regs;
795         ctx->total_allocation = 0;
796
797         INIT_LIST_HEAD(&ctx->buffer_list);
798         if (context_add_buffer(ctx) < 0)
799                 return -ENOMEM;
800
801         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
802                         struct descriptor_buffer, list);
803
804         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
805         ctx->callback = callback;
806
807         /*
808          * We put a dummy descriptor in the buffer that has a NULL
809          * branch address and looks like it's been sent.  That way we
810          * have a descriptor to append DMA programs to.
811          */
812         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
813         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
814         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
815         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
816         ctx->last = ctx->buffer_tail->buffer;
817         ctx->prev = ctx->buffer_tail->buffer;
818
819         return 0;
820 }
821
822 static void context_release(struct context *ctx)
823 {
824         struct fw_card *card = &ctx->ohci->card;
825         struct descriptor_buffer *desc, *tmp;
826
827         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
828                 dma_free_coherent(card->device, PAGE_SIZE, desc,
829                         desc->buffer_bus -
830                         ((void *)&desc->buffer - (void *)desc));
831 }
832
833 /* Must be called with ohci->lock held */
834 static struct descriptor *context_get_descriptors(struct context *ctx,
835                                                   int z, dma_addr_t *d_bus)
836 {
837         struct descriptor *d = NULL;
838         struct descriptor_buffer *desc = ctx->buffer_tail;
839
840         if (z * sizeof(*d) > desc->buffer_size)
841                 return NULL;
842
843         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
844                 /* No room for the descriptor in this buffer, so advance to the
845                  * next one. */
846
847                 if (desc->list.next == &ctx->buffer_list) {
848                         /* If there is no free buffer next in the list,
849                          * allocate one. */
850                         if (context_add_buffer(ctx) < 0)
851                                 return NULL;
852                 }
853                 desc = list_entry(desc->list.next,
854                                 struct descriptor_buffer, list);
855                 ctx->buffer_tail = desc;
856         }
857
858         d = desc->buffer + desc->used / sizeof(*d);
859         memset(d, 0, z * sizeof(*d));
860         *d_bus = desc->buffer_bus + desc->used;
861
862         return d;
863 }
864
865 static void context_run(struct context *ctx, u32 extra)
866 {
867         struct fw_ohci *ohci = ctx->ohci;
868
869         reg_write(ohci, COMMAND_PTR(ctx->regs),
870                   le32_to_cpu(ctx->last->branch_address));
871         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
872         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
873         flush_writes(ohci);
874 }
875
876 static void context_append(struct context *ctx,
877                            struct descriptor *d, int z, int extra)
878 {
879         dma_addr_t d_bus;
880         struct descriptor_buffer *desc = ctx->buffer_tail;
881
882         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
883
884         desc->used += (z + extra) * sizeof(*d);
885         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
886         ctx->prev = find_branch_descriptor(d, z);
887
888         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
889         flush_writes(ctx->ohci);
890 }
891
892 static void context_stop(struct context *ctx)
893 {
894         u32 reg;
895         int i;
896
897         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
898         flush_writes(ctx->ohci);
899
900         for (i = 0; i < 10; i++) {
901                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
902                 if ((reg & CONTEXT_ACTIVE) == 0)
903                         return;
904
905                 mdelay(1);
906         }
907         fw_error("Error: DMA context still active (0x%08x)\n", reg);
908 }
909
910 struct driver_data {
911         struct fw_packet *packet;
912 };
913
914 /*
915  * This function apppends a packet to the DMA queue for transmission.
916  * Must always be called with the ochi->lock held to ensure proper
917  * generation handling and locking around packet queue manipulation.
918  */
919 static int at_context_queue_packet(struct context *ctx,
920                                    struct fw_packet *packet)
921 {
922         struct fw_ohci *ohci = ctx->ohci;
923         dma_addr_t d_bus, uninitialized_var(payload_bus);
924         struct driver_data *driver_data;
925         struct descriptor *d, *last;
926         __le32 *header;
927         int z, tcode;
928         u32 reg;
929
930         d = context_get_descriptors(ctx, 4, &d_bus);
931         if (d == NULL) {
932                 packet->ack = RCODE_SEND_ERROR;
933                 return -1;
934         }
935
936         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
937         d[0].res_count = cpu_to_le16(packet->timestamp);
938
939         /*
940          * The DMA format for asyncronous link packets is different
941          * from the IEEE1394 layout, so shift the fields around
942          * accordingly.  If header_length is 8, it's a PHY packet, to
943          * which we need to prepend an extra quadlet.
944          */
945
946         header = (__le32 *) &d[1];
947         switch (packet->header_length) {
948         case 16:
949         case 12:
950                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
951                                         (packet->speed << 16));
952                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
953                                         (packet->header[0] & 0xffff0000));
954                 header[2] = cpu_to_le32(packet->header[2]);
955
956                 tcode = (packet->header[0] >> 4) & 0x0f;
957                 if (TCODE_IS_BLOCK_PACKET(tcode))
958                         header[3] = cpu_to_le32(packet->header[3]);
959                 else
960                         header[3] = (__force __le32) packet->header[3];
961
962                 d[0].req_count = cpu_to_le16(packet->header_length);
963                 break;
964
965         case 8:
966                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
967                                         (packet->speed << 16));
968                 header[1] = cpu_to_le32(packet->header[0]);
969                 header[2] = cpu_to_le32(packet->header[1]);
970                 d[0].req_count = cpu_to_le16(12);
971                 break;
972
973         case 4:
974                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
975                                         (packet->speed << 16));
976                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
977                 d[0].req_count = cpu_to_le16(8);
978                 break;
979
980         default:
981                 /* BUG(); */
982                 packet->ack = RCODE_SEND_ERROR;
983                 return -1;
984         }
985
986         driver_data = (struct driver_data *) &d[3];
987         driver_data->packet = packet;
988         packet->driver_data = driver_data;
989
990         if (packet->payload_length > 0) {
991                 payload_bus =
992                         dma_map_single(ohci->card.device, packet->payload,
993                                        packet->payload_length, DMA_TO_DEVICE);
994                 if (dma_mapping_error(ohci->card.device, payload_bus)) {
995                         packet->ack = RCODE_SEND_ERROR;
996                         return -1;
997                 }
998                 packet->payload_bus     = payload_bus;
999                 packet->payload_mapped  = true;
1000
1001                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1002                 d[2].data_address = cpu_to_le32(payload_bus);
1003                 last = &d[2];
1004                 z = 3;
1005         } else {
1006                 last = &d[0];
1007                 z = 2;
1008         }
1009
1010         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1011                                      DESCRIPTOR_IRQ_ALWAYS |
1012                                      DESCRIPTOR_BRANCH_ALWAYS);
1013
1014         /*
1015          * If the controller and packet generations don't match, we need to
1016          * bail out and try again.  If IntEvent.busReset is set, the AT context
1017          * is halted, so appending to the context and trying to run it is
1018          * futile.  Most controllers do the right thing and just flush the AT
1019          * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1020          * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1021          * up stalling out.  So we just bail out in software and try again
1022          * later, and everyone is happy.
1023          * FIXME: Document how the locking works.
1024          */
1025         if (ohci->generation != packet->generation ||
1026             reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1027                 if (packet->payload_mapped)
1028                         dma_unmap_single(ohci->card.device, payload_bus,
1029                                          packet->payload_length, DMA_TO_DEVICE);
1030                 packet->ack = RCODE_GENERATION;
1031                 return -1;
1032         }
1033
1034         context_append(ctx, d, z, 4 - z);
1035
1036         /* If the context isn't already running, start it up. */
1037         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1038         if ((reg & CONTEXT_RUN) == 0)
1039                 context_run(ctx, 0);
1040
1041         return 0;
1042 }
1043
1044 static int handle_at_packet(struct context *context,
1045                             struct descriptor *d,
1046                             struct descriptor *last)
1047 {
1048         struct driver_data *driver_data;
1049         struct fw_packet *packet;
1050         struct fw_ohci *ohci = context->ohci;
1051         int evt;
1052
1053         if (last->transfer_status == 0)
1054                 /* This descriptor isn't done yet, stop iteration. */
1055                 return 0;
1056
1057         driver_data = (struct driver_data *) &d[3];
1058         packet = driver_data->packet;
1059         if (packet == NULL)
1060                 /* This packet was cancelled, just continue. */
1061                 return 1;
1062
1063         if (packet->payload_mapped)
1064                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1065                                  packet->payload_length, DMA_TO_DEVICE);
1066
1067         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1068         packet->timestamp = le16_to_cpu(last->res_count);
1069
1070         log_ar_at_event('T', packet->speed, packet->header, evt);
1071
1072         switch (evt) {
1073         case OHCI1394_evt_timeout:
1074                 /* Async response transmit timed out. */
1075                 packet->ack = RCODE_CANCELLED;
1076                 break;
1077
1078         case OHCI1394_evt_flushed:
1079                 /*
1080                  * The packet was flushed should give same error as
1081                  * when we try to use a stale generation count.
1082                  */
1083                 packet->ack = RCODE_GENERATION;
1084                 break;
1085
1086         case OHCI1394_evt_missing_ack:
1087                 /*
1088                  * Using a valid (current) generation count, but the
1089                  * node is not on the bus or not sending acks.
1090                  */
1091                 packet->ack = RCODE_NO_ACK;
1092                 break;
1093
1094         case ACK_COMPLETE + 0x10:
1095         case ACK_PENDING + 0x10:
1096         case ACK_BUSY_X + 0x10:
1097         case ACK_BUSY_A + 0x10:
1098         case ACK_BUSY_B + 0x10:
1099         case ACK_DATA_ERROR + 0x10:
1100         case ACK_TYPE_ERROR + 0x10:
1101                 packet->ack = evt - 0x10;
1102                 break;
1103
1104         default:
1105                 packet->ack = RCODE_SEND_ERROR;
1106                 break;
1107         }
1108
1109         packet->callback(packet, &ohci->card, packet->ack);
1110
1111         return 1;
1112 }
1113
1114 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1115 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1116 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1117 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1118 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1119
1120 static void handle_local_rom(struct fw_ohci *ohci,
1121                              struct fw_packet *packet, u32 csr)
1122 {
1123         struct fw_packet response;
1124         int tcode, length, i;
1125
1126         tcode = HEADER_GET_TCODE(packet->header[0]);
1127         if (TCODE_IS_BLOCK_PACKET(tcode))
1128                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1129         else
1130                 length = 4;
1131
1132         i = csr - CSR_CONFIG_ROM;
1133         if (i + length > CONFIG_ROM_SIZE) {
1134                 fw_fill_response(&response, packet->header,
1135                                  RCODE_ADDRESS_ERROR, NULL, 0);
1136         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1137                 fw_fill_response(&response, packet->header,
1138                                  RCODE_TYPE_ERROR, NULL, 0);
1139         } else {
1140                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1141                                  (void *) ohci->config_rom + i, length);
1142         }
1143
1144         fw_core_handle_response(&ohci->card, &response);
1145 }
1146
1147 static void handle_local_lock(struct fw_ohci *ohci,
1148                               struct fw_packet *packet, u32 csr)
1149 {
1150         struct fw_packet response;
1151         int tcode, length, ext_tcode, sel;
1152         __be32 *payload, lock_old;
1153         u32 lock_arg, lock_data;
1154
1155         tcode = HEADER_GET_TCODE(packet->header[0]);
1156         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1157         payload = packet->payload;
1158         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1159
1160         if (tcode == TCODE_LOCK_REQUEST &&
1161             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1162                 lock_arg = be32_to_cpu(payload[0]);
1163                 lock_data = be32_to_cpu(payload[1]);
1164         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1165                 lock_arg = 0;
1166                 lock_data = 0;
1167         } else {
1168                 fw_fill_response(&response, packet->header,
1169                                  RCODE_TYPE_ERROR, NULL, 0);
1170                 goto out;
1171         }
1172
1173         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1174         reg_write(ohci, OHCI1394_CSRData, lock_data);
1175         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1176         reg_write(ohci, OHCI1394_CSRControl, sel);
1177
1178         if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1179                 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1180         else
1181                 fw_notify("swap not done yet\n");
1182
1183         fw_fill_response(&response, packet->header,
1184                          RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1185  out:
1186         fw_core_handle_response(&ohci->card, &response);
1187 }
1188
1189 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1190 {
1191         u64 offset;
1192         u32 csr;
1193
1194         if (ctx == &ctx->ohci->at_request_ctx) {
1195                 packet->ack = ACK_PENDING;
1196                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1197         }
1198
1199         offset =
1200                 ((unsigned long long)
1201                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1202                 packet->header[2];
1203         csr = offset - CSR_REGISTER_BASE;
1204
1205         /* Handle config rom reads. */
1206         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1207                 handle_local_rom(ctx->ohci, packet, csr);
1208         else switch (csr) {
1209         case CSR_BUS_MANAGER_ID:
1210         case CSR_BANDWIDTH_AVAILABLE:
1211         case CSR_CHANNELS_AVAILABLE_HI:
1212         case CSR_CHANNELS_AVAILABLE_LO:
1213                 handle_local_lock(ctx->ohci, packet, csr);
1214                 break;
1215         default:
1216                 if (ctx == &ctx->ohci->at_request_ctx)
1217                         fw_core_handle_request(&ctx->ohci->card, packet);
1218                 else
1219                         fw_core_handle_response(&ctx->ohci->card, packet);
1220                 break;
1221         }
1222
1223         if (ctx == &ctx->ohci->at_response_ctx) {
1224                 packet->ack = ACK_COMPLETE;
1225                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1226         }
1227 }
1228
1229 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1230 {
1231         unsigned long flags;
1232         int ret;
1233
1234         spin_lock_irqsave(&ctx->ohci->lock, flags);
1235
1236         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1237             ctx->ohci->generation == packet->generation) {
1238                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1239                 handle_local_request(ctx, packet);
1240                 return;
1241         }
1242
1243         ret = at_context_queue_packet(ctx, packet);
1244         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1245
1246         if (ret < 0)
1247                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1248
1249 }
1250
1251 static void bus_reset_tasklet(unsigned long data)
1252 {
1253         struct fw_ohci *ohci = (struct fw_ohci *)data;
1254         int self_id_count, i, j, reg;
1255         int generation, new_generation;
1256         unsigned long flags;
1257         void *free_rom = NULL;
1258         dma_addr_t free_rom_bus = 0;
1259
1260         reg = reg_read(ohci, OHCI1394_NodeID);
1261         if (!(reg & OHCI1394_NodeID_idValid)) {
1262                 fw_notify("node ID not valid, new bus reset in progress\n");
1263                 return;
1264         }
1265         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1266                 fw_notify("malconfigured bus\n");
1267                 return;
1268         }
1269         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1270                                OHCI1394_NodeID_nodeNumber);
1271
1272         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1273         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1274                 fw_notify("inconsistent self IDs\n");
1275                 return;
1276         }
1277         /*
1278          * The count in the SelfIDCount register is the number of
1279          * bytes in the self ID receive buffer.  Since we also receive
1280          * the inverted quadlets and a header quadlet, we shift one
1281          * bit extra to get the actual number of self IDs.
1282          */
1283         self_id_count = (reg >> 3) & 0xff;
1284         if (self_id_count == 0 || self_id_count > 252) {
1285                 fw_notify("inconsistent self IDs\n");
1286                 return;
1287         }
1288         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1289         rmb();
1290
1291         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1292                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1293                         fw_notify("inconsistent self IDs\n");
1294                         return;
1295                 }
1296                 ohci->self_id_buffer[j] =
1297                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1298         }
1299         rmb();
1300
1301         /*
1302          * Check the consistency of the self IDs we just read.  The
1303          * problem we face is that a new bus reset can start while we
1304          * read out the self IDs from the DMA buffer. If this happens,
1305          * the DMA buffer will be overwritten with new self IDs and we
1306          * will read out inconsistent data.  The OHCI specification
1307          * (section 11.2) recommends a technique similar to
1308          * linux/seqlock.h, where we remember the generation of the
1309          * self IDs in the buffer before reading them out and compare
1310          * it to the current generation after reading them out.  If
1311          * the two generations match we know we have a consistent set
1312          * of self IDs.
1313          */
1314
1315         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1316         if (new_generation != generation) {
1317                 fw_notify("recursive bus reset detected, "
1318                           "discarding self ids\n");
1319                 return;
1320         }
1321
1322         /* FIXME: Document how the locking works. */
1323         spin_lock_irqsave(&ohci->lock, flags);
1324
1325         ohci->generation = generation;
1326         context_stop(&ohci->at_request_ctx);
1327         context_stop(&ohci->at_response_ctx);
1328         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1329
1330         if (ohci->bus_reset_packet_quirk)
1331                 ohci->request_generation = generation;
1332
1333         /*
1334          * This next bit is unrelated to the AT context stuff but we
1335          * have to do it under the spinlock also.  If a new config rom
1336          * was set up before this reset, the old one is now no longer
1337          * in use and we can free it. Update the config rom pointers
1338          * to point to the current config rom and clear the
1339          * next_config_rom pointer so a new udpate can take place.
1340          */
1341
1342         if (ohci->next_config_rom != NULL) {
1343                 if (ohci->next_config_rom != ohci->config_rom) {
1344                         free_rom      = ohci->config_rom;
1345                         free_rom_bus  = ohci->config_rom_bus;
1346                 }
1347                 ohci->config_rom      = ohci->next_config_rom;
1348                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1349                 ohci->next_config_rom = NULL;
1350
1351                 /*
1352                  * Restore config_rom image and manually update
1353                  * config_rom registers.  Writing the header quadlet
1354                  * will indicate that the config rom is ready, so we
1355                  * do that last.
1356                  */
1357                 reg_write(ohci, OHCI1394_BusOptions,
1358                           be32_to_cpu(ohci->config_rom[2]));
1359                 ohci->config_rom[0] = ohci->next_header;
1360                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1361                           be32_to_cpu(ohci->next_header));
1362         }
1363
1364 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1365         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1366         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1367 #endif
1368
1369         spin_unlock_irqrestore(&ohci->lock, flags);
1370
1371         if (free_rom)
1372                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1373                                   free_rom, free_rom_bus);
1374
1375         log_selfids(ohci->node_id, generation,
1376                     self_id_count, ohci->self_id_buffer);
1377
1378         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1379                                  self_id_count, ohci->self_id_buffer);
1380 }
1381
1382 static irqreturn_t irq_handler(int irq, void *data)
1383 {
1384         struct fw_ohci *ohci = data;
1385         u32 event, iso_event, cycle_time;
1386         int i;
1387
1388         event = reg_read(ohci, OHCI1394_IntEventClear);
1389
1390         if (!event || !~event)
1391                 return IRQ_NONE;
1392
1393         /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1394         reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1395         log_irqs(event);
1396
1397         if (event & OHCI1394_selfIDComplete)
1398                 tasklet_schedule(&ohci->bus_reset_tasklet);
1399
1400         if (event & OHCI1394_RQPkt)
1401                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1402
1403         if (event & OHCI1394_RSPkt)
1404                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1405
1406         if (event & OHCI1394_reqTxComplete)
1407                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1408
1409         if (event & OHCI1394_respTxComplete)
1410                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1411
1412         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1413         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1414
1415         while (iso_event) {
1416                 i = ffs(iso_event) - 1;
1417                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1418                 iso_event &= ~(1 << i);
1419         }
1420
1421         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1422         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1423
1424         while (iso_event) {
1425                 i = ffs(iso_event) - 1;
1426                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1427                 iso_event &= ~(1 << i);
1428         }
1429
1430         if (unlikely(event & OHCI1394_regAccessFail))
1431                 fw_error("Register access failure - "
1432                          "please notify linux1394-devel@lists.sf.net\n");
1433
1434         if (unlikely(event & OHCI1394_postedWriteErr))
1435                 fw_error("PCI posted write error\n");
1436
1437         if (unlikely(event & OHCI1394_cycleTooLong)) {
1438                 if (printk_ratelimit())
1439                         fw_notify("isochronous cycle too long\n");
1440                 reg_write(ohci, OHCI1394_LinkControlSet,
1441                           OHCI1394_LinkControl_cycleMaster);
1442         }
1443
1444         if (event & OHCI1394_cycle64Seconds) {
1445                 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1446                 if ((cycle_time & 0x80000000) == 0)
1447                         atomic_inc(&ohci->bus_seconds);
1448         }
1449
1450         return IRQ_HANDLED;
1451 }
1452
1453 static int software_reset(struct fw_ohci *ohci)
1454 {
1455         int i;
1456
1457         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1458
1459         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1460                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1461                      OHCI1394_HCControl_softReset) == 0)
1462                         return 0;
1463                 msleep(1);
1464         }
1465
1466         return -EBUSY;
1467 }
1468
1469 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1470 {
1471         size_t size = length * 4;
1472
1473         memcpy(dest, src, size);
1474         if (size < CONFIG_ROM_SIZE)
1475                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1476 }
1477
1478 static int ohci_enable(struct fw_card *card,
1479                        const __be32 *config_rom, size_t length)
1480 {
1481         struct fw_ohci *ohci = fw_ohci(card);
1482         struct pci_dev *dev = to_pci_dev(card->device);
1483         u32 lps;
1484         int i;
1485
1486         if (software_reset(ohci)) {
1487                 fw_error("Failed to reset ohci card.\n");
1488                 return -EBUSY;
1489         }
1490
1491         /*
1492          * Now enable LPS, which we need in order to start accessing
1493          * most of the registers.  In fact, on some cards (ALI M5251),
1494          * accessing registers in the SClk domain without LPS enabled
1495          * will lock up the machine.  Wait 50msec to make sure we have
1496          * full link enabled.  However, with some cards (well, at least
1497          * a JMicron PCIe card), we have to try again sometimes.
1498          */
1499         reg_write(ohci, OHCI1394_HCControlSet,
1500                   OHCI1394_HCControl_LPS |
1501                   OHCI1394_HCControl_postedWriteEnable);
1502         flush_writes(ohci);
1503
1504         for (lps = 0, i = 0; !lps && i < 3; i++) {
1505                 msleep(50);
1506                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1507                       OHCI1394_HCControl_LPS;
1508         }
1509
1510         if (!lps) {
1511                 fw_error("Failed to set Link Power Status\n");
1512                 return -EIO;
1513         }
1514
1515         reg_write(ohci, OHCI1394_HCControlClear,
1516                   OHCI1394_HCControl_noByteSwapData);
1517
1518         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1519         reg_write(ohci, OHCI1394_LinkControlClear,
1520                   OHCI1394_LinkControl_rcvPhyPkt);
1521         reg_write(ohci, OHCI1394_LinkControlSet,
1522                   OHCI1394_LinkControl_rcvSelfID |
1523                   OHCI1394_LinkControl_cycleTimerEnable |
1524                   OHCI1394_LinkControl_cycleMaster);
1525
1526         reg_write(ohci, OHCI1394_ATRetries,
1527                   OHCI1394_MAX_AT_REQ_RETRIES |
1528                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1529                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1530
1531         ar_context_run(&ohci->ar_request_ctx);
1532         ar_context_run(&ohci->ar_response_ctx);
1533
1534         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1535         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1536         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1537         reg_write(ohci, OHCI1394_IntMaskSet,
1538                   OHCI1394_selfIDComplete |
1539                   OHCI1394_RQPkt | OHCI1394_RSPkt |
1540                   OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1541                   OHCI1394_isochRx | OHCI1394_isochTx |
1542                   OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1543                   OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
1544                   OHCI1394_masterIntEnable);
1545         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1546                 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1547
1548         /* Activate link_on bit and contender bit in our self ID packets.*/
1549         if (ohci_update_phy_reg(card, 4, 0,
1550                                 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1551                 return -EIO;
1552
1553         /*
1554          * When the link is not yet enabled, the atomic config rom
1555          * update mechanism described below in ohci_set_config_rom()
1556          * is not active.  We have to update ConfigRomHeader and
1557          * BusOptions manually, and the write to ConfigROMmap takes
1558          * effect immediately.  We tie this to the enabling of the
1559          * link, so we have a valid config rom before enabling - the
1560          * OHCI requires that ConfigROMhdr and BusOptions have valid
1561          * values before enabling.
1562          *
1563          * However, when the ConfigROMmap is written, some controllers
1564          * always read back quadlets 0 and 2 from the config rom to
1565          * the ConfigRomHeader and BusOptions registers on bus reset.
1566          * They shouldn't do that in this initial case where the link
1567          * isn't enabled.  This means we have to use the same
1568          * workaround here, setting the bus header to 0 and then write
1569          * the right values in the bus reset tasklet.
1570          */
1571
1572         if (config_rom) {
1573                 ohci->next_config_rom =
1574                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1575                                            &ohci->next_config_rom_bus,
1576                                            GFP_KERNEL);
1577                 if (ohci->next_config_rom == NULL)
1578                         return -ENOMEM;
1579
1580                 copy_config_rom(ohci->next_config_rom, config_rom, length);
1581         } else {
1582                 /*
1583                  * In the suspend case, config_rom is NULL, which
1584                  * means that we just reuse the old config rom.
1585                  */
1586                 ohci->next_config_rom = ohci->config_rom;
1587                 ohci->next_config_rom_bus = ohci->config_rom_bus;
1588         }
1589
1590         ohci->next_header = ohci->next_config_rom[0];
1591         ohci->next_config_rom[0] = 0;
1592         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1593         reg_write(ohci, OHCI1394_BusOptions,
1594                   be32_to_cpu(ohci->next_config_rom[2]));
1595         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1596
1597         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1598
1599         if (request_irq(dev->irq, irq_handler,
1600                         IRQF_SHARED, ohci_driver_name, ohci)) {
1601                 fw_error("Failed to allocate shared interrupt %d.\n",
1602                          dev->irq);
1603                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1604                                   ohci->config_rom, ohci->config_rom_bus);
1605                 return -EIO;
1606         }
1607
1608         reg_write(ohci, OHCI1394_HCControlSet,
1609                   OHCI1394_HCControl_linkEnable |
1610                   OHCI1394_HCControl_BIBimageValid);
1611         flush_writes(ohci);
1612
1613         /*
1614          * We are ready to go, initiate bus reset to finish the
1615          * initialization.
1616          */
1617
1618         fw_core_initiate_bus_reset(&ohci->card, 1);
1619
1620         return 0;
1621 }
1622
1623 static int ohci_set_config_rom(struct fw_card *card,
1624                                const __be32 *config_rom, size_t length)
1625 {
1626         struct fw_ohci *ohci;
1627         unsigned long flags;
1628         int ret = -EBUSY;
1629         __be32 *next_config_rom;
1630         dma_addr_t uninitialized_var(next_config_rom_bus);
1631
1632         ohci = fw_ohci(card);
1633
1634         /*
1635          * When the OHCI controller is enabled, the config rom update
1636          * mechanism is a bit tricky, but easy enough to use.  See
1637          * section 5.5.6 in the OHCI specification.
1638          *
1639          * The OHCI controller caches the new config rom address in a
1640          * shadow register (ConfigROMmapNext) and needs a bus reset
1641          * for the changes to take place.  When the bus reset is
1642          * detected, the controller loads the new values for the
1643          * ConfigRomHeader and BusOptions registers from the specified
1644          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1645          * shadow register. All automatically and atomically.
1646          *
1647          * Now, there's a twist to this story.  The automatic load of
1648          * ConfigRomHeader and BusOptions doesn't honor the
1649          * noByteSwapData bit, so with a be32 config rom, the
1650          * controller will load be32 values in to these registers
1651          * during the atomic update, even on litte endian
1652          * architectures.  The workaround we use is to put a 0 in the
1653          * header quadlet; 0 is endian agnostic and means that the
1654          * config rom isn't ready yet.  In the bus reset tasklet we
1655          * then set up the real values for the two registers.
1656          *
1657          * We use ohci->lock to avoid racing with the code that sets
1658          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1659          */
1660
1661         next_config_rom =
1662                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1663                                    &next_config_rom_bus, GFP_KERNEL);
1664         if (next_config_rom == NULL)
1665                 return -ENOMEM;
1666
1667         spin_lock_irqsave(&ohci->lock, flags);
1668
1669         if (ohci->next_config_rom == NULL) {
1670                 ohci->next_config_rom = next_config_rom;
1671                 ohci->next_config_rom_bus = next_config_rom_bus;
1672
1673                 copy_config_rom(ohci->next_config_rom, config_rom, length);
1674
1675                 ohci->next_header = config_rom[0];
1676                 ohci->next_config_rom[0] = 0;
1677
1678                 reg_write(ohci, OHCI1394_ConfigROMmap,
1679                           ohci->next_config_rom_bus);
1680                 ret = 0;
1681         }
1682
1683         spin_unlock_irqrestore(&ohci->lock, flags);
1684
1685         /*
1686          * Now initiate a bus reset to have the changes take
1687          * effect. We clean up the old config rom memory and DMA
1688          * mappings in the bus reset tasklet, since the OHCI
1689          * controller could need to access it before the bus reset
1690          * takes effect.
1691          */
1692         if (ret == 0)
1693                 fw_core_initiate_bus_reset(&ohci->card, 1);
1694         else
1695                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1696                                   next_config_rom, next_config_rom_bus);
1697
1698         return ret;
1699 }
1700
1701 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1702 {
1703         struct fw_ohci *ohci = fw_ohci(card);
1704
1705         at_context_transmit(&ohci->at_request_ctx, packet);
1706 }
1707
1708 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1709 {
1710         struct fw_ohci *ohci = fw_ohci(card);
1711
1712         at_context_transmit(&ohci->at_response_ctx, packet);
1713 }
1714
1715 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1716 {
1717         struct fw_ohci *ohci = fw_ohci(card);
1718         struct context *ctx = &ohci->at_request_ctx;
1719         struct driver_data *driver_data = packet->driver_data;
1720         int ret = -ENOENT;
1721
1722         tasklet_disable(&ctx->tasklet);
1723
1724         if (packet->ack != 0)
1725                 goto out;
1726
1727         if (packet->payload_mapped)
1728                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1729                                  packet->payload_length, DMA_TO_DEVICE);
1730
1731         log_ar_at_event('T', packet->speed, packet->header, 0x20);
1732         driver_data->packet = NULL;
1733         packet->ack = RCODE_CANCELLED;
1734         packet->callback(packet, &ohci->card, packet->ack);
1735         ret = 0;
1736  out:
1737         tasklet_enable(&ctx->tasklet);
1738
1739         return ret;
1740 }
1741
1742 static int ohci_enable_phys_dma(struct fw_card *card,
1743                                 int node_id, int generation)
1744 {
1745 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1746         return 0;
1747 #else
1748         struct fw_ohci *ohci = fw_ohci(card);
1749         unsigned long flags;
1750         int n, ret = 0;
1751
1752         /*
1753          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
1754          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
1755          */
1756
1757         spin_lock_irqsave(&ohci->lock, flags);
1758
1759         if (ohci->generation != generation) {
1760                 ret = -ESTALE;
1761                 goto out;
1762         }
1763
1764         /*
1765          * Note, if the node ID contains a non-local bus ID, physical DMA is
1766          * enabled for _all_ nodes on remote buses.
1767          */
1768
1769         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1770         if (n < 32)
1771                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1772         else
1773                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1774
1775         flush_writes(ohci);
1776  out:
1777         spin_unlock_irqrestore(&ohci->lock, flags);
1778
1779         return ret;
1780 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1781 }
1782
1783 static u64 ohci_get_bus_time(struct fw_card *card)
1784 {
1785         struct fw_ohci *ohci = fw_ohci(card);
1786         u32 cycle_time;
1787         u64 bus_time;
1788
1789         cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1790         bus_time = ((u64)atomic_read(&ohci->bus_seconds) << 32) | cycle_time;
1791
1792         return bus_time;
1793 }
1794
1795 static void copy_iso_headers(struct iso_context *ctx, void *p)
1796 {
1797         int i = ctx->header_length;
1798
1799         if (i + ctx->base.header_size > PAGE_SIZE)
1800                 return;
1801
1802         /*
1803          * The iso header is byteswapped to little endian by
1804          * the controller, but the remaining header quadlets
1805          * are big endian.  We want to present all the headers
1806          * as big endian, so we have to swap the first quadlet.
1807          */
1808         if (ctx->base.header_size > 0)
1809                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1810         if (ctx->base.header_size > 4)
1811                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
1812         if (ctx->base.header_size > 8)
1813                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
1814         ctx->header_length += ctx->base.header_size;
1815 }
1816
1817 static int handle_ir_dualbuffer_packet(struct context *context,
1818                                        struct descriptor *d,
1819                                        struct descriptor *last)
1820 {
1821         struct iso_context *ctx =
1822                 container_of(context, struct iso_context, context);
1823         struct db_descriptor *db = (struct db_descriptor *) d;
1824         __le32 *ir_header;
1825         size_t header_length;
1826         void *p, *end;
1827
1828         if (db->first_res_count != 0 && db->second_res_count != 0) {
1829                 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1830                         /* This descriptor isn't done yet, stop iteration. */
1831                         return 0;
1832                 }
1833                 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1834         }
1835
1836         header_length = le16_to_cpu(db->first_req_count) -
1837                 le16_to_cpu(db->first_res_count);
1838
1839         p = db + 1;
1840         end = p + header_length;
1841         while (p < end) {
1842                 copy_iso_headers(ctx, p);
1843                 ctx->excess_bytes +=
1844                         (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1845                 p += max(ctx->base.header_size, (size_t)8);
1846         }
1847
1848         ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1849                 le16_to_cpu(db->second_res_count);
1850
1851         if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1852                 ir_header = (__le32 *) (db + 1);
1853                 ctx->base.callback(&ctx->base,
1854                                    le32_to_cpu(ir_header[0]) & 0xffff,
1855                                    ctx->header_length, ctx->header,
1856                                    ctx->base.callback_data);
1857                 ctx->header_length = 0;
1858         }
1859
1860         return 1;
1861 }
1862
1863 static int handle_ir_packet_per_buffer(struct context *context,
1864                                        struct descriptor *d,
1865                                        struct descriptor *last)
1866 {
1867         struct iso_context *ctx =
1868                 container_of(context, struct iso_context, context);
1869         struct descriptor *pd;
1870         __le32 *ir_header;
1871         void *p;
1872
1873         for (pd = d; pd <= last; pd++) {
1874                 if (pd->transfer_status)
1875                         break;
1876         }
1877         if (pd > last)
1878                 /* Descriptor(s) not done yet, stop iteration */
1879                 return 0;
1880
1881         p = last + 1;
1882         copy_iso_headers(ctx, p);
1883
1884         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1885                 ir_header = (__le32 *) p;
1886                 ctx->base.callback(&ctx->base,
1887                                    le32_to_cpu(ir_header[0]) & 0xffff,
1888                                    ctx->header_length, ctx->header,
1889                                    ctx->base.callback_data);
1890                 ctx->header_length = 0;
1891         }
1892
1893         return 1;
1894 }
1895
1896 static int handle_it_packet(struct context *context,
1897                             struct descriptor *d,
1898                             struct descriptor *last)
1899 {
1900         struct iso_context *ctx =
1901                 container_of(context, struct iso_context, context);
1902
1903         if (last->transfer_status == 0)
1904                 /* This descriptor isn't done yet, stop iteration. */
1905                 return 0;
1906
1907         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1908                 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1909                                    0, NULL, ctx->base.callback_data);
1910
1911         return 1;
1912 }
1913
1914 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
1915                                 int type, int channel, size_t header_size)
1916 {
1917         struct fw_ohci *ohci = fw_ohci(card);
1918         struct iso_context *ctx, *list;
1919         descriptor_callback_t callback;
1920         u64 *channels, dont_care = ~0ULL;
1921         u32 *mask, regs;
1922         unsigned long flags;
1923         int index, ret = -ENOMEM;
1924
1925         if (type == FW_ISO_CONTEXT_TRANSMIT) {
1926                 channels = &dont_care;
1927                 mask = &ohci->it_context_mask;
1928                 list = ohci->it_context_list;
1929                 callback = handle_it_packet;
1930         } else {
1931                 channels = &ohci->ir_context_channels;
1932                 mask = &ohci->ir_context_mask;
1933                 list = ohci->ir_context_list;
1934                 if (ohci->use_dualbuffer)
1935                         callback = handle_ir_dualbuffer_packet;
1936                 else
1937                         callback = handle_ir_packet_per_buffer;
1938         }
1939
1940         spin_lock_irqsave(&ohci->lock, flags);
1941         index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
1942         if (index >= 0) {
1943                 *channels &= ~(1ULL << channel);
1944                 *mask &= ~(1 << index);
1945         }
1946         spin_unlock_irqrestore(&ohci->lock, flags);
1947
1948         if (index < 0)
1949                 return ERR_PTR(-EBUSY);
1950
1951         if (type == FW_ISO_CONTEXT_TRANSMIT)
1952                 regs = OHCI1394_IsoXmitContextBase(index);
1953         else
1954                 regs = OHCI1394_IsoRcvContextBase(index);
1955
1956         ctx = &list[index];
1957         memset(ctx, 0, sizeof(*ctx));
1958         ctx->header_length = 0;
1959         ctx->header = (void *) __get_free_page(GFP_KERNEL);
1960         if (ctx->header == NULL)
1961                 goto out;
1962
1963         ret = context_init(&ctx->context, ohci, regs, callback);
1964         if (ret < 0)
1965                 goto out_with_header;
1966
1967         return &ctx->base;
1968
1969  out_with_header:
1970         free_page((unsigned long)ctx->header);
1971  out:
1972         spin_lock_irqsave(&ohci->lock, flags);
1973         *mask |= 1 << index;
1974         spin_unlock_irqrestore(&ohci->lock, flags);
1975
1976         return ERR_PTR(ret);
1977 }
1978
1979 static int ohci_start_iso(struct fw_iso_context *base,
1980                           s32 cycle, u32 sync, u32 tags)
1981 {
1982         struct iso_context *ctx = container_of(base, struct iso_context, base);
1983         struct fw_ohci *ohci = ctx->context.ohci;
1984         u32 control, match;
1985         int index;
1986
1987         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1988                 index = ctx - ohci->it_context_list;
1989                 match = 0;
1990                 if (cycle >= 0)
1991                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1992                                 (cycle & 0x7fff) << 16;
1993
1994                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1995                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1996                 context_run(&ctx->context, match);
1997         } else {
1998                 index = ctx - ohci->ir_context_list;
1999                 control = IR_CONTEXT_ISOCH_HEADER;
2000                 if (ohci->use_dualbuffer)
2001                         control |= IR_CONTEXT_DUAL_BUFFER_MODE;
2002                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2003                 if (cycle >= 0) {
2004                         match |= (cycle & 0x07fff) << 12;
2005                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2006                 }
2007
2008                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2009                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2010                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2011                 context_run(&ctx->context, control);
2012         }
2013
2014         return 0;
2015 }
2016
2017 static int ohci_stop_iso(struct fw_iso_context *base)
2018 {
2019         struct fw_ohci *ohci = fw_ohci(base->card);
2020         struct iso_context *ctx = container_of(base, struct iso_context, base);
2021         int index;
2022
2023         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2024                 index = ctx - ohci->it_context_list;
2025                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2026         } else {
2027                 index = ctx - ohci->ir_context_list;
2028                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2029         }
2030         flush_writes(ohci);
2031         context_stop(&ctx->context);
2032
2033         return 0;
2034 }
2035
2036 static void ohci_free_iso_context(struct fw_iso_context *base)
2037 {
2038         struct fw_ohci *ohci = fw_ohci(base->card);
2039         struct iso_context *ctx = container_of(base, struct iso_context, base);
2040         unsigned long flags;
2041         int index;
2042
2043         ohci_stop_iso(base);
2044         context_release(&ctx->context);
2045         free_page((unsigned long)ctx->header);
2046
2047         spin_lock_irqsave(&ohci->lock, flags);
2048
2049         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2050                 index = ctx - ohci->it_context_list;
2051                 ohci->it_context_mask |= 1 << index;
2052         } else {
2053                 index = ctx - ohci->ir_context_list;
2054                 ohci->ir_context_mask |= 1 << index;
2055                 ohci->ir_context_channels |= 1ULL << base->channel;
2056         }
2057
2058         spin_unlock_irqrestore(&ohci->lock, flags);
2059 }
2060
2061 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2062                                    struct fw_iso_packet *packet,
2063                                    struct fw_iso_buffer *buffer,
2064                                    unsigned long payload)
2065 {
2066         struct iso_context *ctx = container_of(base, struct iso_context, base);
2067         struct descriptor *d, *last, *pd;
2068         struct fw_iso_packet *p;
2069         __le32 *header;
2070         dma_addr_t d_bus, page_bus;
2071         u32 z, header_z, payload_z, irq;
2072         u32 payload_index, payload_end_index, next_page_index;
2073         int page, end_page, i, length, offset;
2074
2075         /*
2076          * FIXME: Cycle lost behavior should be configurable: lose
2077          * packet, retransmit or terminate..
2078          */
2079
2080         p = packet;
2081         payload_index = payload;
2082
2083         if (p->skip)
2084                 z = 1;
2085         else
2086                 z = 2;
2087         if (p->header_length > 0)
2088                 z++;
2089
2090         /* Determine the first page the payload isn't contained in. */
2091         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2092         if (p->payload_length > 0)
2093                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2094         else
2095                 payload_z = 0;
2096
2097         z += payload_z;
2098
2099         /* Get header size in number of descriptors. */
2100         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2101
2102         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2103         if (d == NULL)
2104                 return -ENOMEM;
2105
2106         if (!p->skip) {
2107                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2108                 d[0].req_count = cpu_to_le16(8);
2109
2110                 header = (__le32 *) &d[1];
2111                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2112                                         IT_HEADER_TAG(p->tag) |
2113                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2114                                         IT_HEADER_CHANNEL(ctx->base.channel) |
2115                                         IT_HEADER_SPEED(ctx->base.speed));
2116                 header[1] =
2117                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2118                                                           p->payload_length));
2119         }
2120
2121         if (p->header_length > 0) {
2122                 d[2].req_count    = cpu_to_le16(p->header_length);
2123                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2124                 memcpy(&d[z], p->header, p->header_length);
2125         }
2126
2127         pd = d + z - payload_z;
2128         payload_end_index = payload_index + p->payload_length;
2129         for (i = 0; i < payload_z; i++) {
2130                 page               = payload_index >> PAGE_SHIFT;
2131                 offset             = payload_index & ~PAGE_MASK;
2132                 next_page_index    = (page + 1) << PAGE_SHIFT;
2133                 length             =
2134                         min(next_page_index, payload_end_index) - payload_index;
2135                 pd[i].req_count    = cpu_to_le16(length);
2136
2137                 page_bus = page_private(buffer->pages[page]);
2138                 pd[i].data_address = cpu_to_le32(page_bus + offset);
2139
2140                 payload_index += length;
2141         }
2142
2143         if (p->interrupt)
2144                 irq = DESCRIPTOR_IRQ_ALWAYS;
2145         else
2146                 irq = DESCRIPTOR_NO_IRQ;
2147
2148         last = z == 2 ? d : d + z - 1;
2149         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2150                                      DESCRIPTOR_STATUS |
2151                                      DESCRIPTOR_BRANCH_ALWAYS |
2152                                      irq);
2153
2154         context_append(&ctx->context, d, z, header_z);
2155
2156         return 0;
2157 }
2158
2159 static int ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2160                                              struct fw_iso_packet *packet,
2161                                              struct fw_iso_buffer *buffer,
2162                                              unsigned long payload)
2163 {
2164         struct iso_context *ctx = container_of(base, struct iso_context, base);
2165         struct db_descriptor *db = NULL;
2166         struct descriptor *d;
2167         struct fw_iso_packet *p;
2168         dma_addr_t d_bus, page_bus;
2169         u32 z, header_z, length, rest;
2170         int page, offset, packet_count, header_size;
2171
2172         /*
2173          * FIXME: Cycle lost behavior should be configurable: lose
2174          * packet, retransmit or terminate..
2175          */
2176
2177         p = packet;
2178         z = 2;
2179
2180         /*
2181          * The OHCI controller puts the isochronous header and trailer in the
2182          * buffer, so we need at least 8 bytes.
2183          */
2184         packet_count = p->header_length / ctx->base.header_size;
2185         header_size = packet_count * max(ctx->base.header_size, (size_t)8);
2186
2187         /* Get header size in number of descriptors. */
2188         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2189         page     = payload >> PAGE_SHIFT;
2190         offset   = payload & ~PAGE_MASK;
2191         rest     = p->payload_length;
2192         /*
2193          * The controllers I've tested have not worked correctly when
2194          * second_req_count is zero.  Rather than do something we know won't
2195          * work, return an error
2196          */
2197         if (rest == 0)
2198                 return -EINVAL;
2199
2200         /* FIXME: make packet-per-buffer/dual-buffer a context option */
2201         while (rest > 0) {
2202                 d = context_get_descriptors(&ctx->context,
2203                                             z + header_z, &d_bus);
2204                 if (d == NULL)
2205                         return -ENOMEM;
2206
2207                 db = (struct db_descriptor *) d;
2208                 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2209                                           DESCRIPTOR_BRANCH_ALWAYS);
2210                 db->first_size =
2211                     cpu_to_le16(max(ctx->base.header_size, (size_t)8));
2212                 if (p->skip && rest == p->payload_length) {
2213                         db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2214                         db->first_req_count = db->first_size;
2215                 } else {
2216                         db->first_req_count = cpu_to_le16(header_size);
2217                 }
2218                 db->first_res_count = db->first_req_count;
2219                 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2220
2221                 if (p->skip && rest == p->payload_length)
2222                         length = 4;
2223                 else if (offset + rest < PAGE_SIZE)
2224                         length = rest;
2225                 else
2226                         length = PAGE_SIZE - offset;
2227
2228                 db->second_req_count = cpu_to_le16(length);
2229                 db->second_res_count = db->second_req_count;
2230                 page_bus = page_private(buffer->pages[page]);
2231                 db->second_buffer = cpu_to_le32(page_bus + offset);
2232
2233                 if (p->interrupt && length == rest)
2234                         db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2235
2236                 context_append(&ctx->context, d, z, header_z);
2237                 offset = (offset + length) & ~PAGE_MASK;
2238                 rest -= length;
2239                 if (offset == 0)
2240                         page++;
2241         }
2242
2243         return 0;
2244 }
2245
2246 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2247                                         struct fw_iso_packet *packet,
2248                                         struct fw_iso_buffer *buffer,
2249                                         unsigned long payload)
2250 {
2251         struct iso_context *ctx = container_of(base, struct iso_context, base);
2252         struct descriptor *d, *pd;
2253         struct fw_iso_packet *p = packet;
2254         dma_addr_t d_bus, page_bus;
2255         u32 z, header_z, rest;
2256         int i, j, length;
2257         int page, offset, packet_count, header_size, payload_per_buffer;
2258
2259         /*
2260          * The OHCI controller puts the isochronous header and trailer in the
2261          * buffer, so we need at least 8 bytes.
2262          */
2263         packet_count = p->header_length / ctx->base.header_size;
2264         header_size  = max(ctx->base.header_size, (size_t)8);
2265
2266         /* Get header size in number of descriptors. */
2267         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2268         page     = payload >> PAGE_SHIFT;
2269         offset   = payload & ~PAGE_MASK;
2270         payload_per_buffer = p->payload_length / packet_count;
2271
2272         for (i = 0; i < packet_count; i++) {
2273                 /* d points to the header descriptor */
2274                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2275                 d = context_get_descriptors(&ctx->context,
2276                                 z + header_z, &d_bus);
2277                 if (d == NULL)
2278                         return -ENOMEM;
2279
2280                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
2281                                               DESCRIPTOR_INPUT_MORE);
2282                 if (p->skip && i == 0)
2283                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2284                 d->req_count    = cpu_to_le16(header_size);
2285                 d->res_count    = d->req_count;
2286                 d->transfer_status = 0;
2287                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2288
2289                 rest = payload_per_buffer;
2290                 pd = d;
2291                 for (j = 1; j < z; j++) {
2292                         pd++;
2293                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2294                                                   DESCRIPTOR_INPUT_MORE);
2295
2296                         if (offset + rest < PAGE_SIZE)
2297                                 length = rest;
2298                         else
2299                                 length = PAGE_SIZE - offset;
2300                         pd->req_count = cpu_to_le16(length);
2301                         pd->res_count = pd->req_count;
2302                         pd->transfer_status = 0;
2303
2304                         page_bus = page_private(buffer->pages[page]);
2305                         pd->data_address = cpu_to_le32(page_bus + offset);
2306
2307                         offset = (offset + length) & ~PAGE_MASK;
2308                         rest -= length;
2309                         if (offset == 0)
2310                                 page++;
2311                 }
2312                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2313                                           DESCRIPTOR_INPUT_LAST |
2314                                           DESCRIPTOR_BRANCH_ALWAYS);
2315                 if (p->interrupt && i == packet_count - 1)
2316                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2317
2318                 context_append(&ctx->context, d, z, header_z);
2319         }
2320
2321         return 0;
2322 }
2323
2324 static int ohci_queue_iso(struct fw_iso_context *base,
2325                           struct fw_iso_packet *packet,
2326                           struct fw_iso_buffer *buffer,
2327                           unsigned long payload)
2328 {
2329         struct iso_context *ctx = container_of(base, struct iso_context, base);
2330         unsigned long flags;
2331         int ret;
2332
2333         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2334         if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2335                 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2336         else if (ctx->context.ohci->use_dualbuffer)
2337                 ret = ohci_queue_iso_receive_dualbuffer(base, packet,
2338                                                         buffer, payload);
2339         else
2340                 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2341                                                         buffer, payload);
2342         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2343
2344         return ret;
2345 }
2346
2347 static const struct fw_card_driver ohci_driver = {
2348         .enable                 = ohci_enable,
2349         .update_phy_reg         = ohci_update_phy_reg,
2350         .set_config_rom         = ohci_set_config_rom,
2351         .send_request           = ohci_send_request,
2352         .send_response          = ohci_send_response,
2353         .cancel_packet          = ohci_cancel_packet,
2354         .enable_phys_dma        = ohci_enable_phys_dma,
2355         .get_bus_time           = ohci_get_bus_time,
2356
2357         .allocate_iso_context   = ohci_allocate_iso_context,
2358         .free_iso_context       = ohci_free_iso_context,
2359         .queue_iso              = ohci_queue_iso,
2360         .start_iso              = ohci_start_iso,
2361         .stop_iso               = ohci_stop_iso,
2362 };
2363
2364 #ifdef CONFIG_PPC_PMAC
2365 static void ohci_pmac_on(struct pci_dev *dev)
2366 {
2367         if (machine_is(powermac)) {
2368                 struct device_node *ofn = pci_device_to_OF_node(dev);
2369
2370                 if (ofn) {
2371                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2372                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2373                 }
2374         }
2375 }
2376
2377 static void ohci_pmac_off(struct pci_dev *dev)
2378 {
2379         if (machine_is(powermac)) {
2380                 struct device_node *ofn = pci_device_to_OF_node(dev);
2381
2382                 if (ofn) {
2383                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2384                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2385                 }
2386         }
2387 }
2388 #else
2389 #define ohci_pmac_on(dev)
2390 #define ohci_pmac_off(dev)
2391 #endif /* CONFIG_PPC_PMAC */
2392
2393 #define PCI_VENDOR_ID_AGERE             PCI_VENDOR_ID_ATT
2394 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
2395
2396 static int __devinit pci_probe(struct pci_dev *dev,
2397                                const struct pci_device_id *ent)
2398 {
2399         struct fw_ohci *ohci;
2400         u32 bus_options, max_receive, link_speed, version;
2401         u64 guid;
2402         int err;
2403         size_t size;
2404
2405         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2406         if (ohci == NULL) {
2407                 err = -ENOMEM;
2408                 goto fail;
2409         }
2410
2411         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2412
2413         ohci_pmac_on(dev);
2414
2415         err = pci_enable_device(dev);
2416         if (err) {
2417                 fw_error("Failed to enable OHCI hardware\n");
2418                 goto fail_free;
2419         }
2420
2421         pci_set_master(dev);
2422         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2423         pci_set_drvdata(dev, ohci);
2424
2425         spin_lock_init(&ohci->lock);
2426
2427         tasklet_init(&ohci->bus_reset_tasklet,
2428                      bus_reset_tasklet, (unsigned long)ohci);
2429
2430         err = pci_request_region(dev, 0, ohci_driver_name);
2431         if (err) {
2432                 fw_error("MMIO resource unavailable\n");
2433                 goto fail_disable;
2434         }
2435
2436         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2437         if (ohci->registers == NULL) {
2438                 fw_error("Failed to remap registers\n");
2439                 err = -ENXIO;
2440                 goto fail_iomem;
2441         }
2442
2443         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2444         ohci->use_dualbuffer = version >= OHCI_VERSION_1_1;
2445
2446         /* dual-buffer mode is broken if more than one IR context is active */
2447         if (dev->vendor == PCI_VENDOR_ID_AGERE &&
2448             dev->device == PCI_DEVICE_ID_AGERE_FW643)
2449                 ohci->use_dualbuffer = false;
2450
2451         /* dual-buffer mode is broken */
2452         if (dev->vendor == PCI_VENDOR_ID_RICOH &&
2453             dev->device == PCI_DEVICE_ID_RICOH_R5C832)
2454                 ohci->use_dualbuffer = false;
2455
2456 /* x86-32 currently doesn't use highmem for dma_alloc_coherent */
2457 #if !defined(CONFIG_X86_32)
2458         /* dual-buffer mode is broken with descriptor addresses above 2G */
2459         if (dev->vendor == PCI_VENDOR_ID_TI &&
2460             dev->device == PCI_DEVICE_ID_TI_TSB43AB22)
2461                 ohci->use_dualbuffer = false;
2462 #endif
2463
2464 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2465         ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2466                              dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2467 #endif
2468         ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI;
2469
2470         ar_context_init(&ohci->ar_request_ctx, ohci,
2471                         OHCI1394_AsReqRcvContextControlSet);
2472
2473         ar_context_init(&ohci->ar_response_ctx, ohci,
2474                         OHCI1394_AsRspRcvContextControlSet);
2475
2476         context_init(&ohci->at_request_ctx, ohci,
2477                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2478
2479         context_init(&ohci->at_response_ctx, ohci,
2480                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2481
2482         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2483         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2484         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2485         size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2486         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2487
2488         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2489         ohci->ir_context_channels = ~0ULL;
2490         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2491         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2492         size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2493         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2494
2495         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2496                 err = -ENOMEM;
2497                 goto fail_contexts;
2498         }
2499
2500         /* self-id dma buffer allocation */
2501         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2502                                                SELF_ID_BUF_SIZE,
2503                                                &ohci->self_id_bus,
2504                                                GFP_KERNEL);
2505         if (ohci->self_id_cpu == NULL) {
2506                 err = -ENOMEM;
2507                 goto fail_contexts;
2508         }
2509
2510         bus_options = reg_read(ohci, OHCI1394_BusOptions);
2511         max_receive = (bus_options >> 12) & 0xf;
2512         link_speed = bus_options & 0x7;
2513         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2514                 reg_read(ohci, OHCI1394_GUIDLo);
2515
2516         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2517         if (err)
2518                 goto fail_self_id;
2519
2520         fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2521                   dev_name(&dev->dev), version >> 16, version & 0xff);
2522
2523         return 0;
2524
2525  fail_self_id:
2526         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2527                           ohci->self_id_cpu, ohci->self_id_bus);
2528  fail_contexts:
2529         kfree(ohci->ir_context_list);
2530         kfree(ohci->it_context_list);
2531         context_release(&ohci->at_response_ctx);
2532         context_release(&ohci->at_request_ctx);
2533         ar_context_release(&ohci->ar_response_ctx);
2534         ar_context_release(&ohci->ar_request_ctx);
2535         pci_iounmap(dev, ohci->registers);
2536  fail_iomem:
2537         pci_release_region(dev, 0);
2538  fail_disable:
2539         pci_disable_device(dev);
2540  fail_free:
2541         kfree(&ohci->card);
2542         ohci_pmac_off(dev);
2543  fail:
2544         if (err == -ENOMEM)
2545                 fw_error("Out of memory\n");
2546
2547         return err;
2548 }
2549
2550 static void pci_remove(struct pci_dev *dev)
2551 {
2552         struct fw_ohci *ohci;
2553
2554         ohci = pci_get_drvdata(dev);
2555         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2556         flush_writes(ohci);
2557         fw_core_remove_card(&ohci->card);
2558
2559         /*
2560          * FIXME: Fail all pending packets here, now that the upper
2561          * layers can't queue any more.
2562          */
2563
2564         software_reset(ohci);
2565         free_irq(dev->irq, ohci);
2566
2567         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2568                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2569                                   ohci->next_config_rom, ohci->next_config_rom_bus);
2570         if (ohci->config_rom)
2571                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2572                                   ohci->config_rom, ohci->config_rom_bus);
2573         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2574                           ohci->self_id_cpu, ohci->self_id_bus);
2575         ar_context_release(&ohci->ar_request_ctx);
2576         ar_context_release(&ohci->ar_response_ctx);
2577         context_release(&ohci->at_request_ctx);
2578         context_release(&ohci->at_response_ctx);
2579         kfree(ohci->it_context_list);
2580         kfree(ohci->ir_context_list);
2581         pci_iounmap(dev, ohci->registers);
2582         pci_release_region(dev, 0);
2583         pci_disable_device(dev);
2584         kfree(&ohci->card);
2585         ohci_pmac_off(dev);
2586
2587         fw_notify("Removed fw-ohci device.\n");
2588 }
2589
2590 #ifdef CONFIG_PM
2591 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2592 {
2593         struct fw_ohci *ohci = pci_get_drvdata(dev);
2594         int err;
2595
2596         software_reset(ohci);
2597         free_irq(dev->irq, ohci);
2598         err = pci_save_state(dev);
2599         if (err) {
2600                 fw_error("pci_save_state failed\n");
2601                 return err;
2602         }
2603         err = pci_set_power_state(dev, pci_choose_state(dev, state));
2604         if (err)
2605                 fw_error("pci_set_power_state failed with %d\n", err);
2606         ohci_pmac_off(dev);
2607
2608         return 0;
2609 }
2610
2611 static int pci_resume(struct pci_dev *dev)
2612 {
2613         struct fw_ohci *ohci = pci_get_drvdata(dev);
2614         int err;
2615
2616         ohci_pmac_on(dev);
2617         pci_set_power_state(dev, PCI_D0);
2618         pci_restore_state(dev);
2619         err = pci_enable_device(dev);
2620         if (err) {
2621                 fw_error("pci_enable_device failed\n");
2622                 return err;
2623         }
2624
2625         return ohci_enable(&ohci->card, NULL, 0);
2626 }
2627 #endif
2628
2629 static struct pci_device_id pci_table[] = {
2630         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2631         { }
2632 };
2633
2634 MODULE_DEVICE_TABLE(pci, pci_table);
2635
2636 static struct pci_driver fw_ohci_pci_driver = {
2637         .name           = ohci_driver_name,
2638         .id_table       = pci_table,
2639         .probe          = pci_probe,
2640         .remove         = pci_remove,
2641 #ifdef CONFIG_PM
2642         .resume         = pci_resume,
2643         .suspend        = pci_suspend,
2644 #endif
2645 };
2646
2647 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2648 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2649 MODULE_LICENSE("GPL");
2650
2651 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2652 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2653 MODULE_ALIAS("ohci1394");
2654 #endif
2655
2656 static int __init fw_ohci_init(void)
2657 {
2658         return pci_register_driver(&fw_ohci_pci_driver);
2659 }
2660
2661 static void __exit fw_ohci_cleanup(void)
2662 {
2663         pci_unregister_driver(&fw_ohci_pci_driver);
2664 }
2665
2666 module_init(fw_ohci_init);
2667 module_exit(fw_ohci_cleanup);