Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6
[linux-3.10.git] / arch / sh / kernel / traps.c
1 /*
2  * 'traps.c' handles hardware traps and faults after we have saved some
3  * state in 'entry.S'.
4  *
5  *  SuperH version: Copyright (C) 1999 Niibe Yutaka
6  *                  Copyright (C) 2000 Philipp Rumpf
7  *                  Copyright (C) 2000 David Howells
8  *                  Copyright (C) 2002 - 2007 Paul Mundt
9  *
10  * This file is subject to the terms and conditions of the GNU General Public
11  * License.  See the file "COPYING" in the main directory of this archive
12  * for more details.
13  */
14 #include <linux/kernel.h>
15 #include <linux/ptrace.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
18 #include <linux/module.h>
19 #include <linux/kallsyms.h>
20 #include <linux/io.h>
21 #include <linux/bug.h>
22 #include <linux/debug_locks.h>
23 #include <linux/kdebug.h>
24 #include <linux/kexec.h>
25 #include <linux/limits.h>
26 #include <asm/system.h>
27 #include <asm/uaccess.h>
28
29 #ifdef CONFIG_SH_KGDB
30 #include <asm/kgdb.h>
31 #define CHK_REMOTE_DEBUG(regs)                  \
32 {                                               \
33         if (kgdb_debug_hook && !user_mode(regs))\
34                 (*kgdb_debug_hook)(regs);       \
35 }
36 #else
37 #define CHK_REMOTE_DEBUG(regs)
38 #endif
39
40 #ifdef CONFIG_CPU_SH2
41 # define TRAP_RESERVED_INST     4
42 # define TRAP_ILLEGAL_SLOT_INST 6
43 # define TRAP_ADDRESS_ERROR     9
44 # ifdef CONFIG_CPU_SH2A
45 #  define TRAP_DIVZERO_ERROR    17
46 #  define TRAP_DIVOVF_ERROR     18
47 # endif
48 #else
49 #define TRAP_RESERVED_INST      12
50 #define TRAP_ILLEGAL_SLOT_INST  13
51 #endif
52
53 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
54 {
55         unsigned long p;
56         int i;
57
58         printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
59
60         for (p = bottom & ~31; p < top; ) {
61                 printk("%04lx: ", p & 0xffff);
62
63                 for (i = 0; i < 8; i++, p += 4) {
64                         unsigned int val;
65
66                         if (p < bottom || p >= top)
67                                 printk("         ");
68                         else {
69                                 if (__get_user(val, (unsigned int __user *)p)) {
70                                         printk("\n");
71                                         return;
72                                 }
73                                 printk("%08x ", val);
74                         }
75                 }
76                 printk("\n");
77         }
78 }
79
80 static DEFINE_SPINLOCK(die_lock);
81
82 void die(const char * str, struct pt_regs * regs, long err)
83 {
84         static int die_counter;
85
86         oops_enter();
87
88         console_verbose();
89         spin_lock_irq(&die_lock);
90         bust_spinlocks(1);
91
92         printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
93
94         CHK_REMOTE_DEBUG(regs);
95         print_modules();
96         show_regs(regs);
97
98         printk("Process: %s (pid: %d, stack limit = %p)\n",
99                current->comm, current->pid, task_stack_page(current) + 1);
100
101         if (!user_mode(regs) || in_interrupt())
102                 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
103                          (unsigned long)task_stack_page(current));
104
105         bust_spinlocks(0);
106         spin_unlock_irq(&die_lock);
107
108         if (kexec_should_crash(current))
109                 crash_kexec(regs);
110
111         if (in_interrupt())
112                 panic("Fatal exception in interrupt");
113
114         if (panic_on_oops)
115                 panic("Fatal exception");
116
117         oops_exit();
118         do_exit(SIGSEGV);
119 }
120
121 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
122                                  long err)
123 {
124         if (!user_mode(regs))
125                 die(str, regs, err);
126 }
127
128 /*
129  * try and fix up kernelspace address errors
130  * - userspace errors just cause EFAULT to be returned, resulting in SEGV
131  * - kernel/userspace interfaces cause a jump to an appropriate handler
132  * - other kernel errors are bad
133  * - return 0 if fixed-up, -EFAULT if non-fatal (to the kernel) fault
134  */
135 static int die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
136 {
137         if (!user_mode(regs)) {
138                 const struct exception_table_entry *fixup;
139                 fixup = search_exception_tables(regs->pc);
140                 if (fixup) {
141                         regs->pc = fixup->fixup;
142                         return 0;
143                 }
144                 die(str, regs, err);
145         }
146         return -EFAULT;
147 }
148
149 /*
150  * handle an instruction that does an unaligned memory access by emulating the
151  * desired behaviour
152  * - note that PC _may not_ point to the faulting instruction
153  *   (if that instruction is in a branch delay slot)
154  * - return 0 if emulation okay, -EFAULT on existential error
155  */
156 static int handle_unaligned_ins(u16 instruction, struct pt_regs *regs)
157 {
158         int ret, index, count;
159         unsigned long *rm, *rn;
160         unsigned char *src, *dst;
161
162         index = (instruction>>8)&15;    /* 0x0F00 */
163         rn = &regs->regs[index];
164
165         index = (instruction>>4)&15;    /* 0x00F0 */
166         rm = &regs->regs[index];
167
168         count = 1<<(instruction&3);
169
170         ret = -EFAULT;
171         switch (instruction>>12) {
172         case 0: /* mov.[bwl] to/from memory via r0+rn */
173                 if (instruction & 8) {
174                         /* from memory */
175                         src = (unsigned char*) *rm;
176                         src += regs->regs[0];
177                         dst = (unsigned char*) rn;
178                         *(unsigned long*)dst = 0;
179
180 #ifdef __LITTLE_ENDIAN__
181                         if (copy_from_user(dst, src, count))
182                                 goto fetch_fault;
183
184                         if ((count == 2) && dst[1] & 0x80) {
185                                 dst[2] = 0xff;
186                                 dst[3] = 0xff;
187                         }
188 #else
189                         dst += 4-count;
190
191                         if (__copy_user(dst, src, count))
192                                 goto fetch_fault;
193
194                         if ((count == 2) && dst[2] & 0x80) {
195                                 dst[0] = 0xff;
196                                 dst[1] = 0xff;
197                         }
198 #endif
199                 } else {
200                         /* to memory */
201                         src = (unsigned char*) rm;
202 #if !defined(__LITTLE_ENDIAN__)
203                         src += 4-count;
204 #endif
205                         dst = (unsigned char*) *rn;
206                         dst += regs->regs[0];
207
208                         if (copy_to_user(dst, src, count))
209                                 goto fetch_fault;
210                 }
211                 ret = 0;
212                 break;
213
214         case 1: /* mov.l Rm,@(disp,Rn) */
215                 src = (unsigned char*) rm;
216                 dst = (unsigned char*) *rn;
217                 dst += (instruction&0x000F)<<2;
218
219                 if (copy_to_user(dst,src,4))
220                         goto fetch_fault;
221                 ret = 0;
222                 break;
223
224         case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
225                 if (instruction & 4)
226                         *rn -= count;
227                 src = (unsigned char*) rm;
228                 dst = (unsigned char*) *rn;
229 #if !defined(__LITTLE_ENDIAN__)
230                 src += 4-count;
231 #endif
232                 if (copy_to_user(dst, src, count))
233                         goto fetch_fault;
234                 ret = 0;
235                 break;
236
237         case 5: /* mov.l @(disp,Rm),Rn */
238                 src = (unsigned char*) *rm;
239                 src += (instruction&0x000F)<<2;
240                 dst = (unsigned char*) rn;
241                 *(unsigned long*)dst = 0;
242
243                 if (copy_from_user(dst,src,4))
244                         goto fetch_fault;
245                 ret = 0;
246                 break;
247
248         case 6: /* mov.[bwl] from memory, possibly with post-increment */
249                 src = (unsigned char*) *rm;
250                 if (instruction & 4)
251                         *rm += count;
252                 dst = (unsigned char*) rn;
253                 *(unsigned long*)dst = 0;
254
255 #ifdef __LITTLE_ENDIAN__
256                 if (copy_from_user(dst, src, count))
257                         goto fetch_fault;
258
259                 if ((count == 2) && dst[1] & 0x80) {
260                         dst[2] = 0xff;
261                         dst[3] = 0xff;
262                 }
263 #else
264                 dst += 4-count;
265
266                 if (copy_from_user(dst, src, count))
267                         goto fetch_fault;
268
269                 if ((count == 2) && dst[2] & 0x80) {
270                         dst[0] = 0xff;
271                         dst[1] = 0xff;
272                 }
273 #endif
274                 ret = 0;
275                 break;
276
277         case 8:
278                 switch ((instruction&0xFF00)>>8) {
279                 case 0x81: /* mov.w R0,@(disp,Rn) */
280                         src = (unsigned char*) &regs->regs[0];
281 #if !defined(__LITTLE_ENDIAN__)
282                         src += 2;
283 #endif
284                         dst = (unsigned char*) *rm; /* called Rn in the spec */
285                         dst += (instruction&0x000F)<<1;
286
287                         if (copy_to_user(dst, src, 2))
288                                 goto fetch_fault;
289                         ret = 0;
290                         break;
291
292                 case 0x85: /* mov.w @(disp,Rm),R0 */
293                         src = (unsigned char*) *rm;
294                         src += (instruction&0x000F)<<1;
295                         dst = (unsigned char*) &regs->regs[0];
296                         *(unsigned long*)dst = 0;
297
298 #if !defined(__LITTLE_ENDIAN__)
299                         dst += 2;
300 #endif
301
302                         if (copy_from_user(dst, src, 2))
303                                 goto fetch_fault;
304
305 #ifdef __LITTLE_ENDIAN__
306                         if (dst[1] & 0x80) {
307                                 dst[2] = 0xff;
308                                 dst[3] = 0xff;
309                         }
310 #else
311                         if (dst[2] & 0x80) {
312                                 dst[0] = 0xff;
313                                 dst[1] = 0xff;
314                         }
315 #endif
316                         ret = 0;
317                         break;
318                 }
319                 break;
320         }
321         return ret;
322
323  fetch_fault:
324         /* Argh. Address not only misaligned but also non-existent.
325          * Raise an EFAULT and see if it's trapped
326          */
327         return die_if_no_fixup("Fault in unaligned fixup", regs, 0);
328 }
329
330 /*
331  * emulate the instruction in the delay slot
332  * - fetches the instruction from PC+2
333  */
334 static inline int handle_unaligned_delayslot(struct pt_regs *regs)
335 {
336         u16 instruction;
337
338         if (copy_from_user(&instruction, (u16 *)(regs->pc+2), 2)) {
339                 /* the instruction-fetch faulted */
340                 if (user_mode(regs))
341                         return -EFAULT;
342
343                 /* kernel */
344                 die("delay-slot-insn faulting in handle_unaligned_delayslot",
345                     regs, 0);
346         }
347
348         return handle_unaligned_ins(instruction,regs);
349 }
350
351 /*
352  * handle an instruction that does an unaligned memory access
353  * - have to be careful of branch delay-slot instructions that fault
354  *  SH3:
355  *   - if the branch would be taken PC points to the branch
356  *   - if the branch would not be taken, PC points to delay-slot
357  *  SH4:
358  *   - PC always points to delayed branch
359  * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
360  */
361
362 /* Macros to determine offset from current PC for branch instructions */
363 /* Explicit type coercion is used to force sign extension where needed */
364 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
365 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
366
367 /*
368  * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit
369  * opcodes..
370  */
371 #ifndef CONFIG_CPU_SH2A
372 static int handle_unaligned_notify_count = 10;
373
374 static int handle_unaligned_access(u16 instruction, struct pt_regs *regs)
375 {
376         u_int rm;
377         int ret, index;
378
379         index = (instruction>>8)&15;    /* 0x0F00 */
380         rm = regs->regs[index];
381
382         /* shout about the first ten userspace fixups */
383         if (user_mode(regs) && handle_unaligned_notify_count>0) {
384                 handle_unaligned_notify_count--;
385
386                 printk(KERN_NOTICE "Fixing up unaligned userspace access "
387                        "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
388                        current->comm,current->pid,(u16*)regs->pc,instruction);
389         }
390
391         ret = -EFAULT;
392         switch (instruction&0xF000) {
393         case 0x0000:
394                 if (instruction==0x000B) {
395                         /* rts */
396                         ret = handle_unaligned_delayslot(regs);
397                         if (ret==0)
398                                 regs->pc = regs->pr;
399                 }
400                 else if ((instruction&0x00FF)==0x0023) {
401                         /* braf @Rm */
402                         ret = handle_unaligned_delayslot(regs);
403                         if (ret==0)
404                                 regs->pc += rm + 4;
405                 }
406                 else if ((instruction&0x00FF)==0x0003) {
407                         /* bsrf @Rm */
408                         ret = handle_unaligned_delayslot(regs);
409                         if (ret==0) {
410                                 regs->pr = regs->pc + 4;
411                                 regs->pc += rm + 4;
412                         }
413                 }
414                 else {
415                         /* mov.[bwl] to/from memory via r0+rn */
416                         goto simple;
417                 }
418                 break;
419
420         case 0x1000: /* mov.l Rm,@(disp,Rn) */
421                 goto simple;
422
423         case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
424                 goto simple;
425
426         case 0x4000:
427                 if ((instruction&0x00FF)==0x002B) {
428                         /* jmp @Rm */
429                         ret = handle_unaligned_delayslot(regs);
430                         if (ret==0)
431                                 regs->pc = rm;
432                 }
433                 else if ((instruction&0x00FF)==0x000B) {
434                         /* jsr @Rm */
435                         ret = handle_unaligned_delayslot(regs);
436                         if (ret==0) {
437                                 regs->pr = regs->pc + 4;
438                                 regs->pc = rm;
439                         }
440                 }
441                 else {
442                         /* mov.[bwl] to/from memory via r0+rn */
443                         goto simple;
444                 }
445                 break;
446
447         case 0x5000: /* mov.l @(disp,Rm),Rn */
448                 goto simple;
449
450         case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
451                 goto simple;
452
453         case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
454                 switch (instruction&0x0F00) {
455                 case 0x0100: /* mov.w R0,@(disp,Rm) */
456                         goto simple;
457                 case 0x0500: /* mov.w @(disp,Rm),R0 */
458                         goto simple;
459                 case 0x0B00: /* bf   lab - no delayslot*/
460                         break;
461                 case 0x0F00: /* bf/s lab */
462                         ret = handle_unaligned_delayslot(regs);
463                         if (ret==0) {
464 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
465                                 if ((regs->sr & 0x00000001) != 0)
466                                         regs->pc += 4; /* next after slot */
467                                 else
468 #endif
469                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
470                         }
471                         break;
472                 case 0x0900: /* bt   lab - no delayslot */
473                         break;
474                 case 0x0D00: /* bt/s lab */
475                         ret = handle_unaligned_delayslot(regs);
476                         if (ret==0) {
477 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
478                                 if ((regs->sr & 0x00000001) == 0)
479                                         regs->pc += 4; /* next after slot */
480                                 else
481 #endif
482                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
483                         }
484                         break;
485                 }
486                 break;
487
488         case 0xA000: /* bra label */
489                 ret = handle_unaligned_delayslot(regs);
490                 if (ret==0)
491                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
492                 break;
493
494         case 0xB000: /* bsr label */
495                 ret = handle_unaligned_delayslot(regs);
496                 if (ret==0) {
497                         regs->pr = regs->pc + 4;
498                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
499                 }
500                 break;
501         }
502         return ret;
503
504         /* handle non-delay-slot instruction */
505  simple:
506         ret = handle_unaligned_ins(instruction,regs);
507         if (ret==0)
508                 regs->pc += instruction_size(instruction);
509         return ret;
510 }
511 #endif /* CONFIG_CPU_SH2A */
512
513 #ifdef CONFIG_CPU_HAS_SR_RB
514 #define lookup_exception_vector(x)      \
515         __asm__ __volatile__ ("stc r2_bank, %0\n\t" : "=r" ((x)))
516 #else
517 #define lookup_exception_vector(x)      \
518         __asm__ __volatile__ ("mov r4, %0\n\t" : "=r" ((x)))
519 #endif
520
521 /*
522  * Handle various address error exceptions:
523  *  - instruction address error:
524  *       misaligned PC
525  *       PC >= 0x80000000 in user mode
526  *  - data address error (read and write)
527  *       misaligned data access
528  *       access to >= 0x80000000 is user mode
529  * Unfortuntaly we can't distinguish between instruction address error
530  * and data address errors caused by read accesses.
531  */
532 asmlinkage void do_address_error(struct pt_regs *regs,
533                                  unsigned long writeaccess,
534                                  unsigned long address)
535 {
536         unsigned long error_code = 0;
537         mm_segment_t oldfs;
538         siginfo_t info;
539 #ifndef CONFIG_CPU_SH2A
540         u16 instruction;
541         int tmp;
542 #endif
543
544         /* Intentional ifdef */
545 #ifdef CONFIG_CPU_HAS_SR_RB
546         lookup_exception_vector(error_code);
547 #endif
548
549         oldfs = get_fs();
550
551         if (user_mode(regs)) {
552                 int si_code = BUS_ADRERR;
553
554                 local_irq_enable();
555
556                 /* bad PC is not something we can fix */
557                 if (regs->pc & 1) {
558                         si_code = BUS_ADRALN;
559                         goto uspace_segv;
560                 }
561
562 #ifndef CONFIG_CPU_SH2A
563                 set_fs(USER_DS);
564                 if (copy_from_user(&instruction, (u16 *)(regs->pc), 2)) {
565                         /* Argh. Fault on the instruction itself.
566                            This should never happen non-SMP
567                         */
568                         set_fs(oldfs);
569                         goto uspace_segv;
570                 }
571
572                 tmp = handle_unaligned_access(instruction, regs);
573                 set_fs(oldfs);
574
575                 if (tmp==0)
576                         return; /* sorted */
577 #endif
578
579 uspace_segv:
580                 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
581                        "access (PC %lx PR %lx)\n", current->comm, regs->pc,
582                        regs->pr);
583
584                 info.si_signo = SIGBUS;
585                 info.si_errno = 0;
586                 info.si_code = si_code;
587                 info.si_addr = (void __user *)address;
588                 force_sig_info(SIGBUS, &info, current);
589         } else {
590                 if (regs->pc & 1)
591                         die("unaligned program counter", regs, error_code);
592
593 #ifndef CONFIG_CPU_SH2A
594                 set_fs(KERNEL_DS);
595                 if (copy_from_user(&instruction, (u16 *)(regs->pc), 2)) {
596                         /* Argh. Fault on the instruction itself.
597                            This should never happen non-SMP
598                         */
599                         set_fs(oldfs);
600                         die("insn faulting in do_address_error", regs, 0);
601                 }
602
603                 handle_unaligned_access(instruction, regs);
604                 set_fs(oldfs);
605 #else
606                 printk(KERN_NOTICE "Killing process \"%s\" due to unaligned "
607                        "access\n", current->comm);
608
609                 force_sig(SIGSEGV, current);
610 #endif
611         }
612 }
613
614 #ifdef CONFIG_SH_DSP
615 /*
616  *      SH-DSP support gerg@snapgear.com.
617  */
618 int is_dsp_inst(struct pt_regs *regs)
619 {
620         unsigned short inst = 0;
621
622         /*
623          * Safe guard if DSP mode is already enabled or we're lacking
624          * the DSP altogether.
625          */
626         if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
627                 return 0;
628
629         get_user(inst, ((unsigned short *) regs->pc));
630
631         inst &= 0xf000;
632
633         /* Check for any type of DSP or support instruction */
634         if ((inst == 0xf000) || (inst == 0x4000))
635                 return 1;
636
637         return 0;
638 }
639 #else
640 #define is_dsp_inst(regs)       (0)
641 #endif /* CONFIG_SH_DSP */
642
643 #ifdef CONFIG_CPU_SH2A
644 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
645                                 unsigned long r6, unsigned long r7,
646                                 struct pt_regs __regs)
647 {
648         siginfo_t info;
649
650         switch (r4) {
651         case TRAP_DIVZERO_ERROR:
652                 info.si_code = FPE_INTDIV;
653                 break;
654         case TRAP_DIVOVF_ERROR:
655                 info.si_code = FPE_INTOVF;
656                 break;
657         }
658
659         force_sig_info(SIGFPE, &info, current);
660 }
661 #endif
662
663 /* arch/sh/kernel/cpu/sh4/fpu.c */
664 extern int do_fpu_inst(unsigned short, struct pt_regs *);
665 extern asmlinkage void do_fpu_state_restore(unsigned long r4, unsigned long r5,
666                 unsigned long r6, unsigned long r7, struct pt_regs __regs);
667
668 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
669                                 unsigned long r6, unsigned long r7,
670                                 struct pt_regs __regs)
671 {
672         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
673         unsigned long error_code;
674         struct task_struct *tsk = current;
675
676 #ifdef CONFIG_SH_FPU_EMU
677         unsigned short inst = 0;
678         int err;
679
680         get_user(inst, (unsigned short*)regs->pc);
681
682         err = do_fpu_inst(inst, regs);
683         if (!err) {
684                 regs->pc += instruction_size(inst);
685                 return;
686         }
687         /* not a FPU inst. */
688 #endif
689
690 #ifdef CONFIG_SH_DSP
691         /* Check if it's a DSP instruction */
692         if (is_dsp_inst(regs)) {
693                 /* Enable DSP mode, and restart instruction. */
694                 regs->sr |= SR_DSP;
695                 return;
696         }
697 #endif
698
699         lookup_exception_vector(error_code);
700
701         local_irq_enable();
702         CHK_REMOTE_DEBUG(regs);
703         force_sig(SIGILL, tsk);
704         die_if_no_fixup("reserved instruction", regs, error_code);
705 }
706
707 #ifdef CONFIG_SH_FPU_EMU
708 static int emulate_branch(unsigned short inst, struct pt_regs* regs)
709 {
710         /*
711          * bfs: 8fxx: PC+=d*2+4;
712          * bts: 8dxx: PC+=d*2+4;
713          * bra: axxx: PC+=D*2+4;
714          * bsr: bxxx: PC+=D*2+4  after PR=PC+4;
715          * braf:0x23: PC+=Rn*2+4;
716          * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
717          * jmp: 4x2b: PC=Rn;
718          * jsr: 4x0b: PC=Rn      after PR=PC+4;
719          * rts: 000b: PC=PR;
720          */
721         if ((inst & 0xfd00) == 0x8d00) {
722                 regs->pc += SH_PC_8BIT_OFFSET(inst);
723                 return 0;
724         }
725
726         if ((inst & 0xe000) == 0xa000) {
727                 regs->pc += SH_PC_12BIT_OFFSET(inst);
728                 return 0;
729         }
730
731         if ((inst & 0xf0df) == 0x0003) {
732                 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
733                 return 0;
734         }
735
736         if ((inst & 0xf0df) == 0x400b) {
737                 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
738                 return 0;
739         }
740
741         if ((inst & 0xffff) == 0x000b) {
742                 regs->pc = regs->pr;
743                 return 0;
744         }
745
746         return 1;
747 }
748 #endif
749
750 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
751                                 unsigned long r6, unsigned long r7,
752                                 struct pt_regs __regs)
753 {
754         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
755         unsigned long error_code;
756         struct task_struct *tsk = current;
757 #ifdef CONFIG_SH_FPU_EMU
758         unsigned short inst = 0;
759
760         get_user(inst, (unsigned short *)regs->pc + 1);
761         if (!do_fpu_inst(inst, regs)) {
762                 get_user(inst, (unsigned short *)regs->pc);
763                 if (!emulate_branch(inst, regs))
764                         return;
765                 /* fault in branch.*/
766         }
767         /* not a FPU inst. */
768 #endif
769
770         lookup_exception_vector(error_code);
771
772         local_irq_enable();
773         CHK_REMOTE_DEBUG(regs);
774         force_sig(SIGILL, tsk);
775         die_if_no_fixup("illegal slot instruction", regs, error_code);
776 }
777
778 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
779                                    unsigned long r6, unsigned long r7,
780                                    struct pt_regs __regs)
781 {
782         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
783         long ex;
784
785         lookup_exception_vector(ex);
786         die_if_kernel("exception", regs, ex);
787 }
788
789 #if defined(CONFIG_SH_STANDARD_BIOS)
790 void *gdb_vbr_vector;
791
792 static inline void __init gdb_vbr_init(void)
793 {
794         register unsigned long vbr;
795
796         /*
797          * Read the old value of the VBR register to initialise
798          * the vector through which debug and BIOS traps are
799          * delegated by the Linux trap handler.
800          */
801         asm volatile("stc vbr, %0" : "=r" (vbr));
802
803         gdb_vbr_vector = (void *)(vbr + 0x100);
804         printk("Setting GDB trap vector to 0x%08lx\n",
805                (unsigned long)gdb_vbr_vector);
806 }
807 #endif
808
809 void __init per_cpu_trap_init(void)
810 {
811         extern void *vbr_base;
812
813 #ifdef CONFIG_SH_STANDARD_BIOS
814         gdb_vbr_init();
815 #endif
816
817         /* NOTE: The VBR value should be at P1
818            (or P2, virtural "fixed" address space).
819            It's definitely should not in physical address.  */
820
821         asm volatile("ldc       %0, vbr"
822                      : /* no output */
823                      : "r" (&vbr_base)
824                      : "memory");
825 }
826
827 void *set_exception_table_vec(unsigned int vec, void *handler)
828 {
829         extern void *exception_handling_table[];
830         void *old_handler;
831
832         old_handler = exception_handling_table[vec];
833         exception_handling_table[vec] = handler;
834         return old_handler;
835 }
836
837 extern asmlinkage void address_error_handler(unsigned long r4, unsigned long r5,
838                                              unsigned long r6, unsigned long r7,
839                                              struct pt_regs __regs);
840
841 void __init trap_init(void)
842 {
843         set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
844         set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
845
846 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
847     defined(CONFIG_SH_FPU_EMU)
848         /*
849          * For SH-4 lacking an FPU, treat floating point instructions as
850          * reserved. They'll be handled in the math-emu case, or faulted on
851          * otherwise.
852          */
853         set_exception_table_evt(0x800, do_reserved_inst);
854         set_exception_table_evt(0x820, do_illegal_slot_inst);
855 #elif defined(CONFIG_SH_FPU)
856         set_exception_table_evt(0x800, do_fpu_state_restore);
857         set_exception_table_evt(0x820, do_fpu_state_restore);
858 #endif
859
860 #ifdef CONFIG_CPU_SH2
861         set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_handler);
862 #endif
863 #ifdef CONFIG_CPU_SH2A
864         set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
865         set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
866 #endif
867
868         /* Setup VBR for boot cpu */
869         per_cpu_trap_init();
870 }
871
872 #ifdef CONFIG_BUG
873 void handle_BUG(struct pt_regs *regs)
874 {
875         enum bug_trap_type tt;
876         tt = report_bug(regs->pc, regs);
877         if (tt == BUG_TRAP_TYPE_WARN) {
878                 regs->pc += 2;
879                 return;
880         }
881
882         die("Kernel BUG", regs, TRAPA_BUG_OPCODE & 0xff);
883 }
884
885 int is_valid_bugaddr(unsigned long addr)
886 {
887         return addr >= PAGE_OFFSET;
888 }
889 #endif
890
891 void show_trace(struct task_struct *tsk, unsigned long *sp,
892                 struct pt_regs *regs)
893 {
894         unsigned long addr;
895
896         if (regs && user_mode(regs))
897                 return;
898
899         printk("\nCall trace: ");
900 #ifdef CONFIG_KALLSYMS
901         printk("\n");
902 #endif
903
904         while (!kstack_end(sp)) {
905                 addr = *sp++;
906                 if (kernel_text_address(addr))
907                         print_ip_sym(addr);
908         }
909
910         printk("\n");
911
912         if (!tsk)
913                 tsk = current;
914
915         debug_show_held_locks(tsk);
916 }
917
918 void show_stack(struct task_struct *tsk, unsigned long *sp)
919 {
920         unsigned long stack;
921
922         if (!tsk)
923                 tsk = current;
924         if (tsk == current)
925                 sp = (unsigned long *)current_stack_pointer;
926         else
927                 sp = (unsigned long *)tsk->thread.sp;
928
929         stack = (unsigned long)sp;
930         dump_mem("Stack: ", stack, THREAD_SIZE +
931                  (unsigned long)task_stack_page(tsk));
932         show_trace(tsk, sp, NULL);
933 }
934
935 void dump_stack(void)
936 {
937         show_stack(NULL, NULL);
938 }
939 EXPORT_SYMBOL(dump_stack);