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[MIPS] SB1250: Use the right irqaction for the timer interrupt.
[linux-3.10.git] / arch / mips / sibyte / sb1250 / time.c
1 /*
2  * Copyright (C) 2000, 2001 Broadcom Corporation
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * as published by the Free Software Foundation; either version 2
7  * of the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
17  */
18
19 /*
20  * These are routines to set up and handle interrupts from the
21  * sb1250 general purpose timer 0.  We're using the timer as a
22  * system clock, so we set it up to run at 100 Hz.  On every
23  * interrupt, we update our idea of what the time of day is,
24  * then call do_timer() in the architecture-independent kernel
25  * code to do general bookkeeping (e.g. update jiffies, run
26  * bottom halves, etc.)
27  */
28 #include <linux/clockchips.h>
29 #include <linux/interrupt.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/kernel_stat.h>
33
34 #include <asm/irq.h>
35 #include <asm/addrspace.h>
36 #include <asm/time.h>
37 #include <asm/io.h>
38
39 #include <asm/sibyte/sb1250.h>
40 #include <asm/sibyte/sb1250_regs.h>
41 #include <asm/sibyte/sb1250_int.h>
42 #include <asm/sibyte/sb1250_scd.h>
43
44
45 #define IMR_IP2_VAL     K_INT_MAP_I0
46 #define IMR_IP3_VAL     K_INT_MAP_I1
47 #define IMR_IP4_VAL     K_INT_MAP_I2
48
49 #define SB1250_HPT_NUM          3
50 #define SB1250_HPT_VALUE        M_SCD_TIMER_CNT /* max value */
51
52
53 /*
54  * The general purpose timer ticks at 1 Mhz independent if
55  * the rest of the system
56  */
57 static void sibyte_set_mode(enum clock_event_mode mode,
58                            struct clock_event_device *evt)
59 {
60         unsigned int cpu = smp_processor_id();
61         void __iomem *timer_cfg, *timer_init;
62
63         timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
64         timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
65
66         switch(mode) {
67         case CLOCK_EVT_MODE_PERIODIC:
68                 __raw_writeq(0, timer_cfg);
69                 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init);
70                 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
71                              timer_cfg);
72                 break;
73
74         case CLOCK_EVT_MODE_ONESHOT:
75                 /* Stop the timer until we actually program a shot */
76         case CLOCK_EVT_MODE_SHUTDOWN:
77                 __raw_writeq(0, timer_cfg);
78                 break;
79
80         case CLOCK_EVT_MODE_UNUSED:     /* shuddup gcc */
81         case CLOCK_EVT_MODE_RESUME:
82                 ;
83         }
84 }
85
86 static int
87 sibyte_next_event(unsigned long delta, struct clock_event_device *evt)
88 {
89         unsigned int cpu = smp_processor_id();
90         void __iomem *timer_cfg, *timer_init;
91
92         timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
93         timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
94
95         __raw_writeq(0, timer_cfg);
96         __raw_writeq(delta, timer_init);
97         __raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg);
98
99         return 0;
100 }
101
102 static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
103 {
104         unsigned int cpu = smp_processor_id();
105         struct clock_event_device *cd = dev_id;
106
107         /* ACK interrupt */
108         ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
109                        IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
110
111         cd->event_handler(cd);
112
113         return IRQ_HANDLED;
114 }
115
116 static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
117 static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
118 static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
119
120 void __cpuinit sb1250_clockevent_init(void)
121 {
122         unsigned int cpu = smp_processor_id();
123         unsigned int irq = K_INT_TIMER_0 + cpu;
124         struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu);
125         struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
126         unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
127
128         /* Only have 4 general purpose timers, and we use last one as hpt */
129         BUG_ON(cpu > 2);
130
131         sprintf(name, "sb1250-counter-%d", cpu);
132         cd->name                = name;
133         cd->features            = CLOCK_EVT_FEAT_PERIODIC |
134                                   CLOCK_EVT_FEAT_ONESHOT;
135         clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
136         cd->max_delta_ns        = clockevent_delta2ns(0x7fffff, cd);
137         cd->min_delta_ns        = clockevent_delta2ns(1, cd);
138         cd->rating              = 200;
139         cd->irq                 = irq;
140         cd->cpumask             = cpumask_of_cpu(cpu);
141         cd->set_next_event      = sibyte_next_event;
142         cd->set_mode            = sibyte_set_mode;
143         clockevents_register_device(cd);
144
145         sb1250_mask_irq(cpu, irq);
146
147         /* Map the timer interrupt to ip[4] of this cpu */
148         __raw_writeq(IMR_IP4_VAL,
149                      IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
150                             (irq << 3)));
151
152         sb1250_unmask_irq(cpu, irq);
153
154         action->handler = sibyte_counter_handler;
155         action->flags   = IRQF_DISABLED | IRQF_PERCPU;
156         action->name    = name;
157         action->dev_id  = cd;
158         setup_irq(irq, &action);
159 }
160
161 /*
162  * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
163  * again.
164  */
165 static cycle_t sb1250_hpt_read(void)
166 {
167         unsigned int count;
168
169         count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT))));
170
171         return SB1250_HPT_VALUE - count;
172 }
173
174 struct clocksource bcm1250_clocksource = {
175         .name   = "MIPS",
176         .rating = 200,
177         .read   = sb1250_hpt_read,
178         .mask   = CLOCKSOURCE_MASK(23),
179         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
180 };
181
182 void __init sb1250_clocksource_init(void)
183 {
184         struct clocksource *cs = &bcm1250_clocksource;
185
186         /* Setup hpt using timer #3 but do not enable irq for it */
187         __raw_writeq(0,
188                      IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
189                                                  R_SCD_TIMER_CFG)));
190         __raw_writeq(SB1250_HPT_VALUE,
191                      IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
192                                                  R_SCD_TIMER_INIT)));
193         __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
194                      IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
195                                                  R_SCD_TIMER_CFG)));
196
197         clocksource_set_clock(cs, V_SCD_TIMER_FREQ);
198         clocksource_register(cs);
199 }
200
201 void __init plat_time_init(void)
202 {
203         sb1250_clocksource_init();
204         sb1250_clockevent_init();
205 }